WO2020066737A1

WO2020066737A1 - Cpu unit, cpu unit control method, information processing program, and recording medium

Info

Publication number: WO2020066737A1
Application number: PCT/JP2019/036311
Authority: WO
Inventors: 桶田　英男
Original assignee: オムロン株式会社
Priority date: 2018-09-25
Filing date: 2019-09-17
Publication date: 2020-04-02
Also published as: JP2020052550A; CN112534411A; JP7028124B2

Abstract

The present invention prevents erroneous determinations related to synchronization even in the case where duplexed CPU units in a PLC have mutually different processing capacities. A first CPU unit (100A) sets a waiting time (Tw) for a synchronization check process, in consideration of the ratio between the ability (Abm) of the unit and the ability (Aby) of a second CPU unit (100B).

Description

CPU unit, CPU unit control method, information processing program, and recording medium

The present invention relates to a CPU unit and the like that are duplicated in a controller.

Conventionally, for a PLC (Programmable Logic Controller), there is known a configuration in which a CPU unit is duplicated for the purpose of improving system safety and reliability. For example, in Patent Document 1 below, prior to the start of the duplex operation, the CPU unit of the execution system acquires the unit version of the CPU unit of the standby system, compares it with the function version stored and retained by itself, and compares the unit version. A configuration is disclosed that determines that redundant operation is possible when is a function version or higher. Hereinafter, with reference to FIG. 8 and FIG. 9, a description will be given of the conventional duplication of the CPU unit in the PLC.

FIG. 8 is a diagram illustrating an outline of a conventional process of a CPU unit duplexed in a PLC. As illustrated in FIG. 8, each of the CPU units duplicated in the PLC repeatedly executes a self-diagnosis process, an instruction execution process, and an I / O refresh process in this order. The period from when the I / O refresh processing is performed to when the next I / O refresh processing is performed is also referred to as “one cycle (one cycle)”. That is, each of the CPU units duplicated in the PLC executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order in "one cycle (one cycle)". A period required for “one cycle” (that is, a period from the execution of the I / O refresh processing to the execution of the next I / O refresh) is also referred to as “cycle time”.

The self-diagnosis process is a process for diagnosing whether the hardware of the self-unit is operating normally, and in particular, whether there is any abnormality in the memory and the hard disk. The instruction execution process is a process for executing a user program or the like, executes various operations using data obtained in the I / O refresh process executed in the previous cycle, and executes the I / O refresh process in the current cycle. This is the process of generating the data to be output. The I / O refresh process is a process for exchanging data with an external device and an external unit other than the duplicated CPU unit of the other party, outputting data generated in the immediately preceding instruction execution process, and outputting the next cycle. This is a process of acquiring data used for the instruction execution process.

One of the duplicated CPU units in the PLC is an active system and the other is a standby system (STB), and mutually confirms the status of the duplicated CPU unit. When the active CPU unit goes down, the standby CPU unit is switched to the down active CPU unit to continue the operation. Hereinafter, the CPU unit serving as the execution system may be abbreviated as “ACT”, and the CPU unit serving as the standby system may be abbreviated as “STB”.

In order to smoothly switch from ACT to STB when ACT is down, ACT and STB are synchronized during the internal processing of each CPU unit, as shown in FIG. That is, in each of the ACT and the STB, at the timing when the self-unit completes the execution of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, an abnormality occurs in the unit of the other party to be duplexed. Make sure you are not. "Confirmation that no abnormality has occurred in the other unit to be duplexed", which is executed at the timing when the own unit completes execution of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. Is also referred to as “synchronization check processing”.

By synchronizing during the internal processing, the cycle of each CPU unit (more precisely, the start time of the internal processing of each CPU unit) does not deviate, and the duplicated CPU units execute the same processing at the same timing. Can be run with Each of the ACT and the STB executes a synchronization check process at the completion of each of the self-diagnosis process, the instruction execution process, and the I / O refresh process, and performs synchronization (that is, when an abnormality occurs in the partner unit). Is not checked), and then the execution of the next process is started. Therefore, each of the ACT and the STB can start the execution of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing at the same timing.

In this synchronization check processing, each of the ACT and the STB basically monitors the state of the other party (in other words, confirms), and if the ACT is abnormally stopped, the STB replaces the abnormally stopped ACT. Take over the driving.

Here, assuming a case where the ACT or STB cannot detect an abnormality of the synchronization target (that is, the duplicated CPU unit) (in particular, the ACT cannot detect an abnormality of the STB), Each performs a synchronization check process as follows. In other words, if each of the ACT and STB fails to acquire the response of the partner CPU unit within a predetermined period in each synchronization check process, the ACT and the STB indicate that an error has occurred in the duplicated partner CPU unit (that is, the synchronization error has occurred). Has occurred). " Specifically, if each of the ACT and the STB cannot obtain a notification indicating that “the execution of the corresponding process has been completed” from the partner CPU unit in the respective synchronization check processes within the determination period, An abnormality has occurred in the specified CPU unit of the other party ".

判定する When it is determined that “an error has occurred in the duplicated CPU unit of the other party”, each of the ACT and the STB executes the “cancel the duplication” process. By "cancelling the duplication", each of the ACT and the STB prevents the "cycle time from becoming extremely long by maintaining synchronization with the partner CPU unit in which the abnormality has occurred". If the duplication is not canceled, that is, if “the next processing is not started until it is confirmed that no abnormality has occurred in the partner unit”, and if an abnormality occurs in the partner CPU unit, No abnormality has occurred ". Therefore, execution of the next process cannot be started, and the cycle time becomes extremely long.

FIG. 9 is a diagram for explaining the details of the self-diagnosis processing, the instruction execution processing, and the synchronization check processing executed at the completion of each of the I / O refresh processing. As described above, in the synchronization check process, each of the ACT and the STB confirms whether or not a notification that “the execution of the corresponding process has been completed” can be obtained from the partner CPU unit within the determination period.

The synchronization check processing is performed, for example, by providing a register (common register) that can be read and written by each CPU unit inside or outside each of the CPU units (that is, ACT and STB) that are duplicated in the PLC. ,realizable. At the time when the processing up to the synchronization check processing is completed, that is, at the time when the execution of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing is completed, the “own unit performs processing execution”. Is completed "in the common register. Each CPU unit reads that "the own unit has completed the execution of the process" written in the common register by the other CPU unit, thereby confirming that the other CPU unit has completed the execution of the process. Confirm.

That is, as illustrated in FIG. 9, when the CPU unit 99P completes the processing, that is, when the execution of the processing is completed, the REG1 of the common register 98 indicates that the processing has been completed (that is, “the own unit is Has been completed "). By reading out REG1, the CPU unit 99Q recognizes that the CPU unit 99P has completed the processing. When the CPU unit 99Q completes the process, that is, when the execution of the process is completed, the REG2 of the common register 98 indicates that the process has been completed (that is, “the own unit has completed the execution of the process”). Write. By reading REG2, the CPU unit 99P recognizes that the CPU unit 99Q has completed the processing. When the CPU unit 99P and the CPU unit 99Q recognize that the processing has been completed, the CPU unit 99P and the CPU unit 99Q each shift to the next processing.

In the case where the synchronization check process using the common register 98 is adopted, when an error occurs in the partner CPU unit, the fact that “the own unit has completed the execution of the process” by the partner CPU unit is written in the common register 98. Absent. Therefore, each CPU unit waits for a predetermined period from the time when the execution of the process by the own unit is completed, and then writes, to the common register 98, the writing of "the own unit has completed the execution of the process" by the partner CPU unit. Determine the presence or absence. For example, even if a predetermined period has elapsed from the time when the CPU unit 99P has completed the execution of the process, the CPU unit 99P will not write a message to the REG2 that "the unit has completed the execution of the process". It is determined that an abnormality has occurred in 99Q. Even if a predetermined period has elapsed from the time when the CPU unit 99Q has completed the execution of the process, the CPU unit 99Q does not write "the unit has completed the execution of the process" to the REG1. It is determined that an abnormality has occurred. In the following description, each CPU unit performs processing from completion of execution of processing by its own unit to determination of presence / absence of writing of “the own unit has completed execution of processing” by the partner CPU unit. The predetermined period is also referred to as “waiting time”.

Japanese Unexamined Patent Publication "JP 2005-122716 A"

The prior art as described above is based on the premise that the hardware of the CPU unit duplicated in the PLC is almost the same, that is, both have substantially the same processing capacity. However, there is a problem that it is not possible to assume a case where is different.

Conventionally, under the assumption that the processing capabilities of the duplicated CPU units are almost the same, each CPU unit has a common “waiting time” between the duplicated CPU units from the time when the execution of the processing by the own unit is completed. After the elapse, the CPU unit of the other party is determined to be abnormal.

(4) The reason why the redundant CPU unit performs the synchronization check process using the common "waiting time" is as follows. That is, under the assumption that the processing capacity of the duplicated CPU units is the same, the time points at which the execution of the processing by the duplicated CPU units is completed should be substantially the same. In other words, under the assumption that the processing performance of the own unit and the CPU unit of the other party to be duplicated are the same, the time when the execution of the processing by the own unit is completed and the time when the execution of the processing by the other CPU unit is completed are completed. The time should be almost the same timing. Therefore, in each of the duplicated CPU units, the "waiting time" used to determine the abnormality of the partner CPU unit, that is, the "waiting time" used for the synchronization check processing is conventionally common to the duplicated CPU units. , For a fixed period of length.

However, the CPU unit is often used for a long period of time, for example, about 20 years or more, and during that time, the production of parts used in the CPU unit is stopped, and the CPU unit is largely renewed. May be done. Then, for example, when the hardware of the CPU unit is significantly renewed, the performance of the CPU unit before and after the renewal, that is, the processing capacity may greatly change.

If the CPU unit before the renewal is duplicated with the CPU unit after the renewal, if the "waiting time" used for the synchronization check processing is common to the CPU units to be duplicated, the synchronization check processing cannot be executed correctly. Problems occur.

(Occurrence of misjudgment)
That is, even if the processing is the same, the execution completion time differs between the CPU unit before the renewal and the CPU unit after the renewal. Therefore, if the determination is made after a common “waiting time”, the other CPU unit normally operates. Even if it is operating, it is erroneously determined to be abnormal.

For example, if the processing capacity is increased by a factor of four due to the renewal compared to before the renewal, if the CPU unit after the renewal is about “10 ms (milliseconds)” during the period required to execute a certain process, the CPU before the renewal is executed. The unit is about “40 ms”. When the “waiting time” used for the synchronization check process is fixed to “5 ms” common to both units, the CPU unit before the renewal and the CPU unit after the renewal. Make a decision.

That is, the CPU unit after the renewal synchronizes, that is, the CPU unit before the renewal executes the certain process at a time when “5 ms” has elapsed from the time when the own unit has completed the execution of the certain process. It is determined whether the process has been completed. However, the CPU unit before the renewal cannot complete the execution of the certain process unless “30 ms” has elapsed from “the time when the CPU unit after the renewal has completed the execution of the certain process”. Therefore, the CPU unit after the renewal, from the time when 5 ms has passed from the time when the own unit has completed the execution of the certain process, the CPU unit before the renewal, "the CPU unit before the renewal executes the execution of the certain process. I can't get the notification of "Completed." Therefore, even if the CPU unit before the renewal is operating normally, the CPU unit after the renewal may incorrectly report that an error has occurred in the CPU unit before the renewal (that is, a synchronization error has occurred). Judgment.

(Delay of judgment occurs)
In the above example, by fixing the "waiting time" common to the CPU unit before the renewal and the CPU unit after the renewal to, for example, "30 ms", erroneous determination by the CPU unit after the renewal can be prevented. .

That is, the CPU unit before the renewal can complete the execution of the certain process if "30 ms" has elapsed from "the time when the CPU unit after the renewal completed execution of the certain process". . Therefore, if the CPU unit after the renewal has passed “30 ms” from the time when the own unit has completed the execution of the certain process, the CPU unit determines whether or not an abnormality has occurred in the CPU unit before the renewal. It can be determined correctly.

However, since the waiting time of “30 ms” is common to the CPU unit before the renewal and the CPU unit after the renewal, the CPU unit before the renewal starts when the own unit completes the execution of the certain process. The determination is made after "30 ms" has elapsed. That is, the CPU unit before the renewal determines “whether or not an abnormality has occurred in the CPU unit after the renewal” after “30 ms” has elapsed from the time when the own unit has completed the execution of the certain process.

The CPU unit before the renewal and the CPU unit after the renewal recognize the completion of the processing of the other CPU unit, and then shift to the next processing. Then, the execution start of the next process is delayed. The CPU unit after the renewal determines the abnormality of the partner CPU unit after a lapse of “30 ms” from the time when the own unit completes the execution of the certain process, and further, after “30 ms”, the CPU unit before the renewal Is performed to determine the abnormality. That is, the CPU unit after the renewal cannot start execution of the next process unless "60 ms" has elapsed from the point at which the own unit has completed execution of the certain process. That is, if the CPU unit before the renewal and the CPU unit before the renewal and the CPU unit after the renewal are set to a common “30 ms” for both, the completion of the determination of both is delayed.

Since the CPU unit before the renewal does not execute the determination unless "30 ms" has elapsed from the time when the own unit has completed the execution of the certain process, the operation is continued when the CPU unit after the renewal has an abnormality. Switching from ACT to STB for the delay.

As described above, in the related art on the premise that the duplicated CPU units have almost the same processing capability in the PLC, the erroneous determination and the ACT to STB transition are performed when the duplicated CPU units have different processing capabilities. There is a problem that a delay in switching occurs.

In order to solve the above-described problem, a CPU unit according to one embodiment of the present invention is a CPU unit that is duplicated in a controller, and has a processing capability of its own unit and a processing capability of a partner CPU unit that is duplicated. A setting unit that sets a waiting time in consideration of the ratio, and from the completion of execution of the processing in the own unit to the lapse of the waiting time set by the setting unit, the processing of the processing in the partner CPU unit. A determination unit that determines that an abnormality has occurred in the partner CPU unit when execution completion cannot be confirmed.

In order to solve the above problem, a control method according to one embodiment of the present invention is a control method of a CPU unit that is duplicated in a controller, and includes a processing capability of the own unit and a processing of a duplicated CPU unit. A setting step of setting a waiting time in consideration of a ratio with the capacity, and a CPU unit of the other party from the time when the execution of the process in the own unit is completed to the time when the waiting time set in the setting step elapses. And determining that an abnormality has occurred in the partner CPU unit if the completion of execution of the processing cannot be confirmed.

According to one aspect of the present invention, for a CPU unit that is duplicated in a PLC, a synchronization check can be performed without providing an unnecessary waiting time in consideration of the difference in processing capacity between the CPU unit of the other party that is duplicated and its own unit. The effect is that the processing can be performed accurately.

FIG. 2 is a block diagram illustrating a main configuration of a CPU unit and the like according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating an outline of a process executed by each of two CPU units illustrated in FIG. 1. FIG. 2 is a diagram illustrating a specific example of a process in which each of the two CPU units illustrated in FIG. 1 acquires performance information indicating the performance of the CPU unit of the other party to be duplicated. FIG. 9 is a block diagram illustrating a main configuration of a CPU unit and the like according to a second embodiment of the present invention. FIG. 5 is a diagram illustrating an example of a hardware configuration for realizing the CPU unit illustrated in FIG. 4. FIG. 5 is a diagram illustrating an outline of processing executed by each of two CPU units illustrated in FIG. 4. FIG. 5 is a diagram illustrating a specific example of a process in which each of the two CPU units illustrated in FIG. 4 acquires performance information indicating the performance of a partner CPU unit to be duplexed. FIG. 7 is a diagram for explaining an outline of processing performed by a CPU unit duplexed in a PLC up to the present. FIG. 11 is a diagram for explaining details of a synchronization check process executed at the completion of execution of each of a self-diagnosis process, an instruction execution process, and an I / O refresh process.

[Embodiment 1]
Hereinafter, an embodiment according to one aspect of the present invention (hereinafter, also referred to as “the present embodiment”) will be described with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated. In the following embodiments, a PLC (Programmable Logic Controller) 10 that controls a control target such as a machine and equipment will be described as a typical example of a controller in which two CPU units are duplicated.

In the following, first, in order to facilitate understanding of each of the first CPU unit 100A and the second CPU unit 100B that are duplicated in the PLC 10, an outline of processing executed by each of them will be described with reference to FIG.

§1. Application Example FIG. 2 is a diagram illustrating an outline of processing executed by each of two CPU units (that is, first CPU unit 100A and second CPU unit 100B) described later with reference to FIG. The first CPU unit 100A and the second CPU unit 100B are duplexed in the PLC 10, and one of them becomes an active system (ACT) and the other becomes a standby system (STB), and confirms the state of the other CPU unit. When the active CPU unit (ACT) goes down, the first CPU unit 100A and the second CPU unit 100B switch over to the ACT of the standby CPU unit (STB) to continue the operation. Hereinafter, for ease of understanding, an example in which the first CPU unit 100A is an ACT and the second CPU unit 100B is an STB will be described.

(Summary of waiting time)
As shown in FIG. 2, each of the ACT and the STB repeatedly executes a self-diagnosis process, an instruction execution process, and an I / O refresh process in this order. Hereinafter, a set of “self-diagnosis processing, instruction execution processing, and I / O refresh processing” executed repeatedly in this order is referred to as “one cycle (one cycle)”.

The self-diagnosis process is a process for diagnosing whether the hardware of the own unit is operating normally. The instruction execution process is a process for executing a user program or the like, executes various operations using data obtained in the I / O refresh process executed in the previous cycle, and executes the I / O refresh process in the current cycle. This is the process of generating the data to be output. In the instruction execution processing, a control signal is generated for an external device other than the partner CPU unit, which is a control target of the PLC 10 (more precisely, the first CPU unit 100A or the second CPU unit 100B). The I / O refresh process is a process for exchanging data with an external device and an external unit other than the duplicated CPU unit of the other party. The I / O refresh process outputs data generated in the instruction execution process in the current cycle, and outputs the data. This is a process of acquiring data used for the instruction execution process in the cycle of. The control signal generated in the instruction execution processing is output to a control target in the I / O refresh processing.

As shown in FIG. 2, each of ACT (first CPU unit 100A) and STB (second CPU unit 100B) performs its own self-diagnosis processing, instruction execution processing, and I / O refresh processing. After that, the “synchronization check process” is executed. In this synchronization check process, each of the ACT and the STB monitors (in other words, confirms) the status of the other CPU unit. If the ACT is abnormally stopped, the STB replaces the abnormally stopped ACT. Take over, driving.

The “synchronization check process” is a process of confirming that the partner CPU unit has completed execution of the process completed by the own unit in the same manner as the own unit, and it is not possible to confirm the completion of the process of the partner CPU unit. In this case, it is determined that an abnormality has occurred. For example, after the ACT completes the execution of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, the STB executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. Confirm (determine) whether has been completed. For example, after the STB completes the execution of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, the ACT executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. Confirm (determine) whether has been completed.

In the “synchronization check process”, each of the ACT and the STB sends a “the certain process” from the partner CPU unit after a lapse of a predetermined time (= waiting time Tw) from the completion of the execution of the process by the own unit. Has been completed. " Each of the ACT and the STB cannot acquire the notification of “completion of the execution of the certain process” of the partner CPU unit after the waiting time Tw has elapsed since the execution of the certain process by the own unit is completed. Is determined as "an error has occurred in the duplicated CPU unit of the other party". When the first CPU unit 100A is ACT and the second CPU unit 100B is STB, if it is determined that an abnormality has occurred in the first CPU unit 100A, the second CPU unit 100B switches to ACT and continues operation. I do.

As described above, if the ACT (first CPU unit 100A) and STB (second CPU unit 100B) have the same length of “waiting time Tw”, if the performance Ab differs between ACT and STB, erroneous determination and ACT There is a problem that a delay in switching from the STB to the STB occurs. Therefore, each of the ACT and the STB executes the following processing to execute an accurate synchronization check processing without providing an unnecessary waiting time Tw even when the performances Ab of the two are different.

That is, first, a “CPU unit of reference hardware (reference CPU unit)” is assumed in advance, and the performance Ab (processing capacity) and the processing time are defined in advance for this reference CPU unit. In the following description, the performance Ab of the reference CPU unit may be referred to as “performance Abb”.

Each of the ACT and the STB includes information indicating the performance Ab of the own unit, for example, information indicating “how much performance Ab the own unit has compared to the reference CPU unit” (self Machine performance information). When the ACT and the STB are duplicated in the PLC 10, each of the ACT and the STB grasps each other's performance Ab (the relative performance Ab of the partner CPU unit with respect to the performance Abb of the reference CPU unit). Then, each of the ACT and the STB flexibly sets the waiting time Tw for the synchronization check process based on the grasped performance Ab. In the following description, the performance Ab of the own unit (the relative performance Ab of the own unit with respect to the performance Abb of the reference CPU unit) may be expressed as “performance Abm”. Similarly, the performance Ab of the partner CPU unit (the relative performance Ab of the partner CPU unit with respect to the performance Abb of the reference CPU unit) may be referred to as “performance Aby”.

{Specifically, when the ACT and the STB are duplexed in the PLC 10, the waiting time Tw for the synchronization check processing is set as follows. That is, when the performance Aby of the CPU unit of the other party to be duplicated is higher than the performance Abm of the own unit, that is, when the execution speed of the processing of the CPU unit of the other party to be duplicated is faster than that of the own unit, the normal waiting time Two is set to the waiting time Tw. When the performance Aby of the CPU unit of the other party to be duplicated is equal to the performance Abm of the own unit, that is, when the execution speed of the processing is the same between the CPU unit of the other party and the own unit to be duplicated, the normal waiting time Two is set. The waiting time Tw is set. When the performance Aby of the CPU unit of the other party to be duplicated is lower than the performance Abm of the own unit, that is, when the execution speed of the processing of the CPU unit of the other party to be duplicated is lower than that of the own unit, the waiting time Tw is set to the other party. Is set according to the performance Aby of the CPU unit.

For example, if the performance Abm of the own unit is twice the performance Abb of the reference CPU unit and the performance Aby of the other CPU unit to be duplexed is 1/2 the performance Abb of the reference CPU unit, the performance Abm is the performance 4 times Aby. In this case, if the own unit requires “10 ms (milliseconds)” to execute a certain process to be subjected to the synchronization check process, the other CPU unit requires “40 ms”. Is set to “30 ms + normal waiting time Two”.

For example, if the performance Abm of the own unit is half the performance Abb of the reference CPU unit and the performance Aby of the other CPU unit to be duplexed is twice the performance Abb of the reference CPU unit, the performance Abm is the performance Abm. It is 1/4 times Aby. In this case, if the own unit requires “40 ms” to execute a certain process to be subjected to the synchronization check process, the other CPU unit requires “10 ms”. Is set to “normal waiting time Two”.

Each of the ACT (first CPU unit 100A) and the STB (second CPU unit 100B) flexibly sets the waiting time Tw of its own unit according to the difference in performance Ab between its own unit and the other CPU unit that is duplexed. .

(Specific example of processing)
As shown in FIG. 2, when the first CPU unit 100A (ACT) and the second CPU unit 100B (STB) are duplicated in the PLC 10, each of the ACT and the STB executes “duplication processing” separately from a normal cycle. I do. In other words, each of the ACT and the STB executes the “duplication process” before the “self-diagnosis process, the instruction execution process, and the I / O refresh process”, which are cyclically (periodically) repeatedly executed.

Each of the ACT and the STB grasps each other's performance Ab in the “duplication process” and enters a duplex state. The performance information (own apparatus performance information) of each of the ACT and the STB is written to a nonvolatile memory included in each CPU unit, for example, when each CPU unit is produced. The own device performance information is, for example, based on the performance Abb of the CPU unit having the specific hardware specifications (the above-mentioned “reference CPU unit”) as a reference, the performance Abb of the reference CPU unit and the performance Abb of the own unit. Abm indicates what percentage of the performance is UP / DOWN.

Each of the ACT and the STB stores the performance information of its own unit in the nonvolatile memory of each CPU unit as “own device performance information”. Each of the ACT and the STB transfers the own device performance information to each other in the duplex processing, and stores the own device performance information of the partner CPU unit as “other device performance information” in the non-volatile memory of each CPU unit. Store.

For example, the own device performance information is 150% (that is, the processing execution speed (processing speed) is 1.5 times the reference CPU unit), and the other device performance information is 75% (the processing speed is lower than the reference CPU unit). ACT knows the following information. That is, the ACT grasps that the processing speed of the own unit (ACT) is “2 times (= 1.5 times / 0.75 times)” the processing speed of the partner CPU unit (STB).

For example, the own device performance information is 75% (the processing speed is 0.75 times that of the reference CPU unit), and the other device performance information is 150% (that is, the execution speed (processing speed) of the process is STB, the STB knows the following information. That is, it is understood that the processing speed of the own unit (STB) is “１／ times (= 0.75 times / 1.5 times)” the processing speed of the other CPU unit (ACT).

In the “duplexing process”, the difference between the performance Abs of the own unit and the partner CPU unit is grasped, and when the state becomes a duplex state, each of the ACT and the STB uses the difference of the performance Abs to determine the waiting time of the own unit. Set Tw.

Each of the ACT and the STB measures, for example, the execution time from the start of the execution of the “instruction execution” process of FIG. 2 to the completion of the execution in each CPU unit using the internal timer of each CPU unit. Here, assuming that the execution time of the ACT is “100 ms” in the “instruction execution” process, the difference between the performance Ab and the STB is “2 times” as described above, so that the other CPU unit (STB) is “200 ms”. "It will be.

Therefore, the ACT sets a period obtained by adding “100 ms (= 200 ms−100 ms)” to the normal waiting time Two as the waiting time Tw of the synchronization check process related to the “instruction execution” process of the own unit. In the example illustrated in FIG. 2, the ACT executes a standby process for a period of “100 ms” from the completion of execution of the “instruction execution” process in its own unit, and then performs a synchronization check process related to the “instruction execution” process. Running. That is, the ACT executes the “instruction execution” process from the partner CPU unit (STB) from the completion of the execution of the “instruction execution” process in the own unit until “100 ms + normal waiting time Two” elapses. It is determined whether or not to acquire the notification of the completion of the execution. The ACT sends a notification of the completion of the execution of the “instruction execution” process from the STB during a period from the completion of the execution of the “instruction execution” process in the own unit until “100 ms + normal waiting time Two” elapses. If the STB cannot be obtained, it is determined that an abnormality has occurred in the STB.

The STB that has grasped that the partner CPU unit (ACT) has higher performance Ab or equal performance Ab (that is, the processing speed is faster or the same), keeps the normal waiting time Two as it is. Is set as the waiting time Tw of the synchronization check process related to the “instruction execution” process of the own unit. In the example shown in FIG. 2, the STB executes the synchronization check process related to the “instruction execution” process immediately after completing the execution of the “instruction execution” process in the STB. In other words, the STB performs the execution of the “instruction execution” process from the partner CPU unit (ACT) from the completion of the execution of the “instruction execution” process in its own unit to the lapse of the normal waiting time Two. It is determined whether or not to obtain the notification. If the STB cannot acquire from the ACT a notification of the completion of the execution of the “instruction execution” process from the time when the normal waiting time Two elapses after the completion of the execution of the “instruction execution” process in its own unit. , ACT is determined to be abnormal. When it is determined that an abnormality has occurred in ACT (first CPU unit 100A), STB (second CPU unit 100B) switches its own unit to ACT and continues operation.

§2. Configuration Example Next, the details of the first CPU unit 100A and the second CPU unit 100B whose outline has been described with reference to FIG. 2 will be described with reference to FIG.

FIG. 1 is a block diagram showing a main configuration of a PLC 10 including a first CPU unit 100A and a second CPU unit 100B CPU unit according to the first embodiment of the present invention. As exemplified in FIG. 1, the PLC 10 includes a first CPU unit 100A and a second CPU unit 100B that are duplicated in the PLC 10. Each of the first CPU unit 100A and the second CPU unit 100B is a functional unit that controls the control of the entire PLC 10.

The PLC 10 may further include a functional unit not shown in FIG. The PLC 10 further includes a power supply unit (not shown) that supplies power to the entire PLC 10 including the first CPU unit 100A and the second CPU unit 100B, for example. The PLC 10 also includes an unillustrated input unit for inputting a signal of a switch and a sensor attached to an appropriate position of a production device and an equipment device, an output unit for outputting a control signal to an actuator and the like, a communication unit for connecting to a communication network, and the like. It may include a functional unit.

As described above, each of the first CPU unit 100A and the second CPU unit 100B repeatedly executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order. In the I / O refresh processing, various input signals acquired by the input unit and the like are taken into the I / O memory of each CPU unit (IN refresh), and the processing result of the instruction execution processing is written in the I / O memory. Output (OUT refresh) to an output unit or the like. In other words, the I / O refresh processing is performed by cyclically performing “each of the first CPU unit 100A and the second CPU unit 100B” and “an external unit and an external device other than the first CPU unit 100A and the second CPU unit 100B”. Data exchange. In the instruction execution processing, various control signals output from the PLC 10 as a controller to a control target are generated. For example, based on a user program, a logical operation using an input signal taken into the I / O memory by IN refresh is performed. Is executed, and a control signal is generated.

In the PLC 10, the first CPU unit 100A and the second CPU unit 100B are duplicated in order to improve the safety and reliability of a control system controlled by the PLC 10, and both are connected by, for example, a bus between CPUs. If there is no abnormality in both the first CPU unit 100A and the second CPU unit 100B, execution of the same processing (each of self-diagnosis processing, instruction execution processing, and I / O refresh processing) is started at the same timing. For example, if there is no abnormality in both the first CPU unit 100A and the second CPU unit 100B, execution of the same user program using the same input signal is started at the same timing.

One of the first CPU unit 100A and the second CPU unit 100B is an active CPU unit (ACT), and the other is a standby CPU unit (STB). As described above, in this specification, an example will be described in which “the first CPU unit 100A is an ACT and the second CPU unit 100B is an STB”, but “the first CPU unit 100A is an STB and the second CPU unit 100B is an STB. ACT ".

The first CPU unit 100A, which is an ACT, actually performs cyclic processing, reads and writes data from and to a memory, and transmits and receives control data (I / O data) to and from an external I / O device or the like. And controls the control system controlled by the PLC 10. The second CPU unit 100B that is the STB executes the same user program as that executed by the first CPU unit 100A that is the ACT during standby (that is, while no abnormality occurs in the first CPU unit 100A that is the ACT). I do. However, the second CPU unit 100B, which is the STB, does not output the execution result (calculation execution result) of the executed user program to an external I / O device or the like. The second CPU unit 100B, which is an STB, receives processing results (calculation execution results and various input signals obtained by the first CPU unit 100A, which is an ACT) from the first CPU unit 100A, which is an ACT. Then, the second CPU unit 100B, which is the STB, updates the contents of the memory of the own unit based on the processing result and the like received from the first CPU unit 100A, which is the ACT. As a result, the identity of the contents of the memories of the second CPU unit 100B serving as the STB and the first CPU unit 100A serving as the ACT is secured.

When the first CPU unit 100A, which is ACT, fails, the second CPU unit 100B, which is STB, switches to the first CPU unit 100A, which is ACT, and performs operations such as actual control. By duplicating the first CPU unit 100A and the second CPU unit 100B in the PLC 10, even if the first CPU unit 100A that is the ACT fails, the entire PLC 10 can be continuously operated without immediately stopping. , Reliability is improved.

(Details of CPU unit)
As shown in FIG. 1, the PLC 10 includes, in addition to a first CPU unit 100A and a second CPU unit 100B that are duplicated in the PLC 10, a common register 200 that can execute writing and reading. To ensure the simplicity of the description, components that are not directly related to the present embodiment are omitted from the description and block diagrams. However, the PLC 10 may have the omitted configuration in accordance with the actual situation of implementation.

The common register 200 includes a first register 210 and a second register 220.

The first register 210 indicates, by the first CPU unit 100A, that the own unit (that is, the first CPU unit 100) executes a certain process (each of a self-diagnosis process, an instruction execution process, and an I / O refresh process). "Completed" is written. The information written to the first register 210 by the first CPU unit 100A is read by the second CPU unit 100B.

The second register 220 causes the second CPU unit 100 </ b> B to execute a process (each of the self-diagnosis process, the instruction execution process, and the I / O refresh process) performed by the own unit (that is, the second CPU unit 100 </ b> B). "Completed" is written. The information written to the second register 220 by the second CPU unit 100B is read by the first CPU unit 100A.

The first CPU unit 100A includes a capability acquisition unit 110A, a process execution unit 120A, a waiting time setting unit 160A, and a determination unit 170A as functional blocks in addition to the storage unit 130A. The storage unit 130A stores the other function table 140A and the own function table 150A.

The second CPU unit 100B includes a capability acquisition unit 110B, a process execution unit 120B, a waiting time setting unit 160B, and a determination unit 170B as functional blocks in addition to the storage unit 130B. The storage unit 130B stores the other function table 140B and the own function table 150B.

In the following, each of the capability acquiring unit 110A and the capability acquiring unit 110B is simply referred to as “the capability acquiring unit 110” unless it is necessary to particularly distinguish each of them. Similarly, the processing execution unit 120A and the processing execution unit 120B are simply referred to as “processing execution unit 120” when it is not necessary to particularly distinguish each of them. The storage unit 130A and the storage unit 130B are simply referred to as the “storage unit 130” when it is not necessary to particularly distinguish each of them. When it is not necessary to particularly distinguish each of the other function strength table 140A and the other function strength table 140B, they are simply referred to as “other function strength table 140”. When there is no need to particularly distinguish each of the self-function table 150A and the self-function table 150B, it is simply referred to as “self-function table 150”. When there is no need to particularly distinguish between the waiting time setting unit 160A and the waiting time setting unit 160B, they are simply referred to as “waiting time setting unit 160”. When it is not necessary to particularly distinguish each of the determination unit 170A and the determination unit 170B, they are simply referred to as “determination unit 170”.

The functional blocks such as the capability acquisition unit 110, the processing execution unit 120, the waiting time setting unit 160, and the determination unit 170 are, for example, a CPU (central processing unit), a ROM (read only memory), an NVRAM (non- This can be realized by reading a program stored in a storage device (storage unit 130) realized by Volatile @ random @ access @ memory or the like into a RAM (random @ access @ memory) or the like (not shown) and executing it.

(Details of functional blocks)
The capability acquisition unit 110 acquires information (“performance information”) indicating the performance Aby (processing capability) of the CPU unit of the other party to be duplicated with reference to the own function table 150 of the other CPU unit. The capability acquiring unit 110 stores the acquired performance information (other device performance information) of the other CPU unit in the other function capability table 140 of the own unit.

In particular, the capability acquisition unit 110 performs the “duplication process” illustrated in FIG. 2 once before the process execution unit 120 repeatedly executes the self-diagnosis process, the instruction execution process, and the I / O refresh process in this order. , The other device performance information is acquired.

FIG. 3 is a diagram illustrating a specific example of the process of “acquiring performance information indicating the performance Aby of the CPU unit of the other party to be duplexed” executed once in the “duplexing process”. As illustrated in FIG. 3, the capability acquiring unit 110A acquires performance information indicating the performance Aby of the second CPU unit 100B with reference to the function capability table 150B, and acquires the acquired performance information of the second CPU unit 100B (the other device). Performance information) is stored in the other function capability table 140A. In addition, the capability acquisition unit 110B acquires performance information indicating the performance Aby of the first CPU unit 100A with reference to the function capability table 150A, and acquires the acquired performance information (other device performance information) of the first CPU unit 100A. It is stored in the other function strength table 140B.

The processing execution unit 120 repeatedly executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order, and when the execution of each processing is completed, “the own unit has completed the execution of each processing”. Is written to the common register 200.

When the execution of each process is completed, the process execution unit 120 notifies the waiting time setting unit 160 and the determination unit 170 that “the unit has completed the execution of each process”. The process execution unit 120 sets the “execution time of each process (time from execution start to execution completion for each process)” to the waiting time setting unit 160 along with “the unit has completed execution of each process”. You may be notified. That is, the process execution unit 120 may measure the “execution time of each process” using the internal timer, and notify the waiting time setting unit 160 of the measured “execution time of each process”.

<Write of completion of execution of processing> When the execution of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing has been completed, the processing Is completed) in the common register 200. That is, the process execution unit 120A that has completed the execution of the self-diagnosis process writes, in the first register 210, a message that “the unit has completed execution of the self-diagnosis process” in the first register 210, and 120 writes into the second register 220 that “the unit has completed the execution of the self-diagnosis processing”. The processing execution unit 120A, which has completed the execution of the instruction execution process, writes, to the first register 210, that "the unit has completed the execution of the instruction execution process", and the processing execution unit 120B, which has completed the execution of the instruction execution process, , "The own unit has completed the execution of the instruction execution process" is written in the second register 220. The processing execution unit 120A, which has completed the execution of the I / O refresh processing, writes in the first register 210 that "the unit has completed the execution of the I / O refresh processing", and completes the execution of the I / O refresh processing. The executed processing unit 120B writes in the second register 220 that "the unit has completed the execution of the I / O refresh processing".

<Process Execution Start Timing> While the first CPU unit 100A and the second CPU unit 100B are duplicated, the process execution unit 120 executes each of the self-diagnosis process, the instruction execution process, and the I / O refresh process. Is started at the following timing. In other words, while it is not determined that an abnormality has occurred in each of the first CPU unit 100A and the second CPU unit 100B, the processing execution unit 120 executes each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. Is started at the following timing.

That is, the processing execution unit 120 performs each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in a synchronization check processing after completion of the previous processing by the first CPU unit 100A and the second CPU unit. It starts after the normality with 100B is confirmed.

Specifically, in the synchronization check processing after the completion of the execution of the self-diagnosis processing, the normality of the first CPU unit 100A and the second CPU unit 100B is confirmed, and then the processing execution unit 120 starts executing the instruction execution processing. . In the synchronization check process after the execution of the instruction execution process is completed, after the normality of the first CPU unit 100A and the second CPU unit 100B is confirmed, the process execution unit 120 starts executing the I / O refresh process. In the synchronization check processing after the execution of the I / O refresh processing is completed, the normality of the first CPU unit 100A and the second CPU unit 100B is confirmed, and then the processing execution unit 120 starts executing the self-diagnosis processing in the next cycle. I do.

The waiting time setting unit 160 acquires the other device performance information by referring to the other function capability table 140, and acquires the own device performance information by referring to the own function capability table 150. Further, the waiting time setting unit 160 acquires from the processing execution unit 120 that “the unit has completed the execution of each processing”. The waiting time setting unit 160 adds the message “the unit has started executing each process” obtained from the process execution unit 120 before acquiring the message “the unit has completed execution of each process”. , Calculate the execution time of each process. That is, the waiting time setting unit 160 calculates the time “the own unit has started execution of each process” measured by the internal timer and the time “the own unit has completed execution of each process” measured by the internal timer. The execution time of each process is calculated. The execution time of each process may be measured by the process execution unit 120 using an internal timer, and may be notified from the process execution unit 120 to the waiting time setting unit 160.

The waiting time setting unit 160 calculates a “waiting time Tw” for a synchronization check process for each process from the acquired other device performance information, own device performance information, and the execution time of each process, and calculates the calculated waiting time. The time Tw is notified to the determination unit 170. Specifically, the waiting time setting unit 160 uses the other device performance information, the own device performance information, and the execution time of each process to perform a “wait” for the synchronization check process for each process as follows. Time Tw ”is calculated.

That is, when the “performance Aby of the CPU unit of the other party to be duplicated” indicated in the performance information of the other device is higher than the “performance Abm of the own device” indicated in the performance information of the own device, the waiting time setting unit 160 sets the “normal Waiting time Two ”is referred to as“ waiting time Tw ”. Further, when the performance Aby of the CPU unit of the other party to be duplicated is equal to the performance Abm of the own unit, the waiting time setting unit 160 sets the “normal waiting time Two” to the “waiting time Tw”.

The “normal waiting time Two” is a period common to the first CPU unit 100A and the second CPU unit 100B whose length is determined in advance, and is set, for example, at the time of factory shipment of each unit and can be updated by the user. Period. The “normal waiting time Two” is a period set on the assumption that the performance Ab is equal between the first CPU unit 100A and the second CPU unit 100B.

If the performance Aby of the partner CPU unit to be duplexed is lower than the performance Abm of the own unit, the waiting time setting unit 160 executes each processing to a value obtained by dividing the performance Abm of the own unit by the performance Aby of the other CPU unit. The period multiplied by the time is referred to as an adjustment waiting time Ta. Then, the waiting time setting unit 160 sets the “period obtained by adding the adjustment waiting time Ta to the normal waiting time Two (that is,“ the normal waiting time Two + the adjustment waiting time Ta ”)” to the “waiting time Tw”.

The determination unit 170 determines, for the processing that has been completed by the processing execution unit 120 from the completion of execution of each processing by the processing execution unit 120 to the elapse of the waiting time Tw notified from the waiting time setting unit 160, the CPU of the other party. It is determined whether the unit has completed execution (synchronization check processing). For example, the determination unit 170 refers to the common register 200 at the time when the waiting time Tw has elapsed from the time “the own unit has completed the execution of each process”, and performs the duplexing for a certain process whose own unit has completed the execution. The execution of the other CPU unit is completed.

The determination unit 170 that has been notified of the “normal waiting time Two + the adjustment waiting time Ta” as the waiting time Tw executes the standby processing until the adjustment waiting time Ta elapses from the point of “the unit has completed execution of each process”. . Then, the determination unit 170 executes the synchronization check process after the completion of the execution of the standby process (that is, after the adjustment waiting time Ta has elapsed from the time when “the unit has completed execution of each process”). In other words, after the execution of the standby process is completed, the determination unit 170 can confirm that the execution of the process completed by the own unit is completed by the partner CPU unit before the normal waiting time Two elapses. ? In other words, the determination unit 170 determines whether the completion of the execution by the partner CPU unit can be confirmed for the processing completed by the own unit before the normal waiting time Two elapses from the completion of the execution of the standby processing. The “time when the execution of the standby process is completed” is “the time when the execution of a certain process that has been completed by the own unit is expected to be completed in the partner CPU unit”.

The determination unit 170, which has been notified of the “normal waiting time Two” as the waiting time Tw, immediately executes the synchronization check processing at the time of “the unit has completed execution of each processing”. That is, the determination unit 170 determines “whether it is possible to confirm that the execution of the processing that has been completed by the own unit is completed by the partner CPU unit before the normal waiting time Two elapses”. In other words, the determination unit 170 determines whether the execution completion of the own unit can be confirmed by the partner CPU unit before the normal waiting time Two elapses from the execution completion time of the own unit.

The determining unit 170A refers to the second register 220 of the common register 200, and determines whether or not there is a write to the effect that “the execution by the process execution unit 120B has been completed” for a certain process that has been completed by the process execution unit 120A. Confirm. If there is no write in the second register 220 that “the execution by the process execution unit 120B has been completed” for the certain process that has been completed by the process execution unit 120A, the determination unit 170A determines that an abnormality has occurred in the second CPU unit 100B. It is determined that an error has occurred.

The determination unit 170B refers to the first register 210 of the common register 200, and determines whether or not there is a write to the effect that “the execution by the process execution unit 120A has been completed” for a certain process that has been completed by the process execution unit 120B. Confirm. If there is no writing in the first register 210 that “the execution by the process execution unit 120A has been completed” for a certain process that has been completed by the process execution unit 120B, the determination unit 170B determines that the first CPU unit 100A has an error. It is determined that an error has occurred.

(Details of storage unit)
The storage unit 130 is a storage device that stores various data used by each of the first CPU unit 100A and the second CPU unit 100B. The storage unit 130 stores (1) a control program, (2) an OS program, and (3) each of the first CPU unit 100A and the second CPU unit 100B that are executed by the first CPU unit 100A and the second CPU unit 100B. An application program for executing various functions provided therein, and (4) various data to be read when the application program is executed may be temporarily stored. The above data (1) to (4) are, for example, ROM (read only memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), HDD (Hard Disc Drive), etc. Stored in a non-volatile storage device. Each of the first CPU unit 100A and the second CPU unit 100B may include a temporary storage unit (not shown). The temporary storage unit is a so-called working memory that temporarily stores data used for calculation, calculation results, and the like in the course of various processes executed by each of the first CPU unit 100A and the second CPU unit 100B. Access Memory). Which data is stored in which storage device is appropriately determined based on the purpose of use, convenience, cost, physical restrictions, and the like of each of the first CPU unit 100A and the second CPU unit 100B. The storage unit 130 further stores another function strength table 140 and own function strength table 150.

(4) The other-function capability table 140 stores other-device performance information that is information indicating the performance Aby of the CPU unit of the other party to be duplicated. As described with reference to FIG. 3, the capability acquiring unit 110 stores the other device performance information acquired with reference to the own function table 150 of the CPU unit of the other party to be duplicated in the other function table 140 of the own unit. Store.

The own function table 150 stores own device performance information, which is information indicating the performance Abm of the own unit. For example, “How much performance Ab (processing capacity) of the own unit as compared with the reference CPU unit” is stored. Is provided, own device performance information is stored. The own device performance information is stored in the own function table 150 when each of the first CPU unit 100A and the second CPU unit 100B is shipped from the factory, for example.

(Arrangement of CPU unit)
Each of the first CPU unit 100A and the second CPU unit 100B whose configuration has been described with reference to FIG. 1 is arranged as follows in order to facilitate understanding. That is, each of the first CPU unit 100A and the second CPU unit 100B is a duplicated CPU unit in the PLC 10 (controller), and includes the waiting time setting unit 160 (setting unit) and the determination unit 170. The waiting time setting unit 160 sets the waiting time Tw in consideration of the ratio between the performance Abm (processing capacity) of the own unit and the performance Aby of the CPU unit of the other party to be duplicated. If the determination unit 170 cannot confirm that the execution of the process by the other CPU unit has been completed before the elapse of the waiting time Tw set by the waiting time setting unit 160 from the time when the execution of the process in the own unit is completed, It is determined that an abnormality has occurred in the CPU unit.

According to the above configuration, each of the first CPU unit 100A and the second CPU unit 100B sets the waiting time Tw in consideration of the ratio of the performance Ab (processing capacity) between the own CPU unit and the partner CPU unit. Then, each of the first CPU unit 100A and the second CPU unit 100B uses the set waiting time Tw to determine the synchronization between its own unit and the partner CPU unit (that is, the coincidence of the executed processes).

For example, when the performance Ab of the other CPU unit is higher than that of the own CPU unit (that is, the execution speed of the process is faster), each of the first CPU unit 100A and the second CPU unit 100B is determined in advance as the waiting time Tw. The normal waiting time Two is set. Further, when the performance Ab is equal between the partner CPU unit and the own unit, each of the first CPU unit 100A and the second CPU unit 100B sets a predetermined “normal waiting time Two” as the waiting time Tw.

If the performance Ab of the other CPU unit is higher than that of the own unit, the other CPU unit should have already completed execution of the certain process when the own unit completes execution of a certain process. If the performance Ab is equal between the partner CPU unit and the own unit, the partner CPU unit should complete the execution of the certain process when the own unit completes the execution of a certain process.

Therefore, even when the performance of the other CPU unit is higher than that of the own CPU unit, each of the first CPU unit 100A and the second CPU unit 100B sets the normal waiting time Two as the waiting time Tw, thereby enabling the other CPU unit to set the normal waiting time Two. It is possible to accurately determine whether an abnormality has occurred in the CPU unit.

For example, when the performance Ab of the partner CPU unit is lower than that of the own CPU unit, each of the first CPU unit 100A and the second CPU unit 100B sets “the normal waiting time Two plus the adjustment waiting time Ta as the waiting time Tw”. Period "is set. The adjustment waiting time Ta is set in consideration of a difference in performance Ab between the own unit and the partner CPU unit. For example, the “difference between the time when the execution of the process in the own unit is completed and the time when the execution of the process in the partner CPU unit is expected to be completed” is the adjustment waiting time Ta.

If the performance Ab of the other CPU unit is lower than that of the own unit, the other CPU unit has not completed execution of the certain process at the time when the own unit has completed execution of a certain process. Therefore, each of the first CPU unit 100A and the second CPU unit 100B waits until “the time when the execution of the processing by the other CPU unit is expected to be completed (execution completion expected time)”. Then, each of the first CPU unit 100A and the second CPU unit 100B determines whether the completion of the execution of the processing by the partner CPU unit can be confirmed before the normal waiting time Two elapses from the predicted completion time of the execution. That is, each of the first CPU unit 100A and the second CPU unit 100B waits for a period from the completion of the execution of the processing in the own unit until the “period in which the adjustment wait time Ta is added to the normal wait time Two” elapses. It is determined whether the CPU unit can confirm the completion of the processing.

Therefore, even when the other CPU unit has a lower performance Ab than the own CPU unit, each of the first CPU unit 100A and the second CPU unit 100B sets the “adjustment waiting time Ta to the normal waiting time Twoo” as the waiting time Tw. By setting the “added period”, the above determination can be accurately performed.

As described above, each of the first CPU unit 100A and the second CPU unit 100B has a difference in performance Ab between its own unit and the partner CPU unit even when the performance Ab of the own unit and the partner CPU unit do not match. In consideration of the above, there is an effect that an appropriate waiting time Tw can be set. That is, each of the first CPU unit 100A and the second CPU unit 100B performs the synchronization check processing without providing an unnecessary waiting time Tw in consideration of the difference in performance Ab between the CPU unit of the other party and the own unit. This has the effect that it can be performed accurately.

In each of the first CPU unit 100A and the second CPU unit 100B, the processing (processing to be subjected to the synchronization check processing) includes a self-diagnosis processing, an instruction execution processing, and an I / O refresh processing. The self-diagnosis process is a process for diagnosing whether there is any abnormality in the hardware of the own unit. The instruction execution process is a process of generating a signal for controlling “an external device and an external unit other than the partner CPU unit”. The I / O refresh process is a process of exchanging data with “an external device and an external unit other than the partner CPU unit”. The waiting time setting unit 160 sets a waiting time Tw for each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. The determination unit 170 performs the determination, that is, the synchronization check process, for each of the self-diagnosis process, the instruction execution process, and the I / O refresh process.

Each of the first CPU unit 100A and the second CPU unit 100B synchronizes the self-diagnosis process, the instruction execution process, and the I / O refresh process between the self-unit and the partner CPU unit (that is, the process that has been completed). Match).

Each of the first CPU unit 100A and the second CPU unit 100B determines the synchronization between its own unit and the partner CPU unit at the timing of completion of execution of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. It has the effect of being able to.

(1) Each of the first CPU unit 100A and the second CPU unit 100B executes the duplex processing once before repeatedly executing the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order. Each of the first CPU unit 100A and the second CPU unit 100B acquires the performance Aby of the partner CPU unit from the partner CPU unit in the duplex processing.

According to the above configuration, each of the first CPU unit 100A and the second CPU unit 100B repeats the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order with the performance Aby of the partner CPU unit. Acquire once before executing. Each of the first CPU unit 100A and the second CPU unit 100B takes into account the ratio of the acquired performance Aby of the partner CPU unit to the performance Abm of its own unit, and the waiting time used for the determination for each of the processes. Set Tw.

Each of the first CPU unit 100A and the second CPU unit 100B takes into account the performance Aby of the partner CPU unit acquired before repeatedly executing each of the processes, and the waiting time used for the determination of each process. This has an effect that Tw can be set.

§3. Operation Example Each of the first CPU unit 100A and the second CPU unit 100B executes the following processing as shown in FIG. That is, each of the first CPU unit 100A and the second CPU unit 100B repeatedly executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order. Specifically, the processing execution unit 120 of each unit repeatedly executes the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order. Before each of the first CPU unit 100A and the second CPU unit 100B (particularly, the capability acquisition unit 110 of each unit) performs the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order. The duplication processing is executed once. Each of the first CPU unit 100A and the second CPU unit 100B acquires other device performance information indicating the performance Aby of the partner CPU unit to be duplexed in the duplexing process.

When each unit (particularly, the processing execution unit 120 of each unit) completes the execution of each processing of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, the message “the own unit has completed the execution of each processing. Is written in the common register 200.

Each unit (particularly, the waiting time setting unit 160 of each unit) performs a synchronization check process for each process from the other device performance information, the own device performance information, and the execution time of each process completed by the own unit. Is set.

Specifically, the waiting time setting unit 160 calculates the “adjustment waiting time Ta calculated in consideration of the ratio between the performance Abm of the own unit and the performance Aby of the CPU unit of the other party to be duplicated” for each process. . Then, the waiting time setting unit 160 adds a period obtained by adding the “adjusted waiting time Ta calculated for each process” to the “normal waiting time Two of each process” for the synchronization check process of each process. This is set as “waiting time Tw”.

場合 When “Abm / Aby” is equal to or less than “1”, the waiting time setting unit 160 sets “adjustment waiting time Ta = 0” for each process. When “Abm / Aby” is larger than “1”, the waiting time setting unit 160 sets the “adjustment waiting time Ta” of each process to a value obtained by multiplying the execution time of each process by “Abm / Aby”.

Each unit (particularly, the determination unit 170 of each unit) executes a synchronization check process after completion of each of the self-diagnosis process, the instruction execution process, and the I / O refresh process by the own unit. That is, the determination unit 170 refers to the common register 200, and executes the processing completed by the own unit by the partner CPU unit from the time when the execution of each processing by the own unit is completed to the time when the waiting time Tw elapses. Determine if it is complete.

The synchronization check process is a process of mutually monitoring the statuses of the CPU units of the other party to be duplicated. Specifically, the synchronization check process is a process of confirming (determining) whether or not the execution of the process has been completed in the CPU unit of the other party which has been completed in the own unit.

(4) In the synchronization check process, if synchronization cannot be confirmed, that is, if the completion of execution of the process completed by the own unit cannot be confirmed by the partner CPU unit, the duplication between the first CPU unit 100A and the second CPU unit 100B is eliminated. Then, for example, when the STB determines that an abnormality has occurred in the ACT, its own unit continues to operate instead of the ACT.

When the synchronization can be confirmed in the synchronization check processing, each unit (particularly, the processing execution unit 120 of each unit) performs the next processing after the “processing in which execution completion by the own unit and the other CPU unit has been confirmed in the synchronization check processing”. Start running. The synchronization check process is specifically executed as described below.

That is, when completing the execution of a certain process, the process execution unit 120A stores, in the first register 210 of the common register 200, a message indicating that “the own unit (that is, the process execution unit 120A) has completed the execution of a certain process”. Write. By reading the first register 210, the determination unit 170B recognizes that the first CPU unit 100A has completed execution of a certain process. Further, when completing the execution of a certain process, the process execution unit 120B stores, in the second register 220 of the common register 200, a message indicating that “the own unit (that is, the process execution unit 120B) has completed the execution of a certain process”. Write. By reading the second register 220, the determination unit 170A recognizes that the second CPU unit 100B has completed execution of a certain process. When the determination unit 170A and the determination unit 170B each recognize "the completion of execution of a certain process by the partner CPU unit", the process execution unit 120A and the process execution unit 120B respectively perform the next process of the certain process. Start running.

The “processing executed by each of the first CPU unit 100A and the second CPU unit 100B” described above can be summarized as follows. That is, “the processing executed by each of the first CPU unit 100A and the second CPU unit 100B” is a control method of a CPU unit that is duplicated in the PLC 10 (controller), and includes a setting step and a determination step. In the setting step, the waiting time Tw is set in consideration of the ratio between the performance Abm of the own unit and the performance Aby of the CPU unit to be duplicated. The determination step includes, when the completion of the processing in the partner CPU unit cannot be confirmed from the time when the execution of the processing in the own unit is completed to the time when the waiting time Tw set in the setting step elapses, to the partner CPU unit. It is determined that an abnormality has occurred.

According to the above method, the control method uses the waiting time Tw set in consideration of the ratio of the performance Ab between the own unit and the other party's CPU unit to synchronize the own unit and the other party's CPU unit ( That is, it is determined whether the processes have been completed.

For example, when the performance Ab of the other CPU unit is higher than that of the own CPU unit (that is, the execution speed of the process is faster), the control method sets a predetermined “normal waiting time Two” as the waiting time Tw. Set. When the performance Ab is equal between the other CPU unit and the own unit, the control method sets a predetermined “normal waiting time Two” as the waiting time Tw.

If the performance Ab of the other CPU unit is higher than that of the own unit, the other CPU unit should have already completed the execution of the certain process when the own unit completes the execution of a certain process. If the performance Ab is equal between the partner CPU unit and the own unit, the partner CPU unit should complete the execution of the certain process when the own unit completes the execution of a certain process.

For example, when the performance Ab of the other CPU unit is lower than that of the own CPU unit (that is, the execution speed of the process is slower), the control method sets the waiting time Tw as “the difference between the performance Ab and the normal waiting time Two. Is set in consideration of the adjustment waiting time Ta. Specifically, the difference between the time when the execution of the process in the own unit is completed and the time when the execution of the process in the partner CPU unit is expected to be completed is defined as the adjustment waiting time Ta.

If the performance Ab of the other CPU unit is lower than that of the own unit, the other CPU unit has not completed execution of the certain process at the time when the own unit has completed execution of a certain process. Therefore, the control method waits until “the time at which the execution of the processing in the partner CPU unit is expected to be completed”, and then the processing in the partner CPU unit until the “normal waiting time Two” elapses. It is determined whether the execution completion of can be confirmed. That is, in the control method, the execution of the process in the partner CPU unit is performed until the “period in which the adjustment wait time Ta is added to the normal wait time Two” from the completion of the execution of the process in the own unit. Determine whether completion can be confirmed.

Therefore, even when the performance Ab of the partner CPU unit is lower than that of the own CPU unit, the control method sets the “period obtained by adding the adjustment waiting time Ta to the normal waiting time Two” as the waiting time Tw. Thus, the above determination can be accurately performed.

As described above, even when the performance Ab does not match between the own unit and the partner CPU unit, the control method can set an appropriate waiting time in consideration of the difference in the performance Ab between the own unit and the partner CPU unit. This has an effect that Tw can be set. That is, the control method can accurately perform the synchronization check processing without providing an unnecessary waiting time Tw in consideration of the difference in performance Ab between the CPU unit of the other party and the own unit to be duplicated. It works.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. In order to ensure the simplicity of the description, only the configuration (procedure of processing and contents of processing) different from the first embodiment will be described. That is, the configuration and the like described in the first embodiment can all be included in the present embodiment. The definitions of the terms described in the first embodiment are the same.

In the first embodiment, the performance Aby of the partner CPU unit used by the first CPU unit 100A and the second CPU unit 100B that are duplicated in the PLC 10 to set the “waiting time Tw” of the own unit is one type. .

On the other hand, the first CPU unit 300A and the second CPU unit 300B, which are duplicated in the PLC 20 according to the present embodiment, have a plurality of performance Aby of the partner CPU unit used for setting the “waiting time Tw” of the own unit. It is. Hereinafter, the details will be described.

FIG. 5 is a diagram showing an example of a hardware configuration for realizing each of the first CPU unit 300A and the second CPU unit 300B. That is, each of the first CPU unit 300A and the second CPU unit 300B is realized using the memory 410, the CPU 420 (microcomputer), and the dedicated LSI (Large Scale Integration) 430. The dedicated LSI is also called “ASIC (Application Specific Integrated Circuit)”, and an FPGA (Field Programmable Gate Array) may be used instead of the dedicated LSI.

Each of first CPU unit 300A and second CPU unit 300B repeatedly executes a self-diagnosis process, an instruction execution process, and an I / O refresh process in the same order as each of first CPU unit 100A and second CPU unit 100B. . For example, the self-diagnosis processing is mainly executed by the CPU 420, the instruction execution processing is mainly executed by the dedicated LSI 430, and the I / O refresh processing is mainly executed by the CPU 420 via the dedicated LSI 430.

When the hardware mainly executing each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing is different, the performance Ab may be different between the first CPU unit 300A and the second CPU unit 300B for each processing. . For example, the CPU 420 of the first CPU unit 300A may have higher performance Ab than the CPU 420 of the second CPU unit 300B, and the dedicated LSI 430 of the first CPU unit 300A may have lower performance Ab than the dedicated LSI 430 of the second CPU unit 300B. In this case, the first CPU unit 300A completes the execution of the self-diagnosis processing earlier than the second CPU unit 300B, and the instruction execution processing of the first CPU unit 300A completes later than the second CPU unit 300B.

Therefore, each of the first CPU unit 300A and the second CPU unit 300B grasps the performance Ab of its own unit and the partner CPU unit for each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing that are repeatedly executed. . Each of the first CPU unit 300A and the second CPU unit 300B sets the “waiting time Tw” at the time of the synchronization check process for each process, using the performance Ab of the own unit and the partner CPU unit related to each process. I do. Hereinafter, the details will be described.

(Details of CPU unit)
FIG. 4 is a block diagram showing a main configuration of PLC 20 including first CPU unit 300A and second CPU unit 300B. Like the PLC 10, the PLC 20 may include a power supply unit, an input unit, an output unit, and a functional unit (not shown) such as a communication unit.

Each of the first CPU unit 300A and the second CPU unit 300B is a functional unit that controls the entire control of the PLC 10, like the first CPU unit 100A and the second CPU unit 100B. The first CPU unit 300A and the second CPU unit 300B are duplicated in the PLC 20. That is, one of the first CPU unit 300A and the second CPU unit 300B serves as an active CPU unit (ACT), and the other serves as a standby CPU unit (STB), and monitors the state of each other. If the STB determines that an abnormality has occurred in the ACT during the synchronization check processing, the STB switches its own unit to the ACT instead of the CPU unit that has been the ACT, and continues operation. In the present embodiment, an example in which “the first CPU unit 300A is ACT and the second CPU unit 300B is STB” will be described, but “the first CPU unit 300A is STB and the second CPU unit 300B is ACT”. The same applies to the case.

As shown in FIG. 4, the PLC 20 includes, in addition to the first CPU unit 300A and the second CPU unit 300B that are duplicated in the PLC 20, a common register 200 that can execute writing and reading. Since the common register 200 has already been described, the details will be omitted here.

(4) In order to ensure the simplicity of the description, components not directly related to the present embodiment are omitted from the description and the block diagram. However, the PLC 10 may have the omitted configuration in accordance with the actual situation of implementation.

The first CPU unit 300A includes a capability acquisition unit 310A, a process execution unit 120A, a waiting time setting unit 360A, and a determination unit 370A as functional blocks in addition to the storage unit 330A. The storage unit 330A stores the other function table 340A and the own function table 350A.

The waiting time setting unit 360A includes a first waiting time setting unit 361A, a second waiting time setting unit 362A, and a third waiting time setting unit 363A, and the determining unit 370A includes a first determining unit 371A, a second determining unit 372A, A third determination unit 373A is included. The other function table 340A includes a first other function table 341A, a second other function table 342A, and a third other function table 343A. The own function table 350A includes a first function table 351A, a second function table 352A, and a third function table 353A.

The second CPU unit 300B includes a capability acquisition unit 310B, a process execution unit 120B, a waiting time setting unit 360B, and a determination unit 370B as functional blocks in addition to the storage unit 330B. The storage unit 330B stores the other function table 340B and the own function table 350B.

The waiting time setting unit 360B includes a first waiting time setting unit 361B, a second waiting time setting unit 362B, and a third waiting time setting unit 363B, and the determining unit 370B includes a first determining unit 371B, a second determining unit 372B, A third determination unit 373B is included. The other function table 340B includes a first other function table 341B, a second other function table 342B, and a third other function table 343B. The own function table 350B includes a first function table 351B, a second function table 352B, and a third function table 353B.

4 Similarly to the first CPU unit 100A and the second CPU unit 100B in the first embodiment, the first CPU unit 300A and the second CPU unit 300B shown in FIG. 4 have the same configuration. When it is necessary to particularly distinguish the configuration commonly provided by each of the first CPU unit 300A and the second CPU unit 300B, "A" is used for the configuration of the first CPU unit 300A, and the configuration of the second CPU unit 300B. In this case, “B” is added. When there is no particular need to distinguish which of the configurations the first CPU unit 300A and the second CPU unit 300B have in common, the suffix “A” or “B” is abbreviated.

The functional blocks of the capability acquisition unit 310, the processing execution unit 120, the waiting time setting unit 360, the determination unit 370, and the like include, for example, a CPU (central processing unit), a ROM (read only memory), an NVRAM (non- This can be realized by reading a program stored in a storage device (storage unit 330) realized by Volatile (random access memory) or the like into a RAM (random access memory) (not shown) and executing the program.

(Details of functional blocks)
The capability acquisition unit 310 calculates the performance Aby (processing capability) of the duplicated CPU unit in each of the self-diagnosis process, the instruction execution process, and the I / O refresh process repeatedly executed by the process execution unit 120. Information ("performance information"). Specifically, the capability acquisition unit 310 stores the performance information of the partner CPU unit relating to each of the self-diagnosis process, the instruction execution process, and the I / O refresh process in the self-functionality table 350 of the partner CPU unit. Get by reference. The capability acquisition unit 310 transmits the acquired “performance information (other device performance information) of the partner CPU unit related to each of the self-diagnosis process, the instruction execution process, and the I / O refresh process” to another function of the own unit. Stored in the force table 340.

In particular, the capability acquisition unit 310 performs the “duplication process” illustrated in FIG. 6 once before the process execution unit 120 repeatedly executes the self-diagnosis process, the instruction execution process, and the I / O refresh process in this order. In, the other device performance information related to each process is acquired.

The capability acquisition unit 310 refers to the first self-functionality table 351 of the CPU unit of the other party to be duplicated, and refers to the performance information indicating the performance Aby of the CPU unit of the other party to be duplicated in the self-diagnosis processing (for self-diagnosis). Other device performance information) ". The capability acquiring unit 310 stores the acquired other device performance information for self-diagnosis in the first other function capability table 341 of the unit.

The capability acquisition unit 310 refers to the second self-functionality table 352 of the partner CPU unit to be duplicated and refers to “performance information indicating the performance Aby of the duplicated partner CPU unit related to the instruction execution process (for instruction execution). Other device performance information) ". The capability acquiring unit 310 stores the acquired instruction execution other device performance information in the second other function capability table 342 of the own unit.

The capability acquiring unit 310 refers to the third self-functionality table 353 of the CPU unit of the other party to be duplicated, and reads the performance information (I relating to the I / O refresh processing indicating the performance Aby of the CPU unit of the other party to be duplicated. / O refresh other device performance information) ". The capability acquiring unit 310 stores the acquired other device performance information for I / O refresh in the third other function capability table 343 of the unit.

FIG. 7 is a diagram illustrating a specific example of the process of “acquiring performance information indicating the performance Aby of the CPU unit of the other party to be duplexed” executed once in the “duplexing process”. As illustrated in FIG. 7, the capability acquisition unit 310A stores “performance information indicating the performance Aby of the second CPU unit 300B related to the self-diagnosis processing (self-diagnosis other device performance information)” in the first CPU unit 300B. It is acquired with reference to the own function table 351B. The capability acquisition unit 310A stores the acquired self-diagnosis other-device performance information in the first other-function capability table 341A of the own unit.

The ability acquisition unit 310B refers to “performance information indicating the performance Aby of the first CPU unit 300A relating to the self-diagnosis processing (other-machine performance information for self-diagnosis)” and the first self-function capability table 351A of the first CPU unit 300A. And get. The capability acquiring unit 310B stores the acquired self-diagnosis other-device performance information in the first other-function capability table 341B of the own unit.

The capability acquisition unit 310A refers to “performance information indicating the performance Aby of the second CPU unit 300B related to the instruction execution process (instruction execution other device performance information)” and the second own function table 352B of the second CPU unit 300B. And get. The capability acquiring unit 310A stores the acquired instruction execution other device performance information in the second other function capability table 342A of the own unit.

The capability acquisition unit 310B refers to “performance information indicating the performance Aby of the first CPU unit 300A related to the instruction execution process (performance information of other device for instruction execution)” and the second own function table 352A of the first CPU unit 300A. And get. The capability acquiring unit 310B stores the acquired instruction execution other device performance information in the second other function capability table 342B of the own unit.

The capability acquisition unit 310A stores the “performance information indicating the performance Aby of the second CPU unit 300B related to the I / O refresh process (the performance information of the other device for the I / O refresh process)” in the third function of the second CPU unit 300B. It is acquired with reference to the force table 353B. The capability acquiring unit 310A stores the acquired other device performance information for I / O refresh processing in the third other function capability table 343A of the own unit.

The capability acquisition unit 310B stores the “performance information indicating the performance Aby of the first CPU unit 300A related to the I / O refresh process (I / O refresh process other device performance information)” in the third self-function of the first CPU unit 300A. It is acquired with reference to the force table 353A. The capability acquiring unit 310B stores the acquired other device performance information for I / O refresh processing in the third other function capability table 343B of its own unit.

As described in the first embodiment, the process execution unit 120 repeatedly executes the self-diagnosis process, the instruction execution process, and the I / O refresh process in this order. Has completed execution of each process "in the common register 200.

When the execution of each process is completed, the process execution unit 120 notifies the waiting time setting unit 360 and the determination unit 370 that “the unit has completed the execution of each process”. The process execution unit 120 sets the “execution time of each process (the time from the start of execution to the completion of execution for each process)” in the waiting time setting unit 360 together with “the unit has completed execution of each process” in the waiting time setting unit 360. You may be notified. That is, the process execution unit 120 may measure the “execution time of each process” using the internal timer, and notify the waiting time setting unit 360 of the measured “execution time of each process”.

The waiting time setting unit 360 acquires the other device performance information by referring to the other function capability table 340, and acquires the own device performance information by referring to the own function capability table 350. Further, the waiting time setting unit 360 acquires from the processing executing unit 120 that “the unit has completed execution of each processing”. The waiting time setting unit 360 adds the message “the own unit has started executing each process” acquired from the process execution unit 120 before acquiring the message “the own unit has completed execution of each process”. , Calculate the execution time of each process. That is, the waiting time setting unit 360 calculates the time “the own unit has started execution of each process” measured by the internal timer and the time “the own unit has completed execution of each process” measured by the internal timer. The execution time of each process is calculated. The execution time of each process may be measured by the process execution unit 120 using an internal timer, and notified from the process execution unit 120 to the waiting time setting unit 360.

The waiting time setting unit 360 calculates a “waiting time Tw” for a synchronization check process for each process from the acquired other device performance information, own device performance information, and the execution time of each process, and calculates the calculated waiting time. The determination unit 370 is notified of the time Tw. Specifically, the waiting time setting unit 360 uses the other device performance information, the own device performance information, and the execution time of each process to execute the “waiting” for the synchronization check process for each process as follows. Time Tw ”is calculated.

That is, when the “performance Aby of the CPU unit of the other party to be duplicated” indicated in the performance information of the other device is higher than the “performance Abm of the own unit” indicated in the performance information of the own device, the waiting time setting unit 360 sets the “normal Waiting time Two ”is referred to as“ waiting time Tw ”. When the performance Aby of the CPU unit of the other party to be duplicated is equal to the performance Abm of the own unit, the waiting time setting unit 360 sets the “normal waiting time Two” to the “waiting time Tw”.

The “normal waiting time Two” is a period common to the first CPU unit 300A and the second CPU unit 300B whose length is determined in advance, and is set, for example, at the time of factory shipment of each unit and can be updated by the user. Period. The “normal waiting time Two” is that the performance Ab (particularly, the performance Ab related to each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing) is equal between the first CPU unit 300A and the second CPU unit 300B. Is a period set based on the assumption of

If the performance Aby of the partner CPU unit to be duplexed is lower than the performance Abm of the own unit, the waiting time setting unit 360 executes each process by dividing the performance Abm of the own unit by the performance Aby of the partner CPU unit. The period multiplied by the time is referred to as “adjustment waiting time Ta”. When the performance Aby of the CPU unit of the other party to be duplicated is lower than the performance Abm of the own unit, the waiting time setting unit 360 sets the “period obtained by adding the adjustment waiting time Ta to the normal waiting time Two (that is,“ the normal waiting time Two + adjustment waiting time Ta ”)” is referred to as “waiting time Tw”.

<“Wait time” for synchronization check processing related to “self-diagnosis processing”> “Wait time Tw” for synchronization check processing related to “self-diagnosis processing” is set by the first waiting time setting unit 361. .

The first waiting time setting unit 361 acquires the self-diagnosis other-device performance information by referring to the first other-function capability table 341, and refers to the first self-function capability table 351 to acquire the self-diagnosis own-device performance information. get. Further, the first waiting time setting unit 361 sends a message from the processing execution unit 120 indicating that “the own unit has started executing the self-diagnosis process” and that “the own unit has completed execution of the self-diagnosis process”. The execution time of the self-diagnosis processing is calculated from the notification.

The first waiting time setting unit 361 synchronizes the self-diagnosis process with the acquired self-diagnosis other-device performance information and self-diagnosis self-device performance information and the “execution time of the self-diagnosis process” calculated. The “waiting time Tw” for the check processing is calculated.

Specifically, the first waiting time setting unit 361 determines the ratio of “the performance Abm of the own unit related to the self-diagnosis processing” to “the performance Aby of the duplicated CPU unit related to the self-diagnosis processing”. Is calculated, the “adjustment waiting time Ta related to the self-diagnosis processing” is calculated. Then, the first waiting time setting unit 361 sets a period in which the calculated “adjustment waiting time Ta related to the self-diagnosis processing” is added to the “normal waiting time Two related to the self-diagnosis processing” for the self-diagnosis processing. Is set as the “waiting time Tw” for the synchronization check processing of the above. When “Abm / Aby” is equal to or less than “1”, the first waiting time setting unit 361 sets “adjustment waiting time Ta related to the self-diagnosis processing” to “0”. When “Abm / Aby” is greater than “1”, the first waiting time setting unit 361 sets “adjustment waiting time Ta related to the self-diagnosis processing” to “Abm / Aby” as the execution time of the self-diagnosis processing of the own unit. / Aby ”).

The first waiting time setting unit 361 notifies the determining unit 370 of the “waiting time Tw for the synchronization check process for the self-diagnosis process” calculated by the above method.

<“Wait time” for synchronization check processing related to “instruction execution processing”> “Wait time Tw” for synchronization check processing related to “instruction execution processing” is set by the second waiting time setting unit 362. .

The second waiting time setting unit 362 acquires the instruction execution other device performance information by referring to the second other function table 342, and refers to the second own function table 352 to acquire the instruction execution own device performance information. get. In addition, the second waiting time setting unit 362 receives a message from the processing execution unit 120 indicating that “the own unit has started execution of the instruction execution process” and that “the own unit has completed execution of the instruction execution process”. From the notification, the execution time of the instruction execution processing is calculated.

The second waiting time setting unit 362 synchronizes the instruction execution process with the acquired instruction execution other device performance information and the instruction execution own device performance information, and the “execution time of the instruction execution process” calculated. The “waiting time Tw” for the check processing is calculated.

Specifically, the second waiting time setting unit 362 calculates the ratio of “the performance Abm of the own unit related to the instruction execution process” to “the performance Aby of the other CPU unit to be duplicated related to the instruction execution process”. Is calculated, the “adjustment waiting time Ta related to the instruction execution process” is calculated. Then, the second waiting time setting unit 362 sets a period in which the calculated “adjustment waiting time Ta related to the instruction execution processing” is added to the “normal waiting time Two related to the instruction execution processing” for the instruction execution processing. Is set as the “waiting time Tw” for the synchronization check processing of the above. When “Abm / Aby” is equal to or less than “1”, the second waiting time setting unit 362 sets “adjustment waiting time Ta related to the instruction execution process” to “0”. When “Abm / Aby” is greater than “1”, the second waiting time setting unit 362 sets “adjustment waiting time Ta related to the instruction execution processing” to “Abm / Aby” as “the execution time of the instruction execution processing of the own unit”. / Aby ”).

The first wait time setting unit 361 notifies the determination unit 370 of the “wait time Tw for the synchronization check process for the instruction execution process” calculated by the above method.

<“Wait time” for synchronization check processing related to “I / O refresh processing”> “Wait time Tw” for synchronization check processing related to “I / O refresh processing” is the third wait time setting unit 363 Is set by

The third waiting time setting unit 363 acquires the other device performance information for I / O refresh with reference to the third other function table 343, and refers to the third own function table 353 to acquire the I / O refresh self-function. Get machine performance information. Further, the third waiting time setting unit 363 sends a message from the processing execution unit 120 stating that “the own unit has started executing the I / O refresh processing” and “the own unit has completed the execution of the I / O refresh processing”. Then, the execution time of the I / O refresh processing is calculated from the notification that "I did".

The third waiting time setting unit 363 calculates the I / O refresh other device performance information, the I / O refresh own device performance information, and the calculated “I / O refresh processing execution time”. The “waiting time Tw” for the synchronization check processing for the I / O refresh processing is calculated.

Specifically, the third waiting time setting unit 363 includes “the performance Abm of the own unit related to the I / O refresh processing” and “the performance Aby of the other CPU unit to be duplexed related to the I / O refresh processing”. , The "adjustment wait time Ta related to the I / O refresh processing" is calculated. Then, the third waiting time setting unit 363 adds a period in which the calculated “adjustment waiting time Ta related to the I / O refresh processing” is added to the “normal waiting time Two related to the I / O refresh processing”, This is set as a "waiting time Tw" for the synchronization check processing for the I / O refresh processing. When “Abm / Aby” is equal to or less than “1”, the third waiting time setting unit 363 sets “adjustment waiting time Ta related to I / O refresh processing” to “0”. When “Abm / Aby” is greater than “1”, the third waiting time setting unit 363 sets “adjustment waiting time Ta related to I / O refresh processing” to “execution time of I / O refresh processing of the own unit”. Is multiplied by “Abm / Aby” ”.

The third wait time setting unit 363 notifies the determination unit 370 of the “wait time Tw” for the synchronization check process for the I / O refresh process calculated by the above method.

The determination unit 370 executes the synchronization check process after the elapse of the waiting time Tw notified from the waiting time setting unit 360 from the point of “the own unit has completed execution of each process”. For example, the determination unit 370 refers to the common register 200 at the time when the waiting time Tw has elapsed from the time “the own unit has completed the execution of each process”, and performs the duplexing for a certain process whose own unit has completed the execution. The execution of the other CPU unit is completed.

The determination unit 370 notified of the “normal waiting time Two + adjustment waiting time Ta” as the waiting time Tw executes the standby processing from the time “the own unit has completed execution of each process” until the adjustment waiting time Ta is reached. . Then, the determination unit 370 executes the synchronization check process after the execution of the standby process is completed (that is, after the adjustment waiting time Ta has elapsed from the time when “the own unit has completed the execution of each process”). That is, after the execution of the standby process is completed, the determination unit 370 can confirm that the execution of the process completed by the own unit is completed by the partner CPU unit before the normal waiting time Two elapses. ? In other words, the determination unit 370 determines whether the completion of the execution by the partner CPU unit can be confirmed for the processing that has been completed by the own unit before the normal waiting time Two elapses from the completion of the execution of the standby processing.

The determination unit 370, which has been notified of the “normal waiting time Two” as the waiting time Tw, immediately executes the synchronization check processing at the time of “the own unit has completed execution of each processing”. That is, the determination unit 370 determines whether or not it is possible to confirm that the CPU unit of the other party has completed the execution of the process completed by the own unit before the normal waiting time Two elapses. In other words, the determination unit 370 determines whether the execution completion of the own unit can be confirmed by the partner CPU unit before the normal waiting time Two elapses from the execution completion time of the own unit.

<Synchronization Check Processing According to “Self-diagnosis Processing”> The first determination unit 371 executes synchronization check processing according to “Self-diagnosis processing”. In other words, the first determination unit 371 determines that the “waiting time Tw for the self-diagnosis processing” notified from the first waiting time setting unit 361 elapses from the completion of the self-diagnosis processing of the own unit. , It is checked whether the other CPU unit has completed the execution of the self-diagnosis processing. If the “waiting time Tw” for the self-diagnosis process has not elapsed before the completion of execution of the self-diagnosis process by the partner CPU unit cannot be confirmed, the first determination unit 371 determines the CPU of the partner device. It is determined that an error has occurred in the unit.

<Synchronization Check Process Related to “Instruction Execution Process”> The second determination unit 372 executes a synchronization check process related to “instruction execution process”. That is, the second determination unit 372 determines whether the “wait time Tw” for the instruction execution process notified from the second wait time setting unit 362 elapses from the completion of the execution of the instruction execution process of the own unit. , It is checked whether the partner CPU unit has completed the execution of the instruction execution process. If it is not possible to confirm that “the other CPU unit has completed the execution of the instruction execution process” before the “wait time Tw” for the instruction execution process has elapsed, the second determination unit 372 determines It is determined that an error has occurred in the unit.

<Synchronization Check Process Related to “I / O Refresh Process”> The third determination unit 373 executes a synchronization check process related to “I / O refresh process”. That is, the third determination unit 373 sets the “waiting time Tw” for the I / O refreshing process notified from the third waiting time setting unit 363 from the completion of the execution of the I / O refreshing process of the own unit. By the elapse of time, it is checked whether "the other CPU unit has completed the execution of the I / O refresh processing". If it is not possible to confirm that “the other CPU unit has completed the execution of the instruction execution process” before the “waiting time Tw” for the I / O refresh process has elapsed, the third determination unit 373 determines It is determined that an abnormality has occurred in the CPU unit.

The determination unit 370A refers to the second register 220 of the common register 200, and determines whether or not there is a write indicating that “the execution by the process execution unit 120B has been completed” for a certain process that has been completed by the process execution unit 120A. Confirm. If there is no write in the second register 220 that “the execution by the process execution unit 120B has been completed” for a certain process that has been completed by the process execution unit 120A, the determination unit 370A determines that an abnormality has occurred in the second CPU unit 300B. It is determined that an error has occurred.

The determination unit 370B refers to the first register 210 of the common register 200, and determines whether or not there is a write indicating that “the execution by the process execution unit 120A has been completed” for a certain process that has been completed by the process execution unit 120B. Confirm. If there is no write in the first register 210 that “the execution by the process execution unit 120A has been completed” for a certain process that has been completed by the process execution unit 120B, the determination unit 370B determines that an abnormality has occurred in the first CPU unit 300A. It is determined that an error has occurred.

(Details of storage unit)
The storage unit 330 is a storage device that stores various data used by each of the first CPU unit 300A and the second CPU unit 300B. The storage unit 330 stores (1) a control program, (2) an OS program, and (3) each of the first CPU unit 300A and the second CPU unit 300B executed by the first CPU unit 300A and the second CPU unit 300B. An application program for executing various functions provided therein, and (4) various data to be read when the application program is executed may be temporarily stored. The above data (1) to (4) are, for example, ROM (read only memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), HDD (Hard Disc Drive), etc. Stored in a non-volatile storage device. Each of the first CPU unit 300A and the second CPU unit 300B may include a temporary storage unit (not shown). The temporary storage unit is a so-called working memory that temporarily stores data used for calculation, calculation results, and the like in the course of various processes executed by each of the first CPU unit 300A and the second CPU unit 300B. Access Memory). Which data is stored in which storage device is appropriately determined based on the purpose of use, convenience, cost, physical restrictions, and the like of each of the first CPU unit 300A and the second CPU unit 300B. The storage unit 330 further stores another function table 340 and own function table 350.

(4) The other function capability table 340 stores other device performance information that is information indicating the performance Aby (processing capability) of the CPU unit of the other party to be duplicated. As described with reference to FIG. 3, the capability acquiring unit 310 stores the other device performance information acquired with reference to the own function table 350 of the CPU unit of the other party to be duplicated in the other function table 340 of the own unit. Store.

In the first other function table 341, “the performance indicating the performance Aby of the partner CPU unit to be duplicated, which is related to the self-diagnosis processing and stored in the first self function table 351 of the partner CPU unit to be duplicated. “Information” is stored by the capability acquisition unit 310.

In the second other function table 342, the “performance indicating the performance Aby of the partner CPU unit to be duplicated, which is related to the instruction execution processing and stored in the second own function table 352 of the partner CPU unit to be duplicated. “Information” is stored by the capability acquisition unit 310.

In the third other function table 343, “the performance Aby of the partner CPU unit to be duplicated, which is related to the I / O refresh processing and stored in the third own function table 353 of the partner CPU unit to be duplicated, is stored. The “performance information shown” is stored by the capability acquisition unit 310.

The own function table 350 stores own device performance information that is information indicating the performance Abm (processing capacity) of the own unit. For example, “How much performance (the own unit is compared with the reference CPU unit) Own device performance information is stored. The own device performance information is stored in the own function table 350 when each of the first CPU unit 300A and the second CPU unit 300B is shipped from the factory, for example.

The first self-functionality table 351 includes performance information indicating the performance Abm of the self-unit related to the self-diagnosis processing (particularly, relative performance Abm with respect to “performance Abb of the reference CPU unit related to the self-diagnosis processing”). ) "Is stored.

The second self-functionality table 352 includes “Performance information indicating the performance Abm of the own unit related to the instruction execution process (particularly, relative performance Abm with respect to“ performance Abb of the reference CPU unit related to the instruction execution process ”). ) "Is stored.

The third self-functionality table 353 includes performance information indicating the performance Abm of the own unit related to the I / O refresh processing (particularly, relative to the “performance Abb of the reference CPU unit related to the I / O refresh processing”). Performance Abm) "is stored.

(Arrangement of CPU unit)
Each of the first CPU unit 300A and the second CPU unit 300B, whose configurations have been described with reference to FIG. 4 and the like, will be arranged as follows in order to facilitate understanding. That is, each of the first CPU unit 300A and the second CPU unit 300B is a duplicated CPU unit in the PLC 20 (controller), similarly to each of the first CPU unit 100A and the second CPU unit 100B. Each of the first CPU unit 300A and the second CPU unit 300B includes a waiting time setting unit 360 (setting unit) and a determination unit 370. The waiting time setting unit 360 sets the waiting time Tw in consideration of the ratio between the performance Abm (processing capacity) of the own unit and the performance Aby of the CPU unit of the other party to be duplicated. If the determination unit 370 cannot confirm that the execution of the process by the other CPU unit has been completed before the elapse of the waiting time Tw set by the waiting time setting unit 360 from the time when the execution of the process in the own unit is completed, It is determined that an abnormality has occurred in the CPU unit.

Therefore, each of the first CPU unit 300A and the second CPU unit 300B, like each of the first CPU unit 100A and the second CPU unit 100B, takes an appropriate wait time in consideration of the difference in performance Ab between the own unit and the partner CPU unit. Time Tw can be set. That is, each of the first CPU unit 300A and the second CPU unit 300B performs the synchronization check processing without providing an unnecessary waiting time Tw in consideration of the difference in the performance Ab between the CPU unit of the other party and the own unit. Can be done accurately.

In each of the first CPU unit 300A and the second CPU unit 300B, the processing (processing to be subjected to the synchronization check processing) includes a self-diagnosis processing, an instruction execution processing, and an I / O refresh processing. The waiting time setting unit 360 (specifically, each of the first waiting time setting unit 361, the second waiting time setting unit 362, and the third waiting time setting unit 363) includes a self-diagnosis process, an instruction execution process, , I / O refresh processing, a wait time Tw is set. The determination unit 370 (specifically, each of the first determination unit 371, the second determination unit 372, and the third determination unit 373) includes a self-diagnosis process, an instruction execution process, and an I / O refresh process. , The above-mentioned determination, that is, the synchronization check process is executed.

Each of the first CPU unit 300A and the second CPU unit 300B determines the synchronization between its own unit and the partner CPU unit at the timing of completion of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. be able to.

(1) Each of the first CPU unit 300A and the second CPU unit 300B executes the duplexing process once before repeatedly executing the self-diagnosis process, the instruction execution process, and the I / O refresh process in this order. Each of the first CPU unit 300A and the second CPU unit 300B acquires the performance Aby of the partner CPU unit from the partner CPU unit in the duplex processing.

Each of the first CPU unit 300A and the second CPU unit 300B takes into account the performance Aby of the partner CPU unit that has been acquired before repeatedly executing each of the processes, and the waiting time used for the determination of each of the processes. This has an effect that Tw can be set.

In each of the first CPU unit 300A and the second CPU unit 300B, the waiting time setting unit 360 sets the waiting time Tw of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing as follows. That is, the waiting time setting unit 360 considers the ratio between the performance Abm of the own unit and the performance Aby of the CPU unit of the partner, which are related to the execution of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. Then, the waiting time Tw of each process is set. Specifically, the first waiting time setting unit 361 performs the synchronization check processing for the self-diagnosis processing in consideration of the ratio between the performance Abm of the own unit and the performance Aby of the partner CPU unit in the self-diagnosis processing. Is set for the waiting time Tw. The second wait time setting unit 362 is a wait time for the synchronization check processing of the instruction execution processing, taking into account the ratio of the performance Abm of the own unit and the performance Aby of the partner CPU unit in the instruction execution processing. Tw is set. The third waiting time setting unit 363 performs the synchronization check processing for the I / O refresh processing in consideration of the ratio between the performance Abm of the own unit and the performance Aby of the partner CPU unit related to the I / O refresh processing. Waiting time Tw is set.

Each of the first CPU unit 300A and the second CPU unit 300B considers a difference in performance Ab between the own unit and the partner CPU unit in each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. , A waiting time Tw for each process is set.

Therefore, each of the first CPU unit 100A and the second CPU unit 100B can set the waiting time Tw of each process according to the performance Ab of each of the own unit and the partner CPU unit related to each process. To play.

(motion)
FIG. 6 is a diagram illustrating an outline of processing executed by each of first CPU unit 300A and second CPU unit 300B. The processing executed by each of first CPU unit 300A and second CPU unit 300B shown in FIG. 6 is different from the processing executed by each of first CPU unit 100A and second CPU unit 100B shown in FIG. 2 in the following points. .

That is, each of the first CPU unit 300A and the second CPU unit 300B grasps the performance Ab of the own unit and the partner CPU unit for each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing that are repeatedly executed. . Each of the first CPU unit 300A and the second CPU unit 300B sets the “waiting time Tw” at the time of the synchronization check process for each process, using the performance Ab of the own unit and the partner CPU unit related to each process. I do. Each of the first CPU unit 300A and the second CPU unit 300B indicates that the execution of each process by the partner CPU unit has been completed until the “waiting time Tw” for each process has elapsed since the completion of the execution of each process by the own unit. Is determined.

In other respects, “the processing executed by each of the first CPU unit 300A and the second CPU unit 300B” is the same as “the processing executed by each of the first CPU unit 100A and the second CPU unit 100B”.

That is, “the processing executed by each of the first CPU unit 300A and the second CPU unit 300B” is a control method of a CPU unit that is duplicated in the PLC 20 (controller), and includes a setting step and a determination step. In the setting step, the waiting time Tw is set in consideration of the ratio between the performance Abm of the own unit and the performance Aby of the CPU unit to be duplicated. The determination step includes, when the completion of the processing in the partner CPU unit cannot be confirmed from the time when the execution of the processing in the own unit is completed to the time when the waiting time Tw set in the setting step elapses, to the partner CPU unit. It is determined that an abnormality has occurred.

Therefore, “the processing executed by each of the first CPU unit 300A and the second CPU unit 300B” indicates that even if the performance Ab does not match between the own CPU unit and the other CPU unit, the processing between the own CPU unit and the other CPU unit may not be performed. There is an effect that an appropriate waiting time Tw can be set in consideration of the difference in the performance Ab. That is, “the processing executed by each of the first CPU unit 300A and the second CPU unit 300B” does not provide an unnecessary waiting time Tw in consideration of the difference in the performance Ab between the CPU unit of the other party to be duplicated and the own unit. In addition, there is an effect that the synchronization check process can be performed accurately.

§4. Modified Example So far, an example has been described in which the first CPU unit 100A and the second CPU unit 100B (or the first CPU unit 300A and the second CPU unit 300B) perform a synchronization check process using the common register 200. . However, the method of using the common register 200 is only an example of a method for implementing the synchronization check process. The synchronization check processing is performed by, for example, a method in which the first CPU unit 100A and the second CPU unit 100B (or the first CPU unit 300A and the second CPU unit 300B) check synchronization while communicating with each other through serial ports. It may be realized. The first CPU unit 100A and the second CPU unit 100B (or the first CPU unit 300A and the second CPU unit 300B) communicate with each other through their serial ports and confirm the execution completion of the processing of the partner CPU unit with each other. May be.

Further, an example in which the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing are repeatedly executed in this order, and the synchronization check processing related to each of these processings is executed after the execution of each of these processings is completed. I have explained. However, in addition to the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, another processing may be repeatedly executed similarly to the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. Good. In this case, the synchronization check processing is also performed after the completion of the other processing.

For example, in addition to the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, transmission and reception of signals to and from a communication network different from the communication network in which signals are transmitted and received in the I / O refresh processing are performed. Other communication processes "may be repeatedly executed. That is, the self-diagnosis processing, the instruction execution processing, the I / O refresh processing, and other communication processing are repeatedly executed in this order, and after the execution of each of these processings is completed, the synchronization check processing relating to each of these processings is executed. May be done.

[Example of software implementation]
The control blocks of each of the first CPU unit 100A, the second CPU unit 100B, the first CPU unit 300A, and the second CPU unit 300B (particularly, the capability acquisition unit 110, the process execution unit 120, the waiting time setting unit 160, the determination unit 170, The acquiring unit 310, the waiting time setting unit 360, and the determining unit 370) may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or may be a CPU (CenTral Processing Unit). And may be realized by software.

In the latter case, each of the first CPU unit 100A, the second CPU unit 100B, the first CPU unit 300A, and the second CPU unit 300B is a CPU that executes instructions of a program that is software for realizing each function, the above-described program and various data. Is provided with a ROM (Read Only Memory) or a storage device (these are referred to as “recording media”) recorded readable by a computer (or CPU), a RAM (Random Access Memory) for expanding the program, and the like. Then, the object of the present invention is achieved when the computer (or CPU) reads the program from the recording medium and executes the program. As the recording medium, a “temporary tangible medium”, for example, a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. Further, the program may be supplied to the computer via an arbitrary transmission medium (a communication network, a broadcast wave, or the like) capable of transmitting the program. Note that the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the program is embodied by electronic transmission.

(Appendix)
A CPU unit according to one embodiment of the present invention is a CPU unit that is duplexed in a controller, and takes a waiting time into consideration in consideration of a ratio between the processing capability of its own unit and the processing capability of a partner CPU unit that is duplicated. A setting unit to be set, and if the completion of the execution of the process in the CPU unit of the other party cannot be confirmed before the elapse of the waiting time set by the setting unit from the time when the execution of the process in the own unit is completed, And a determination unit that determines that an abnormality has occurred in the CPU unit.

According to the above configuration, the CPU unit uses the waiting time set in consideration of the processing capacity ratio between the own unit and the partner CPU unit, and performs communication between the own unit and the partner CPU unit. The synchronization (that is, the coincidence of the executed processing) is determined.

For example, when the other CPU unit has higher performance than its own unit (that is, the execution speed of the process is faster), the CPU unit sets a predetermined “normal waiting time” as the waiting time. I do. If the performance Ab is equal between the other CPU unit and the own unit, the control method sets a predetermined “normal waiting time” as the waiting time Tw.

If the partner CPU unit has higher performance than the own unit, the partner CPU unit should have already completed execution of the certain process when the own unit completes execution of a certain process. . If the performance Ab is equal between the partner CPU unit and the own unit, the partner CPU unit should complete the execution of the certain process when the own unit completes the execution of a certain process.

Therefore, even when the performance of the other CPU unit is higher than that of the own unit, the CPU unit sets the “normal waiting time” as the waiting time, so that the abnormality of the other CPU unit occurs. It can be accurately determined whether or not the occurrence has occurred.

For example, when the performance of the other CPU unit is lower than that of the own CPU unit (that is, the execution speed of the process is slower), the CPU unit considers the performance difference in the normal waiting time as the waiting time. Period after adding the adjusted waiting time ”. Specifically, the "difference between the time when the execution of the process in the own unit is completed and the time when the execution of the process in the partner CPU unit is expected to be completed" is defined as the adjustment waiting time.

(4) When the performance of the partner CPU unit is lower than that of the own unit, the partner CPU unit has not completed execution of the certain process at the time when the self unit has completed execution of a certain process. Therefore, the CPU unit waits until “the time point at which the execution of the processing in the other CPU unit is expected to be completed”, and then the CPU unit in the other CPU unit until “normal waiting time” elapses. It is determined whether the execution completion of the process can be confirmed. In other words, the CPU unit performs the processing in the partner CPU unit from the time when the execution of the processing in the own unit is completed to the time when “the period in which the adjustment waiting time is added to the normal waiting time” elapses. Determine whether execution completion can be confirmed.

Therefore, even when the performance of the other CPU unit is lower than that of the own unit, the CPU unit sets “the period in which the adjustment waiting time is added to the normal waiting time” as the waiting time. Thus, the above determination can be accurately performed.

As described above, the CPU unit considers the difference in the processing capability between the own unit and the counterpart CPU unit, even when the processing capabilities of the own unit and the counterpart CPU unit do not match. This has an effect that an appropriate waiting time can be set. That is, the CPU unit can accurately perform the synchronization check processing without providing an unnecessary waiting time in consideration of the difference in processing capacity between the CPU unit of the other party and the own unit to be duplicated. To play.

In the CPU unit according to one aspect of the present invention, the processing includes: a self-diagnosis processing for diagnosing whether there is an abnormality in hardware of the own unit; Processing, and an I / O refresh processing for exchanging data with an external device other than the partner CPU unit. The setting unit performs the self-diagnosis processing, the instruction execution processing, and the I / O processing. The waiting time may be set for each of the refresh processing, and the determination unit may perform the determination for each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing.

According to the above configuration, the CPU unit synchronizes the self-diagnosis process, the instruction execution process, and the I / O refresh process between the self-unit and the counterpart CPU unit (that is, execution completion). Is determined).

Therefore, the CPU unit may determine the synchronization between the self unit and the partner CPU unit at the timing of completion of execution of each of the self-diagnosis process, the instruction execution process, and the I / O refresh process. It has the effect of being able to do it.

Before repeatedly executing the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order, the CPU unit according to an aspect of the present invention may increase the processing capability of the partner CPU unit. The duplication processing obtained from the partner CPU unit may be executed once.

According to the configuration, the CPU unit determines the processing capability of the partner CPU unit before repeatedly executing the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order. Acquire once. Then, the CPU unit sets the waiting time used for the determination for each process in consideration of the ratio of the acquired processing capability of the partner CPU unit to the processing capability of the own unit.

Therefore, the CPU unit sets the waiting time used for the determination on each process in consideration of the processing capability of the partner CPU unit acquired in advance before repeatedly executing each process. The effect is that it can be done.

In the CPU unit according to an aspect of the present invention, the setting unit may determine the waiting time of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing by the self-diagnosis processing, the instruction execution processing. The setting may be made in consideration of the ratio between the processing capacity of the own unit and the processing capacity of the CPU unit of the other party, relating to the execution of the processing and the I / O refresh processing.

According to the above configuration, the CPU unit is configured to execute the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing, respectively, in the processing capability of the own unit and the partner CPU unit. The waiting time for each process is set in consideration of the difference.

Therefore, the CPU unit sets the waiting time of each of the self-diagnosis process, the instruction execution process, and the I / O refresh process to the processing capability of the own unit and the counterpart CPU unit for each process. It can be set according to the effect.

The control method according to one embodiment of the present invention is a control method for a CPU unit that is duplicated in a controller, and in consideration of a ratio between the processing capability of the own unit and the processing capability of the other CPU unit that is duplicated, The completion of the execution of the process by the partner CPU unit cannot be confirmed from the setting step of setting the waiting time and the completion of the execution of the process in the own unit until the elapse of the waiting time set in the setting step And a determining step of determining that an abnormality has occurred in the partner CPU unit.

According to the above method, the control method uses the waiting time set in consideration of the processing capacity ratio between the own unit and the partner CPU unit, and uses the waiting time between the own unit and the partner CPU unit. The synchronization (that is, the coincidence of the executed processing) is determined.

For example, if the partner CPU unit has higher performance than the own unit (that is, the execution speed of the process is faster), the control method sets a predetermined “normal waiting time” as the waiting time. I do. If the performance Ab is equal between the other CPU unit and the own unit, the control method sets a predetermined “normal waiting time” as the waiting time Tw.

Therefore, even when the other CPU unit has higher performance than the own CPU unit, the control method sets the “normal waiting time” as the waiting time so that the other CPU unit has no abnormality. It can be accurately determined whether or not the occurrence has occurred.

For example, when the partner CPU unit has lower performance than the own CPU unit (that is, the execution speed of the process is slower), the control method sets “the normal waiting time to the performance difference in consideration of the performance difference” as the waiting time. Period after adding the adjusted waiting time ”. Specifically, the "difference between the time when the execution of the process in the own unit is completed and the time when the execution of the process in the partner CPU unit is expected to be completed" is defined as the adjustment waiting time.

(4) When the performance of the partner CPU unit is lower than that of the own unit, the partner CPU unit has not completed execution of the certain process at the time when the self unit completes execution of a certain process. Therefore, the control method waits until “the time point at which the execution of the processing in the other party's CPU unit is expected to be completed”, and then, until the “normal waiting time” elapses, It is determined whether the execution completion of the process can be confirmed. In other words, the control method performs the processing of the processing in the partner CPU unit from the time when the execution of the processing in the own unit is completed to the time when “the period in which the adjustment waiting time is added to the normal waiting time” elapses. Determine whether execution completion can be confirmed.

Therefore, even when the performance of the other CPU unit is lower than that of the own CPU unit, the control method may set “a period obtained by adding the adjustment waiting time to the normal waiting time” as the waiting time. Thus, the above determination can be accurately performed.

As described above, the control method considers the difference in the processing capabilities between the own unit and the counterpart CPU unit even when the processing capacities of the own unit and the counterpart CPU unit do not match. This has an effect that an appropriate waiting time can be set. That is, the control method can accurately perform the synchronization check processing without providing an unnecessary waiting time in consideration of the difference in processing capacity between the CPU unit of the other party and the own unit to be duplicated. To play.

The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

10 PLC
20 PLC
100A first CPU unit (CPU unit)
100B 2nd CPU unit (CPU unit)
300A first CPU unit (CPU unit)
300B 2nd CPU unit (CPU unit)
160 Time setting part (setting part)
360 time setting part (setting part)
170 Judgment unit 370 Judgment unit Ab Performance (processing capacity)
Tw wait time

Claims

A CPU unit duplicated in the controller,
A setting unit for setting a waiting time in consideration of a ratio between the processing capacity of the own unit and the processing capacity of the CPU unit of the other party to be duplicated;
If it is not possible to confirm the completion of the execution of the processing by the other CPU unit from the time when the execution of the processing in the own unit is completed and before the elapse of the waiting time set by the setting unit, an abnormality occurs in the other CPU unit. A determining unit that determines that the occurrence has occurred;
CPU unit comprising:
The processing includes a self-diagnosis processing for diagnosing whether there is any abnormality in the hardware of the own unit, an instruction execution processing for generating a signal for controlling an external device other than the counterpart CPU unit, and an instruction execution processing other than the counterpart CPU unit. Including an I / O refresh process for exchanging data with an external device,
The setting unit sets the waiting time for each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing,
The CPU unit according to claim 1, wherein the determination unit performs the determination for each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing.
Before repeatedly executing the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing in this order, a duplex processing for acquiring the processing capacity of the partner CPU unit from the partner CPU unit is performed. 3. The CPU unit according to claim 2, wherein the CPU unit is executed once.
The setting unit may determine the waiting time of each of the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing by the self-diagnosis processing, the instruction execution processing, and the I / O refresh processing. 4. The CPU unit according to claim 2, wherein the CPU unit is set in consideration of a ratio between a processing capability of the own unit and a processing capability of the partner CPU unit in each execution.
A method for controlling a CPU unit that is duplicated in a controller,
A setting step of setting a waiting time in consideration of a ratio between the processing capacity of the own unit and the processing capacity of the CPU unit of the other party to be duplicated;
If it is not possible to confirm the completion of the execution of the processing by the other CPU unit from the time when the execution of the processing in the own unit is completed to the time when the waiting time set in the setting step elapses, the other CPU unit may fail. A determining step of determining that an error has occurred;
Control method including:
An information processing program for causing a computer to function as the CPU unit according to any one of claims 1 to 4, wherein the information processing program causes the computer to function as each of the units.
A computer-readable recording medium storing the information processing program according to claim 6.