CN112534411A

CN112534411A - CPU unit, control method for CPU unit, information processing program, and recording medium

Info

Publication number: CN112534411A
Application number: CN201980051961.6A
Authority: CN
Inventors: 桶田英男
Original assignee: Omron Corp
Current assignee: Omron Corp
Priority date: 2018-09-25
Filing date: 2019-09-17
Publication date: 2021-03-19
Also published as: JP2020052550A; WO2020066737A1; JP7028124B2

Abstract

Even if the processing capacities of the CPU units duplexed in the PLC are different from each other, erroneous determination regarding synchronization can be prevented. The first CPU unit (100A) sets a wait time (Tw) for the synchronization check process in consideration of a ratio of the performance (Abm) of the own unit to the performance (Aby) of the second CPU unit (100B).

Description

CPU unit, control method for CPU unit, information processing program, and recording medium

Technical Field

The present invention relates to a Central Processing Unit (CPU) Unit or the like that is duplexed in a controller.

Background

Conventionally, a configuration is known in which a CPU unit is duplexed in a Programmable Logic Controller (PLC) in order to improve the safety, reliability, and the like of a system. For example, patent document 1 below discloses a structure in which: before the start of the duplex operation, the CPU unit of the execution system acquires the unit version (unit version) of the CPU unit of the standby system, compares the unit version with the function version stored and held by the CPU unit, and judges that the duplex operation is possible if the unit version is greater than or equal to the function version. Hereinafter, a conventional duplexing of the CPU unit in the PLC will be described with reference to fig. 8 and 9.

Fig. 8 is a diagram for explaining an outline of a conventional process of a CPU unit duplexed in a PLC. As illustrated in fig. 8, the CPU units duplexed in the PLC each sequentially and repeatedly perform the self-diagnosis process, the command execution process, and the I/O refresh process. The period from when the I/O refresh process is executed until when the next I/O refresh process is executed is also referred to as "1 cycle (1 cycle)". That is, in the PLC, the duplexed CPU units each execute the self-diagnosis process, the command execution process, and the I/O refresh process in sequence in "1 cycle (1 cycle)". The period required for "1 cycle" (i.e., the period from the execution of the I/O refresh process to the execution of the next I/O refresh) is also referred to as "cycle time".

The self-diagnosis process is a process of diagnosing whether or not the hardware of the self unit is operating normally, particularly, whether or not there is an abnormality in the memory, the hard disk, or the like. The command execution process is a process of executing a user program or the like, and is a process of generating data output in the I/O refresh process of the current cycle by performing various operations using data acquired in the I/O refresh process executed in the previous cycle. The I/O refresh processing is processing for executing data exchange with an external device and an external unit other than the duplexed counterpart CPU unit, and is processing for outputting data generated in the previous command execution processing and acquiring data used in the command execution processing of the next cycle.

One of the CPU units duplexed in the PLC is an execution system, and the other is a Standby System (STB), and the states of the duplexed CPU units are confirmed. When the CPU unit of the execution system is turned off, the CPU unit of the standby system switches to the CPU unit of the execution system that is turned off and continues the operation. Hereinafter, a CPU unit serving as an execution system may be simply referred to as "ACT", and a CPU unit serving as a standby system may be simply referred to as "STB".

In order to smoothly switch from the ACT to the STB when the ACT is turned off, the ACT and the STB are synchronized in the middle of the internal processing of each CPU unit as shown in fig. 8. That is, the ACT and the STB confirm that the duplex counterpart unit has not been abnormal at the timing when the self-diagnosis process, the command execution process, and the I/O refresh process are executed in the self unit. The "confirmation processing that no abnormality occurs in the duplexed counterpart unit" performed at the timing when the self-diagnosis processing, the command execution processing, and the I/O refresh processing have been completed in the self-unit is also referred to as "synchronization check processing".

By synchronizing the CPU units in the middle of the internal processing, the cycles of the CPU units (more precisely, the start times of the internal processing of the CPU units) do not deviate, and the duplexed CPU units can execute the same processing at the same timing. The ACT and the STB each execute the synchronization check process at the execution completion time point of the self-diagnosis process, the command execution process, and the I/O refresh process, and start the execution of the next process after the synchronization is confirmed (i.e., the other unit is not abnormal). Therefore, the ACT and the STB can start the execution of the self-diagnosis process, the command execution process, and the I/O refresh process at the same timing.

Basically, in the synchronization check process, the ACT and the STB monitor (in other words, confirm) the state of each other, and if the ACT is abnormally stopped, the STB continues the operation instead of the ACT that is abnormally stopped.

Here, assume a case where "the ACT or the STB cannot detect an abnormality of a synchronization target (i.e., a duplexed counterpart CPU unit) (particularly, the ACT cannot detect an abnormality of the STB)", and the ACT and the STB each execute a synchronization check process as follows. That is, when the ACT and the STB fail to acquire the response of the CPU unit of the other party within a predetermined period of time in each synchronization check process, it is determined that "the duplex CPU unit of the other party has an abnormality (that is, a synchronization error has occurred)". Specifically, in each of the ACT and the STB, when a notification indicating that the execution of the corresponding process has been completed cannot be acquired from the other CPU unit within the determination period in each synchronization check process, it is determined that "an abnormality has occurred in the duplex other CPU unit".

When it is determined that "an abnormality occurs in the duplexed CPU units", the ACT and the STB each execute a process of "duplexed release". By "de-duplexing", the ACT and the STB prevent "the cycle time becomes extremely long by maintaining synchronization with the CPU unit of the partner in which the abnormality has occurred". If duplexing is not canceled, that is, if "execution of next processing is not started until it can be confirmed that the counterpart unit is not abnormal", when the counterpart CPU unit is abnormal, it is not possible to confirm that the counterpart unit is not abnormal. Therefore, the execution of the next process cannot be started, and the cycle time becomes extremely long.

Fig. 9 is a diagram illustrating details of the synchronization check processing executed at the execution completion time point of each of the self-diagnosis processing, the command execution processing, and the I/O refresh processing. As described above, in the synchronization check process, the ACT and the STB each check whether or not a notification indicating that "the execution of the corresponding process has been completed" has been acquired from the CPU unit of the other party within the determination period.

The synchronization check process can be realized by, for example, providing registers (common registers) in the PLC, which enable the CPU units to read and write with each other, inside or outside the CPU units (i.e., ACT and STB) that are duplexed. Each CPU unit writes a word "the unit has completed execution of processing" to the shared register at a time point when the processing up to the synchronization check processing has completed, that is, at a time point when the self-diagnosis processing, the command execution processing, and the I/O refresh processing have completed their respective execution. Each CPU unit confirms that the other CPU unit has completed execution of the processing by reading the meaning of "the own unit has completed execution of the processing" written in the shared register by the other CPU unit.

That is, as illustrated in fig. 9, when the CPU unit 99P completes the processing, that is, when the execution of the processing is completed, the case where the processing is completed (that is, the meaning of "the own unit has completed the execution of the processing") is written into the REG1 of the common register 98. The CPU unit 99Q recognizes that the CPU unit 99P has completed the processing by reading out the REG 1. When the CPU unit 99Q completes the processing, that is, when the execution of the processing is completed, the case where the processing is completed (that is, the meaning of "the own unit has completed the execution of the processing") is written into the REG2 of the common register 98. The CPU unit 99P recognizes that the CPU unit 99Q has completed the processing by reading out the REG 2. After the CPU unit 99P and the CPU unit 99Q recognize each other that the processing is completed, the CPU unit 99P and the CPU unit 99Q respectively shift to the next processing.

When the synchronization check processing using the common register 98 is employed, the counterpart CPU unit does not write the "execution of the processing by its own unit" to the common register 98 when the counterpart CPU unit has an abnormality. Therefore, after waiting for a predetermined period from the time when the CPU unit completes the execution of the processing, the CPU unit determines whether or not the CPU unit on the other side writes "the unit has completed the execution of the processing" into the shared register 98. For example, if the "execution of the process by the CPU unit 99P is completed" is not written to the REG2 even if a predetermined period has elapsed from the time when the CPU unit 99P completes the execution of the process, the CPU unit 99P determines that an abnormality has occurred in the CPU unit 99Q. Even if a predetermined period of time has elapsed since the CPU unit 99Q completed the execution of the process, the CPU unit 99Q determines that an abnormality has occurred in the CPU unit 99P when the "execution of the process by the unit itself has been completed" is not written into the REG 1. In the following description, the predetermined period from the time when the CPU unit completes the execution of the process to the time when the CPU unit determines whether or not the CPU unit on the other side writes the "execution of the process completed by the CPU unit" will also be referred to as "waiting time".

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 2005-122716 "

Disclosure of Invention

Problems to be solved by the invention

In the conventional technique described above, it is assumed that the hardware of the CPU units duplexed in the PLC is substantially the same, that is, both have substantially the same processing capability, and therefore there is a problem that the difference in the processing capability between both is not assumed.

Conventionally, on the premise that the processing capabilities of the duplexed CPU units are substantially the same, each CPU unit determines an abnormality of the other CPU unit after a "wait time" common to the duplexed CPU units has elapsed from the time when the CPU unit completes execution of processing.

The reason why the duplex CPU units in the related art perform the synchronization check process using the common "waiting time" is as follows. That is, on the premise that the processing capabilities of the duplexed CPU units are the same, the time points at which the duplexed CPU units complete the execution of the processing should be at substantially the same timing. In other words, on the premise that the processing capabilities of the own unit and the duplexed counterpart CPU unit are the same, the time point at which the own unit completes the execution of the processing and the time point at which the counterpart CPU unit completes the execution of the processing should be at substantially the same timing. Therefore, in each of the duplexed CPU units, the "waiting time" used for determining the abnormality of the counterpart CPU unit, that is, used for the synchronization check processing has conventionally been a period which is common to the duplexed CPU units and has a fixed length.

However, the CPU unit is often used for a long period of time of about 20 years or longer, for example, and during this period, the CPU unit may be significantly updated (rebuilt) due to, for example, a stoppage of production of parts used for the CPU unit. Also, for example, consider: when hardware of a CPU unit is significantly updated, performance of the CPU unit, that is, processing capability, significantly changes before and after the update.

Further, when duplexing the CPU unit before the update and the CPU unit after the update, if the "waiting time" for the synchronization check processing is the same in the duplexed CPU units, there occurs a problem that the synchronization check processing cannot be executed correctly.

(occurrence of erroneous judgment)

That is, even in the same process, since the time points at which execution is completed in the CPU unit before the update and the CPU unit after the update are different, if the determination is performed after the common "waiting time", the determination is erroneously determined as abnormal even if the CPU unit on the other side is operating normally.

For example, when the processing capacity is increased four times as much as that before update by update, if the CPU unit after update is about "10 ms (milliseconds)", the CPU unit before update is about "40 ms" for the period required for execution of a certain process. Then, if the "waiting time" for the synchronization check processing is fixed to "5 ms" common to both the CPU unit before the update and the CPU unit after the update, the CPU unit after the update performs the following determination.

That is, the CPU unit after the update determines whether or not synchronization has been performed, that is, whether or not the CPU unit before the update has completed execution of the certain process, at a time point when "5 ms" has elapsed from the time point when the CPU unit has completed execution of the certain process. However, if "30 ms" does not elapse from the time point at which the updated CPU unit completes execution of the certain process, the CPU unit before update cannot complete execution of the certain process. Therefore, the CPU unit after the update cannot acquire a notification indicating that the CPU unit before the update has completed the execution of the certain process from the CPU unit before the update at a time point when 5ms has elapsed from the time point when the CPU unit itself has completed the execution of the certain process. Therefore, even when the CPU unit before update is operating normally, the CPU unit after update is erroneously determined to be "the CPU unit before update is abnormal (that is, a synchronization error occurs)".

(determination of occurrence of delay)

In the above example, by fixing the "waiting time" common to the CPU unit before the update and the CPU unit after the update to, for example, "30 ms", it is possible to prevent erroneous determination by the CPU unit after the update.

That is, when "30 ms" has elapsed from "the time point at which the updated CPU unit completed execution of the certain process", the CPU unit before update can complete execution of the certain process. Therefore, the CPU unit after the update can correctly determine whether or not the CPU unit before the update has an abnormality, as long as "30 ms" has elapsed from the time point when the CPU unit itself has completed execution of the certain process.

However, since the waiting time of "30 ms" is common between the CPU unit before the update and the CPU unit after the update, the CPU unit before the update determines that "30 ms" has elapsed from the time point at which the unit itself completed execution of the certain process. That is, the CPU unit before updating determines "whether or not an abnormality has occurred in the CPU unit after" 30ms "has elapsed from the time point when the CPU unit itself completed execution of the certain process.

Since the CPU unit before the update and the CPU unit after the update recognize each other that the processing of the CPU unit on the other side is completed, the process proceeds to the next process, and therefore, if the waiting time of both is set to "30 ms" which is common, the execution start of the next process is delayed. The CPU unit after the update determines an abnormality of the CPU unit of the other party after "30 ms" has elapsed from the time point when the unit itself completed the execution of the certain process, and further performs an abnormality determination of the CPU unit before the update after "30 ms". That is, if "60 ms" has not elapsed from the time point when the unit itself completes execution of the certain process, the updated CPU unit cannot start execution of the next process. That is, if the waiting time used by the CPU unit before update and the waiting time used by the CPU unit after update are both made to be "30 ms" common to the CPU unit before update, the completion of the determination of both will be delayed.

If "30 ms" has not elapsed from the time point when the unit itself completes execution of the certain process, the CPU unit before update does not perform determination, and therefore, when an abnormality occurs in the CPU unit after update, switching from ACT to STB for continuing the operation is delayed.

As described above, in the conventional technology assuming that the duplexed CPU units in the PLC have substantially the same processing capability, there is a problem that erroneous determination and delay in switching from the ACT to the STB occur when the duplexed CPU units have different processing capabilities.

Means for solving the problems

To solve the problem, a CPU unit of an embodiment of the present invention is a CPU unit duplexed in a controller, the CPU unit including: a setting unit that sets a waiting time in consideration of a ratio of a processing capacity of the own unit to a processing capacity of the duplexed counterpart CPU unit; and a determination unit configured to determine that an abnormality has occurred in the CPU unit of the other party if completion of execution of the processing in the CPU unit of the other party cannot be confirmed from a time point when execution of the processing in the own unit is completed until the wait time set by the setting unit elapses.

In order to solve the problem, a control method of an embodiment of the present invention is a control method of a CPU unit duplexed in a controller, the control method including: a setting step of setting a waiting time in consideration of a ratio of a processing capacity of the own unit to a processing capacity of the duplexed counterpart CPU unit; and a determination step of determining that an abnormality has occurred in the CPU unit of the other party if completion of execution of the processing in the CPU unit of the other party cannot be confirmed from a time point when execution of the processing in the own unit is completed until the wait time set in the setting step elapses.

ADVANTAGEOUS EFFECTS OF INVENTION

According to an embodiment of the present invention, regarding the CPU unit duplexed in the PLC, there is an effect that the synchronization check processing can be accurately performed without setting an unnecessary waiting time in consideration of a difference in processing capability between the duplexed counterpart CPU unit and the own unit.

Drawings

Fig. 1 is a block diagram showing a main part configuration of a CPU unit and the like according to embodiment 1 of the present invention.

Fig. 2 is a diagram illustrating an outline of processing performed by each of the two CPU units shown in fig. 1.

Fig. 3 is a diagram for explaining a specific example of processing in which each of the two CPU units shown in fig. 1 acquires performance information indicating the performance of the duplexed counterpart CPU unit.

Fig. 4 is a block diagram showing a main part configuration of a CPU unit and the like according to embodiment 2 of the present invention.

Fig. 5 is a diagram showing an example of a hardware configuration for realizing the CPU unit shown in fig. 4.

Fig. 6 is a diagram illustrating an outline of processing performed by each of the two CPU units shown in fig. 4.

Fig. 7 is a diagram for explaining a specific example of processing in which each of the two CPU units shown in fig. 4 acquires performance information indicating the performance of the duplexed counterpart CPU unit.

Fig. 8 is a diagram illustrating an outline of a conventional process of a CPU unit duplexed in a PLC.

Fig. 9 is a diagram illustrating details of the synchronization check processing executed at the execution completion time point of each of the self-diagnosis processing, the command execution processing, and the I/O refresh processing.

Detailed Description

[ embodiment mode 1 ]

Hereinafter, an embodiment (hereinafter also referred to as "the present embodiment") according to one aspect of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals, and description thereof will not be repeated. In each of the embodiments below, a Programmable Logic Controller (PLC) 10 that controls a control target such as a machine or a device will be described as a typical example of a Controller that duplexes two CPU units.

First, in order to facilitate understanding of the first CPU unit 100A and the second CPU unit 100B duplexed in the PLC10, the outline of the processing executed by each of the two units will be described with reference to fig. 2.

Application example § 1

Fig. 2 is a diagram illustrating an outline of processing executed by each of the two CPU units (i.e., the first CPU unit 100A and the second CPU unit 100B) described later using fig. 1. The first CPU unit 100A and the second CPU unit 100B are duplexed in the PLC10, one of which is an execution system (ACT) and the other is a standby System (STB), and confirm the states of the CPU units of the other sides with each other. When the CPU unit (ACT) of the execution system is turned off, the first CPU unit 100A and the second CPU unit 100B switch the CPU unit (STB) of the standby system to the ACT and continue the operation. Hereinafter, for the sake of easy understanding, an example will be described in which the first CPU unit 100A is an ACT and the second CPU unit 100B is an STB.

(outline of waiting time)

As shown in fig. 2, the ACT and the STB each repeatedly perform the self-diagnosis process, the command execution process, and the I/O refresh process in this order. Hereinafter, a set of "self-diagnosis processing, command execution processing, and I/O refresh processing" that is repeatedly and sequentially executed is referred to as "1 cycle (1 cycle)".

The self-diagnosis process is a process of diagnosing whether the hardware of the own unit is operating normally. The command execution process is a process of executing a user program or the like, and is a process of generating data output in the I/O refresh process of the current cycle by executing various operations using data acquired in the I/O refresh process executed in the previous cycle. In the command execution processing, a control signal is generated for an external device other than the counterpart CPU unit, which is a control target of the PLC10 (more precisely, the first CPU unit 100A or the second CPU unit 100B). The I/O refresh processing is processing for performing data exchange with an external device and an external unit other than the duplexed counterpart CPU unit, and is processing for outputting data generated in the command execution processing of the current cycle and acquiring data used in the command execution processing of the next cycle. The control signal generated in the command execution process is output to the control target in the I/O refresh process.

As shown in fig. 2, each of the ACT (first CPU unit 100A) and the STB (second CPU unit 100B) executes "synchronous check processing" after the self-diagnosis processing, the command execution processing, and the I/O refresh processing have been completed in its own unit. In the synchronization check process, the ACT and the STB monitor (in other words, confirm) the state of the CPU unit of the other party, and if the ACT is abnormally stopped, the STB continues the operation instead of the ACT that is abnormally stopped.

The "synchronization check processing" is processing in which the own unit has completed execution, and is processing for confirming whether or not the other CPU unit has also completed execution in the same manner as the own unit. For example, the ACT checks (determines) whether the STB has completed the execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process after the self-diagnosis process, the command execution process, and the I/O refresh process have completed the execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process. For example, after the STB completes the execution of the self-diagnosis process, the command execution process, and the I/O refresh process, the STB checks (determines) whether the ACT completes the execution (determination) of the self-diagnosis process, the command execution process, and the I/O refresh process.

In the "synchronization check processing", the ACT and the STB each check whether or not a notification indicating that "the execution of a certain processing has been completed" has been acquired from the CPU unit of the other party after a predetermined time (waiting time Tw) has elapsed since the execution of the certain processing has been completed by the own unit. In the ACT and the STB, when the waiting time Tw has elapsed since the execution of a certain process by the own unit, and the notification indicating that the CPU unit on the other side has completed the execution of the certain process cannot be acquired, it is determined that "an abnormality has occurred in the CPU unit on the other side that has been duplexed". When the first CPU unit 100A is an ACT and the second CPU unit 100B is an STB, if it is determined that an abnormality has occurred in the first CPU unit 100A, the second CPU unit 100B switches its own unit to the ACT and continues the operation.

As described above, when the lengths of the "waiting times Tw" are set to be the same in the ACT (first CPU unit 100A) and the STB (second CPU unit 100B), if the performances Ab of the ACT and the STB are different, there is a problem that erroneous determination and delay in switching from the ACT to the STB occur. Therefore, by executing the following processing in ACT and STB, even when the performance Ab of both is different, the accurate synchronization check processing is not executed without setting the unnecessary waiting time Tw.

That is, first, a "CPU unit of hardware as a reference (reference CPU unit)" is assumed in advance, and the performance Ab (processing capability) and the processing time are defined in advance for the reference CPU unit. In the following description, the performance Ab of the reference CPU unit is sometimes referred to as "performance Abb".

In each of the ACT and the STB, information indicating the capability Ab of the own unit, for example, information indicating "how much capability Ab the own unit has compared with the reference CPU unit" (local capability information) is held in advance. When the ACT and the STB are subjected to double man-hours in the PLC10, the ACT and the STB each grasp the performance Ab of each other (relative performance Ab of the counterpart CPU unit with respect to the performance Abb of the reference CPU unit). In addition, the ACT and the STB flexibly set the waiting time Tw for the synchronization check process based on the grasped performance Ab. In the following description, the performance Ab of the self unit (relative performance Ab of the self unit with respect to the performance Abb of the reference CPU unit) may be expressed as "performance Abm". Similarly, the performance Ab of the counterpart CPU unit (the relative performance Ab of the counterpart CPU unit with respect to the performance Abb of the reference CPU unit) is sometimes expressed as "performance Aby".

Specifically, the ACT and the STB are set as follows regarding the waiting time Tw for the synchronization check process in the PLC10 by two steps. That is, in the case where the performance Aby of the duplexed counterpart CPU unit is higher than the performance Abm of the own unit, that is, in the case where the processing execution speed of the duplexed counterpart CPU unit is faster than the own unit, the normal wait time Two is set as the wait time Tw. In the case where the performance Aby of the duplexed counterpart CPU unit is equal to the performance Abm of the own unit, that is, in the case where the processing execution speeds in the duplexed counterpart CPU unit and the own unit are equal, the normal wait time Two is set as the wait time Tw. In the case where the performance Aby of the duplexed counterpart CPU unit is lower than the performance Abm of the own unit, that is, in the case where the processing execution speed of the duplexed counterpart CPU unit is slower than that of the own unit, the waiting time Tw is set in accordance with the performance Aby of the counterpart CPU unit.

For example, if the performance Abm of the self unit is twice the performance Abb of the reference CPU unit and the performance Aby of the duplexed counterpart CPU unit is 1/2 times the performance Abb of the reference CPU unit, the performance Abm is four times the performance Aby. At this time, when some processing to be a synchronization check processing target is executed, the own unit needs "10 ms (millisecond)" and the counterpart CPU unit needs "40 ms", and therefore the waiting time Tw of the own unit is set to "30 ms + the normal waiting time Two".

For example, if the performance Abm of the self unit is 1/2 times the performance Abb of the reference CPU unit and the performance Aby of the duplexed counterpart CPU unit is twice the performance Abb of the reference CPU unit, the performance Abm is 1/4 times the performance Aby. At this time, if a certain process to be executed as a synchronization check process target requires "40 ms" in the own unit and "10 ms" in the counterpart CPU unit, the waiting time Tw of the own unit is set to the "normal waiting time Two".

In ACT (first CPU unit 100A) and STB (second CPU unit 100B), the waiting time Tw of the own unit is flexibly set according to the difference between the performance Ab of the own unit and the performance Ab of the duplexed counterpart CPU unit.

(specific example of treatment)

As shown in fig. 2, when the PLC10 duplexes the first CPU unit 100A (ACT) and the second CPU unit 100b (STB), the ACT and the STB each execute "duplex processing" independently of the normal cycle. That is, the ACT and the STB each execute "duplex processing" before "self-diagnosis processing, command execution processing, and I/O refresh processing" that are cyclically (periodically) repeatedly executed.

In the "duplex processing", ACT and STB respectively grasp their performance Ab and enter a duplex state. The performance information (local performance information) of each of the ACT and the STB is written into a nonvolatile memory included in each CPU unit, for example, at the time of production of each CPU unit. The local performance information indicates, for example, "how much the performance Abm of the own unit is improved/reduced in performance by percentage with respect to the performance Abb of the reference CPU unit with respect to the performance Abb of the CPU unit of the specific hardware specification (the aforementioned" reference CPU unit ").

The ACT and the STB store performance information of their own units as "local performance information" in the nonvolatile memory of each CPU unit. The ACT and STB mutually forward the local performance information in duplex processing, and store the local performance information of the other CPU unit as "other CPU performance information" in the non-volatile memory of each CPU unit.

For example, when the local performance information is 150% (that is, the processing execution speed (processing speed) is 1.5 times the reference CPU unit) and the other performance information is 75% (the processing speed is 0.75 times the reference CPU unit), the ACT grasps the following information. That is, the ACT grasps that the processing speed of the own unit (ACT) is "twice (1.5 times/0.75 times)" the processing speed of the counterpart CPU unit (STB).

For example, if the own-device performance information is 75% (the processing speed is 0.75 times the reference CPU unit) and the other-device performance information is 150% (that is, the processing execution speed (processing speed) is 1.5 times the reference CPU unit), the STB grasps the following information. That is, the processing speed of the self unit (STB) is "1/2 times (0.75 times/1.5 times)" the processing speed of the partner CPU unit (ACT).

In the "duplex processing", when the difference between the performance Ab of the own unit and the performance Ab of the CPU unit of the other party is grasped and the duplex state is achieved, the ACT and the STB each set the waiting time Tw of the own unit using the difference between the performance Ab.

Each of the ACT and the STB measures an execution time from the start of execution of the "command execution" process of fig. 2 to the completion of the execution in each CPU unit, for example, using an internal timer included in each CPU unit. Here, regarding the "command execution" processing, assuming that the execution time of the ACT is "100 ms", the difference from the performance Ab of the STB is "twice" as described above, and therefore the counterpart CPU unit (STB) takes "200 ms".

Therefore, in the ACT, a period obtained by adding "100 ms (200 ms to 100 ms)" to the normal wait time Two is set as the wait time Tw of the synchronization check process related to the "command execution" process of the own unit. In the example shown in fig. 2, the ACT executes the standby process for a period of "100 ms" from the execution completion time point of the "command execution" process in the own unit, and then executes the synchronization check process related to the "command execution" process. That is, the ACT determines whether or not to acquire a notification of completion of execution of the "command execution" process from the counterpart CPU unit (STB) during a period from the execution completion time point of the "command execution" process in the own unit until "100 ms + the normal waiting time Two" elapses. Then, if the notification of the completion of the execution of the "command execution" process cannot be acquired from the STB until the "100 ms + the normal waiting time Two" elapses from the execution completion time point of the "command execution" process in the self unit, the ACT determines that an abnormality has occurred in the STB.

The STB which grasps that "the performance Ab of the counterpart CPU unit (ACT) is high or equal (i.e., the processing speed is fast or the same)" directly sets the normal waiting time Two to the waiting time Tw of the synchronization check processing relating to the "command execution" processing of the own unit. In the example shown in fig. 2, as soon as the STB completes execution of the "command execution" process in its own unit, the synchronization check process related to the "command execution" process is executed immediately. That is, the STB determines whether or not to acquire the notification of the completion of the execution of the "command execution" process from the counterpart CPU unit (ACT) during the period from the execution completion time point of the "command execution" process in the own unit until the normal wait time Two elapses. If the notification of completion of execution of the "command execution" process cannot be acquired from the ACT until the normal wait time Two elapses from the time when execution of the "command execution" process in the self unit is completed, the STB determines that an abnormality has occurred in the ACT. When it is determined that an abnormality has occurred in the ACT (first CPU unit 100A), the STB (second CPU unit 100B) switches its own unit to the ACT and continues the operation.

Construction example 2

The first CPU unit 100A and the second CPU unit 100B, which have been described in the summary manner up to now with reference to fig. 2, will be described in detail with reference to fig. 1.

Fig. 1 is a block diagram showing a configuration of a main part of a PLC10 including a first CPU unit 100A and a second CPU unit 100BCPU unit according to embodiment 1 of the present invention. As illustrated in fig. 1, the PLC10 includes a first CPU unit 100A and a second CPU unit 100B duplexed in the PLC 10. The first CPU unit 100A and the second CPU unit 100B are each a functional unit that collectively controls the entire PLC 10.

The PLC10 may also include a functional unit not shown in fig. 1. The PLC10 further includes, for example, a power supply unit, not shown, which supplies power to the entire PLC10 including the first CPU unit 100A and the second CPU unit 100B. The PLC10 may include a function unit, not shown, such as an input unit that inputs signals of switches and sensors mounted at appropriate positions of the production apparatus and the facility apparatus, an output unit that sends control signals to actuators and the like, and a communication unit for connecting to a communication network.

As described above, the first CPU unit 100A and the second CPU unit 100B each repeatedly execute the self-diagnosis process, the command execution process, and the I/O refresh process in this order. The I/O refresh processing includes processing (input (IN) refresh) of introducing various input signals acquired by an input unit or the like to an I/O memory of each CPU unit, and processing (output (OUT) refresh) of writing a processing result of command execution processing to the I/O memory and outputting the processing result to an output unit or the like. That is, the I/O refresh process is a cyclic data exchange between the "first CPU unit 100A and the second CPU unit 100B" and the "external unit or external device other than the first CPU unit 100A and the second CPU unit 100B". In the command execution process, the PLC10 as a controller generates various control signals to be output to a control target, and for example, generates control signals by executing a logical operation using an input signal introduced to the I/O memory in input refresh based on a user program.

In the PLC10, in order to improve the safety and reliability of the control system controlled by the PLC10, the first CPU unit 100A and the second CPU unit 100B are duplexed and connected by, for example, an inter-CPU bus. The first CPU unit 100A and the second CPU unit 100B start execution of the same process (each of the self-diagnosis process, the command execution process, and the I/O refresh process) at the same timing if there is no abnormality in both. For example, if there is no abnormality in the first CPU unit 100A and the second CPU unit 100B, the execution of the same user program using the same input signal is started at the same timing.

One of the first CPU unit 100A and the second CPU unit 100B is a CPU unit (ACT) of an execution system, and the other is a CPU unit (STB) of a standby system. As described above, in the present specification, an example of "the first CPU unit 100A is an ACT and the second CPU unit 100B is an STB" is described, but the same applies to the case of "the first CPU unit 100A is an STB and the second CPU unit 100B is an ACT".

The first CPU unit 100A as an ACT actually performs a loop process, reads and writes data from and into a memory, and transmits and receives control data (I/O data) to and from an external I/O device or the like, and is responsible for control of a control system controlled by the PLC 10. The second CPU unit 100B as the STB executes the same user program as the user program executed by the first CPU unit 100A as the ACT while standing by (i.e., while no abnormality occurs in the first CPU unit 100A as the ACT). However, the second CPU unit 100B as the STB does not output the execution result (operation execution result) of the executed user program to an external I/O device or the like. Also, the second CPU unit 100B as an STB receives processing results (operation execution results, and various input signals acquired by the first CPU unit 100A as an ACT) and the like from the first CPU unit 100A as an ACT. The second CPU unit 100B as the STB updates the contents of the memory of the own unit based on the processing result and the like received from the first CPU unit 100A as the ACT. Thereby, the identity of the memory contents of the second CPU unit 100B as the STB and the first CPU unit 100A as the ACT is ensured.

When the first CPU unit 100A as the ACT has a failure, the second CPU unit 100B as the STB switches to the first CPU unit 100A as the ACT to perform an operation such as actual control. By duplexing the first CPU unit 100A and the second CPU unit 100B in advance in the PLC10, even if the first CPU unit 100A as the ACT fails, the PLC10 can continue its operation without immediately stopping, and thus reliability is improved.

(details of CPU unit)

As shown in fig. 1, the PLC10 includes a common register 200 capable of performing writing and reading of data in each of the first CPU unit 100A and the second CPU unit 100B duplexed in the PLC 10. In order to ensure the simplicity of description, the configuration that is not directly related to the present embodiment is omitted from the description and the block diagram. However, the PLC10 may also include the omitted configuration, depending on the actual implementation.

The common register 200 includes a first register 210 and a second register 220.

The first register 210 is written by the first CPU unit 100A with information indicating that "the own unit (i.e., the first CPU unit 100) has completed execution of some processing (each of self-diagnosis processing, command execution processing, and I/O refresh processing)". The information written to the first register 210 by the first CPU unit 100A is read by the second CPU unit 100B.

The second register 220 is written by the second CPU unit 100B with information indicating that "the execution of a certain process (each of the self-diagnosis process, the command execution process, and the I/O refresh process) has been completed by its own unit (i.e., the second CPU unit 100B)". The information written to the second register 220 by the second CPU unit 100B is read by the first CPU unit 100A.

The first CPU unit 100A includes, as functional blocks, a capability acquisition unit 110A, a process execution unit 120A, a waiting time setting unit 160A, and a determination unit 170A in addition to the storage unit 130A. The storage unit 130A stores another function table 140A and a local function table 150A.

The second CPU unit 100B includes, as functional blocks, a capability acquisition unit 110B, a process execution unit 120B, a waiting time setting unit 160B, and a determination unit 170B in addition to the storage unit 130B. The storage unit 130B stores another function table 140B and the own function table 150B.

Hereinafter, the capability acquisition unit 110A and the capability acquisition unit 110B are simply referred to as "capability acquisition unit 110" when there is no need to particularly distinguish between them. Similarly, the process execution unit 120A and the process execution unit 120B are simply referred to as "process execution unit 120" when there is no need to distinguish them from each other. When it is not necessary to distinguish between storage unit 130A and storage unit 130B, they are simply referred to as "storage unit 130". The other function meter 140A and the other function meter 140B are simply referred to as "the other function meter 140" when there is no need to distinguish them from each other. The local capability table 150 is simply referred to as the "local capability table 150" when it is not necessary to distinguish the local capability table 150A from the local capability table 150B. When it is not necessary to distinguish between the waiting time setting unit 160A and the waiting time setting unit 160B, they are simply referred to as "waiting time setting unit 160". When it is not necessary to distinguish the determination unit 170A from the determination unit 170B, they are simply referred to as "determination unit 170".

Each of the functional blocks such as the capability acquisition Unit 110, the process execution Unit 120, the wait time setting Unit 160, and the determination Unit 170 can be realized by, for example, a Central Processing Unit (CPU) or the like reading a program stored in a storage device (storage Unit 130) realized by a Read Only Memory (ROM), a Non-Volatile Memory (NVRAM), or the like, into a Random Access Memory (not shown) or the like and executing the program.

(details of functional blocks)

The capability acquisition unit 110 refers to the local capability table 150 of the CPU unit of the other party to acquire information ("capability information") indicating the capability Aby (processing capability) of the CPU unit of the other party that has been duplexed. The capability acquisition unit 110 stores the acquired performance information (other-device performance information) of the CPU unit of the other party in the other-device capability table 140 of the own unit.

In particular, the capability acquiring unit 110 acquires the other-device performance information once in the "duplex process" illustrated in fig. 2 before the process executing unit 120 repeatedly executes the self-diagnosis process, the command execution process, and the I/O refresh process in this order.

Fig. 3 is a diagram for explaining a specific example of processing for "acquiring performance information Aby indicating the performance of the duplexed counterpart CPU unit" which is executed once in the "duplex processing". As shown in fig. 3, the capability acquiring unit 110A refers to the own function capability table 150B to acquire the performance information indicating the performance Aby of the second CPU unit 100B, and stores the acquired performance information (other-unit performance information) of the second CPU unit 100B in the other-unit capability table 140A. The capability acquiring unit 110B refers to the own capability table 150A to acquire the performance information indicating the performance Aby of the first CPU unit 100A, and stores the acquired performance information (other-unit performance information) of the first CPU unit 100A in the other-unit capability table 140B.

The process execution unit 120 repeatedly executes the self-diagnosis process, the command execution process, and the I/O flush process in this order, and when the execution of each process is completed, writes the word "the execution of each process has been completed in the own unit" to the common register 200.

When the execution of each process is completed, the process execution unit 120 notifies the waiting time setting unit 160 and the determination unit 170 of the fact that "the execution of each process has been completed in its own unit". The process execution unit 120 may notify the wait time setting unit 160 of "the execution time of each process (the time from the start of execution to the completion of execution of each process)" together with the "the execution of each process by its own unit" being completed. That is, the process execution unit 120 may measure the "execution time of each process" using an internal timer, and notify the wait time setting unit 160 of the "execution time of each process" measured.

The process execution unit 120 writes the fact that the self-diagnosis process, the command execution process, and the I/O flush process are executed (i.e., the fact that the "execution of the process has been completed in the own unit") to the shared register 200. That is, the process execution unit 120A that has completed execution of the self-diagnosis process writes a message "the self-unit has completed execution of the self-diagnosis process" to the first register 210, and the process execution unit 120 that has completed execution of the self-diagnosis process writes a message "the self-unit has completed execution of the self-diagnosis process" to the second register 220. The process execution unit 120A that has completed the execution of the command execution process writes a message "the execution of the command execution process has been completed in its own unit" to the first register 210, and the process execution unit 120B that has completed the execution of the command execution process writes a message "the execution of the command execution process has been completed in its own unit" to the second register 220. The process execution unit 120A that has completed the execution of the I/O refresh process writes the meaning of "the own cell has completed the execution of the I/O refresh process" to the first register 210, and the process execution unit 120B that has completed the execution of the I/O refresh process writes the meaning of "the own cell has completed the execution of the I/O refresh process" to the second register 220.

The processing execution unit 120 starts the execution of the self-diagnosis process, the command execution process, and the I/O refresh process at the following timings while the first CPU unit 100A and the second CPU unit 100B are duplexed. In other words, while the first CPU unit 100A and the second CPU unit 100B are not determined to have the abnormality, the process execution unit 120 starts the execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process at the following timing.

That is, the process execution unit 120 starts the execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process after confirming the normality of the first CPU unit 100A and the second CPU unit 100B in the synchronization check process after the completion of the execution of the previous process.

Specifically, after the normality of the first CPU unit 100A and the second CPU unit 100B is confirmed in the synchronization check process after the execution of the self-diagnosis process is completed, the process execution unit 120 starts the execution of the command execution process. After the normality of the first CPU unit 100A and the second CPU unit 100B is confirmed in the synchronization check processing after the execution of the command execution processing is completed, the processing execution section 120 starts the execution of the I/O refresh processing. After the normality of the first CPU unit 100A and the second CPU unit 100B is confirmed in the synchronization check process after the execution of the I/O refresh process is completed, the process execution unit 120 starts the execution of the self-diagnosis process of the next cycle.

The waiting time setting unit 160 refers to the other-device capability table 140 to acquire the other-device capability information, and refers to the local capability table 150 to acquire the local capability information. The wait time setting unit 160 acquires the "execution of each process by its own unit" from the process execution unit 120. The wait time setting unit 160 calculates the execution time of each process, together with the fact that the "execution of each process has been started by the own unit" acquired from the process execution unit 120 before the fact that the "execution of each process has been completed by the own unit" is acquired. That is, the wait time setting unit 160 calculates the execution time of each process based on the time "the self-unit has started execution of each process" measured by the internal timer and the time "the self-unit has completed execution of each process" measured by the internal timer. The execution time of each process may be measured by the process execution unit 120 using an internal timer, and notified from the process execution unit 120 to the waiting time setting unit 160.

The waiting time setting unit 160 calculates a "waiting time Tw" for the synchronization check process for each process based on the acquired other-device performance information, the own-device performance information, and the execution time of each process, and notifies the determination unit 170 of the calculated waiting time Tw. Specifically, the waiting time setting unit 160 calculates the "waiting time Tw" for the synchronization check process for each process as described below, using the other-device performance information, the local performance information, and the execution time of each process.

That is, when the "duplex counterpart CPU unit performance Aby" indicated by the other unit performance information is higher than the "own unit performance Abm" indicated by the own unit performance information, the wait time setting unit 160 sets the "normal wait time Two" to the "wait time Tw". When the performance Aby of the duplexed CPU unit of the other party is equal to the performance Abm of the own unit, the wait time setting unit 160 sets the "normal wait time Two" to the "wait time Tw".

The "normal waiting time Two" is a period of time that is common to the first CPU unit 100A and the second CPU unit 100B and has a predetermined length, and is set at the time of factory shipment of each unit, for example, and is updatable by the user. The "normal waiting time Two" is a period set on the premise that the performance Ab is equal in the first CPU unit 100A and the second CPU unit 100B.

When the performance Aby of the duplexed counterpart CPU unit is lower than the performance Abm of the own unit, the latency setting unit 160 sets a period obtained by multiplying the execution time of each process by a value obtained by dividing the performance Abm of the own unit by the performance Aby of the counterpart CPU unit as the adjustment latency Ta. The waiting-time setting unit 160 sets a "waiting time Tw" to a period obtained by adding the "normal waiting time Two to the adjustment waiting time Ta (that is," normal waiting time Two + adjustment waiting time Ta ").

The determination unit 170 determines whether or not the CPU unit on the other side has completed execution of the process executed by the process execution unit 120 (synchronization check process) until the wait time Tw notified from the wait time setting unit 160 has elapsed from the time when the process execution unit 120 completes execution of each process. For example, the determination unit 170 refers to the shared register 200 at a point in time when the wait time Tw has elapsed from the point in time when "the own unit has completed execution of each process", and checks whether or not the execution of the duplexed counterpart CPU unit has completed with respect to a certain process for which the own unit has completed execution.

The determination unit 170 notified of "normal waiting time Two + adjustment waiting time Ta" as the waiting time Tw executes the standby process until the adjustment waiting time Ta elapses from the time point when "the own unit has completed execution of each process". Then, the determination unit 170 executes the synchronization check process after the execution of the standby process is completed (that is, after the adjustment waiting time Ta has elapsed from the time point when the "own unit has completed the execution of each process"). That is, the determination unit 170 determines "whether or not the other CPU unit can confirm that the execution of the process executed by the own unit is completed until the normal waiting time Two elapses after the execution of the standby process is completed". In other words, the determination unit 170 determines whether or not the execution completion of the CPU unit on the other side can be confirmed with respect to the process that has been executed by the own unit until the normal waiting time Two elapses from the execution completion time point of the standby process. The "execution completion time point of the standby processing" is "a time point of execution completion in the CPU unit of the other party, which is expected to be the processing that has been completed by the own unit".

The determination unit 170 notified of the "normal waiting time Two" as the waiting time Tw immediately executes the synchronization check process at the time point "the own unit has completed execution of each process". That is, the determination unit 170 determines "whether or not the CPU unit on the other side can confirm that the execution of the process executed by the CPU unit on its own side has been completed until the normal waiting time Two elapses". In other words, the determination unit 170 determines whether or not the execution completion of the CPU unit on the other side can be confirmed, with respect to the processing that the own unit has already performed, from the execution completion time point of the own unit until the normal waiting time Two elapses.

The judgment unit 170A refers to the second register 220 of the common register 200, and checks whether or not there is a write indicating that "the execution of the process execution unit 120B is completed" with respect to a certain process that the process execution unit 120A has completed execution. When the second register 220 is not written with the meaning of "execution of the process execution unit 120B is completed" with respect to a certain process executed by the process execution unit 120A, the determination unit 170A determines that an abnormality has occurred in the second CPU unit 100B.

The judgment unit 170B refers to the first register 210 of the shared register 200, and checks whether or not there is a write indicating that "the execution of the process execution unit 120A is completed" with respect to a certain process that the process execution unit 120B has completed execution. When the first register 210 is not written with the meaning of "execution of the process execution unit 120A is completed" with respect to any process that the process execution unit 120B has completed execution, the determination unit 170B determines that an abnormality has occurred in the first CPU unit 100A.

(details of the storage section)

The storage unit 130 is a storage device that stores various data used by the first CPU unit 100A and the second CPU unit 100B. The storage unit 130 may store, in a non-transitory manner, (1) a control program, (2) an OS program, (3) an application program for executing various functions of each of the first CPU unit 100A and the second CPU unit 100B, and (4) various data read when the application program is executed, the control program being executed by each of the first CPU unit 100A and the second CPU unit 100B. The data (1) to (4) are stored in a nonvolatile storage device such as a Read Only Memory (ROM), a flash Memory, an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), and a Hard Disk Drive (HDD)). Each of the first CPU unit 100A and the second CPU unit 100B may include a temporary storage unit not shown. The temporary storage unit is a so-called work Memory that temporarily stores data used for calculation, calculation results, and the like during various processes executed by the first CPU unit 100A and the second CPU unit 100B, and includes a volatile storage device such as a Random Access Memory (RAM). Which data is stored in which storage device is appropriately determined according to the purpose of use, convenience, cost, physical limitations, and the like of each of the first CPU unit 100A and the second CPU unit 100B. The storage unit 130 also stores another capability table 140 and a local capability table 150.

The other-device capability table 140 stores other-device capability information, which is information indicating the capability Aby of the CPU unit of the other party that has undergone the duplexing. As described with reference to fig. 3, the capability acquiring unit 110 stores the other-device capability information acquired by referring to the own capability table 150 of the duplexed counterpart CPU unit in the other-device capability table 140 of the own unit.

The local capability table 150 stores local capability information, which is information indicating the capability Abm of the local unit, and stores local capability information indicating, for example, "how much capability Ab (processing capability) the local unit has compared with the reference CPU unit". The local performance information is stored in the local performance table 150, for example, when the first CPU unit 100A and the second CPU unit 100B are shipped from the factory.

(arrangement of CPU Unit)

The first CPU unit 100A and the second CPU unit 100B having the configurations described above with reference to fig. 1 are organized as follows for ease of understanding. That is, each of the first CPU unit 100A and the second CPU unit 100B is a CPU unit duplexed in the PLC10 (controller), and includes a waiting time setting unit 160 (setting unit) and a determination unit 170. The wait time setting unit 160 sets the wait time Tw in consideration of the ratio of the performance Abm (processing capability) of the own unit and the performance Aby of the duplexed counterpart CPU unit. The determination unit 170 determines that an abnormality has occurred in the CPU unit of the other party if the completion of the execution of the processing by the CPU unit of the other party cannot be confirmed from the time when the processing by the own unit is completed until the wait time Tw set by the wait time setting unit 160 has elapsed.

According to the above configuration, the first CPU unit 100A and the second CPU unit 100B each set the wait time Tw in consideration of the ratio of the performance Ab (processing capability) of the own unit to the counterpart CPU unit. Then, the first CPU unit 100A and the second CPU unit 100B each determine synchronization between the own unit and the counterpart CPU unit (that is, coincidence of the executed processes) by using the set waiting time Tw.

For example, when the performance Ab of the counterpart CPU unit is higher than that of the own unit (i.e., the processing execution speed is faster), the first CPU unit 100A and the second CPU unit 100B each set a predetermined normal waiting time Tw to the waiting time Tw. When the performance Ab of the other CPU unit is equal to that of the own CPU unit, the first CPU unit 100A and the second CPU unit 100B set a predetermined "normal waiting time Two" as the waiting time Tw, respectively.

In the case where the performance Ab of the counterpart CPU unit is higher than the own unit, the counterpart CPU unit should have completed execution of a certain process at the point in time when the own unit has completed execution of the certain process. Further, in the case where the performance Ab is equal between the counterpart CPU unit and the own unit, the counterpart CPU unit should complete execution of a certain process at a point in time when the own unit has completed execution of the certain process.

Therefore, even when the performance Ab of the other CPU unit is higher than that of the own unit, the first CPU unit 100A and the second CPU unit 100B can accurately determine whether or not the other CPU unit has an abnormality by setting the normal waiting time Tw to the waiting time Tw.

For example, when the performance Ab of the other CPU unit is lower than that of the own unit, the first CPU unit 100A and the second CPU unit 100B each set "a period obtained by adding the normal waiting time Two to the adjustment waiting time Ta" as the waiting time Tw. The adjustment waiting time Ta is set in consideration of the difference between the performance Ab of the own unit and the performance Ab of the CPU unit of the other party. For example, the "difference between the execution completion time point of the process in the own unit and the execution completion time point of the process in the counterpart CPU unit in advance" is set as the adjustment wait time Ta.

In the case where the performance Ab of the counterpart CPU unit is lower than that of the own unit, the counterpart CPU unit has not completed execution of a certain process at a point in time when the own unit has completed execution of the certain process. Therefore, the first CPU unit 100A and the second CPU unit 100B each stand by until "a time point (execution completion expected time point) expected to be the completion of the execution of the processing in the counterpart CPU unit". The first CPU unit 100A and the second CPU unit 100B each determine: whether or not the execution of the processing in the CPU unit of the other party is completed can be confirmed from the execution completion expectation time point until the normal waiting time Two elapses. That is, the first CPU unit 100A and the second CPU unit 100B each determine: whether or not the execution of the process in the CPU unit of the other party is completed can be confirmed until a "period obtained by adding the adjustment waiting time Ta to the normal waiting time Two" elapses from the execution completion time of the process in the own unit.

Therefore, even when the performance Ab of the other CPU unit is lower than that of the own unit, the first CPU unit 100A and the second CPU unit 100B can accurately perform the determination by setting "a period obtained by adding the normal waiting time Two to the adjustment waiting time Ta" as the waiting time Tw.

As described above, the following effects are exhibited: each of the first CPU unit 100A and the second CPU unit 100B can set an appropriate wait time Tw in consideration of the difference in performance Ab between the own unit and the counterpart CPU unit even when the performance Ab does not match between the own unit and the counterpart CPU unit. Namely, the following effects are exhibited: the first CPU unit 100A and the second CPU unit 100B can accurately perform the synchronization check process without providing an unnecessary waiting time Tw, taking into account the difference in performance Ab between the duplexed counterpart CPU unit and the own unit.

In each of the first CPU unit 100A and the second CPU unit 100B, the processes (processes to be subjected to the synchronization check process) include a self-diagnosis process, a command execution process, and an I/O refresh process. The self-diagnosis process is a process of diagnosing whether or not there is an abnormality in the hardware of the self unit. The command execution process is a process of generating a signal for controlling "an external device and an external unit other than the CPU unit of the other party". The I/O refresh processing is processing for exchanging data with "an external device and an external unit other than the CPU unit of the other party". The latency setting unit 160 sets a latency Tw for each of the self-diagnosis process, the command execution process, and the I/O refresh process. The determination section 170 performs the determination, that is, performs the synchronization check process, with respect to each of the self-diagnosis process, the command execution process, and the I/O refresh process.

The first CPU unit 100A and the second CPU unit 100B each determine synchronization of the own unit with the counterpart CPU unit (i.e., coincidence of the executed processes) with respect to the self-diagnosis process, the command execution process, and the I/O refresh process, respectively.

The following effects are achieved: the first CPU unit 100A and the second CPU unit 100B can determine synchronization between the own unit and the counterpart CPU unit at the timing when execution of the self-diagnosis process, the command execution process, and the I/O refresh process is completed.

The first CPU unit 100A and the second CPU unit 100B each execute one-time duplex processing before sequentially repeating the self-diagnosis processing, the command execution processing, and the I/O refresh processing. The first CPU unit 100A and the second CPU unit 100B each acquire the performance Aby of the counterpart CPU unit from the counterpart CPU unit in the duplex processing.

According to the above configuration, each of the first CPU unit 100A and the second CPU unit 100B obtains Aby the performance of the counterpart CPU unit once before the self-diagnosis process, the command execution process, and the I/O refresh process are repeatedly executed in this order. Also, the first CPU unit 100A and the second CPU unit 100B each set the wait time Tw for the determination regarding the respective processes in consideration of the ratio of the acquired performance Aby of the CPU unit of the partner to the performance Abm of the own unit.

The following effects are achieved: the first CPU unit 100A and the second CPU unit 100B can each set the waiting time Tw used for the determination regarding each process in consideration of the performance Aby of the CPU unit on the other side acquired before the respective processes are repeatedly executed.

Operation example 3

The first CPU unit 100A and the second CPU unit 100B each execute the following processing as shown in fig. 2. That is, the first CPU unit 100A and the second CPU unit 100B each repeatedly execute the self-diagnosis process, the command execution process, and the I/O refresh process in this order. Specifically, the process execution unit 120 of each unit repeatedly executes the self-diagnosis process, the command execution process, and the I/O refresh process in this order. Each of the first CPU unit 100A and the second CPU unit 100B (in particular, the capability acquiring unit 110 of each unit) executes a duplex process once before the self-diagnosis process, the command execution process, and the I/O refresh process are sequentially repeated. The first CPU unit 100A and the second CPU unit 100B each acquire other performance information indicating the performance Aby of the duplexed counterpart CPU unit in the duplex processing.

When each unit (particularly, the process execution unit 120 of each unit) completes execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process, the unit writes a word "the unit itself has completed execution of each process" to the common register 200.

Each unit (particularly, the waiting time setting unit 160 of each unit) sets the "waiting time Tw" for the synchronization check process for each process, based on the other-unit performance information, the own-unit performance information, and the execution time of each process executed and completed by the own unit.

Specifically, the wait time setting unit 160 calculates "the adjustment wait time Ta calculated in consideration of the ratio of the performance Abm of the own unit to the performance Aby of the duplexed counterpart CPU unit" for each process. The waiting-time setting unit 160 sets a period in which the "adjustment waiting time Ta calculated for each process" is added to the "normal waiting time Two for each process" as the "waiting time Tw" for the synchronization check process for each process.

When "Abm/Aby" is equal to or less than "1", the wait time setting unit 160 sets "the adjustment wait time Ta is 0" for each process. When "Abm/Aby" is greater than "1", the wait time setting unit 160 sets the "adjustment wait time Ta" of each process to a value obtained by multiplying the execution time of each process by "Abm/Aby".

Each unit (particularly, the determination unit 170 of each unit) executes the synchronization check process after the execution of the self-diagnosis process, the command execution process, and the I/O refresh process of the own unit is completed. That is, the determination unit 170 refers to the shared register 200, and determines whether or not the other CPU unit has completed execution of the process that the own unit has completed, from the execution completion time point of each process of the own unit until the wait time Tw elapses.

The synchronization check processing is processing of monitoring the states of the duplexed counterpart CPU units with each other. Specifically, the synchronization check processing is processing for confirming (determining) whether or not execution of the processing is also completed in the duplexed counterpart CPU unit, with respect to processing that has been completed in the own unit.

If synchronization cannot be confirmed in the synchronization check process, that is, if completion of execution in the CPU unit of the other party cannot be confirmed with respect to the process in which the own unit has already executed, the first CPU unit 100A and the second CPU unit 100B are duplexed. Then, for example, the STB which has determined that the ACT is abnormal replaces the ACT and continues the operation of its own unit.

If the synchronization can be confirmed in the synchronization check processing, each unit (particularly, the processing execution unit 120 of each unit) starts execution of the next processing "processing in which completion of execution of the own unit and the CPU unit of the other party has been confirmed in the synchronization check processing". Specifically, the synchronization check processing is executed as described below.

That is, when the process execution unit 120A completes execution of a certain process, it writes "the execution of the certain process has been completed in its own unit (i.e., the process execution unit 120A)" into the first register 210 of the common register 200. The determination unit 170B recognizes that the first CPU unit 100A has completed execution of a certain process by reading out the first register 210. When the execution of a certain process is completed, the process execution unit 120B writes "the execution of a certain process has been completed in its own unit (i.e., the process execution unit 120B)" into the second register 220 of the common register 200. The determination unit 170A recognizes that the second CPU unit 100B has completed execution of a certain process by reading out the second register 220. When each of the

determination units

170A and 170B recognizes "the other CPU unit has completed executing a certain process", each of the

process execution units

120A and 120B starts execution of a process next to the certain process.

The "processing performed by each of the first CPU unit 100A and the second CPU unit 100B" described so far can be organized as follows. That is, the "processing executed by each of the first CPU unit 100A and the second CPU unit 100B" is a method of controlling the CPU unit duplexed in the PLC10 (controller), and includes a setting step and a determination step. The setting steps are as follows: the waiting time Tw is set in consideration of the ratio of the performance Abm of the own unit to the performance Aby of the duplexed counterpart CPU unit. The judging step is as follows: if the completion of the execution of the processing in the CPU unit of the other party cannot be confirmed from the time when the processing in the own unit is completed until the waiting time Tw set in the setting step elapses, it is determined that an abnormality has occurred in the CPU unit of the other party.

According to the method, the control method determines synchronization of the self unit and the counterpart CPU unit (i.e., coincidence of the executed processes) using the wait time Tw set in consideration of the ratio of the performance Ab of the self unit and the counterpart CPU unit.

For example, in the case where the performance Ab of the counterpart CPU unit is higher than that of the own unit (i.e., the processing execution speed is fast), the control method sets a predetermined "normal waiting time Two" as the waiting time Tw. In addition, when the performance Ab is equal between the counterpart CPU unit and the own unit, the control method sets a predetermined "normal waiting time Two" as the waiting time Tw.

For example, in the case where the performance Ab of the counterpart CPU unit is lower than the own unit (i.e., the processing execution speed is slow), the control method sets "a period obtained by adding the adjustment wait time Ta in consideration of the difference between the performance Ab and the normal wait time Two" as the wait time Tw. Specifically, the "difference between the execution completion time point of the process in the own unit and the time point expected to be the completion of the execution of the process in the counterpart CPU unit" is set as the adjustment wait time Ta.

In the case where the performance Ab of the counterpart CPU unit is lower than that of the own unit, the counterpart CPU unit has not completed execution of a certain process at a point in time when the own unit has completed execution of the certain process. Therefore, the control method stands by to "a point of time when execution of the process in the counterpart CPU unit is expected to be completed", and then determines: until the "normal waiting time Two" elapses, whether or not the execution of the processing in the counterpart CPU unit is completed can be confirmed. That is, the control method determines: whether or not the execution of the process in the CPU unit of the other party is completed can be confirmed until a "period obtained by adding the adjustment waiting time Ta to the normal waiting time Two" elapses from the execution completion time of the process in the own unit.

Therefore, even when the performance Ab of the partner CPU unit is lower than that of the own unit, the control method sets the "period obtained by adding the adjustment wait time Ta to the normal wait time Two" as the wait time Tw, and thereby can accurately perform the determination.

As described above, the following effects are exhibited: the control method can set an appropriate wait time Tw in consideration of the difference in performance Ab between the own unit and the counterpart CPU unit, even when the performance Ab does not match between the own unit and the counterpart CPU unit. Namely, the following effects are exhibited: the control method can accurately perform the synchronization check processing without setting an unnecessary waiting time Tw in consideration of the difference in performance Ab between the duplexed counterpart CPU unit and the own unit.

[ embodiment 2 ]

Another embodiment of the present invention is described below with reference to fig. 4 to 7. In order to ensure the simplicity of description, only the configuration (the flow of processing and the contents of processing) different from that of embodiment 1 will be described. That is, the configuration described in embodiment 1 and the like may be all included in the present embodiment. The same definitions apply to terms described in embodiment 1.

In embodiment 1, the first CPU unit 100A and the second CPU unit 100B which are duplexed in the PLC10 have one of the capabilities Aby of the CPU unit of the other party for setting the "waiting time Tw" of the own unit.

In contrast, in the present embodiment, the first CPU unit 300A and the second CPU unit 300B duplexed in the PLC 20 set a plurality of performances Aby of the CPU units of the other parties for the "waiting time Tw" of the own unit. The details are described below.

Fig. 5 is a diagram showing an example of a hardware configuration for realizing each of the first CPU unit 300A and the second CPU unit 300B. That is, the first CPU unit 300A and the second CPU unit 300B are each implemented using a memory 410, a CPU 420 (microcomputer), and a Large Scale Integration (LSI) 430. The Application Specific Integrated Circuit (ASIC) may be a Field Programmable Gate Array (FPGA) instead of the LSI.

The first CPU unit 300A and the second CPU unit 300B repeatedly execute the self-diagnosis process, the command execution process, and the I/O refresh process in this order, similarly to the first CPU unit 100A and the second CPU unit 100B, respectively. For example, the self-diagnosis process is mainly performed by the CPU 420, the command execution process is mainly performed by the dedicated LSI 430, and the I/O refresh process is mainly performed by the CPU 420 via the dedicated LSI 430.

In the case where hardware mainly executing the self-diagnosis process, the command execution process, and the I/O refresh process is different from each other, the performance Ab may be different between the first CPU unit 300A and the second CPU unit 300B for each process. For example, the performance Ab of the CPU 420 of the first CPU unit 300A may be higher than the CPU 420 of the second CPU unit 300B, and the performance Ab of the dedicated LSI 430 of the first CPU unit 300A may be lower than the dedicated LSI 430 of the second CPU unit 300B. At this time, the first CPU unit 300A performs completion faster than the second CPU unit 300B with respect to the self-diagnosis process, and the first CPU unit 300A performs completion slower than the second CPU unit 300B with respect to the command execution process.

Therefore, the first CPU unit 300A and the second CPU unit 300B grasp the performance Ab of the own unit and the counterpart CPU unit with respect to each of the self-diagnosis process, the command execution process, and the I/O refresh process which are repeatedly executed. The first CPU unit 300A and the second CPU unit 300B each set the "waiting time Tw" for the synchronization check process of each process, using the performance Ab of the own CPU unit and the counterpart CPU unit related to each process. The details are described below.

(details of CPU unit)

Fig. 4 is a block diagram showing a configuration of a main part of the PLC 20 including the first CPU unit 300A and the second CPU unit 300B. The PLC 20 may include functional units, not shown, such as a power supply unit, an input unit, an output unit, and a communication unit, as in the PLC 10.

The first CPU unit 300A and the second CPU unit 300B are function units that collectively control the entire PLC10, as are the first CPU unit 100A and the second CPU unit 100B. The first CPU unit 300A and the second CPU unit 300B are duplexed in the PLC 20. That is, one of the first CPU unit 300A and the second CPU unit 300B is a CPU unit (ACT) of an execution system, and the other is a CPU unit (STB) of a standby system, and the states of the other are monitored by each other. If it is determined in the synchronization check process that an abnormality has occurred in the ACT, the STB replaces the CPU unit that has been the ACT so far and switches its own unit to the ACT to continue the operation. In the present embodiment, an example in which "the first CPU unit 300A is an ACT and the second CPU unit 300B is an STB" is described, but the same applies to the case in which "the first CPU unit 300A is an STB and the second CPU unit 300B is an ACT".

As shown in fig. 4, the PLC 20 includes a common register 200 capable of performing writing and reading of each of the first CPU unit 300A and the second CPU unit 300B duplexed in the PLC 20. Since the common register 200 has already been described, the details thereof are briefly described here.

In order to ensure the simplicity of description, the configuration that is not directly related to the present embodiment is omitted from the description and the block diagram. However, the PLC10 may also include the omitted configuration, depending on the actual implementation.

The first CPU unit 300A includes, as functional blocks, a capacity acquisition unit 310A, a process execution unit 120A, a waiting time setting unit 360A, and a determination unit 370A in addition to the storage unit 330A. The storage unit 330A stores the other-function table 340A and the own-function table 350A.

The waiting time setting unit 360A includes a first waiting time setting unit 361A, a second waiting time setting unit 362A, and a third waiting time setting unit 363A, and the judgment unit 370A includes a first judgment unit 371A, a second judgment unit 372A, and a third judgment unit 373A. The other function table 340A includes a first other function table 341A, a second other function table 342A, and a third other function table 343A. The local performance meter 350A includes a first local performance meter 351A, a second local performance meter 352A, and a third local performance meter 353A.

The second CPU unit 300B includes, as functional blocks, a capacity acquisition unit 310B, a process execution unit 120B, a waiting time setting unit 360B, and a determination unit 370B in addition to the storage unit 330B. The storage unit 330B stores the other-function table 340B and the own-function table 350B.

The waiting time setting unit 360B includes a first waiting time setting unit 361B, a second waiting time setting unit 362B, and a third waiting time setting unit 363B, and the determination unit 370B includes a first determination unit 371B, a second determination unit 372B, and a third determination unit 373B. The other function table 340B includes a first other function table 341B, a second other function table 342B, and a third other function table 343B. The local performance meter 350B includes a first local performance meter 351B, a second local performance meter 352B, and a third local performance meter 353B.

The first CPU unit 300A and the second CPU unit 300B shown in fig. 4 have the same configuration as the first CPU unit 100A and the second CPU unit 100B in embodiment 1. In the case where it is necessary to particularly distinguish between the structures commonly included in the first CPU unit 300A and the second CPU unit 300B, the structure of the first CPU unit 300A is denoted by "a" and the structure of the second CPU unit 300B is denoted by "B". Note that, regarding the configuration commonly included in each of the first CPU unit 300A and the second CPU unit 300B, the reference to "a" or "B" is omitted unless it is necessary to particularly distinguish which included configuration is included.

Each of the functional blocks such as the capability acquisition Unit 310, the process execution Unit 120, the wait time setting Unit 360, and the determination Unit 370 can be realized by, for example, a Central Processing Unit (CPU) or the like reading a program stored in a storage device (storage Unit 330) realized by a Read Only Memory (ROM), a Non-Volatile Memory (NVRAM), or the like into a Random Access Memory (RAM) or the like (not shown) and executing the program.

(details of functional blocks)

The capability acquisition unit 310 acquires information ("capability information") indicating the capability Aby (processing capability) of the duplexed CPU unit of the other party, which relates to the self-diagnosis process, the command execution process, and the I/O refresh process repeatedly executed by the process execution unit 120. Specifically, the capability acquisition unit 310 refers to the local capability table 350 of the CPU unit of the other party to acquire the performance information of the CPU unit of the other party relating to each of the self-diagnosis process, the command execution process, and the I/O refresh process. The capability acquisition unit 310 stores the acquired "performance information (other-device performance information) of the CPU unit on the other side, which is related to the self-diagnosis process, the command execution process, and the I/O refresh process, in the other-device capability table 340 of the own unit.

In particular, the capability acquiring unit 310 acquires the other-device performance information related to each process once in the "duplex process" illustrated in fig. 6 before the process executing unit 120 repeatedly executes the self-diagnosis process, the command execution process, and the I/O refresh process in this order.

The capability acquiring unit 310 refers to the first local capability table 351 of the duplexed counterpart CPU unit to acquire "performance information (other-device performance information for self-diagnosis)" which is related to the self-diagnosis process and indicates the performance Aby of the duplexed counterpart CPU unit. The capability acquiring unit 310 stores the acquired self-diagnosis separate-device performance information in the first separate-device capability table 341 of the self-unit.

The capability acquiring unit 310 refers to the second local capability table 352 of the duplexed counterpart CPU unit to acquire "capability information (other-party-for-command capability information) indicating the capability Aby of the duplexed counterpart CPU unit, which relates to the command execution processing". The capability acquiring unit 310 stores the acquired command execution separate-device capability information in the second separate-device capability table 342 of the self unit.

The capability acquiring unit 310 refers to the third local capability table 353 of the duplexed counterpart CPU unit to acquire "performance information (I/O refresh other-device performance information)" related to the I/O refresh process and indicating the performance Aby of the duplexed counterpart CPU unit. The capability acquisition unit 310 stores the acquired I/O refresh other-device performance information in the third other-device capability table 343 of the self-device.

Fig. 7 is a diagram for explaining a specific example of processing for "acquiring performance information Aby indicating the performance of the duplexed counterpart CPU unit" which is executed once in the "duplex processing". As shown in fig. 7, the capability acquiring unit 310A refers to the first local capability table 351B of the second CPU unit 300B to acquire "performance information (other-device performance information for self-diagnosis)" related to the self-diagnosis process and indicating the performance Aby of the second CPU unit 300B. The capability acquiring unit 310A stores the acquired self-diagnosis separate-device performance information in the first separate-device capability table 341A of the self-unit.

The capability acquiring unit 310B refers to the first local capability table 351A of the first CPU unit 300A to acquire "performance information (other-unit performance information for self-diagnosis)" related to the self-diagnosis process and indicating the performance Aby of the first CPU unit 300A. The capability acquiring unit 310B stores the acquired self-diagnosis separate-device performance information in the first separate-device capability table 341B of the self-unit.

The capability acquiring unit 310A refers to the second local capability table 352B of the second CPU unit 300B to acquire "capability information (other-unit-for-command performance information) indicating the capability Aby of the second CPU unit 300B relating to the command execution processing". The capability acquiring unit 310A stores the acquired command execution separate-device capability information in the second separate-device capability table 342A of the self unit.

The capability acquiring unit 310B refers to the second local capability table 352A of the first CPU unit 300A to acquire "capability information (other-unit-for-command-execution capability information) indicating the capability Aby of the first CPU unit 300A relating to the command execution processing". The capability acquiring unit 310B stores the acquired command execution separate-device capability information in the second separate-device capability table 342B of the self unit.

The capability acquiring unit 310A refers to the third local capability table 353B of the second CPU unit 300B to acquire "performance information (I/O refresh processing other-device performance information)" related to the I/O refresh processing and indicating the performance Aby of the second CPU unit 300B. The capability acquisition unit 310A stores the acquired I/O refresh processing separate-device capability information in the third separate-device capability table 343A of the self unit.

The capability acquiring unit 310B refers to the third local capability table 353A of the first CPU unit 300A to acquire "performance information (I/O refresh processing other-device performance information) indicating the performance Aby of the first CPU unit 300A relating to the I/O refresh processing". The capability acquiring unit 310B stores the acquired I/O refresh processing separate-device capability information in the third separate-device capability table 343B of the self unit.

As described in embodiment 1, the process execution unit 120 repeatedly executes the self-diagnosis process, the command execution process, and the I/O refresh process in this order, and when the execution of each process is completed, writes the word "the execution of each process has been completed in its own unit" to the shared register 200.

When the execution of each process is completed, the process execution unit 120 notifies the waiting time setting unit 360 and the determination unit 370 of "the execution of each process has been completed in its own unit". The process execution unit 120 may notify the wait time setting unit 360 of "the execution time of each process (the time from the start of execution to the completion of execution of each process)" together with the "the execution of each process by its own unit" being completed. That is, the process execution unit 120 may measure the "execution time of each process" using an internal timer, and notify the wait time setting unit 360 of the "execution time of each process" measured.

The waiting time setting unit 360 refers to the other-machine capability table 340 to acquire the other-machine capability information, and refers to the local capability table 350 to acquire the local capability information. The wait time setting unit 360 acquires the "execution of each process by its own unit" from the process execution unit 120. The wait time setting unit 360 calculates the execution time of each process while acquiring the "execution of each process has been started by the own unit" acquired by the process execution unit 120 before acquiring the "execution of each process has been completed by the own unit". That is, the wait time setting unit 360 calculates the execution time of each process based on the time "the self-unit has started execution of each process" measured by the internal timer and the time "the self-unit has completed execution of each process" measured by the internal timer. The execution time of each process may be measured by the process execution unit 120 using an internal timer, and notified from the process execution unit 120 to the waiting time setting unit 360.

The waiting time setting unit 360 calculates a "waiting time Tw" for the synchronization check process for each process based on the acquired other-device performance information, the own-device performance information, and the execution time of each process, and notifies the determination unit 370 of the calculated waiting time Tw. Specifically, the waiting time setting unit 360 calculates the "waiting time Tw" for the synchronization check process for each process as described below, using the other-device performance information, the local performance information, and the execution time of each process.

That is, when the "duplex counterpart CPU unit performance Aby" indicated by the other unit performance information is higher than the "own unit performance Abm" indicated by the own unit performance information, the wait time setting unit 360 sets the "normal wait time Two" to the "wait time Tw". When the performance Aby of the duplexed CPU unit of the partner is equal to the performance Abm of the own unit, the wait time setting unit 360 sets the "normal wait time Two" to the "wait time Tw".

The "normal waiting time Two" is a period of time that is common to the first CPU unit 300A and the second CPU unit 300B and has a predetermined length, and is set at the time of factory shipment of each unit, for example, and is updatable by the user. The "normal wait time Two" is a period set on the premise that the performances Ab (particularly, the performances Ab related to the self-diagnosis process, the command execution process, and the I/O refresh process) in the first CPU unit 300A and the second CPU unit 300B are equal to each other.

When the performance Aby of the duplexed counterpart CPU unit is lower than the performance Abm of the own unit, the latency setting unit 360 sets a period obtained by multiplying the execution time of each process by a value obtained by dividing the performance Abm of the own unit by the performance Aby of the counterpart CPU unit as the "adjustment latency Ta". When the performance Aby of the duplexed counterpart CPU unit is lower than the performance Abm of the own unit, the wait time setting unit 360 sets "wait time Tw" to a period obtained by adding "normal wait time Two to the adjustment wait time Ta (that is," normal wait time Two + adjustment wait time Ta ").

The "waiting time" for the synchronous inspection process related to the "self-diagnosis process" > the "waiting time Tw" for the synchronous inspection process related to the "self-diagnosis process" is set by the first waiting time setting unit 361.

The first latency setting unit 361 refers to the first other function table 341 to acquire the other device performance information for self-diagnosis, and refers to the first own function table 351 to acquire the own device performance information for self-diagnosis. The first latency setting unit 361 calculates the execution time of the self-diagnosis process based on the notification from the process execution unit 120 indicating that the self-diagnosis process has been started by the self-unit and the notification indicating that the self-diagnosis process has been completed by the self-unit.

The first wait time setting unit 361 calculates the "wait time Tw" for the synchronous check process related to the self-diagnosis process, based on the acquired self-diagnosis other device performance information and self-diagnosis local device performance information and the "execution time of the self-diagnosis process" obtained by the calculation.

Specifically, the first latency setting unit 361 calculates the "adjustment latency Ta relating to the self-diagnosis process" in consideration of the ratio of the "performance Abm of the self-diagnosis process" to the "performance Aby of the duplexed counterpart CPU unit relating to the self-diagnosis process". The first wait time setting unit 361 sets the "wait time Tw" for the synchronization check process related to the self-diagnosis process, to a period in which the calculated "adjustment wait time Ta" related to the self-diagnosis process is added to the "normal wait time Two related to the self-diagnosis process". When "Abm/Aby" is equal to or less than "1", the first wait time setting unit 361 sets "0" to the "adjustment wait time Ta relating to the self-diagnosis process". When "Abm/Aby" is greater than "1", the first latency setting unit 361 sets "the adjustment latency Ta relating to the self-diagnosis process" to "a value obtained by multiplying the execution time of the self-diagnosis process by" "Abm/Aby".

The first waiting time setting unit 361 notifies the "waiting time Tw for the synchronization check process concerning the self-diagnosis process" calculated by the above-described method to the determination unit 370.

"waiting time" for synchronization check processing relating to "command execution processing" > the "waiting time Tw" for synchronization check processing relating to "command execution processing" is set by the second waiting time setting portion 362.

The second latency setting unit 362 refers to the second other function table 342 to acquire the other-machine performance information for command execution, and refers to the second local function table 352 to acquire the local performance information for command execution. The second latency setting unit 362 calculates the execution time of the command execution process based on the notification from the process execution unit 120 indicating that the "own unit has started the execution of the command execution process" and the "own unit has completed the execution of the command execution process".

The second wait time setting unit 362 calculates the "wait time Tw" for the synchronization check processing concerning the command execution processing, based on the acquired other-device performance information for command execution and the local performance information for command execution, and the "execution time of command execution processing" obtained by the calculation.

Specifically, the second latency setting unit 362 calculates "the adjustment latency Ta relating to the command execution processing" in consideration of a ratio of "the performance Abm of the own unit relating to the command execution processing" to "the performance Aby of the duplexed counterpart CPU unit relating to the command execution processing". The second latency setting unit 362 sets a period in which the calculated "adjustment latency Ta for the command execution process" is added to the "normal latency Two for the command execution process" as the "latency Tw" for the synchronization check process for the command execution process. When "Abm/Aby" is equal to or less than "1", the second latency setting unit 362 sets "0" to the "adjustment latency Ta relating to the command execution process". When "Abm/Aby" is greater than "1", the second latency setting unit 362 sets "the adjustment latency Ta relating to the command execution processing" to "a value obtained by multiplying the execution time of the command execution processing of the own cell by" "Abm/Aby".

The first latency setting unit 361 notifies the "latency Tw for the synchronization check process concerning the command execution process" calculated by the above method to the determination unit 370.

"waiting time" for synchronization check processing relating to "I/O refresh processing" > waiting time Tw for synchronization check processing relating to "I/O refresh processing" is set by the third waiting time setting portion 363.

The third latency setting unit 363 acquires the other-device performance information for I/O refresh with reference to the third other-device performance table 343, and acquires the local performance information for I/O refresh with reference to the third local-device performance table 353. The third latency setting unit 363 calculates the execution time of the I/O refresh process based on the notification from the process execution unit 120 indicating that the "own cell has started the execution of the I/O refresh process" and the "own cell has completed the execution of the I/O refresh process".

The third latency setting unit 363 calculates the "latency Tw" for the synchronization check process related to the I/O refresh process, based on the acquired I/O refresh other-device performance information and I/O refresh local performance information and the "I/O refresh process execution time" obtained by the calculation.

Specifically, the third latency setting unit 363 calculates the "adjustment latency Ta for the I/O refresh process" in consideration of the ratio of the "performance Abm of the own unit relating to the I/O refresh process" to the "performance Aby of the duplexed counterpart CPU unit relating to the I/O refresh process". The third latency setting unit 363 sets a period in which the calculated "adjustment latency Ta for the I/O refresh process" is added to the "normal latency Two for the I/O refresh process" as the "latency Tw" for the synchronization check process for the I/O refresh process. When "Abm/Aby" is equal to or less than "1", the third latency setting unit 363 sets "0" to "adjustment latency Ta relating to the I/O refresh processing". When "Abm/Aby" is greater than "1", the third latency setting unit 363 sets "the adjustment latency Ta for the I/O refresh process" to "a value obtained by multiplying the execution time of the I/O refresh process of the own cell by" "Abm/Aby".

The third latency setting unit 363 notifies the determination unit 370 of "latency Tw for synchronization check processing with respect to I/O refresh processing" calculated in the above-described manner.

The determination unit 370 executes the synchronization check process after the wait time Tw notified from the wait time setting unit 360 has elapsed from the time "the own unit has completed execution of each process". For example, the determination unit 370 refers to the shared register 200 at a time point when the waiting time Tw has elapsed from a time point when "the own unit has completed execution of each process", and confirms whether or not execution of the duplexed counterpart CPU unit has completed with respect to a certain process for which the own unit has completed execution.

The determination unit 370 notified of "normal waiting time Two + adjustment waiting time Ta" as the waiting time Tw executes the standby processing from the time "the own unit has completed execution of each process" until the adjustment waiting time Ta elapses. Then, the determination unit 370 executes the synchronization check process after the execution of the standby process is completed (that is, after the adjustment waiting time Ta has elapsed from the time point "the own unit has completed the execution of each process"). That is, the determination unit 370 determines "whether or not the counterpart CPU unit can confirm that the execution of the process executed by the own unit has been completed until the normal waiting time Two elapses after the execution of the standby process is completed". In other words, the determination unit 370 determines whether or not the execution completion of the CPU unit on the other side can be confirmed with respect to the process that has been executed by the own unit until the normal waiting time Two elapses from the execution completion time point of the standby process.

The determination unit 370 notified of the "normal waiting time Two" as the waiting time Tw immediately executes the synchronization check process at a time point "the own unit has completed execution of each process". That is, the determination unit 370 determines "whether or not it can be confirmed that the CPU unit on the other side has completed execution of the process that has been executed by the CPU unit on its own until the normal waiting time Two elapses". In other words, the determination unit 370 determines whether or not the execution completion of the CPU unit on the other side can be confirmed, with respect to the processing that the own unit has already performed, from the execution completion time point of the own unit until the normal waiting time Two elapses.

< synchronous check process related to "self-diagnosis process > the first determination section 371 executes synchronous check process related to" self-diagnosis process ". That is, the first determination unit 371 confirms whether or not the counterpart CPU unit has completed execution of the self-diagnosis process from the time when execution of the self-diagnosis process of the own unit is completed to the time when "wait time Tw for the self-diagnosis process" notified from the first wait time setting unit 361 has elapsed. If it is not confirmed that the "counterpart CPU unit has completed execution of the self-diagnosis process" until "the waiting time Tw for the self-diagnosis process" elapses, the first determination unit 371 determines that an abnormality has occurred in the counterpart CPU unit.

< synchronization check processing relating to "command execution processing > the second decision section 372 executes synchronization check processing relating to" command execution processing ". That is, the second determination unit 372 checks whether or not the CPU unit of the other party has completed execution of the command execution process from the time when execution of the command execution process of the own unit is completed until the "wait time Tw for the command execution process" notified from the second wait time setting unit 362 elapses. If "the counterpart CPU unit has completed execution of the command execution processing" cannot be confirmed until "the wait time Tw for the command execution processing" elapses, the second judgment section 372 judges that an abnormality has occurred in the counterpart CPU unit.

< synchronization check processing relating to "I/O refresh processing > the third determination section 373 executes synchronization check processing relating to" I/O refresh processing ". That is, the third determination unit 373 confirms whether or not the opposing CPU cell has completed the execution of the I/O refresh process, from the time when the execution of the I/O refresh process of the own cell is completed, until the "wait time Tw for the I/O refresh process" notified from the third wait time setting unit 363 has elapsed. If it is not confirmed that "the counterpart CPU unit has completed execution of the command execution processing" until "the wait time Tw for the I/O refresh processing" elapses, the third determination unit 373 determines that an abnormality has occurred in the counterpart CPU unit.

The judgment unit 370A refers to the second register 220 of the shared register 200, and checks whether or not there is a write indicating that "the execution of the process execution unit 120B is completed" with respect to a certain process that the process execution unit 120A has completed execution. When the process execution unit 120A has completed executing a certain process, and there is no write in the second register 220 indicating that the process execution unit 120B has completed executing, the determination unit 370A determines that an abnormality has occurred in the second CPU unit 300B.

The judgment unit 370B refers to the first register 210 of the common register 200, and checks whether or not there is a write indicating that "the execution of the process execution unit 120A is completed" with respect to a certain process that the process execution unit 120B has completed execution. When the processing execution unit 120B has completed executing any of the processes, the determination unit 370B determines that an abnormality has occurred in the first CPU unit 300A if there is no write indicating that "the execution of the processing execution unit 120A has completed" in the first register 210.

(details of the storage section)

The storage unit 330 is a storage device that stores various data used by the first CPU unit 300A and the second CPU unit 300B. The storage unit 330 may store, in a non-transitory manner, (1) a control program, (2) an OS program, (3) an application program for executing various functions of each of the first CPU unit 300A and the second CPU unit 300B, and (4) various data read when the application program is executed, the control program being executed by each of the first CPU unit 300A and the second CPU unit 300B. The data (1) to (4) are stored in a nonvolatile storage device such as a Read Only Memory (ROM), a flash Memory, an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), and a Hard Disk Drive (HDD)). Each of the first CPU unit 300A and the second CPU unit 300B may include a temporary storage unit not shown. The temporary storage unit is a so-called work Memory that temporarily stores data used for calculation, calculation results, and the like in various processes executed by the first CPU unit 300A and the second CPU unit 300B, and includes a volatile storage device such as a Random Access Memory (RAM). Which data is stored in which storage device is appropriately determined according to the purpose of use, convenience, cost, physical limitations, and the like of each of the first CPU unit 300A and the second CPU unit 300B. The storage unit 330 also stores another capability table 340 and a local capability table 350.

The other-device capability table 340 stores other-device capability information, which is information indicating the capability Aby (processing capability) of the duplexed CPU unit of the other party. As described with reference to fig. 3, the capability acquiring unit 310 stores the other-device capability information acquired by referring to the own capability table 350 of the duplexed counterpart CPU unit in the other-device capability table 340 of the own unit.

The "performance information related to the self-diagnosis process and indicating the performance Aby of the duplexed counterpart CPU unit" stored in the first local performance table 351 of the duplexed counterpart CPU unit is stored in the first other performance table 341 by the performance acquisition unit 310.

The "performance information indicating the performance Aby of the duplexed counterpart CPU unit relating to the command execution processing" stored in the second local performance table 352 of the duplexed counterpart CPU unit is stored in the second other performance table 342 by the capability acquisition section 310.

The "performance information related to the I/O refresh processing and indicating the performance Aby of the duplexed counterpart CPU unit" stored in the third local performance table 353 of the duplexed counterpart CPU unit is stored in the third other performance table 343 by the performance acquiring section 310.

The local capability table 350 stores local capability information, which is information indicating the capability Abm (processing capability) of the local unit, and for example, stores local capability information indicating "how much capability (processing capability) the local unit has compared with the reference CPU unit". The local performance information is stored in the local performance table 350, for example, when the first CPU unit 300A and the second CPU unit 300B are shipped from the factory.

In the first local capability table 351, "performance information indicating the performance Abm of the own unit (in particular, the relative performance Abm with respect to" the performance Abb of the reference CPU unit relating to the self-diagnosis process ") relating to the self-diagnosis process is stored.

In the second local capability table 352, "capability information indicating the capability Abm of the own unit relating to the command execution processing (in particular, the relative capability Abm with respect to the" capability Abb of the reference CPU unit relating to the command execution processing ") is stored.

In the third local capability table 353, "performance information indicating the performance Abm of the own unit relating to the I/O refresh processing (in particular, the relative performance Abm with respect to" the performance Abb of the reference CPU unit relating to the I/O refresh processing ") is stored.

(arrangement of CPU Unit)

The first CPU unit 300A and the second CPU unit 300B having the configurations described above with reference to fig. 4 and the like are organized as follows for ease of understanding. That is, the first CPU unit 300A and the second CPU unit 300B are each a CPU unit duplexed in the PLC 20 (controller) similarly to the first CPU unit 100A and the second CPU unit 100B. Each of the first CPU unit 300A and the second CPU unit 300B includes a waiting time setting unit 360 (setting unit) and a determination unit 370. The wait time setting portion 360 sets the wait time Tw in consideration of the ratio of the performance Abm (processing capability) of the own unit and the performance Aby of the duplexed counterpart CPU unit. The determination unit 370 determines that an abnormality has occurred in the CPU unit of the other party, if the completion of the execution of the processing by the CPU unit of the other party cannot be confirmed from the time when the processing by the own unit is completed until the wait time Tw set by the wait time setting unit 360 elapses.

Therefore, the first CPU unit 300A and the second CPU unit 300B can set the appropriate waiting time Tw in consideration of the difference in the performance Ab between the own unit and the counterpart CPU unit, as in the first CPU unit 100A and the second CPU unit 100B. That is, the first CPU unit 300A and the second CPU unit 300B can accurately perform the synchronization check process without providing the unnecessary waiting time Tw, taking into account the difference in performance Ab between the duplexed counterpart CPU unit and the own unit.

In each of the first CPU unit 300A and the second CPU unit 300B, the processes (processes to be subjected to the synchronization check process) include a self-diagnosis process, a command execution process, and an I/O refresh process. The latency setting unit 360 (specifically, each of the first latency setting unit 361, the second latency setting unit 362, and the third latency setting unit 363) sets a latency Tw for each of the self-diagnosis process, the command execution process, and the I/O refresh process. The determination section 370 (specifically, each of the first determination section 371, the second determination section 372, and the third determination section 373) performs the determination, that is, performs the synchronization check process, with respect to each of the self-diagnosis process, the command execution process, and the I/O refresh process.

The first CPU unit 300A and the second CPU unit 300B can determine synchronization between the own unit and the counterpart CPU unit at the timing when execution of the self-diagnosis process, the command execution process, and the I/O refresh process is completed.

The first CPU unit 300A and the second CPU unit 300B each perform one-time duplex processing before sequentially repeating the self-diagnosis processing, the command execution processing, and the I/O refresh processing. The first CPU unit 300A and the second CPU unit 300B each acquire the performance Aby of the counterpart CPU unit from the counterpart CPU unit in the duplex processing.

The following effects are achieved: each of the first CPU unit 300A and the second CPU unit 300B can set the waiting time Tw used for the determination regarding each process in consideration of the performance Aby of the CPU unit on the other side acquired before the respective processes are repeatedly executed.

In each of the first CPU unit 300A and the second CPU unit 300B, the latency setting unit 360 sets the latency Tw of each of the self-diagnosis process, the command execution process, and the I/O refresh process as follows. That is, the latency setting unit 360 sets the latency Tw of each process in consideration of the ratio of the performance Abm of the self-unit to the performance Aby of the CPU unit of the other party with respect to the execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process. Specifically, the first latency setting unit 361 sets the latency Tw for the synchronization check process with respect to the self-diagnosis process, taking into account the ratio of the performance Abm of the self-unit to the performance Aby of the counterpart CPU unit, which is related to the self-diagnosis process. The second latency setting section 362 sets the latency Tw for the synchronization check processing with respect to the command execution processing, taking into account the ratio of the performance Abm of the own unit to the performance Aby of the counterpart CPU unit in relation to the command execution processing. The third latency setting section 363 sets the latency Tw for the synchronization check processing with respect to the I/O refresh processing, taking into account the ratio of the performance Abm of the own unit to the performance Aby of the counterpart CPU unit in relation to the I/O refresh processing.

The first CPU unit 300A and the second CPU unit 300B each set the waiting time Tw of each process in consideration of the difference in performance Ab between the own unit and the counterpart CPU unit, which is associated with each of the self-diagnosis process, the command execution process, and the I/O refresh process.

Therefore, the following effects are obtained: the first CPU unit 100A and the second CPU unit 100B can set the waiting time Tw of each process according to the performance Ab of each of the own CPU unit and the counterpart CPU unit related to each process.

(operation)

Fig. 6 is a diagram for explaining an outline of processing executed by each of the first CPU unit 300A and the second CPU unit 300B. The processing performed by each of the first CPU unit 300A and the second CPU unit 300B shown in fig. 6 is different from the processing performed by each of the first CPU unit 100A and the second CPU unit 100B shown in fig. 2 as follows.

That is, the first CPU unit 300A and the second CPU unit 300B grasp the performance Ab of the own unit and the counterpart CPU unit with respect to each of the self-diagnosis process, the command execution process, and the I/O refresh process which are repeatedly executed. The first CPU unit 300A and the second CPU unit 300B each set the "waiting time Tw" for the synchronization check process of each process, using the performance Ab of the own CPU unit and the counterpart CPU unit related to each process. The first CPU unit 300A and the second CPU unit 300B each determine whether or not "the execution of each process by the other CPU unit" is completed "from the execution completion time point of each process by the own unit until the" wait time Tw "for each process elapses.

Otherwise, "the processing performed by each of the first CPU unit 300A and the second CPU unit 300B" is the same as "the processing performed by each of the first CPU unit 100A and the second CPU unit 100B".

That is, the "processing executed by each of the first CPU unit 300A and the second CPU unit 300B" is a method for controlling the CPU units duplexed in the PLC 20 (controller), and includes a setting step and a determination step. The setting steps are as follows: the waiting time Tw is set in consideration of the ratio of the performance Abm of the own unit to the performance Aby of the duplexed counterpart CPU unit. The judging step is as follows: if the completion of the execution of the processing in the CPU unit of the other party cannot be confirmed from the time when the processing in the own unit is completed until the waiting time Tw set in the setting step elapses, it is determined that an abnormality has occurred in the CPU unit of the other party.

Therefore, the following effects are obtained: even when the performance Ab does not match between the own unit and the counterpart CPU unit, the "processing executed by each of the first CPU unit 300A and the second CPU unit 300B" can set the appropriate wait time Tw in consideration of the difference in performance Ab between the own unit and the counterpart CPU unit. Namely, the following effects are exhibited: the "processing executed by each of the first CPU unit 300A and the second CPU unit 300B" can accurately perform the synchronization check processing without providing the unnecessary waiting time Tw, taking into account the difference in performance Ab between the duplexed counterpart CPU unit and the own unit.

Modification example 4

Up to this point, an example in which the first CPU unit 100A and the second CPU unit 100B (or the first CPU unit 300A and the second CPU unit 300B) perform the synchronization check processing using the common register 200 has been described. However, the method of using the common register 200 is merely an example of a method of realizing the synchronization check processing. The synchronization check process can be realized by, for example, checking synchronization while communicating between the first CPU unit 100A and the second CPU unit 100B (or between the first CPU unit 300A and the second CPU unit 300B) via serial ports (serial ports). The first CPU unit 100A and the second CPU unit 100B (or the first CPU unit 300A and the second CPU unit 300B) may check each other that the execution of the processing of the other CPU unit is completed while performing communication using the serial ports of each other.

In addition, an example has been described so far in which the self-diagnosis process, the command execution process, and the I/O refresh process are sequentially and repeatedly executed, and after the execution of each of these processes is completed, the synchronization check process related to each of these processes is executed. However, in addition to the self-diagnosis process, the command execution process, and the I/O refresh process, other processes may be repeatedly executed in the same manner as the self-diagnosis process, the command execution process, and the I/O refresh process. At this time, the synchronization check process is also executed after the execution is completed with respect to the other processes.

For example, in addition to the self-diagnosis process, the command execution process, and the I/O refresh process, the "other communication process", that is, the transmission and reception of signals to and from a communication network different from the communication network that transmits and receives signals in the I/O refresh process, may be repeatedly executed. That is, the self-diagnosis process, the command execution process, the I/O refresh process, and the other communication processes may be repeatedly executed in this order, and after the execution of each of these processes is completed, the synchronization check process related to each of these processes may be executed.

[ implementation by software ]

The control blocks (particularly, the capability acquiring Unit 110, the process executing Unit 120, the latency setting Unit 160, the determining Unit 170, the capability acquiring Unit 310, the latency setting Unit 360, and the determining Unit 370) of the first CPU Unit 100A, the second CPU Unit 100B, the first CPU Unit 300A, and the second CPU Unit 300B may be implemented by a logic circuit (hardware) formed on an integrated circuit (IC chip) or the like, or may be implemented by software using a Central Processing Unit (CPU).

In the latter case, each of the first CPU unit 100A, the second CPU unit 100B, the first CPU unit 300A, and the second CPU unit 300B includes a CPU that executes instructions of a program that is software for realizing each function, a Read Only Memory (ROM) or a storage device (these are referred to as "recording media") in which the program and various data are recorded so as to be readable by a computer (or CPU), a Random Access Memory (RAM) in which the program is developed, and the like. And, the object of the present invention is achieved by reading and executing the program from the recording medium by a computer (or CPU). As the recording medium, "a tangible medium that is not temporary" may be used, and for example, a tape (tape), a disk (disk), a card (card), a semiconductor memory, a programmable logic circuit, or the like may be used. Further, the program may be supplied to the computer via an arbitrary transmission medium (a communication network, a broadcast wave, or the like) that can transmit the program. The present invention can also be realized as an embodiment of a data signal embedded in a carrier wave that embodies the program by electronic transmission.

(matters attached to notes)

A CPU unit of an embodiment of the present invention is a CPU unit duplexed in a controller, the CPU unit including: a setting unit that sets a waiting time in consideration of a ratio of a processing capacity of the own unit to a processing capacity of the duplexed counterpart CPU unit; and a determination unit configured to determine that an abnormality has occurred in the CPU unit of the other party if completion of execution of the processing in the CPU unit of the other party cannot be confirmed from a time point when execution of the processing in the own unit is completed until the wait time set by the setting unit elapses.

According to the configuration, the CPU unit determines synchronization of the own unit with the CPU unit of the partner using the wait time set in consideration of the ratio of the processing capabilities of the own unit and the CPU unit of the partner (i.e., coincidence of the processes that have been executed).

For example, when the performance of the CPU unit of the other side is higher than that of the CPU unit of the other side (that is, the processing execution speed is higher), the CPU unit sets a predetermined "normal waiting time" as the waiting time. In addition, when the performance Ab is equal between the counterpart CPU unit and the own unit, the control method sets a predetermined "normal waiting time" as the waiting time Tw.

In the case where the performance of the CPU unit of the other party is higher than that of the own unit, the CPU unit of the other party should have completed execution of a certain process at a point of time when the own unit has completed execution of the certain process. Further, in the case where the performance Ab is equal between the counterpart CPU unit and the own unit, the counterpart CPU unit should complete execution of a certain process at a point in time when the own unit has completed execution of the certain process.

Therefore, even when the performance of the counter CPU unit is higher than that of the own unit, the CPU unit can accurately determine whether or not an abnormality has occurred in the counter CPU unit by setting the "normal waiting time" as the waiting time.

For example, when the performance of the CPU unit of the other party is lower than that of the CPU unit of the other party (i.e., the processing execution speed is slow), the CPU unit sets a "period obtained by adding the normal latency to the adjustment latency in consideration of the performance difference" as the latency. Specifically, the adjustment waiting time is set to "a difference between a time point at which the execution of the process in the own unit is completed and a time point at which the execution of the process in the partner CPU unit is expected to be completed".

In a case where the performance of the CPU unit of the other party is lower than that of the own unit, the CPU unit of the other party has not completed execution of a certain process at a point of time when the own unit has completed execution of the certain process. Therefore, the CPU unit stands by to "a time point expected to be the completion of the execution of the processing in the counterpart CPU unit", and then determines: whether or not the execution of the processing in the counterpart CPU unit is completed can be confirmed until "normal waiting time" elapses. That is, the CPU unit determines: whether or not the execution of the processing in the counterpart CPU unit is completed can be confirmed from the execution completion time point of the processing in the own unit until a "period obtained by adding the normal waiting time to the adjustment waiting time" elapses.

Therefore, even when the performance of the CPU unit of the other party is lower than that of the CPU unit of the other party, the CPU unit sets the "period obtained by adding the normal waiting time to the adjustment waiting time" as the waiting time, and thereby the determination can be accurately performed.

As described above, the following effects are exhibited: the CPU unit can set the appropriate wait time in consideration of a difference in the processing capabilities of the own unit and the counterpart CPU unit even when the processing capabilities do not coincide in the own unit and the counterpart CPU unit. Namely, the following effects are exhibited: the CPU unit can accurately perform the synchronization check processing without setting the unnecessary waiting time in consideration of the difference in processing capability between the duplexed counterpart CPU unit and the own unit.

In the CPU unit according to an embodiment of the present invention, the processing may include a self-diagnosis process of diagnosing whether or not there is an abnormality in hardware of the CPU unit, a command execution process of generating a signal for controlling an external device other than the CPU unit of the other party, and an I/O refresh process of exchanging data with the external device other than the CPU unit of the other party, the setting unit may set the waiting time for each of the self-diagnosis process, the command execution process, and the I/O refresh process, and the determination unit may execute the determination for each of the self-diagnosis process, the command execution process, and the I/O refresh process.

According to this configuration, the CPU unit determines synchronization of the own unit with the CPU unit of the other party (i.e., coincidence of the executed processes) with respect to the self-diagnosis process, the command execution process, and the I/O refresh process, respectively.

Therefore, the following effects are obtained: the CPU unit may determine synchronization between the CPU unit itself and the CPU unit of the other party at a timing when execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process is completed.

The CPU unit according to an embodiment of the present invention may execute a duplex process before repeatedly executing the self-diagnosis process, the command execution process, and the I/O refresh process in this order, where the duplex process is a process of acquiring the processing capability of the CPU unit of the other party from the CPU unit of the other party.

According to the structure, the CPU unit acquires the processing capability of the CPU unit of the other side once before repeatedly executing the self-diagnosis process, the command execution process, and the I/O refresh process in this order. And the CPU unit sets the wait time for the determination regarding the respective processes in consideration of a ratio of the acquired processing capacity of the counterpart CPU unit to the processing capacity of the own unit.

Therefore, the following effects are obtained: the CPU unit may set the wait time for the determination regarding each of the processes in consideration of a processing capability of the counterpart CPU unit acquired in advance before the respective processes are repeatedly executed.

In the CPU unit according to an embodiment of the present invention, the setting unit may set the waiting times of the self-diagnosis process, the command execution process, and the I/O refresh process in consideration of a ratio of a processing capacity of the self-unit to a processing capacity of the CPU unit of the other party with respect to the execution of the self-diagnosis process, the command execution process, and the I/O refresh process.

According to the above configuration, the CPU unit sets the wait time of each process in consideration of a difference in processing capabilities of the own unit and the counterpart CPU unit regarding the execution of each of the self-diagnosis process, the command execution process, and the I/O refresh process.

Therefore, the following effects are obtained: the CPU unit may set the respective waiting times of the self-diagnosis process, the command execution process, and the I/O refresh process according to respective processing capacities of the own unit and the counterpart CPU unit related to the respective processes.

A control method of an embodiment of the present invention is a control method of a CPU unit subjected to duplexing in a controller, the control method including: a setting step of setting a waiting time in consideration of a ratio of a processing capacity of the own unit to a processing capacity of the duplexed counterpart CPU unit; and a determination step of determining that an abnormality has occurred in the CPU unit of the other party if completion of execution of the processing in the CPU unit of the other party cannot be confirmed from a time point when execution of the processing in the own unit is completed until the wait time set in the setting step elapses.

According to the method, the control method determines synchronization of the self unit with the counterpart CPU unit (i.e., coincidence of the processes that have been completed executed) using the wait time set in consideration of the ratio of the processing capacities of the self unit and the counterpart CPU unit.

For example, in the case where the performance of the partner CPU unit is higher than that of the own unit (i.e., the processing execution speed is fast), the control method sets a predetermined "normal wait time" as the wait time. In addition, when the performance Ab is equal between the counterpart CPU unit and the own unit, the control method sets a predetermined "normal waiting time" as the waiting time Tw.

Therefore, even when the performance of the counter CPU unit is higher than that of the own unit, the control method can accurately determine whether or not an abnormality has occurred in the counter CPU unit by setting the "normal waiting time" as the waiting time.

For example, in the case where the performance of the partner CPU unit is lower than that of the own unit (i.e., the processing execution speed is slow), the control method sets "a period in which the normal latency is added to an adjustment latency in consideration of the performance difference" as the latency. Specifically, the adjustment waiting time is set to "a difference between a time point at which the execution of the process in the own unit is completed and a time point at which the execution of the process in the partner CPU unit is expected to be completed".

In a case where the performance of the CPU unit of the other party is lower than that of the own unit, the CPU unit of the other party has not completed execution of a certain process at a point of time when the own unit has completed execution of the certain process. Therefore, the control method stands by to "a time point expected to be the completion of the execution of the processing in the counterpart CPU unit", and then determines: whether or not the execution of the processing in the counterpart CPU unit is completed can be confirmed until "normal waiting time" elapses. That is, the control method determines that: whether or not the execution of the processing in the counterpart CPU unit is completed can be confirmed from the execution completion time point of the processing in the own unit until a "period obtained by adding the normal waiting time to the adjustment waiting time" elapses.

Therefore, when the performance of the CPU unit of the other party is lower than that of the CPU unit of the own party, the control method sets the "period obtained by adding the adjustment waiting time to the normal waiting time" as the waiting time, thereby making it possible to accurately perform the determination.

As described above, the following effects are exhibited: the control method is capable of setting the appropriate wait time in consideration of a difference in the processing capabilities of the own unit and the counterpart CPU unit even in a case where the processing capabilities do not coincide in the own unit and the counterpart CPU unit. Namely, the following effects are exhibited: the control method takes into account the difference in processing capacity between the duplexed counterpart CPU unit and the own unit, and can accurately perform the synchronization check processing without setting unnecessary waiting time.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and embodiments obtained by appropriately combining technical components disclosed in different embodiments are also included in the technical scope of the present invention.

Description of the symbols

10：PLC

20：PLC

100A: first CPU Unit (CPU Unit)

100B: second CPU Unit (CPU Unit)

300A: first CPU Unit (CPU Unit)

300B: second CPU Unit (CPU Unit)

160: time setting unit (setting unit)

360: time setting unit (setting unit)

170: determination unit

370: determination unit

Ab: performance (throughput)

Tw: waiting time

Claims

1. A central processing unit that is duplexed in a controller, the central processing unit comprising:

a setting unit for setting the waiting time in consideration of the ratio of the processing capacity of the self-unit to the processing capacity of the duplexed counterpart central processor unit; and

and a determination unit configured to determine that an abnormality has occurred in the other cpu unit if completion of execution of the process in the other cpu unit cannot be confirmed from a time point when execution of the process in the own unit is completed until the wait time set by the setting unit elapses.

2. The central processor unit of claim 1, wherein

The processing includes self-diagnosis processing for diagnosing whether or not the hardware of the self-unit is abnormal, command execution processing for generating a signal for controlling an external device other than the other central processing unit, and input/output refresh processing for exchanging data with the external device other than the other central processing unit,

the setting section sets the wait time for each of the self-diagnosis process, the command execution process, and the input/output refresh process,

the determination unit performs the determination with respect to each of the self-diagnosis process, the command execution process, and the input/output refresh process.

3. The central processor unit of claim 2, wherein

Executing one-time duplex processing, which is processing of acquiring the processing capability of the counterpart central processing unit from the counterpart central processing unit, before the self-diagnosis processing, the command execution processing, and the input/output refresh processing are repeatedly executed in order.

4. Central processor unit according to claim 2 or 3, wherein

The setting unit sets the wait times of the self-diagnosis process, the command execution process, and the input/output refresh process in consideration of a ratio of a processing capability of the self-unit to a processing capability of the counter central processor unit with respect to execution of the self-diagnosis process, the command execution process, and the input/output refresh process.

5. A control method of a central processing unit duplexed in a controller, the control method comprising:

setting step, considering the ratio of the processing capacity of the self unit and the processing capacity of the duplex opposite CPU unit to set the waiting time; and

a determination step of determining that an abnormality has occurred in the other cpu unit if completion of execution of the processing in the other cpu unit cannot be confirmed from a time point when execution of the processing in the own unit is completed until the wait time set in the setting step elapses.

6. An information processing program for causing a computer to function as the central processing unit according to any one of claims 1 to 4, wherein the information processing program is for causing a computer to function as the respective sections.

7. A computer-readable recording medium on which the information processing program according to claim 6 is recorded.