WO2020062869A1 - 指纹感测装置及其制造方法 - Google Patents

指纹感测装置及其制造方法 Download PDF

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Publication number
WO2020062869A1
WO2020062869A1 PCT/CN2019/085663 CN2019085663W WO2020062869A1 WO 2020062869 A1 WO2020062869 A1 WO 2020062869A1 CN 2019085663 W CN2019085663 W CN 2019085663W WO 2020062869 A1 WO2020062869 A1 WO 2020062869A1
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Prior art keywords
layer
metal oxide
area
polysilicon layer
sensing device
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English (en)
French (fr)
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颜源
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/94—Hardware or software architectures specially adapted for image or video understanding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/70—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising bypass diodes
    • H10F19/75—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising bypass diodes the bypass diodes being integrated or directly associated with the photovoltaic cells, e.g. formed in or on the same substrate

Definitions

  • the present disclosure relates to the technical field of panel recognition, and in particular, to a fingerprint sensing device and a manufacturing method thereof.
  • Fingerprint recognition as a biometric method has recently attracted widespread attention, especially in mobile payment, and it has a broad prospect.
  • Existing fingerprint identification methods also include optical, capacitive, microwave, temperature, and ultrasonic methods.
  • the traditional optical sensor method cannot achieve lightness and thinness, especially under the requirements of high resolution.
  • Traditional devices are bulky and cannot be portable, so it is difficult to integrate them into devices such as mobile phones.
  • other methods solve the problem of thinness and lightness, they cannot implement large-area arrays or combine other functions, and the process is complicated and the cost is high.
  • FIG. 1 shows a pixel unit of an amorphous silicon flat-panel detector in the prior art.
  • a schematic cross-sectional view shows that a plurality of flat-detector pixel units are formed on the transparent substrate 1.
  • Each flat-detector pixel unit includes a thin film transistor 3 and an amorphous silicon photodiode.
  • the amorphous silicon photodiode includes a surface formed on the transparent substrate 1.
  • a first light-shielding layer 2, a first insulating layer 4, a drain electrode layer 5, an N-type layer 6, an intermediate layer 7, a P-type layer 8, and a contact electrode 9 are sequentially formed on the dielectric layer 10.
  • the crystalline silicon photodiode is insulated, a second light-shielding layer 12 is formed on the surface of the thin film transistor 3 and the dielectric layer 10 in a part where light is not required, a connection electrode 11 is formed on the contact electrode 9, and the second light-shielding layer 12 and the connection electrode 11 are formed.
  • a passivation layer 13 is formed on the top.
  • the first light-shielding layer 2 is in the same metal layer as the gate of the thin film transistor 3, and the drain electrode layer 5 is in the same metal layer as the drain of the thin film transistor 3.
  • this amorphous silicon photodiode The main part is the layered structure of the P-type layer 8, the intermediate layer 7, and the N-type layer 6. Therefore, the thickness of the amorphous silicon flat panel detector is about the thickness of the drain of the thin film transistor 3 and the amorphous silicon is superimposed thereon.
  • the thickness of the photodiode stack, and the thickness of the intermediate layer 7 in the amorphous silicon photodiode is about 1 micron, which makes the thickness of the amorphous silicon flat panel detector larger, and the optical path length of the incident light in the pixel unit of the flat panel detector. Longer, it may enter the adjacent pixel unit and cause interference.
  • the pixel unit of the above-mentioned flat panel detector includes a discrete thin film transistor 3 and an amorphous silicon photodiode. The thin film transistor 3 and the amorphous silicon photodiode are separately provided, that is, there is a gap between the thin film transistor 3 and the amorphous silicon photodiode.
  • a certain distance makes the area occupied by the pixel unit of the flat panel detector larger, which in turn makes the resolution lower.
  • the amorphous silicon photodiode needs to be manufactured separately after the thin film transistor 3 is formed, and multiple steps of film formation and photolithography processes are required, making the production cost higher. If such an amorphous silicon flat panel detector is used in fingerprint identification and other fields, there will be defects of higher production cost and lower resolution, which will limit its application to mobile devices such as mobile phones.
  • amorphous silicon flat panel detectors are used in fingerprint identification and other fields, and they have the disadvantages of higher production costs and lower resolution, which will limit their application to mobile devices such as mobile phones.
  • the present disclosure uses a low-temperature polysilicon technology to prepare a thin film transistor.
  • a heterojunction photodiode is formed by an N-type metal oxide layer and a P-type polysilicon layer, and the polysilicon thin film transistor and the heterojunction photodiode are integrated into a whole.
  • the structure provides a low-temperature polysilicon fingerprint sensing device with low production cost and high resolution, and a manufacturing method thereof, so as to overcome the above defects.
  • the present disclosure provides a fingerprint sensing device and a manufacturing method thereof.
  • the device includes: a pixel substrate, a plurality of sensing pixel units are formed on the pixel substrate, and each of the sensing pixel units has a An identification area and a reading area, each of the sensing pixel units includes: a patterned light-shielding layer provided on the identification area and the reading area; a polysilicon layer provided on the patterned light-shielding layer; A gate layer is disposed on the polysilicon layer in the read region; a patterned dielectric layer is disposed on the gate layer in the read region; a metal oxide layer is disposed On the polysilicon layer in the identification area; and a source and drain metal film layer disposed on the metal oxide layer in the identification area and the patterned intermediary in the read area On the electrical layer; wherein the patterned dielectric layer is disposed on both sides of the metal oxide layer in the identification area, but does not cover the metal oxide layer.
  • the polysilicon layer is a P-type polysilicon layer.
  • the metal oxide layer is an N-type metal oxide layer.
  • the N-type metal oxide layer includes a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and cadmium tin.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum zinc oxide
  • cadmium tin one or more of the group consisting of oxide, antimony tin oxide, zinc tin oxide, zinc oxide (ZnO), and tin dioxide (SnO 2 ).
  • the interface between the polysilicon layer and the metal oxide layer is an uneven structure.
  • the present disclosure further provides a fingerprint sensing device and a manufacturing method thereof.
  • the device includes: a pixel substrate, a plurality of sensing pixel units are formed on the pixel substrate, and each of the sensing pixel units has An identification area and a reading area, each of the sensing pixel units includes: a patterned light-shielding layer provided on the identification area and the reading area; a polysilicon layer provided on the patterned light-shielding layer A gate layer disposed on the polysilicon layer in the read region, a patterned dielectric layer disposed on the gate layer in the read region, a metal oxide layer, Disposed on the polysilicon layer in the identification area; and a source-drain metal film layer disposed on the metal oxide layer in the identification area and the patterning in the read area On the dielectric layer.
  • the polysilicon layer is a P-type polysilicon layer.
  • the metal oxide layer is an N-type metal oxide layer.
  • the N-type metal oxide layer includes a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and cadmium tin.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum zinc oxide
  • cadmium tin one or more of the group consisting of oxide, antimony tin oxide, zinc tin oxide, zinc oxide (ZnO), and tin dioxide (SnO 2 ).
  • the interface between the polysilicon layer and the metal oxide layer is an uneven structure.
  • the present disclosure further provides a method for manufacturing a fingerprint sensing device, including: providing a pixel substrate; forming a plurality of sensing pixel units on the pixel substrate, each of the sensing pixel units having an identification area; And a reading area; forming a light shielding layer on the identification area and the reading area on the pixel substrate, patterning the light shielding layer to form a patterned light shielding layer; forming a polysilicon layer on the identification area On the patterned light-shielding layer of the read area; forming a gate layer on the polysilicon layer of the read area; depositing a dielectric layer on the identification area and the read area On the polysilicon layer; patterning the dielectric layer to form a patterned dielectric layer so that the patterned dielectric layer is formed only on the polysilicon layer in the read area; depositing and patterning a metal oxide An object layer on the polysilicon layer without the patterned dielectric layer; and depositing a source and drain metal film layer on the metal
  • the polysilicon layer is a P-type polysilicon layer.
  • the metal oxide layer is an N-type metal oxide layer.
  • the N-type metal oxide layer includes a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum zinc oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum zinc oxide
  • an interface between the polysilicon layer and the metal oxide layer has an uneven structure.
  • the fingerprint sensing device and manufacturing method provided by the present disclosure use a low-temperature polysilicon technology to prepare a thin film transistor, and form a heterojunction photodiode through an N-type metal oxide layer and a P-type polysilicon layer.
  • the photodiode recognizes a signal reflected from a finger.
  • the light beam that is, the light intensity change of the light beam reflected by the fingerprint can be recognized by the photodiode and converted into photocurrent.
  • the thin film transistor reads and recognizes the photocurrent generated by the photodiode, thereby achieving the fingerprint identification function.
  • the interface between the N-type metal oxide layer and the P-type polysilicon layer presents a rough / concavo-convex interface
  • a large-area heterojunction contact area is formed between the N-type metal oxide layer and the P-type polysilicon layer, which is beneficial to fingerprints.
  • the absorption of reflected light increases the separation ability of electron-hole pairs in the P-type polysilicon layer.
  • the thin film transistor and the heterojunction photodiode are implemented together in an integrated structure, eliminating the need for complicated film formation and photolithography processes.
  • FIG. 1 is a schematic diagram of a pixel unit structure of a conventional flat panel sensor.
  • FIG. 2 is a schematic diagram of a structure of a sensing pixel unit of a fingerprint sensing device of the present disclosure.
  • 3A-3E are schematic flowcharts of a method for manufacturing a fingerprint sensing device according to the present disclosure.
  • FIG. 4 is a schematic diagram of steps of a manufacturing method of a fingerprint sensing device according to the present disclosure.
  • FIG. 2 is a schematic diagram of a structure of a sensing pixel unit of a fingerprint sensing device of the present disclosure.
  • a fingerprint sensing device for detecting a finger 300 includes a pixel substrate 101.
  • a plurality of sensing pixel units 102 (one sensing pixel unit 102 is shown in the figure) are formed on the pixel substrate 101.
  • Each of the sensing pixel units 102 has an identification area A and a reading area R.
  • the identification area A photodiode structure is provided on A to identify the intensity change of a signal beam L2 reflected by the finger 300 and convert it into a photocurrent form; the read area R is provided with a thin film transistor (Thin Film Transistor (TFT) structure to read and identify the photocurrent generated by the aforementioned photodiode.
  • TFT Thin Film Transistor
  • Each of the sensing pixel units 102 includes a patterned light-shielding layer 103 provided in the recognition area A and the reading area R, and more specifically, the patterned light-shielding provided in the recognition area A
  • the layer 103 is discontinuous from the patterned light-shielding layer 103 provided in the reading area R; a polysilicon layer 104 is provided on the patterned light-shielding layer corresponding to the identification area A and the reading area R 103; a gate layer 105 is disposed on the polysilicon layer 104 in the reading region R; a patterned dielectric layer (the third dielectric layer 106 described below) is disposed on the read On the gate layer 105 in the region R; a metal oxide layer 107 is disposed on the polysilicon layer 104 in the identification region A; and a source / drain metal film layer 108 is disposed on the identification On the metal oxide layer 107 in the region A and on the patterned dielectric layer (that is, the third dielectric layer 106 described below) in
  • a light emitting unit (not shown) is used to emit a sensing beam L1 to the finger 300, and the finger 300 reflects the sensing beam L1 into a signal beam L2.
  • the above signal beam L2 is not limited to the reflected light beam from the surface of the finger 300 shown in FIG. 1, but also includes the light beam reflected by the tissue inside the finger 300 after penetrating the surface of the finger 300.
  • FIG. 1 is only an exemplary drawing. A light beam is not intended to limit the present disclosure.
  • FIG. 1 illustrates a schematic diagram of one of the sensing pixel units 102.
  • the sensing pixel unit 102 includes a photodiode on the recognition area A and a thin film transistor on the reading area R.
  • the photodiode includes a stacked polysilicon layer 104 and a metal oxide layer 107. More specifically, the polysilicon layer 104 is a P-type polysilicon layer, and the metal oxide layer 107 is an N-type metal oxide layer. The N-type metal oxide layer is stacked on the P-type polysilicon layer.
  • a first dielectric layer 111 is disposed between the patterned light-shielding layer 103 and the polysilicon layer 104, and the P-type polysilicon layer is disposed on the first corresponding to the identification area A and the read area R.
  • the first dielectric layer 111 may be formed by a chemical vapor deposition (CVD) method, such as a low temperature chemical vapor deposition (LTCVD) method, a low pressure chemical vapor deposition (LPCVD) method, and a fast thermal chemical vapor deposition (LTCVD) method.
  • CVD chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • a gate metal layer (not shown) is formed on the P-type polysilicon layer corresponding to the read area R, and the gate metal layer is patterned to the polysilicon layer in the read area R
  • the gate layer 105 is formed at a predetermined position on 104.
  • a second dielectric layer 112 is disposed between the gate layer 105 and the polysilicon layer 104, and the second dielectric layer 112 corresponds to the gate layer 105 after the above patterning.
  • the patterned dielectric layer is a third dielectric layer 106, which is disposed on the polysilicon layer 104 in the reading area R, and is disposed on the polysilicon layer 104 in the identification area A.
  • the two sides of the metal oxide layer 107 are not covered by the metal oxide layer 107.
  • the thickness of the third dielectric layer 106 is greater than the thickness of the metal oxide layer 107.
  • the third dielectric layer 106 is formed on the gate layer 105, and the third dielectric layer 106 forms active / drain region contact holes 151 on both sides corresponding to the gate layer 105.
  • the source / drain formed by the source / drain metal film layer 108 is electrically connected to the polysilicon layer 104 through the source / drain region contact hole 151.
  • the metal oxide layer 107 includes a material selected from Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), Cadmium tin oxide, antimony tin oxide, zinc tin oxide, zinc oxide (ZnO) and tin dioxide (SnO 2 ).
  • the material of the metal oxide layer 107 is indium tin oxide (ITO).
  • the metal oxide layer 107 is only disposed on the polysilicon layer 104 in the identification area A, that is, the identification area A corresponding to the photodiode.
  • an uneven structure 200 is formed at a boundary between the polysilicon layer 104 and the metal oxide layer 107, and the uneven structure 200 has a rough shape, an uneven shape, and a mutual shape. Chimeric patterns and other structures, but not limited to this. Due to the uneven structure 200 described above, the interface between the polysilicon layer 104 and the metal oxide layer 107 will have a larger contact area, that is, a larger area is formed between the N-type metal oxide layer and the P-type polysilicon layer. The heterojunction contact area is conducive to the absorption of the signal beam L2 reflected by the finger, and increases the separation ability of electron-hole pairs in the P-type polysilicon layer.
  • the polysilicon layer 104 is disposed on the first dielectric layer 111 of the identification area A and the read area R, that is, the polysilicon layer 104 is formed on the photodiode of the identification area A and
  • the gate layer 105 is disposed above the patterned light-shielding layer 103, and there is no need to provide a gap between the metal oxide layer 107 and the polysilicon layer 104.
  • the intermediate layer avoids defects caused by the large thickness of the intermediate layer in the amorphous silicon photodiode in the prior art, and does not require complicated film formation and photolithography processes in the manufacturing process.
  • FIGS. 3A-3E to 4 and FIG. 2 are schematic diagrams of steps and processes of a method for manufacturing a fingerprint sensing device according to the present disclosure.
  • the method for manufacturing a fingerprint sensing device of the present disclosure includes: Step S01: providing a pixel substrate 101; Step S02: forming a plurality of sensing pixel units 102 on the pixel substrate 101, each of the sensing pixel units having an identification area A And a reading area R; step S03: forming a light-shielding layer on the identification area A and the reading area R on the pixel substrate 101, and patterning the light-shielding layer to form a patterned light-shielding layer 103; step S04: forming a polysilicon layer 104 on the patterned light-shielding layer 103 in the identification area A and the reading area R; step S05: forming a gate layer 105 on the polysilicon in the reading area R On layer 104; step S06: depositing a dielectric layer on the polysili
  • step S03 further includes forming a light-shielding layer on the identification area A and the reading area R on the pixel substrate using a film-forming process, and patterning the area using a yellow light process.
  • the light-shielding layer forms a patterned light-shielding layer 103, as shown in FIG. 3A.
  • step S04 a chemical vapor deposition process is used to form the polysilicon layer 104 on the patterned light-shielding layer 103.
  • the patterned light-shielding layer 103 is further included.
  • a first dielectric layer 111 is deposited thereon, as shown in FIG. 3B.
  • the polysilicon material forming the polysilicon layer 104 is subjected to laser low temperature annealing at the first dielectric in the identification area A and the read area R.
  • the polysilicon layer 104 is formed on the layer 111, wherein the polysilicon layer 104 is a P-type polysilicon layer, and the polysilicon layer 104 is patterned.
  • a gate metal layer (not shown) is formed on the polysilicon layer 104 in the read region R, and the gate metal layer is patterned to be used in all regions in the read region R.
  • the gate layer 105 is formed at a predetermined position on the polysilicon layer 104.
  • a second dielectric layer 112 is provided between the gate layer 105 and the polysilicon layer 104.
  • the above patterning corresponds to the gate layer 105.
  • source and drain doping is performed on the polysilicon layer 104 by using the gate layer 105 and the second dielectric layer 112 as masks.
  • the regions of the polysilicon layer 104 corresponding to the gate layer 105 and the second dielectric layer 112 are not ion-doped.
  • the patterned dielectric layer is a third dielectric layer 106.
  • the step of patterning the third dielectric layer 106 includes: forming a third dielectric layer 106 with the gate; The source / drain contact hole 151 corresponding to the electrode layer 105, as shown in FIG. 3D, a source / drain (not shown) formed by the source / drain metal film layer 108 subsequently passes through the source / drain region.
  • the contact hole 151 is electrically connected to the polysilicon layer 104.
  • the third dielectric layer 106 insulates the photodiode in the recognition area A from the thin film transistor in the reading area R.
  • step S08 the metal oxide layer 107 is deposited on the remaining portion of the polysilicon layer 104, that is, in the above step, a third dielectric is formed on the polysilicon layer 104 corresponding to the read region R.
  • Layer 106 so the metal oxide layer 107 is deposited on the polysilicon layer 104 without the third dielectric layer 106, that is, the metal oxide layer 107 is correspondingly formed in the corresponding region of the identification area A. Said on the polysilicon layer 104. Therefore, a large-area heterojunction contact region is formed between the metal oxide layer 107 and the polysilicon layer 104.
  • a part of the identification area constitutes a photodiode
  • a part of the reading area constitutes a thin film transistor.
  • the photodiode includes a stacked polysilicon layer 104 and a metal oxide layer 107.
  • the polysilicon layer 104 is a P-type polysilicon layer
  • the metal oxide layer 107 is an N-type metal oxide layer.
  • a source / drain metal film layer 108 is deposited on the third dielectric layer 106, and a source / drain formed by the source / drain metal film layer 108 is patterned through the source / drain region contact hole.
  • 151 is electrically connected to the polysilicon layer 104, as shown in FIG. 3E. That is, the formed source / drain are electrically connected to the metal oxide layer 107 and the polysilicon layer 104, respectively, and are used to transmit a photocurrent formed by a signal beam L2 reflected from a finger and converted by a photodiode.
  • the source / drain is used to assist the movement of the excited electron holes in the metal oxide layer 107 and the polysilicon layer 104 and transmit the photocurrent formed by the electron holes.
  • the interface between the polysilicon layer 104 and the metal oxide layer 107 is an uneven structure 200, and the uneven structure 200 is a rough structure, a concave-convex structure, a mutual-fitting structure, and the like, but Not limited to this. Due to the aforementioned uneven structure, the junction of the polysilicon layer 104 and the metal oxide layer 107 will have a larger contact area, that is, a large-area heterogeneity will be formed between the N-type metal oxide layer and the P-type polysilicon layer. The junction area of the junction facilitates the absorption of the light reflected by the fingerprint and increases the separation ability of electron-hole pairs in the P-type polysilicon layer.
  • the P-type polysilicon layer is formed on the same horizontal layer structure of the photodiode in the recognition area A and the thin film transistor in the reading area R.
  • the photodiode and the thin film transistor are prepared at the same time, and the gate layer 105 is provided in Above the patterned light-shielding layer 103, there is no need to provide an intermediate layer between the metal oxide layer 107 and the polysilicon layer 104, which avoids the large thickness of the intermediate layer in the amorphous silicon photodiode in the prior art. And there is no need for complicated film formation and photolithography processes in the manufacturing process.
  • the fingerprint sensing device and manufacturing method provided by the present disclosure use a low-temperature polysilicon technology to prepare a thin film transistor, and form a heterojunction photodiode through an N-type metal oxide layer and a P-type polysilicon layer.
  • the photodiode recognizes a signal reflected from a finger.
  • the light beam that is, the light intensity change of the light beam reflected by the fingerprint can be recognized by the photodiode and converted into photocurrent.
  • the thin film transistor reads and recognizes the photocurrent generated by the photodiode, thereby achieving the fingerprint identification function.

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Abstract

一种面板识别技术，尤其指一种指纹感测装置及其制造方法，所述装置包括：一像素基板，其上形成多个感测像素单元，各所述感测像素单元具有一识别区与一读取区，各所述感测像素单元包括：一图案化遮光层，设置于所述识别区与读取区；一多晶硅层，设置于所述图案化遮光层上；一栅极层，设置于所述读取区内的所述多晶硅层上；一图案化介电层，设置于所述读取区内的所述栅极层上；一金属氧化物层，设置于所述识别区内的所述多晶硅层上；以及一源漏极金属膜层，设置于所述识别区内的所述金属氧化物层上与所述读取区内的所述图案化介电层上，达到无需复杂的成膜与光刻工艺且分辨率较高的有益效果。

Description

指纹感测装置及其制造方法 技术领域
本揭示涉及面板识别技术领域，尤其涉及一种指纹感测装置及其制造方法。
 背景技术
指纹识别作为生物识别方式在最近引起了广泛的关注，尤其在移动支付上更具有广阔的前景。现有指纹识别的方法也包括了光学、电容式、微波，温度及超声波等多种方式。但是，传统的光学传感器方式无法实现轻薄，尤其是在高分辨率的要求下，传统设备体积庞大无法便携，因此很难集成到手机这样的设备中。其他的方式虽然解决轻薄的问题，但是无法实现大面积阵列，或无法结合其他功能，而且工艺复杂，成本高。
现有技术中的医疗用非晶硅平板探测器即是一种传统光学传感器，包括非晶硅光电二极管与薄膜晶体管，图1示出了现有技术一种非晶硅平板探测器像素单元的剖面示意图，在透明基板1上形成有多个平板探测器像素单元，每个平板探测器像素单元包括：薄膜晶体管3与非晶硅光电二极管，其中非晶硅光电二极管包括形成于透明基板1表面上依次形成的第一遮光层2、第一绝缘层4，漏极电极层5，N型层6，中间层7，P型层8，以及接触电极9，介质层10将薄膜晶体管3与非晶硅光电二极管绝缘，在薄膜晶体管3以及部分无需光照的区域的介质层10表面形成有第二遮光层12，在接触电极9上形成有连接电极11，在第二遮光层12和连接电极11的上方形成钝化层13。其中第一遮光层2与薄膜晶体管3的栅极在同一金属层，漏极电极层5与薄膜晶体管3的漏极在同一金属层，从图1中可以看出，这种非晶硅光电二极管的主要部分为P型层8、中间层7以及N型层6的层迭结构，因此，非晶硅平板探测器的厚度大约是在薄膜晶体管3的漏极的厚度上又叠加了非晶硅光电二极管的叠层厚度，而非晶硅光电二极管中的中间层7的厚度在1微米左右，使得非晶硅平板探测器的厚度较大，入射光在平板探测器的像素单元中的光程较长，可能进入相邻的像素单元而产生干扰。并且上述平板探测器像素单元包括分立式的薄膜晶体管3与非晶硅光电二极管，薄膜晶体管3与非晶硅光电二极管是分开设置的，即薄膜晶体管3与非晶硅光电二极管之间还有一定距离，使平板探测器像素单元所占面积较大，进而使得分辨率较低。此外，非晶硅光电二极管需要在形成薄膜晶体管3后单独制作，需要多个成膜与光刻工艺的步骤，使得生产成本较高。如果将这种非晶硅平板探测器用于指纹识别等领域，会有生产成本较高、分辨率较低的缺陷，将限制其在手机等便携设备上的应用。
因此，有必要提供一种指纹感测装置及其制造方法，解决现有技术中生产成本较高、分辨率较低的缺陷。
 技术问题
现有非晶硅平板探测器用于指纹识别等领域，会有生产成本较高、分辨率较低的缺陷，将限制其在手机等便携设备上的应用。
 技术解决方案
为了解决上述技术问题，本揭示利用低温多晶硅技术制备薄膜晶体管，通过N型金属氧化物层与P型多晶硅层形成异质结光电二极管，并将多晶硅薄膜晶体管和异质结光电二极管集成为一整体结构，提供一种生产成本较低，分辨率较高的低温多晶硅指纹感测装置及其制造方法，以克服上述缺陷。
为了达到上述目的，本揭示提供一种指纹感测装置及其制造方法，所述装置包括：一像素基板，所述像素基板上形成多个感测像素单元，各所述感测像素单元具有一识别区与一读取区，各所述感测像素单元包括：一图案化遮光层，设置于所述识别区与所述读取区；一多晶硅层，设置于所述图案化遮光层上；一栅极层，设置于所述读取区内的所述多晶硅层上；一图案化介电层，设置于所述读取区内的所述栅极层上；一金属氧化物层，设置于所述识别区内的所述多晶硅层上；以及一源漏极金属膜层，设置于所述识别区内的所述金属氧化物层上与所述读取区内的所述图案化介电层上；其中所述图案化介电层并设置于所述识别区内的所述金属氧化物层的两侧，但未覆盖所述金属氧化物层。
根据本文描述的指纹感测装置的一实施例，所述多晶硅层为一P型多晶硅层。
根据本文描述的指纹感测装置的一实施例，所述金属氧化物层为一N型金属氧化物层。
根据本文描述的指纹感测装置的一实施例，所述N型金属氧化物层包括选自铟锡氧化物(ITO)、铟锌氧化物(IZO)、铝锌氧化物(AZO)、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌(ZnO)及二氧化锡(SnO 2)所构成之群组中的一种或多种。
根据本文描述的指纹感测装置的一实施例，所述多晶硅层与所述金属氧化物层的交界处呈一不平坦结构。
为了达到上述目的，本揭示另提供一种指纹感测装置及其制造方法，所述装置包括：一像素基板，所述像素基板上形成多个感测像素单元，各所述感测像素单元具有一识别区与一读取区，各所述感测像素单元包括：一图案化遮光层，设置于所述识别区与所述读取区；一多晶硅层，设置于所述图案化遮光层上；一栅极层，设置于所述读取区内的所述多晶硅层上；一图案化介电层，设置于所述读取区内的所述栅极层上；一金属氧化物层，设置于所述识别区内的所述多晶硅层上；以及一源漏极金属膜层，设置于所述识别区内的所述金属氧化物层上与所述读取区内的所述图案化介电层上。
根据本文描述的指纹感测装置的一实施例，所述多晶硅层为一P型多晶硅层。
根据本文描述的指纹感测装置的一实施例，所述金属氧化物层为一N型金属氧化物层。
根据本文描述的指纹感测装置的一实施例，所述N型金属氧化物层包括选自铟锡氧化物(ITO)、铟锌氧化物(IZO)、铝锌氧化物(AZO)、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌(ZnO)及二氧化锡(SnO 2)所构成之群组中的一种或多种。
根据本文描述的指纹感测装置的一实施例，所述多晶硅层与所述金属氧化物层的交界处呈一不平坦结构。
为了达到上述目的，本揭示另提供一种指纹感测装置的制造方法，包括：提供一像素基板；于所述像素基板形成多个感测像素单元，各所述感测像素单元具有一识别区与一读取区；于所述像素基板上的所述识别区与所述读取区形成一遮光层，图案化所述遮光层形成一图案化遮光层；形成一多晶硅层于所述识别区与所述读取区的所述图案化遮光层上；形成一栅极层于所述读取区的所述多晶硅层上；沉积一介电层于所述识别区与所述读取区的所述多晶硅层上；图案化所述介电层形成一图案化介电层使所述图案化介电层仅形成于所述读取区的所述多晶硅层上；沉积并图案化一金属氧化物层于未设置所述图案化介电层的所述多晶硅层上；以及沉积一源漏极金属膜层于所述识别区的所述金属氧化物层上与所述读取区的所述图案化介电层上以形成源漏极走线。
根据本文描述的指纹感测装置的制造方法的一实施例，所述多晶硅层为一P型多晶硅层。
根据本文描述的指纹感测装置的制造方法的一实施例，所述金属氧化物层为一N型金属氧化物层。
根据本文描述的指纹感测装置的制造方法的一实施例，所述N型金属氧化物层包括选自铟锡氧化物(ITO)、铟锌氧化物(IZO)、铝锌氧化物(AZO)、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌(ZnO)及二氧化锡(SnO 2)所构成之群组中的一种或多种。
根据本文描述的指纹感测装置的制造方法的一实施例，所述多晶硅层与所述金属氧化物层的交界处呈一不平坦结构。
 有益效果
本揭示提供的指纹感测装置及制造方法，通过低温多晶硅技术制备薄膜晶体管，并通过N型金属氧化物层与P型多晶硅层形成异质结光电二极管，由光电二极管识别反射自手指的一讯号光束，即指纹反射讯号光束的光强弱变化可被光电二极管识别，并转换为光电流，薄膜晶体管读取辨识光电二极管产的光电流，从而实现指纹识别功能。由于N型金属氧化物层与P型多晶硅层间的界面呈现一粗糙/凹凸界面，因此N型金属氧化物层与P型多晶硅层间形成较大面积的异质结接触区，有利于对于指纹反射光的吸收，增加P型多晶硅层中电子空穴对的分离能力。同时，薄膜晶体管和异质结光电二极管共同在一集成结构实现，无需复杂的成膜与光刻工艺。
 附图说明
图1为现有平板传感器的像素单元结构示意图。
图2为本揭示指纹感测装置感测像素单元结构示意图。
图3A-3E为本揭示指纹感测装置的制造方法流程示意图。
图4为本揭示指纹感测装置的制造方法步骤示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
请参阅图2，其为本揭示的指纹感测装置感测像素单元结构示意图，在本揭示的一实施例中，用以侦测一手指300的指纹感测装置包括：一像素基板101，所述像素基板101上形成多个感测像素单元102(图中示出一个感测像素单元102)，各所述感测像素单元102具有一识别区A与一读取区R，所述识别区A上设置有一光电二极管构造，用以识别所述手指300所反射的一讯号光束L2的强弱变化，并转换为一光电流形式；所述读取区R设置有一薄膜晶体管(Thin Film Transistor, TFT)构造，用以读取并辨识前述光电二极管产生的光电流。
各所述感测像素单元102包括：一图案化遮光层103，设置于所述识别区A与所述读取区R，更详细地说，设置于所述识别区A的所述图案化遮光层103与设置于所述读取区R的所述图案化遮光层103为不连续；一多晶硅层104，设置于对应所述识别区A与所述读取区R的所述图案化遮光层103上；一栅极层105，设置于所述读取区R内的所述多晶硅层104上；一图案化介电层(即下述第三介电层106)，设置于所述读取区R内的所述栅极层105上；一金属氧化物层107，设置于所述识别区A内的所述多晶硅层104上；以及一源漏极金属膜层108，设置于所述识别区A内的所述金属氧化物层107上与所述读取区R内的所述图案化介电层(即下述第三介电层106)上。
一发光单元(未图示)用以发出一感测光束L1至手指300，手指300将感测光束L1反射为一讯号光束L2。上述讯号光束L2并不限于图1所绘示的来自手指300表面的反射光束，更包括穿透手指300表面后经手指300内组织所反射的光束，图1仅是示例性的绘示出其中一光束，其并非用以限定本揭示。
在本实施例中，指纹感测装置的所有感测像素单元102形成一感光阵列。为了清楚说明上述各组件的配置关系，图1所绘示的是这些感测像素单元102的其中之一的示意图。
所述感测像素单元102包括识别区A上的光电二极管以及读取区R上的薄膜晶体管。所述光电二极管包括层迭的多晶硅层104及金属氧化物层107，更详细的说，所述多晶硅层104为一P型多晶硅层，所述金属氧化物层107为一N型金属氧化物层，N型金属氧化物层堆栈于P型多晶硅层上。所述图案化遮光层103与所述多晶硅层104之间设有一第一介电层111，所述P型多晶硅层设置在对应所述识别区A与所述读取区R的所述第一介电层111上，第一介电层111可以采用化学气相沉积(CVD)法形成，例如低温化学气相沉积(LTCVD)法、低压化学气相沉积(LPCVD)法、快热化学气相沉积(LTCVD)、等离子体化学气相沉积(PECVD)，也可以采用物理气相沉积(PVD)法或溅射法形成。
一栅极金属层(未图示)形成于对应所述读取区R的所述P型多晶硅层上，图案化所述栅极金属层以于所述读取区R内的所述多晶硅层104上的一预定位置形成所述栅极层105。其中，所述栅极层105与所述多晶硅层104之间设有一第二介电层112，其经过上述图案化后对应所述栅极层105。
在一实施例中，所述图案化介电层为一第三介电层106，设置于所述读取区R内的所述多晶硅层104上，并设置于所述识别区A内的所述金属氧化物层107的两侧，但未覆盖所述金属氧化物层107。所述第三介电层106的厚度大于所述金属氧化物层107的厚度。所述第三介电层106形成在所述栅极层105之上，所述第三介电层106对应至所述栅极层105的两侧形成有源/漏区接触孔151，后续由所述源漏极金属膜层108所形成的源极/漏极经由所述源/漏区接触孔151而与所述多晶硅层104电性连接。
另外，所述金属氧化物层107包含一材料选自铟锡氧化物(Indium Tin Oxide,ITO)、铟锌氧化物(Indium Zinc Oxide,IZO)、铝锌氧化物(Aluminum Zinc Oxide,AZO)、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌(ZnO)及二氧化锡(SnO 2)所构成之群组。在本实施例中，所述金属氧化物层107之材料为氧化铟锡(Indium Tin Oxide,ITO)。所述金属氧化物层107仅设置于所述识别区A内的所述多晶硅层104上，即对应光电二极管构成的识别区A。
如图2部分放大图式所示，所述多晶硅层104与所述金属氧化物层107的交界处呈一不平坦结构200，所述不平坦结构200为一粗糙型态、凹凸型态、互相嵌合型态等结构，但不以此为限。由于上述的不平坦结构200，所述多晶硅层104与所述金属氧化物层107的交界处会具有较大的接触面积，即N型金属氧化物层与P型多晶硅层间形成较大面积的异质结接触区，有利于对于手指反射的讯号光束L2的吸收，增加P型多晶硅层中电子空穴对的分离能力。
须注意的是，所述多晶硅层104设置在所述识别区A与所述读取区R的所述第一介电层111上，即所述多晶硅层104形成在识别区A的光电二极管与读取区R的薄膜晶体管的同一水平层级结构上，所述栅极层105设置在所述图案化遮光层103的上方，所述金属氧化物层107与所述多晶硅层104之间无须设置一中间层，避免了现有技术中非晶硅光电二极管中的中间层厚度较大所产生的缺陷，并且在制程上也无需复杂的成膜与光刻工艺。
请参阅图3A-3E至图4并配合图2所示，其为本揭示指纹感测装置的制造方法的步骤及流程示意图。本揭示指纹感测装置的制造方法包括：步骤S01：提供一像素基板101；步骤S02：于所述像素基板101形成多个感测像素单元102，各所述感测像素单元具有一识别区A与一读取区R；步骤S03：于所述像素基板101上的所述识别区A与所述读取区R形成一遮光层，图案化所述遮光层形成一图案化遮光层103；步骤S04：形成一多晶硅层104于所述识别区A与所述读取区R的所述图案化遮光层103上；步骤S05：形成一栅极层105于所述读取区R的所述多晶硅层104上；步骤S06：沉积一介电层于所述识别区A与所述读取区R的所述多晶硅层104上；步骤S07：图案化所述介电层形成一图案化介电层(即第三介电层106)使所述图案化介电层(即第三介电层106) 形成于所述读取区R内的所述多晶硅层104上，并形成于所述识别区A内的所述金属氧化物层107的两侧，但未覆盖所述金属氧化物层107；步骤S08：沉积并图案化一金属氧化物层107于未设置所述图案化介电层(即第三介电层106)的所述多晶硅层104上；以及步骤S09：沉积一源漏极金属膜层108于所述识别区A的所述金属氧化物层107上与所述读取区R的所述图案化介电层上以形成源漏极走线。
更详细地说，在步骤S03之中还包括使用一成膜工艺将遮光层形成于所述像素基板上的所述识别区A与所述读取区R，使用一黄光制程图案化所述遮光层形成一图案化遮光层103，如图3A所示。
在步骤S04中，使用一化学气相沉积工艺将所述多晶硅层104形成于图案化遮光层103上，须注意的是，在形成所述多晶硅层104前，更包括在所述图案化遮光层103上沉积一第一介电层111，如图3B所示，之后，形成多晶硅层104的多晶硅材料经过激光低温退火后在所述识别区A与所述读取区R的所述第一介电层111上形成所述多晶硅层104，其中所述多晶硅层104为一P型多晶硅层，并将所述多晶硅层104图案化。
在步骤S05中，一栅极金属层(未图示)形成于所述读取区R的所述多晶硅层104上，图案化所述栅极金属层以于所述读取区R内的所述多晶硅层104上的一预定位置形成所述栅极层105，其中，如图3C所示，所述栅极层105与所述多晶硅层104之间设有一第二介电层112，其经过上述图案化后对应所述栅极层105。并且以所述栅极层105及所述第二介电层112为掩膜对所述多晶硅层104进行源漏极掺杂。使所述栅极层105及所述第二介电层112所对应的所述多晶硅层104的区域未被离子掺杂。
在步骤S07，所述图案化介电层为第三介电层106，图案化所述第三介电层106的步骤中包括了，在所述第三介电层106形成有与所述栅极层105对应的源/漏区接触孔151，如图3D所示，后续由所述源漏极金属膜层108所形成的源极/漏极(未图示)经由所述源/漏区接触孔151而与所述多晶硅层104电性连接。并且所述第三介电层106将识别区A的光电二极管与读取区R的薄膜晶体管绝缘。
在步骤S08中，沉积所述金属氧化物层107于剩余部分的所述多晶硅层104上，即在上述步骤中，对应所述读取区R的所述多晶硅层104上以形成第三介电层106，因此于未设置所述第三介电层106的所述多晶硅层104上沉积所述金属氧化物层107，即所述金属氧化物层107对应形成于对应所述识别区A的所述多晶硅层104上。也因此金属氧化物层107与多晶硅层104间形成较大面积的异质结接触区。更详细地说，识别区的部分构成一光电二极管，读取区的部分构成一薄膜晶体管。所述光电二极管包括层迭的多晶硅层104及金属氧化物层107，所述多晶硅层104为一P型多晶硅层，所述金属氧化物层107为一N型金属氧化物层。
在步骤S09中，在第三介电层106上沉积源漏极金属膜层108，并图案化所述源漏极金属膜层108形成的源极/漏极经由所述源/漏区接触孔151而与所述多晶硅层104电性连接，如图3E所示。即形成的源极/漏极分别与所述金属氧化物层107及所述多晶硅层104电性连接，用以传输反射自手指的一讯号光束L2经过光电二极管所转换而形成的光电流，具体来说，源极/漏极用于辅助所述金属氧化物层107及所述多晶硅层104中被激发出的电子电洞的移动，并传输所述电子电洞所形成的光电流。
此外，所述多晶硅层104与所述金属氧化物层107的交界处呈一不平坦结构200，所述不平坦结构200为一粗糙型态、凹凸型态、互相嵌合型态等结构，但不以此为限。由于上述的不平坦结构，所述多晶硅层104与所述金属氧化物层107的交界处会具有较大的接触面积，即N型金属氧化物层与P型多晶硅层间形成较大面积的异质结接触区，有利于对于指纹反射光的吸收，增加P型多晶硅层中电子空穴对的分离能力。
由上述可知，所述P型多晶硅层形成在识别区A的光电二极管与读取区R的薄膜晶体管的同一水平层级结构上，光电二极管与薄膜晶体管同时制备，所述栅极层105设置在所述图案化遮光层103的上方，所述金属氧化物层107与所述多晶硅层104之间无须设置一中间层，避免了现有技术中非晶硅光电二极管中的中间层厚度较大所产生的缺陷，并且在制程上也无需复杂的成膜与光刻工艺。
本揭示提供的指纹感测装置及制造方法，通过低温多晶硅技术制备薄膜晶体管，并通过N型金属氧化物层与P型多晶硅层形成异质结光电二极管，由光电二极管识别反射自手指的一讯号光束，即指纹反射讯号光束的光强弱变化可被光电二极管识别，并转换为光电流，薄膜晶体管读取辨识光电二极管产的光电流，从而实现指纹识别功能。由于N型金属氧化物层与P型多晶硅层间的界面呈现一粗糙/凹凸界面，因此N型金属氧化物层与P型多晶硅层间形成较大面积的异质结接触区，有利于对于指纹反射光的吸收，增加P型多晶硅层中电子空穴对的分离能力。同时，薄膜晶体管和异质结光电二极管共同在一集成结构实现，无需复杂的成膜与光刻工艺。为让本揭示的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
以上所述是本揭示的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本揭示的保护范围。

Claims (15)

  1. 一种指纹感测装置，包括：一像素基板，所述像素基板上形成有多个感测像素单元，各所述感测像素单元具有一识别区与一读取区，各所述感测像素单元包括：
    一图案化遮光层，设置于所述感测像素单元的所述识别区与所述读取区；
    一多晶硅层，设置于所述图案化遮光层上；
    一栅极层，设置于所述读取区内的所述多晶硅层上；
    一图案化介电层，设置于所述读取区内的所述栅极层上；
    一金属氧化物层，设置于所述识别区内的所述多晶硅层上；以及
    一源漏极金属膜层，设置于所述识别区内的所述金属氧化物层上与所述读取区内的所述图案化介电层上；
    其中所述图案化介电层并设置于所述识别区内的所述金属氧化物层的两侧，但未覆盖所述金属氧化物层。
  2. 根据权利要求1所述的指纹感测装置，其中所述多晶硅层为一P型多晶硅层。
  3. 根据权利要求1所述的指纹感测装置，其中所述金属氧化物层为一N型金属氧化物层。
  4. 根据权利要求3所述的指纹感测装置，其中所述N型金属氧化物层包括选自铟锡氧化物、铟锌氧化物、铝锌氧化物、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌及二氧化锡所构成之群组中的一种或多种。
  5. 根据权利要求1所述的指纹感测装置，其中所述多晶硅层与所述金属氧化物层的交界处呈一不平坦结构。
  6. 一种指纹感测装置，包括：一像素基板，所述像素基板上形成有多个感测像素单元，各所述感测像素单元具有一识别区与一读取区，各所述感测像素单元包括：
    一图案化遮光层，设置于所述感测像素单元的所述识别区与所述读取区；
    一多晶硅层，设置于所述图案化遮光层上；
    一栅极层，设置于所述读取区内的所述多晶硅层上；
    一图案化介电层，设置于所述读取区内的所述栅极层上；
    一金属氧化物层，设置于所述识别区内的所述多晶硅层上；以及
    一源漏极金属膜层，设置于所述识别区内的所述金属氧化物层上与所述读取区内的所述图案化介电层上。
  7. 根据权利要求6所述的指纹感测装置，其中所述多晶硅层为一P型多晶硅层。
  8. 根据权利要求6所述的指纹感测装置，其中所述金属氧化物层为一N型金属氧化物层。
  9. 根据权利要求8所述的指纹感测装置，其中所述N型金属氧化物层包括选自铟锡氧化物、铟锌氧化物、铝锌氧化物、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌及二氧化锡所构成之群组中的一种或多种。
  10. 根据权利要求6所述的指纹感测装置，其中所述多晶硅层与所述金属氧化物层的交界处呈一不平坦结构。
  11. 一种指纹感测装置的制造方法，包括：
    提供一像素基板；
    于所述像素基板形成多个感测像素单元，各所述感测像素单元具有一识别区与一读取区；
    于所述像素基板上的所述识别区与所述读取区形成一遮光层，图案化所述遮光层形成一图案化遮光层；
    形成一多晶硅层于所述识别区与所述读取区的所述图案化遮光层上；
    形成一栅极层于所述读取区的所述多晶硅层上；
    沉积一介电层于所述识别区与所述读取区的所述多晶硅层上；
    图案化所述介电层形成一图案化介电层使所述图案化介电层仅形成于所述读取区的所述多晶硅层上；
    沉积并图案化一金属氧化物层于未设置所述图案化介电层的所述多晶硅层上；以及
    沉积一源漏极金属膜层于所述识别区的所述金属氧化物层上与所述读取区的所述图案化介电层上以形成源漏极走线。
  12. 根据权利要求11所述的指纹感测装置的制造方法，其中所述多晶硅层为一P型多晶硅层。
  13. 根据权利要求11所述的指纹感测装置的制造方法，其中所述金属氧化物层为一N型金属氧化物层。
  14. 根据权利要求13所述的指纹感测装置的制造方法，其中所述N型金属氧化物层包括选自铟锡氧化物、铟锌氧化物、铝锌氧化物、镉锡氧化物、锑锡氧化物、锌锡氧化物、氧化锌及二氧化锡所构成之群组中的一种或多种。
  15. 根据权利要求11所述的指纹感测装置的制造方法，其中所述多晶硅层与所述金属氧化物层的交界处呈一不平坦结构。
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