WO2020062397A1 - 一种阵列基板和显示面板 - Google Patents

一种阵列基板和显示面板 Download PDF

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Publication number
WO2020062397A1
WO2020062397A1 PCT/CN2018/112862 CN2018112862W WO2020062397A1 WO 2020062397 A1 WO2020062397 A1 WO 2020062397A1 CN 2018112862 W CN2018112862 W CN 2018112862W WO 2020062397 A1 WO2020062397 A1 WO 2020062397A1
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Prior art keywords
layer
color resist
metal layer
display area
array substrate
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Ceased
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PCT/CN2018/112862
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English (en)
French (fr)
Inventor
宋振莉
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/338,998 priority Critical patent/US11205727B2/en
Publication of WO2020062397A1 publication Critical patent/WO2020062397A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • liquid crystal displays have many advantages such as thin body, power saving, no radiation, etc., and have been widely used.
  • Most of the liquid crystal displays on the market are backlit liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the liquid crystal panel includes a color filter substrate (color filter substrate, CF substrate, also referred to as a color filter substrate), and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT substrate).
  • TFT substrate Thin Film Transistor Substrate
  • a layer of liquid crystal (LC) is sandwiched between the two substrates.
  • the basic composition of a thin film transistor includes two layers of metal (commonly Al or Cu), two layers of insulation, an active layer, and an ohmic contact layer between the semiconductor and the metal layer.
  • the two layers of metal electrodes are the scanning signal metal electrode and the data signal metal electrode;
  • the two insulating layers refer to the insulating layer (GI layer) below the active layer and the insulating layer (PV layer) above the active layer, respectively;
  • the active layer and the doped layer with ohmic contact are usually an island pattern in a thin film transistor, so it is sometimes called an active island or a silicon island.
  • the thin film transistor structure can be divided into a bottom gate structure and a top gate structure.
  • the top gate structure is degraded by the backlight.
  • the present application provides an array substrate and a display panel that can shield the backlight from affecting the TFT device.
  • the present application provides a pixel structure design for protecting the performance of a TFT device, including: a base substrate; a second metal layer, including a source metal layer and a drain metal layer, formed on the base substrate; a channel A region between the source metal layer and the drain metal layer; an ohmic contact layer formed on the source metal layer and the drain metal layer; and the channel region; an active region Layer formed on the ohmic contact layer and the channel region; a first insulating layer (GI layer) formed on the active layer, the source metal layer, and the drain metal layer; the first metal Layer is formed on the first insulating layer; a second insulating layer (PV layer) is formed on the first metal layer and the first insulating layer; a first color resist layer is formed on the base substrate; Blocking the channel region; the first color resist layer has at least two color resist layers, and the two color resist layers have different colors and are stacked.
  • GI layer first insulating layer
  • PV layer second insulating layer
  • the array substrate includes a non-display area and a display area, and the display area and the non-display area are connected through the drain metal layer; the first color resist layer and the second metal layer are both The first color resist layer is located in the non-display area corresponding to the position of the second metal layer.
  • the array substrate includes a non-display area and a display area, and the display area and the non-display area are connected through the drain metal layer; the first color resistance layer and the channel area are both located In the non-display region, the first color resist layer is disposed corresponding to a position of the channel region.
  • the array substrate includes a second color resistance layer, and the display area includes pixels; the second color resistance layer is located in the display area, and each color resistance layer of the second color resistance layer is on the display; The areas are arranged side by side and are arranged corresponding to the pixel positions.
  • the first color resist layer includes a red color resist and a green color resist.
  • the first color resist layer includes a red color resist and a blue color resist.
  • the first color resist layer includes a green color resist and a blue color resist.
  • the first color resistance layer includes a red color resistance, a green color resistance, and a blue color resistance.
  • the present application also discloses a pixel structure design for protecting the performance of a TFT device, including: an array substrate including: a substrate substrate; a second metal layer including a source metal layer and a drain metal layer to form On a base substrate; a channel region between the source metal layer and the drain metal layer; an ohmic contact layer formed on the source metal layer and the drain metal layer; and The channel region; an active layer formed on the ohmic contact layer and the channel region; a first insulating layer (GI layer) formed on the active layer, the source metal layer, and the drain On an electrode metal layer; a first metal layer formed on the first insulating layer; a second insulating layer (PV layer) formed on the first metal layer and the first insulating layer; a first color resist layer, Formed on a base substrate, blocking the channel region; the first color resist layer has at least two color resist layers, and the two color resist layers have different colors and are stacked;
  • the array substrate includes a non-display area and a display area, and the display area and the non-display area are connected through the drain metal layer; the first color resist layer and the second metal layer are both located in the non-display area. In the display area, the first color resist layer is disposed corresponding to the position of the second metal layer;
  • the array substrate includes a second color resistance layer, the display area includes pixels, the second color resistance layer is located in the display area, and each color resistance layer of the second color resistance layer is arranged side by side in the display area. , Corresponding to the pixel position.
  • the present application also discloses a display panel, which includes an array substrate as described above.
  • the channel of the top-gate structure is in direct contact with the base substrate.
  • the backlight When the backlight is turned on, the backlight will illuminate the channel through the base substrate, causing the performance of the TFT device to deteriorate.
  • the color resist layer process is used to synchronize The color resist layer is stacked to block the channel region, thereby blocking the backlight from illuminating the channel, and does not need to add additional processes, thereby saving costs.
  • the color resistance is made of a non-conductive material, and no parasitic capacitance is generated between the TFT device and other conductive lines, which stabilizes the performance of the TFT device.
  • FIG. 1 is a schematic diagram of a top gate structure
  • FIG. 2 is a schematic diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a pixel structure of a first color resist layer composed of a red color resist and a green color resist according to an embodiment of the present application;
  • FIG. 4 is a schematic diagram of a pixel structure of a first color resist layer composed of a red color resist and a blue color resist according to an embodiment of the present application;
  • FIG. 5 is a schematic diagram of a pixel structure of a first color resist layer composed of a green color resist and a blue color resist according to an embodiment of the present application;
  • FIG. 6 is a schematic diagram of a pixel structure of a first color resist layer composed of a red color resist, a green color resist, and a blue color resist according to an embodiment of the present application;
  • FIG. 7 is a schematic diagram of an array substrate according to an embodiment of the present application.
  • An array substrate 10 includes: a substrate substrate 11, a second metal layer 115, and a source metal layer. 12 and the drain metal layer 13 are formed on the base substrate 11; the channel region 14 is located between the source metal layer 12 and the drain metal layer 13; the ohmic contact layer 15 forms the source metal layer 12 and the drain On the metal layer 13 and in the channel region 14; an active layer 116 is formed on the ohmic contact layer 15 and in the channel region 14; a first insulating layer 117 (GI layer) is formed on the active layer 116 , The source metal layer 12 and the drain metal layer 13; a first metal layer 16 is formed on the first insulating layer 15; a second insulating layer 118 (PV layer) is formed on the first metal layer 16 and the first insulation Layer 117; a first color resist layer 17 formed on the base substrate 11 to block the channel region 14; the first color resist layer 17 has
  • the channel region 14 of the top-gate structure is in direct contact with the base substrate 11.
  • the backlight When the backlight is turned on, the backlight will be irradiated to the channel region 14 through the base substrate 11, causing the performance of the TFT device to deteriorate.
  • the color resist layer process is used to synchronize The color resist layer is stacked to block the channel region 14 so as to block the backlight from irradiating the channel region 14 without adding additional processes, thereby saving costs.
  • the color resistance is made of a non-conductive material, and no parasitic capacitance is generated between the TFT device and other conductive lines, which stabilizes the performance of the TFT device.
  • the array substrate 10 includes a non-display area 113 and a display area 19, and the display area 19 and the non-display area 113 are connected by a drain metal layer 13.
  • the first color resist layer 17 and the second metal layer 115 are both located within the non-display area 113, the first color resist layer 17 and the second metal layer 115 are disposed correspondingly.
  • the non-display area 113 does not need to transmit light, so the first color resist layer 17 is disposed in the non-display area 113, which can block the backlight from irradiating the non-display area 113; because the second metal layer 115 is located in the non-display area 113 Therefore, the channel region 14 is also located in the non-display region 113. If the first color resist layer 17 and the second metal layer 115 are disposed correspondingly, the first color resist layer 17 can block the second metal layer 115 from Backlight irradiation can also ensure that the channel region 14 is completely shielded from backlight irradiation, thereby stabilizing the performance of the TFT device.
  • the array substrate 10 includes a non-display area 113 and a display area 19, and the display area 19 and the non-display area 113 are connected by a drain metal layer 13.
  • the first color resist layer 17 and the channel area 14 are both located in the non-display area. Within the display region 113, the first color resist layer 17 is disposed corresponding to the position of the channel region 14.
  • the channel region 14 is affected by backlight to affect the TFT device properties, and the channel region is located in the non-display 113 region, the channel region 14 need only be shielded from the substrate substrate 11 to avoid backlight illumination to make the TFT The device performance is stable. Therefore, in this solution, the first color resist layer 17 is deposited only on the channel region 14 of the non-display region 113, and is disposed corresponding to the position of the channel region 14, so that the use efficiency of the color resist can be improved.
  • the array substrate 10 includes a second color resist layer 18, and the display area 19 includes pixels 114.
  • the second color resist layer 18 is located in the display area 19, and each color resist layer of the second color resist layer 18 is in the display area 19. It is arranged side by side in the interior and is arranged corresponding to the position of the pixel 114.
  • the color resistance layer provided on the pixel 114 is distributed side by side in this case, and each pixel 114 A color resist layer with the same color is provided thereon so as not to hinder the function of the pixel 114.
  • the first color resist layer 17 includes a red color resist 110 and a green color resist 111.
  • the red color resist 110 layer can only transmit red light, and the red light cannot pass through the green color resist 111. Then, the first color resist layer 17 composed of the red color resist 110 and the green color resist 111 superimposed can block the backlight, thereby Make TFT device performance stable.
  • the first color resist layer 17 includes a red color resist 110 and a blue color resist 112.
  • the red color resist 110 can only pass through the red light, and the red light cannot pass through the blue color resist 112. Then, the first color resist layer 17 composed of the red color resist 110 and the blue color resist 112 superimposed can block the backlight, so that TFT device performance is stabilized.
  • the first color resist layer 17 includes a green color resist 111 and a blue color resist 112.
  • the green color resist 111 can only transmit green light, and green light cannot pass through the blue color resist 112. Then, the first color resist layer 17 composed of the green color resist 110 and the blue color resist 112 superimposed can block the backlight, so that TFT device performance is stabilized.
  • the first color resist layer 17 includes a red color resist 110, a green color resist 111, and a blue color resist 112.
  • the red color resistor 110 can only pass through the red light, and the red light cannot pass through the green color resistor 111 and the blue color resistor 112, so the first composed of the red color resistor 110, the green color resistor 111, and the blue color resistor 112 is superimposed.
  • the color resist layer 17 can block the backlight, so that the performance of the TFT device can be stabilized.
  • an indium tin oxide layer 119 is formed on the second insulating layer in the display area, and is used as a transparent conductive film, and at the same time, the electronic radiation and ultraviolet and infrared harmful to the human body are reduced.
  • An array substrate 10 includes a substrate substrate 11 and a second metal layer 115.
  • the source metal layer 12 and the drain metal layer 13 are formed on the base substrate 11; the channel region 14 is located between the source metal layer 12 and the drain metal layer 13; the ohmic contact layer 15 forms a source metal On the layer 12 and the drain metal layer 13 and in the channel region 14, an active layer 116 is formed on the ohmic contact layer 15 and in the channel region 14; a first insulating layer 117 (GI layer) is formed On the active layer 116, the source metal layer 12, and the drain metal layer 13, a first metal layer 16 is formed on the first insulating layer 15, and a second insulating layer 118 (PV layer) is formed on the first metal layer. 16 and the first insulating layer 117; the first color resist layer 17 is formed on the base substrate 11 to block the channel region 14; the first color resist layer 17
  • the array substrate 10 includes a non-display area 113 and a display area 19, and the display area 19 and the non-display area 113 are connected by a drain metal layer 13.
  • the first color resist layer 17 and the second metal layer 115 are both located in the non-display area 113.
  • a color resist layer 17 is disposed corresponding to the position of the second metal layer 115;
  • the array substrate 10 includes a non-display region 113 and a display region 19, and the display region 19 and the non-display region 113 are connected by a drain metal layer 13.
  • the first color resist layer 17 and the channel region 14 are both located in the non-display region 113.
  • the color resist layer 17 is disposed corresponding to the position of the channel region 14.
  • the channel region 14 of the top-gate structure is in direct contact with the base substrate 11.
  • the backlight When the backlight is turned on, the backlight will be irradiated to the channel region 14 through the base substrate 11, causing the performance of the TFT device to deteriorate.
  • the color resist layer process is used to synchronize The color resist layer is stacked to block the channel region 14 so as to block the backlight from irradiating the channel region 14 without adding additional processes, thereby saving costs.
  • the color resistance is made of a non-conductive material, and no parasitic capacitance is generated between the TFT device and other conductive lines, which stabilizes the performance of the TFT device.
  • the non-display area 113 does not require light transmission, so the first color resistance
  • the layer 17 is disposed in the non-display area 113, which can block the backlight from irradiating the non-display area 113. Because the channel area 14 is located in the second metal layer 115 area in the display area 19, if the first color resist layer 17 and the first The two metal layers 115 are disposed correspondingly.
  • the first color resist layer 17 can block the second metal layer 115 from backlighting, and at the same time, can completely block the channel region 14 from backlighting, thereby stabilizing the performance of the TFT device. ; Because the position of the pixel 114 in the display area 19 needs to be illuminated by the backlight to display the color of the corresponding pixel 114, the color resistance layer provided on the pixel 114 is arranged side by side in this case, and is set on each pixel 114 A color resist layer of the same color does not hinder the function of the pixel 114.
  • a display panel which includes an array substrate 10 as described above.
  • the array substrate 10 is provided with a first color resist layer 17.
  • a color resist layer 17 blocks the channel region 14.
  • the panel of the present application may be a TN panel (full name TwistedNematic, that is, a twisted nematic panel), an IPS panel (In-PaneSwitcing, plane conversion), a VA panel (Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology), of course, It can also be other types of panels, as long as it is applicable.
  • TN panel full name TwistedNematic, that is, a twisted nematic panel
  • IPS panel In-PaneSwitcing, plane conversion
  • VA panel Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology

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Abstract

本申请公开了一种阵列基板和显示面板。所述阵列基板包括衬底基板和第一色阻层，第一色阻层形成于衬底基板上，隔挡沟道区；第一色阻层至少有两层色阻层，两层色阻层对应的颜色不同且层叠设置。

Description

一种阵列基板和显示面板
本申请要求于2018年9月30日提交中国专利局、申请号为：201821629519.6、申请名称为“一种阵列基板和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(Backlight Module)。液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)、薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。
薄膜晶体管的基本组成包括两层金属(常用Al或Cu)、两层绝缘层、一层有源层和一层位于半导体与金属层之间的欧姆接触层。两层金属构成的电极分别是扫描信号金属电极和 数据信号金属电极；两层绝缘层分别指位于有源层下方的绝缘层(GI层)和位于有源层上方的绝缘层(PV层)；有源层和欧姆接触作用的掺杂层一起在薄膜晶体管中通常是个岛状图形，因此有时又被称为有源岛或硅岛。根据栅极与硅岛的上下位置关系，薄膜晶体管结构可以分为底栅结构和顶栅结构。顶栅结构受到背光照射使得TFT器件性能劣化。
技术解决方案
鉴于上述缺陷，本申请提供一种可以遮挡背光对TFT器件产生影响的一种阵列基板和显示面板。
为实现上述目的，本申请提供一种保护TFT器件性能的画素结构设计，包括：衬底基板；第二金属层，包括源极金属层和漏极金属层，形成于衬底基板上；沟道区，位于所述源极金属层和所述漏极金属层之间；欧姆接触层，形成于所述源极金属层和所述漏极金属层上，以及所述沟道区内；有源层，形成于所述欧姆接触层上，以及所述沟道区内；第一绝缘层(GI层)，形成于所述有源层、源极金属层和漏极金属层上；第一金属层，形成于所述第一绝缘层上；第二绝缘层(PV层)，形成于所述第一金属层和第一绝缘层上；第一色阻层，形成于衬底基板上，隔挡所述沟道区；所述第一色阻层至少有两层色阻层，所述两层色阻层对应的颜色不同且层叠设置。
可选的，所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；所述第一色阻 层和所述第二金属层均位于所述非显示区内，所述第一色阻层与所述第二金属层位置对应设置。
可选的，所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；所述第一色阻层和所述沟道区均位于所述非显示区内，所述第一色阻层与所述沟道区位置对应设置。
可选的，所述阵列基板包括第二色阻层，所述显示区包括像素；所述第二色阻层位于所述显示区，所述第二色阻层的各色阻层在所述显示区内并列分布，与所述像素位置对应设置。
可选的，所述第一色阻层包括红色色阻和绿色色阻。
可选的，所述第一色阻层包括红色色阻和蓝色色阻。
可选的，所述第一色阻层包括绿色色阻和蓝色色阻。
可选的，所述第一色阻层包括红色色阻、绿色色阻和蓝色色阻。
本申请还公开了一种保护TFT器件性能的画素结构设计，包括：一种阵列基板，所述阵列基板包括：衬底基板；第二金属层，包括源极金属层和漏极金属层，形成于衬底基板上；沟道区，位于所述源极金属层和所述漏极金属层之间；欧姆接触层，形成于所述源极金属层和所述漏极金属层上，以及所述沟道区内；有源层，形成于所述欧姆接触层上，以及所述沟道区内；第一绝缘层(GI层)，形成于所述有源层、源极金属层和漏极金属层上；第一金属层，形成于所述第一绝缘层上；第二绝缘层 (PV层)，形成于所述第一金属层和第一绝缘层上；第一色阻层，形成于衬底基板上，隔挡所述沟道区；所述第一色阻层至少有两层色阻层，所述两层色阻层对应的颜色不同且层叠设置；
所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；所述第一色阻层和所述第二金属层均位于所述非显示区内，所述第一色阻层与所述第二金属层位置对应设置；
所述阵列基板包括第二色阻层，所述显示区包括像素，所述第二色阻层位于所述显示区，所述第二色阻层的各色阻层在所述显示区内并列分布，与所述像素位置对应设置。
本申请还公开了一种显示面板，所述显示面板包括如上任意所述的一种阵列基板。
顶栅结构的沟道与衬底基板直接接触，当点亮背光后，背光会通过衬底基板照射到沟道，导致TFT器件性能劣化。考虑到画素结构生产过程中，需要进行多次重复色阻沉积工序，而只要任意两种不同的色阻层层叠设置，就可以隔挡背光，因此，本案通过色阻层制程中,同步在形成层叠设置的色阻层，隔挡沟道区，从而隔挡背光对沟道的照射，并且无需增加额外的工序，节约成本。另外，色阻都采用非导电的材质制成，跟TFT器件以及其它导电线路之间不会产生寄生电容，使TFT器件性能得以稳定。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是的顶栅结构示意图；
图2是本申请实施例一种画素结构示意图；
图3是本申请实施例一种红色色阻和绿色色阻组成的第一色阻层画素结构示意图；
图4是本申请实施例一种红色色阻和蓝色色阻组成的第一色阻层画素结构示意图；
图5是本申请实施例一种绿色色阻和蓝色色阻组成的第一色阻层画素结构示意图；
图6是本申请实施例一种红色色阻、绿色色阻和蓝色色阻组成的第一色阻层画素结构示意图；
图7是本申请实施例一种阵列基板的示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解 的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、和组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、组件和/或其组合。
下面结合附图和可选的实施例对本申请作说明。
如图1至图7所示，本申请实施例公布了一种保护TFT器件性能的画素结构设计：一种阵列基板10，包括：衬底基板11，第二金属层115，包括源极金属层12和漏极金属层13，形成于衬底基板11上；沟道区14，位于源极金属层12和漏极金属层13之间；欧姆接触层15，形成源极金属层12和漏极金属层13上，以及沟道区14内；有源层116，形成于所述欧姆接触层15上，以及沟道区14内；第一绝缘层117(GI层)，形成于有源层116、源极金属层12和漏极金属层13上；第一金属层16，形成于第一绝缘层15上；第二绝缘层118(PV层)，形成于第一金属层16和第一绝缘层117上；第一色阻层17，形成于衬底基板11上，隔挡所述沟道区14；第一色阻层17至少有两层色阻层，两层色阻层对应的颜色不同且层叠设置。
本案中，顶栅结构的沟道区14与衬底基板11直接接触，当点亮背光后，背光会通过衬底基板11照射到沟道区14，导致TFT器件性能劣化。考虑到画素结构生产过程中，需要进行多次重复色阻沉积工序，而只要任意两种不同的色阻层层叠设置，就可以隔挡背光，因此，本案通过色阻层制程中,同步在形成层叠设置的色阻层，隔挡沟道区14，从而隔挡背光对沟道区 14的照射，并且无需增加额外的工序，节约成本。另外，色阻都采用非导电的材质制成，跟TFT器件以及其它导电线路之间不会产生寄生电容，使TFT器件性能得以稳定。
本实施例可选的，阵列基板10包括非显示区113和显示区19，显示区19和非显示区113通过漏极金属层13相连；第一色阻层17和第二金属层115均位于非显示区113内，第一色阻层17与第二金属层115位置对应设置。
本案中，非显示区113不需要透光，因此将第一色阻层17设置在非显示区113，可以隔挡背光对非显示区113的照射；因为第二金属层115位于非显示区113内，所以沟道区14也位于非显示区113内，若使第一色阻层17与第二金属层115位置对应设置，这样第一色阻层17可以隔挡第二金属层115免于背光照射，同时可以保证完全隔挡沟道区14免于背光照射，从而使TFT器件性能得以稳定。
本实施例可选的，阵列基板10包括非显示区113和显示区19，显示区19和非显示区113通过漏极金属层13相连；第一色阻层17和沟道区14均位于非显示区113内，第一色阻层17与沟道区14位置对应设置。
本案中，因为沟道区14受到背光照射才会影响TFT器件性，沟道区位于非显示113区域内，那么只需要隔挡衬底基板11的沟道区14免于背光照射就可以使TFT器件性能稳定，因此，本方案将第一色阻层17只沉积在非显示区113的沟道区 14，并与沟道区14位置对应设置，这样可以提高色阻的使用效率。
本实施例可选的，阵列基板10包括第二色阻层18，显示区19包括像素114；第二色阻层18位于显示区19，第二色阻层18的各色阻层在显示区19内并列分布，与像素114位置对应设置。
本案中，因为显示区19内的像素114位置需要接受背光的照射从而显示出对应像素114的颜色，因此，本案在像素114上设置的色阻层之间为并列分布，并且在每个像素114上设置与其颜色相同的色阻层，这样不会妨碍像素114的功能。
本实施例可选的，第一色阻层17包括红色色阻110和绿色色阻111。
本案中，红色色阻110层可以只透过红光，红光不能穿过绿色色阻111，那么由红色色阻110和绿色色阻111叠加组成的第一色阻层17可以遮挡背光，从而使TFT器件性能得以稳定。
本实施例可选的，第一色阻层17包括红色色阻110和蓝色色阻112。
本案中，红色色阻110可以只透过红光，红光不能穿过蓝色色阻112，那么由红色色阻110和蓝色色阻112叠加组成的第一色阻层17可以遮挡背光，从而使TFT器件性能得以稳定。
本实施例可选的，第一色阻层17包括绿色色阻111和蓝色色阻112。
本案中，绿色色阻111可以只透过绿光，绿光不能穿过蓝色色阻112，那么由绿色色阻110和蓝色色阻112叠加组成的第一色阻层17可以遮挡背光，从而使TFT器件性能得以稳定。
本实施例可选的，第一色阻层17包括红色色阻110、绿色色阻111和蓝色色阻112。
本案中，红色色阻110可以只透过红光，红光不能穿过绿色色阻111和蓝色色阻112，那么由红色色阻110、绿色色阻111和蓝色色阻112叠加组成的第一色阻层17可以遮挡背光，从而使TFT器件性能得以稳定。
本实施例可选的，在显示区内的第二绝缘层上形成氧化铟锡层119(ITO)，用作透明导电薄膜，同时减少对人体有害的电子辐射及紫外、红外。
作为本申请的另一实施例，如图1至图7所示，公开了一种保护TFT器件性能的画素结构设计：一种阵列基板10，包括：衬底基板11，第二金属层115，包括源极金属层12和漏极金属层13，形成于衬底基板11上；沟道区14，位于源极金属层12和漏极金属层13之间；欧姆接触层15，形成源极金属层12和漏极金属层13上，以及沟道区14内；有源层116，形成于所述欧姆接触层15上，以及沟道区14内；第一绝缘层117(GI 层)，形成于有源层116、源极金属层12和漏极金属层13上；第一金属层16，形成于第一绝缘层15上；第二绝缘层118(PV层)，形成于第一金属层16和第一绝缘层117上；第一色阻层17，形成于衬底基板11上，隔挡所述沟道区14；第一色阻层17至少有两层色阻层，两层色阻层对应的颜色不同且层叠设置；
阵列基板10包括非显示区113和显示区19，显示区19和非显示区113通过漏极金属层13相连；第一色阻层17和第二金属层115均位于非显示区113内，第一色阻层17与第二金属层115位置对应设置；
阵列基板10包括非显示区113和显示区19，显示区19和非显示区113通过漏极金属层13相连；第一色阻层17和沟道区14均位于非显示区113内，第一色阻层17与沟道区14位置对应设置。
本案中，顶栅结构的沟道区14与衬底基板11直接接触，当点亮背光后，背光会通过衬底基板11照射到沟道区14，导致TFT器件性能劣化。考虑到画素结构生产过程中，需要进行多次重复色阻沉积工序，而只要任意两种不同的色阻层层叠设置，就可以隔挡背光，因此，本案通过色阻层制程中,同步在形成层叠设置的色阻层，隔挡沟道区14，从而隔挡背光对沟道区14的照射，并且无需增加额外的工序，节约成本。另外，色阻都采用非导电的材质制成，跟TFT器件以及其它导电线路之间不会产生寄生电容，使TFT器件性能得以稳定；非显示区113不需 要透光，因此将第一色阻层17设置在非显示区113，可以隔挡背光对非显示区113的照射；因为沟道区14位于显示区19内的第二金属层115区域内，若使第一色阻层17与第二金属层115位置对应设置，这样第一色阻层17可以隔挡第二金属层115免于背光照射，同时可以保证完全隔挡沟道区14免于背光照射，从而使TFT器件性能得以稳定；因为显示区19内的像素114位置需要接受背光的照射从而显示出对应像素114的颜色，因此，本案在像素114上设置的色阻层之间为并列分布，并且在每个像素114上设置与其颜色相同的色阻层，这样不会妨碍像素114的功能。
作为本申请的另一实施例，如图1至图7所示，公开了一种显示面板，包括如上任意所述的一种阵列基板10，阵列基板10设有第一色阻层17，第一色阻层17隔挡沟道区14。
本申请的面板可以是TN面板(全称为TwistedNematic，即扭曲向列型面板)、IPS面板(In-PaneSwitcing，平面转换)、VA面板(Multi-domain Vertica Aignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的实施方式对本申请所作详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的 保护范围。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板；
    第二金属层，包括源极金属层和漏极金属层，形成于衬底基板上；
    沟道区，位于所述源极金属层和所述漏极金属层之间；
    欧姆接触层，形成于所述源极金属层和所述漏极金属层上，以及所述沟道区内；
    有源层，形成于所述欧姆接触层上，以及所述沟道区内；
    第一绝缘层，形成于所述有源层、源极金属层和漏极金属层上；
    第一金属层，形成于所述第一绝缘层上；
    第二绝缘层，形成于所述第一金属层和第一绝缘层上；以及
    第一色阻层，形成于衬底基板上，隔挡所述沟道区；
    所述第一色阻层至少有两层色阻层，所述两层色阻层对应的颜色不同且层叠设置。
  2. 如权利要求1所述的一种阵列基板，其中，所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；
    所述第一色阻层和所述第二金属层均位于所述非显示区内，所述第一色阻层与所述第二金属层位置对应设置。
  3. 如权利要求1所述的一种阵列基板，其中，所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；
    所述第一色阻层和所述沟道区均位于所述非显示区内，所述第一色阻层与所述沟道区位置对应设置。
  4. 如权利要求2所述的一种阵列基板，其中，所述阵列基板包括第二色阻层，所述显示区包括像素；
    所述第二色阻层位于所述显示区，所述第二色阻层的各色阻层在所述显示区内并列分布，与所述像素位置对应设置。
  5. 如权利要求1所述的一种阵列基板，其中，所述第一色阻层包括红色色阻和绿色色阻。
  6. 如权利要求1所述的一种阵列基板，其中，所述第一色阻层包括红色色阻和蓝色色阻。
  7. 如权利要求1所述的一种阵列基板，其中，所述第一色阻层包括绿色色阻和蓝色色阻。
  8. 如权利要求1所述的一种阵列基板，其中，所述第一色阻层包括红色色阻、绿色色阻和蓝色色阻。
  9. 一种阵列基板，包括：
    衬底基板；
    第二金属层，包括源极金属层和漏极金属层，形成于衬底基板上；
    沟道区，位于所述源极金属层和所述漏极金属层之间；
    欧姆接触层，形成于所述源极金属层和所述漏极金属层上，以及所述沟道区内；
    有源层，形成于所述欧姆接触层上，以及所述沟道区内；
    第一绝缘层，形成于所述有源层、源极金属层和漏极金属层上；
    第一金属层，形成于所述第一绝缘层上；
    第二绝缘层，形成于所述第一金属层和第一绝缘层上；以及
    第一色阻层，形成于衬底基板上，隔挡所述沟道区；
    所述第一色阻层至少有两层色阻层，所述两层色阻层对应的颜色不同且层叠设置；
    所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；所述第一色阻层和所述第二金属层均位于所述非显示区内，所述第一色阻层与所述第二金属层位置对应设置；
    所述阵列基板包括第二色阻层，所述显示区包括像素，所述第二色阻层位于所述显示区，所述第二色阻层的各色阻层在所述显示区内并列分布，与所述像素位置对应设置。
  10. 一种显示面板，包括阵列基板，所述阵列基板包括：
    衬底基板；
    第二金属层，包括源极金属层和漏极金属层，形成于衬底基板上；
    沟道区，位于所述源极金属层和所述漏极金属层之间；
    欧姆接触层，形成于所述源极金属层和所述漏极金属层上，以及所述沟道区内；
    有源层，形成于所述欧姆接触层上，以及所述沟道区内；
    第一绝缘层，形成于所述有源层、源极金属层和漏极金属层上；
    第一金属层，形成于所述第一绝缘层上；
    第二绝缘层，形成于所述第一金属层和第一绝缘层上；以及
    第一色阻层，形成于衬底基板上，隔挡所述沟道区；
    所述第一色阻层至少有两层色阻层，所述两层色阻层对应的颜色不同且层叠设置。
  11. 如权利要求10所述的一种显示面板，其中，所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；
    所述第一色阻层和所述第二金属层均位于所述非显示区内，所述第一色阻层与所述第二金属层位置对应设置。
  12. 如权利要求10所述的一种显示面板，其中，所述阵列基板包括非显示区和显示区，所述显示区和所述非显示区通过所述漏极金属层相连；
    所述第一色阻层和所述沟道区均位于所述非显示区内，所述第一色阻层与所述沟道区位置对应设置。
  13. 如权利要求11所述的一种显示面板，其中，所述阵列基板包括第二色阻层，所述显示区包括像素；
    所述第二色阻层位于所述显示区，所述第二色阻层的各色阻层在所述显示区内并列分布，与所述像素位置对应设置。
  14. 如权利要求10所述的一种显示面板，其中，所述第一色阻层包括红色色阻和绿色色阻。
  15. 如权利要求10所述的一种显示面板，其中，所述第一色阻层包括红色色阻和蓝色色阻。
  16. 如权利要求10所述的一种显示面板，其中，所述第一色阻层包括绿色色阻和蓝色色阻。
  17. 如权利要求10所述的一种显示面板，其中，所述第一色阻层包括红色色阻、绿色色阻和蓝色色阻。
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CN110854173A (zh) * 2019-11-26 2020-02-28 深圳市华星光电半导体显示技术有限公司 一种oled显示面板
CN114447117A (zh) * 2022-01-17 2022-05-06 Tcl华星光电技术有限公司 阵列基板以及显示面板
CN114647109A (zh) * 2022-03-30 2022-06-21 Tcl华星光电技术有限公司 液晶显示面板及显示装置

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