WO2020062366A1 - 显示控制装置、显示器和自检中断方法 - Google Patents

显示控制装置、显示器和自检中断方法 Download PDF

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Publication number
WO2020062366A1
WO2020062366A1 PCT/CN2018/111194 CN2018111194W WO2020062366A1 WO 2020062366 A1 WO2020062366 A1 WO 2020062366A1 CN 2018111194 W CN2018111194 W CN 2018111194W WO 2020062366 A1 WO2020062366 A1 WO 2020062366A1
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WIPO (PCT)
Prior art keywords
transistor
driving circuit
self
circuit
test
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PCT/CN2018/111194
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/318,811 priority Critical patent/US10832607B2/en
Publication of WO2020062366A1 publication Critical patent/WO2020062366A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present application relates to a display control device, a display, and a self-test interrupt method.
  • Liquid crystal display (Liquid Crystal Display, LCD) has many advantages such as thin body, power saving, no radiation, etc., and has been widely used. Such as: LCD TVs, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens or laptop screens, etc., which dominate the field of flat panel displays.
  • LCD Liquid Crystal Display
  • GDL (Gate Driver Less) technology that is, array substrate row driving technology, uses the original array process of liquid crystal display panels to make the driving circuit of horizontal scanning lines on the substrate around the display area, so that it can replace the external integrated circuit board (Integrated Circuit (IC) to complete the drive of the horizontal scanning line.
  • the driving circuit made of GDL technology to drive the display panel can reduce the welding process of external ICs, which has the opportunity to increase productivity and reduce product costs, and can make the display panel more suitable for making narrow-frame or borderless display products.
  • the inventor realized that there are thousands of TFT devices in the driving circuit (GDL circuit), and once the device is poor in uniformity or stability, the driving circuit will be abnormal, causing the display panel to fail, making the display panel display Low reliability.
  • a display control device a display, and a self-test interrupt method are provided.
  • a display control device includes: a first driving circuit, a second driving circuit, and a self-test interruption module;
  • the first driving circuit is configured to drive the display panel from the first side, and an output terminal of the first driving circuit is connected to a first input terminal of the self-test interrupt module;
  • the second driving circuit is configured to drive the display panel from the second side, and an output terminal of the second driving circuit is connected to a second input terminal of the self-test interrupt module;
  • the first output terminal of the self-test interrupt module is connected to the input terminal of the first drive circuit
  • the second output terminal of the self-test interrupt module is connected to the input terminal of the second drive circuit
  • the start signal terminal of the self-test interrupt module is used for connection.
  • the self-test interrupt module is configured to disconnect the vertical synchronization signal to the input path of the first driving circuit when the signal feedback from the output of the first driving circuit is abnormal or to disconnect the vertical synchronization when the signal feedback from the output of the second driving circuit is abnormal A signal to an input path of the second driving circuit.
  • a display includes a display panel and the display control device.
  • a self-test interrupt method applied to the display control device includes:
  • the input path of the vertical synchronization signal to the first driving circuit is disconnected.
  • FIG. 1 is a schematic structural diagram of a display control device according to one or more embodiments
  • FIG. 2 is a schematic structural diagram of a display control device in another embodiment
  • FIG. 3 is a timing diagram of a feedback signal of a first driving circuit according to one or more embodiments
  • FIG. 4 is a schematic diagram of a connection between a first self-test interrupt circuit and a first driving circuit according to one or more embodiments
  • FIG. 5 is a schematic diagram of a connection between a second self-test interrupt circuit and a second driving circuit according to one or more embodiments
  • FIG. 6 is a schematic flowchart of a self-test interrupt method according to one or more embodiments.
  • FIG. 7 is a schematic flowchart of a step of judging an abnormality of a signal fed back by a first driving circuit according to one or more embodiments;
  • FIG. 8 is a schematic flowchart of a step of judging an abnormality of a signal fed back by a second driving circuit according to one or more embodiments;
  • FIG. 9 is a schematic structural diagram of a self-test interruption device according to one or more embodiments.
  • FIG. 10 is an internal structural diagram of a computer device according to one or more embodiments.
  • the display control device includes a first driving circuit 10, a second driving circuit 20, and a self-test interrupt module 30.
  • the first driving circuit 10 is configured to be driven from a first side.
  • the output terminal of the first driving circuit 10 is connected to the first input terminal of the self-test interrupt module 30, and the second driving circuit 20 is configured to drive the display panel 40 from the second side.
  • the second input terminal of the self-test interrupt module 30 is connected, the first output terminal of the self-test interrupt module 30 is connected to the input terminal of the first driving circuit 10, and the second output terminal of the self-test interrupt module 30 is connected to the second driving circuit 20 The input terminal is connected.
  • the start signal terminal of the self-test interrupt module 30 is used to access the vertical synchronization signal.
  • the self-test interrupt module 30 is configured to disconnect the vertical synchronization signal to the first when the signal feedback from the output terminal of the first driving circuit 10 is abnormal.
  • the vertical synchronization signal is disconnected from the input path of the second driving circuit 20.
  • the driving circuit may be a driving circuit that does not require an external gate driver chip (GDL), referred to as a GDL circuit for short. It uses the original array process of the display panel 40 to produce horizontal scanning lines on a substrate around the display area. Drive circuit.
  • the first and second sides refer to the left and right sides facing the display area of the display panel 40 when the display panel 40 is normally used, that is, the first driving circuit 10 and the second driving circuit 20 are separated from the display panel 40 respectively.
  • the left and right sides drive the thin film transistors on the display panel 40.
  • the vertical synchronization signal (STV signal, also called frame synchronization signal) is a control signal output by the timing controller, and is used to indicate the start of a new frame of image.
  • the self-test interrupt module 30 is capable of self-testing the operating conditions of the first driving circuit 10 and the second driving circuit 20, and controlling the driving working states of the first driving circuit 10 and the second driving circuit 20 according to the self-test results Circuit module.
  • the first input terminal of the self-test interruption module 30 receives the output electric signal of the first drive circuit 10, and at the same time, the second input terminal of the self-test interruption module 30 receives the output electric signal of the second drive circuit 20.
  • the first output terminal of the self-test interrupt module 30 outputs a control signal to disconnect the vertical synchronization signal from the input of the first driving circuit 10 Path, the first driving circuit 10 is cut off, the second driving circuit 20 drives the display panel 40 to display from the second side, and switches from the bilateral driving mode to the unilateral operating mode to ensure normal driving when the unilateral driving circuit is abnormal.
  • the display panel 40 performs display.
  • the self-test interruption module 30 disconnects the input path of the vertical synchronization signal to the second driving circuit 20, cuts off the second driving circuit 20, and the first driving circuit 10 and the second driving circuit 20 The mode of double-sided driving is switched to the mode of single-sided driving by the first driving circuit 10.
  • the self-test interrupt module 30 includes a first self-test interrupt circuit 31 and a second self-test interrupt circuit 32; the first driving circuit 10 includes an input terminal and a multi-stage output terminal.
  • the two driving circuits 20 include an input terminal and a multi-stage output terminal; the input terminal of the first self-test interrupt circuit 31 is connected to the output terminal of the first driving circuit 10, and the output terminal of the first self-test interrupt circuit 31 is connected to the first driver.
  • the circuit 10 is connected; the input terminal of the second self-test interrupt circuit 32 is connected to the output terminal of the second stage of the second driving circuit 20, and the output terminal of the second self-test interrupt circuit 32 is connected to the second driving circuit 20.
  • the multi-stage output terminal means that the input signals of the first driving circuit 10 and the second driving circuit 20 are transmitted step by step from the input terminal and correspond to one output terminal at each stage.
  • the first self-test interrupt circuit 31 is used to detect the first A signal fed back from the output terminal of the driving circuit 10 determines whether the current output of the first driving circuit 10 is abnormal. If the output is abnormal, the first self-test interruption circuit 31 cuts off the path from the STV signal to the first driving circuit 10.
  • the second driving circuit 20 unilaterally drives the display panel 40 to display.
  • the second self-test interrupt circuit 32 is used to detect the signal fed back from the output terminal of the second drive circuit 20 to determine whether the current output of the second drive circuit 20 is abnormal. If the output is abnormal, the second self-test interrupt circuit 32 is turned off. The path of the STV signal to the second driving circuit 20 is driven by the first driving circuit 10 to display the display panel 40 unilaterally.
  • the display panel 40 includes a positive power input terminal, a negative power input terminal, and a common electrode.
  • the positive power input terminal is used to connect the gate to turn on the power
  • the negative power input terminal is used to connect the gate.
  • the power source is turned off, and the common electrode is used for accessing a common voltage.
  • the first self-test interruption circuit 31 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor.
  • the first pole of the first transistor T1 is used to connect the power input terminal, the control pole of the first transistor T1 is connected to the output terminal of the first driving circuit 10, and the second pole of the first transistor T1 Connected to the first pole of the second transistor T2; the control pole of the second transistor T2 is used to access the data enable signal, the second pole of the second transistor T2 is used to connect to the common electrode, and is connected to the control pole of the fourth transistor T4
  • the first pole of the third transistor T3 is used to connect to the positive power input terminal, the control pole of the third transistor T3 is connected to the output terminal of the first driving circuit 10, and the second pole of the third transistor T3 is connected to the fourth transistor T4.
  • the control pole of the transistor T5 is connected to the first pole of the sixth transistor T6; the second pole of the fourth transistor T4 is used to connect to the negative power input terminal; the first pole of the fifth transistor T5 is used to access the vertical synchronization signal, and the fifth The second electrode of the transistor T5 is connected to the input terminal of the first driving circuit 10; the control electrode of the sixth transistor T6 is used to receive a scanning signal, and the scanning signal is used to perform line scanning on the display panel 40; The pole is used to connect to the negative power input terminal.
  • One end of the first capacitor C1 is connected to the control pole of the fifth transistor T5, and the other end of the first capacitor C1 is connected to the second pole of the fifth transistor T5.
  • the gate-on power supply refers to a power source for providing a gate-on power supply, which is a positive power supply VGH.
  • the gate-off power supply is used to provide the gate-off power supply, which is a negative power supply VHL.
  • a positive voltage difference is generated between the gate-on power supply voltage VGH and the common voltage of the positive power input terminal of the display panel 40. This voltage difference turns on the thin film transistors of the display panel 40 and turns on the thin film transistors connected to each liquid crystal.
  • the negative power input terminal A negative voltage difference is generated between the connected gate-off power supply voltage VHL and the common voltage, and the voltage difference is loaded on the thin film transistor of the display panel 40 so that the thin film transistor is turned off.
  • the data enable signal (DE signal, also called the effective display data strobe signal) is used to distinguish whether the received video signal is a valid video signal or an invalid video signal.
  • T1 to T6 are all turned on when the gate is loaded with a high level, and at time t1, the data enable signal is at a low level
  • the second transistor T2 and the fourth transistor T4 are turned off, and when the signal fed back by the first driving circuit 10 is a normal signal (FB / normal signal)
  • the first transistor T1 and the third transistor T3 are turned on, and the scan signal G1 is a low voltage.
  • the sixth transistor T6 is turned off, the gate-on power supply voltage VGH charges the gate of the fifth transistor T5, so that the fifth transistor T5 is turned on, and the vertical synchronization signal STV is input to the first driving circuit 10.
  • the gate of the fifth transistor T5 is maintained at a high potential due to the voltage stabilizing effect of the first capacitor C1.
  • the first driving circuit 10 is driven to operate, so that the display panel 40 is driven normally. It is shown that after the high-level output of the vertical synchronization signal STV, that is, at time t4, the high-level input of the scan signal G1 turns on the sixth transistor T6. At this time, the gate of the fifth transistor T5 is low and the fifth transistor T5 is turned off. Perform a pull-down reset.
  • the first driving circuit 10 when the signal fed back to the first driving circuit 10 is a DC signal (FB / abnormal1 signal), since the signal fed back by the first driving circuit 10 is low level, both the first transistor T1 and the third transistor T3 are turned off. Off, the fifth transistor T5 cannot be turned on, and the vertical synchronization signal STV cannot be input to the first driving circuit 10. At this time, the first driving circuit 10 cannot normally drive the display panel 40 to display, and the second driving circuit 20 drives the display panel 40 to display.
  • FB / abnormal1 signal DC signal
  • both the first transistor T1 and the third transistor T3 are turned off.
  • the fifth transistor T5 cannot be turned on, and the vertical synchronization signal STV cannot be input to the first driving circuit 10.
  • the first driving circuit 10 cannot normally drive the display panel 40 to display
  • the second driving circuit 20 drives the display panel 40 to display.
  • the vertical synchronization signal STV can be normally input to the first driving circuit 10, and after the vertical synchronization signal STV is output at a high level,
  • the scanning signal G1 is input at a high level, and the signal (FB / abnormal2 signal) fed back by the first driving circuit 10 is at the same level as the scanning signal G1.
  • the first transistor T1 and the second transistor T2 are turned on at the same time, and the fourth The gate of the transistor T4 stores a high potential, and the fourth transistor T4 remains turned on, so that the gate of the fifth transistor T5 cannot be rushed to a high potential, resulting in that the fifth transistor T5 cannot be turned on, and the vertical synchronization signal STV cannot be normally input to the first In the driving circuit 10, the display panel 40 is driven to be displayed by the normally-operating second driving circuit 20 at this time.
  • the first self-test interruption circuit 31 can automatically interrupt the driving of the display panel 40 by the first driving circuit 10 when the signal fed back by the first driving circuit 10 is a DC signal or a multi-pulse abnormal signal.
  • the driving circuit 20 drives the display panel 40 to display, improving driving efficiency and reliability.
  • the gate of the first transistor T1 and the gate of the third transistor T3 may be connected to the output terminal of the last stage of the first driving circuit 10.
  • the first self-test interrupt circuit further includes a second capacitor C2, and the second capacitor C2 is connected in series between the second transistor T2 and the common electrode.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be N-channel field effect transistors, or may be other types of transistors, as long as they conform to the above-mentioned working logic.
  • the transistors are all protected by this application.
  • the second self-test interrupt circuit 32 includes a circuit having the same structure as the first self-test interrupt circuit 31, and the second one of the fifth transistor T5 in the second self-test interrupt circuit 32 The pole is connected to the input terminal of the second driving circuit 20.
  • the above-mentioned second self-test interrupt circuit 32 includes a circuit having the same structure as the first self-test interrupt circuit 31, which means that the internal circuit structure of the first self-test interrupt circuit 31 is the same as the internal circuit structure of the second self-test interrupt circuit 32, but The external port of each device changes according to the control object of the self-test interrupt.
  • the second pole of the fifth transistor T5 in the second self-test interrupt circuit 32 is connected to the input terminal of the second driving circuit 20.
  • the gate of the first transistor T1 and the gate of the third transistor T3 are connected to the output terminal of the second driving circuit 20, and are used to collect the feedback signal FB1 of the second driving circuit 20 to determine whether the second driving circuit 20 has occurred. abnormal.
  • the gate of the first transistor T1 and the gate of the third transistor T3 are both connected to the output terminal of the last stage of the second driving circuit 20.
  • the second self-test interrupt circuit further includes a second capacitor C2, and the second capacitor C2 is connected in series between the second transistor T2 and the common electrode.
  • An embodiment of the present application further provides a display, as shown in FIG. 1 and FIG. 2, including a display panel 40 and the foregoing display control device.
  • the display when the first driving circuit 10 and the second driving circuit 20 are normal, the display panel is driven by the first driving circuit 10 and the second driving circuit 20 from the second side and the second side, respectively. 40 is displayed.
  • the self-test interruption module 30 determines that the first driving circuit 10 is abnormal according to the acquired signal from the first driving circuit 10, it cuts off the path of the vertical synchronization signal to the first driving circuit 10, so that the first driving circuit 10 cannot perform driving work.
  • the display panel 40 is driven unilaterally by the second driving circuit 20 for display.
  • the self-test interruption module 30 determines that the second driving circuit 20 is abnormal according to the acquired signal from the second driving circuit 20, the path of the vertical synchronization signal to the second driving circuit 20 is cut off, so that the second driving circuit 20 The driving operation cannot be performed, and the display panel 40 is driven unilaterally by the first driving circuit 10 to improve the driving reliability and effectiveness of the display.
  • the display panel 40 may be a liquid crystal display panel.
  • an embodiment of the present application further provides a self-test interrupt method applied to the display control device, including:
  • S20 Acquire a signal fed back by the first driving circuit and a signal fed back by the second driving circuit;
  • the signals from the first driving circuit and the signals from the second driving circuit are obtained. By determining whether the signals from the first driving circuit are abnormal, it can be determined whether the first driving circuit is faulty. If the first driving circuit is faulty, it is disconnected. The input path of the vertical synchronization signal to the first driving circuit is driven by the second driving circuit to display the display panel. Alternatively, when an abnormal signal detected by the second driving circuit is detected, the input path of the vertical synchronization signal to the second driving circuit is disconnected, and the display panel is driven by the first driving circuit to perform display.
  • the self-test interrupt method determines whether the driving circuits on both sides are faulty by detecting the feedback signals of the driving circuits on both sides. If a fault occurs on one driving circuit, the driving operation of the driving circuit on the faulty side is interrupted.
  • the driving circuit on the side drives the display panel and switches from the bilateral driving mode to the unilateral driving mode to ensure that when the single-sided driving circuit fails, the display of the display panel can be driven normally to improve the driving reliability and effectiveness.
  • the step of determining that the signal fed back by the first driving circuit is abnormal includes:
  • the step of judging the abnormal signal fed back by the first driving circuit may be detecting whether the signal fed back by the first driving circuit is a DC signal or a multi-pulse signal. If the signal fed back by the first driving circuit is one of two types of signals, then It is determined that the signal fed back by the first driving circuit is abnormal.
  • the step of determining that the signal fed back by the second driving circuit is abnormal includes:
  • the determining step of the abnormal signal feedback from the second driving circuit may be detecting whether the signal fed back by the second driving circuit is a DC signal or a multi-pulse signal. In one of the cases, it is determined that the signal fed back by the second driving circuit is abnormal.
  • steps in the flowcharts of FIGS. 6-8 are sequentially displayed in accordance with the directions of the arrows, these steps are not necessarily performed sequentially in the order indicated by the arrows. Unless explicitly stated in this document, the execution of these steps is not strictly limited, and these steps can be performed in other orders. Moreover, at least a part of the steps in FIG. 6-8 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. These sub-steps or stages The execution order of is not necessarily performed sequentially, but may be performed in turn or alternately with at least a part of another step or a sub-step or stage of another step.
  • An embodiment of the present application further provides a self-test interruption device, as shown in FIG. 9, including:
  • the feedback signal acquiring unit 1 is configured to acquire a signal fed back by the first driving circuit and a signal fed back by the second driving circuit;
  • the interrupt control unit 2 is configured to disconnect an input path of the vertical synchronization signal to the first driving circuit when an abnormal signal detected by the first driving circuit is detected.
  • the feedback signal acquisition unit 1 acquires a signal fed back by the first driving circuit and a signal fed back by the second driving circuit and sends them to the interrupt control unit 2. Then the interrupt control unit 2 detects whether the signal fed back by the first driving circuit is abnormal. When the signal fed back from the circuit is abnormal, the input path of the vertical synchronization signal to the first driving circuit is disconnected, or when the signal fed back from the second driving circuit is detected to be abnormal, the input path from the vertical synchronization signal to the second driving circuit is disconnected.
  • the self-test interruption device provided in the embodiments of the present application can automatically switch from a bilateral driving mode to a unilateral driving mode when a single-sided driving circuit fails, thereby improving the reliability and yield of the display panel display driving.
  • Each module in the above self-test interruption device may be implemented in whole or in part by software, hardware, and a combination thereof.
  • the above-mentioned modules may be embedded in the hardware form or independent of the processor in the computer device, or may be stored in the memory of the computer device in the form of software, so that the processor calls and performs the operations corresponding to the above modules.
  • a computer device is provided.
  • the computer device may be an interrupt, and its internal structure diagram may be as shown in FIG. 10.
  • the computer equipment includes a processor, a memory, a network interface, a display panel, and an input device connected through a system bus.
  • the processor of the computer device is used to provide computing and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium and an internal memory.
  • the non-volatile storage medium stores an operating system and a computer program.
  • This internal memory provides an environment for the operation of the operating system and computer programs in a non-volatile storage medium.
  • the computer device's network interface is used to communicate with external interrupts via a network connection.
  • the computer program is executed by a processor to implement a self-test interrupt method.
  • the display panel of the computer device may be a liquid crystal display panel or an electronic ink display panel
  • the input device of the computer device may be a touch layer covered on a display screen, or a button, a trackball, or a touchpad provided on the computer device casing , Or an external keyboard, trackpad, or mouse.
  • FIG. 10 is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer equipment to which the scheme of the present application is applied.
  • the computer equipment may include a comparison More or fewer components are shown in the figure, or some components are combined, or have different component arrangements.
  • a computer device includes a memory and a processor.
  • the memory stores a computer program.
  • the processor executes the computer program, the steps shown in FIG. 6 are implemented:
  • S20 Acquire a signal fed back by the first driving circuit and a signal fed back by the second driving circuit;
  • the computer device provided therein can call a computer program stored in the memory.
  • abnormality detection of the first driving circuit and the second driving circuit can be implemented, and As a result of the detection, the driving of the driving circuit on the abnormal side is automatically interrupted, and the display panel is driven by the driving circuit on the normal side to improve the reliability and effectiveness of the driving.
  • a computer-readable storage medium stores a computer program thereon.
  • the steps shown in FIG. 6 are implemented:
  • S20 Acquire a signal fed back by the first driving circuit and a signal fed back by the second driving circuit;
  • Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory can include random access memory (RAM) or external cache memory.
  • RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
  • SRAM static RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDRSDRAM dual data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchronous chain Synchlink DRAM
  • Rambus direct RAM
  • DRAM direct memory bus dynamic RAM
  • RDRAM memory bus dynamic RAM

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Abstract

公开了一种显示控制装置，该控制装置中的自检中断模块（30）通过检测第一驱动电路（10）的反馈信号和第二驱动电路（20）的反馈信号，控制第一驱动电路（10）和第二驱动电路（20）的工作状态。

Description

显示控制装置、显示器和自检中断方法
本申请要求于2018年9月27日提交中国专利局，申请号为2018111318622，申请名称为“显示控制装置、显示器、自检中断方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种显示控制装置、显示器和自检中断方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(Personal Digital Assistant，PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GDL(Gate Driver Less)技术，即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板(Integrated Circuit，IC)来完成水平扫描线的驱动。采用GDL技术制成的驱动电路驱动显示面板，能减少外接IC的焊接工序，有机会提升产能并降低产品成本，而且可以使显示面板更适合制作窄边框或无边框的显示产品。
但是发明人意识到，驱动电路(GDL电路)中存在成千上万颗TFT器件，而一旦器件均匀性较差或稳定性较差，驱动电路就会异常，造成显示面板失效，使得显示面板显示可靠性低。
发明内容
根据本申请公开的各种实施例，提供一种显示控制装置、显示器和自检中断方法。
一种显示控制装置，包括：第一驱动电路，第二驱动电路和自检中断模块；
第一驱动电路设置为从第一侧驱动显示面板，第一驱动电路的输出端与自检中断模块的第一输入端连接；
第二驱动电路设置为从第二侧驱动显示面板，第二驱动电路的输出端与自检中断模块的第二输入端连接；
自检中断模块的第一输出端与第一驱动电路的输入端连接，自检中断模块的第二输出端与第二驱动电路的输入端连接，自检中断模块的开始信号接线端用于接入垂直同步信号；
自检中断模块设置为在第一驱动电路的输出端反馈的信号异常时断开垂直同步信号到第一驱动电路的输入通路或在第二驱动电路的输出端反馈的信号异常时断开垂直同步信号到第二驱动电路的输入通路。
一种显示器，包括显示面板和上述显示控制装置。
一种应用于上述显示控制装置的自检中断方法，包括：
获取第一驱动电路反馈的信号和第二驱动电路反馈的信号；
在检测第一驱动电路反馈的信号异常时，则断开垂直同步信号到第一驱动电路的输入通路，
或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为根据一个或多个实施例中显示控制装置的结构示意图；
图2为另一个实施例中显示控制装置的结构示意图；
图3为根据一个或多个实施例中第一驱动电路的反馈信号的时序图；
图4为根据一个或多个实施例中第一自检中断电路与第一驱动电路的连接示意图；
图5为根据一个或多个实施例中第二自检中断电路与第二驱动电路的连接示意图；
图6为根据一个或多个实施例中自检中断方法的流程示意图；
图7为根据一个或多个实施例中判断第一驱动电路反馈的信号异常的步骤流程示意 图；
图8为根据一个或多个实施例中判断第二驱动电路反馈的信号异常的步骤流程示意图；
图9为根据一个或多个实施例中自检中断装置的结构示意图；
图10为根据一个或多个实施例中计算机设备的内部结构图。
具体实施方式
为了使本申请的技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请实施例提供了一种显示控制装置，如图1所示，包括：第一驱动电路10，第二驱动电路20和自检中断模块30，第一驱动电路10设置为从第一侧驱动显示面板40，第一驱动电路10的输出端与自检中断模块30的第一输入端连接，第二驱动电路20设置为从第二侧驱动显示面板40，第二驱动电路20的输出端与自检中断模块30的第二输入端连接，自检中断模块30的第一输出端与第一驱动电路10的输入端连接，自检中断模块30的第二输出端与第二驱动电路20的输入端连接，自检中断模块30的开始信号接线端用于接入垂直同步信号，自检中断模块30设置为在第一驱动电路10的输出端反馈的信号异常时断开垂直同步信号到第一驱动电路10的输入通路或在第二驱动电路20的输出端反馈的信号异常时断开垂直同步信号到第二驱动电路20的输入通路。
驱动电路可以是无需外置栅极驱动芯片(gate driver less，GDL)的驱动电路，简称为GDL电路，是运用显示面板40的原有阵列制程，制作在显示区周围基板上的水平扫描线的驱动电路。第一侧和第二侧是指正常使用显示面板40时，面对显示面板40显示区域的左侧和右侧两个侧面，即第一驱动电路10和第二驱动电路20分别从显示面板40的左右两侧驱动显示面板40上的薄膜晶体管。垂直同步信号(STV信号，也称帧同步信号)是由时序控制器输出的控制信号，用来指示新的一帧图像的开始。自检中断模块30是指能够对第一驱动电路10和第二驱动电路20的运行情况进行自检，并根据自检结果对第一驱动电路10和第二驱动电路20的驱动工作状态进行控制的电路模块。
自检中断模块30的第一输入端接收第一驱动电路10的输出电信号，同时，自检中断模块30的第二输入端接收第二驱动电路20的输出电信号，当自检中断模块30检测到第一驱动电路10的输出异常时，为保证可以正常驱动显示面板40工作，自检中断模块30的第一输出端输出控制信号，以断开垂直同步信号到第一驱动电路10的输入通路，切除第一驱动电路10，由第二驱动电路20从第二侧驱动显示面板40显示，由双边驱动模式切换为单边工作模式，以保证在单侧驱动电路异常时，仍可以正常驱动显示面板40进行显示。或者，在自检中断模块30检测到第二驱动电路20的输出异常时，则说明可能由于第二驱动电路20的组成器件均匀性差或稳定性较差而导致第二驱动电路20故障，不能从第二侧正常驱动显示面板40，此时自检中断模块30断开垂直同步信号到第二驱动电路20的输入通路，切除第二驱动电路20，由第一驱动电路10和第二驱动电路20双边驱动的模式切换到由第一驱动电路10单边驱动的模式。
在其中一个实施例中，如图2所示，自检中断模块30包括第一自检中断电路31和第二自检中断电路32；第一驱动电路10包括输入端和多级输出端，第二驱动电路20包括输入端和多级输出端；第一自检中断电路31的输入端与第一驱动电路10的后级输出端相连，第一自检中断电路31的输出端与第一驱动电路10连接；第二自检中断电路32的输入端与第二驱动电路20的后级输出端相连，第二自检中断电路32的输出端与第二驱动电路20连接。
多级输出端是指第一驱动电路10和第二驱动电路20的输入信号从输入端开始逐级传递，并在各级均对应一个输出端。为了较好地检测到第一驱动电路10和第二驱动电路20的整体情况，并实现对第一驱动电路10和第二驱动电路20的独立中断控制，采用第一自检中断电路31检测第一驱动电路10的后级输出端反馈的信号，判断当前第一驱动电路10的输出是否异常，若异常，则第一自检中断电路31切断STV信号通向第一驱动电路10的通路，由第二驱动电路20单边驱动显示面板40显示。同理，采用第二自检中断电路32检测第二驱动电路20的后级输出端反馈的信号，判断当前第二驱动电路20的输出是否异常，若异常，则第二自检中断电路32切断STV信号通向第二驱动电路20的通路，由第一驱动电路10单边驱动显示面板40显示。
在其中一个实施例中，如图3所示，显示面板40包括正电源输入端，负电源输入端 和公共电极，正电源输入端用于连接栅极开启电源，负电源输入端用于连接栅极关断电源，公共电极用于接入公共电压；第一自检中断电路31包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第一电容C1；第一晶体管T1的第一极用于接正电源输入端，第一晶体管T1的控制极与第一驱动电路10的输出端连接，第一晶体管T1的第二极与第二晶体管T2的第一极连接；第二晶体管T2的控制极用于接入数据使能信号，第二晶体管T2的第二极用于接公共电极，且与第四晶体管T4的控制极；第三晶体管T3的第一极用于接正电源输入端，第三晶体管T3的控制极与第一驱动电路10的输出端连接，第三晶体管T3的第二极分别与第四晶体管T4的第一极、第五晶体管T5的控制极和第六晶体管T6的第一极连接；第四晶体管T4的第二极用于接负电源输入端；第五晶体管T5的第一极用于接入垂直同步信号，第五晶体管T5的第二极与第一驱动电路10的输入端连接；第六晶体管T6的控制极用于接入扫描信号，扫描信号用于对显示面板40进行行扫描；第六晶体管T6的第二极用于接负电源输入端，第一电容C1的一端连接第五晶体管T5的控制极，第一电容C1的另一端连接第五晶体管T5的第二极。
栅极开启电源，是指用于提供栅极打开的电源，该电源为正电源VGH。栅极关断电源，是指用于提供栅极关端电源，该电源为负电源VHL。显示面板40的正电源输入端接的栅极开启电源电压VGH与公共电压之间产生正电压差，该电压差开启显示面板40的薄膜晶体管，打开与各液晶连接的薄膜晶体管；负电源输入端接的栅极关断电源电压VHL和公共电压之间产生负电压差，该电压差加载在显示面板40的薄膜晶体管上，使得薄膜晶体管关断。数据使能信号(DE信号，也称有效显示数据选通信号)，用于区分接收的视频信号为有效视频信号还是无效视频信号。
为了更好的说明第一驱动电路10的工作过程，以图4所示的时序图为例：T1～T6均在栅极加载高电平时打开，在t1时刻，数据是能信号为低电平，第二晶体管T2和第四晶体管T4关断，对于第一驱动电路10反馈的信号为正常信号(FB/normal信号)时，第一晶体管T1和第三晶体管T3打开，扫描信号G1为低电平，第六晶体管T6关断，栅极开启电源电压VGH对第五晶体管T5的栅极充电，使得第五晶体管T5打开，垂直同步信号STV输入到第一驱动电路10。第五晶体管T5的栅极由于第一电容C1的稳压作用，保持 高电位，待t3时刻，垂直同步信号STV为高电平输出时，驱动第一驱动电路10工作，从而驱动显示面板40正常显示，在垂直同步信号STV高电平输出后，即t4时刻，扫描信号G1高电平输入，打开第六晶体管T6，此时第五晶体管T5的栅极为低电位，第五晶体管T5关断，进行下拉重置。
在任意时刻，对于第一驱动电路10反馈的信号为直流信号(FB/abnormal1信号)时，由于第一驱动电路10反馈的信号为低电平，所以第一晶体管T1和第三晶体管T3均关断，第五晶体管T5无法打开，垂直同步信号STV无法输入到第一驱动电路10，此时第一驱动电路10不能正常驱动显示面板40显示，由第二驱动电路20驱动显示面板40显示。对于第一驱动电路10反馈的信号为多脉冲信号(FB/abnormal2信号)时，即使在t1时刻，垂直同步信号STV可以正常输入到第一驱动电路10，在垂直同步信号STV高电平输出后，扫描信号G1高电平输入，第一驱动电路10反馈的信号(FB/abnormal2信号)与扫描信号G1同为高电平，此时，第一晶体管T1和第二晶体管T2同时打开，第四晶体管T4的栅极储存高电位，第四晶体管T4保持一直打开状态，使得第五晶体管T5的栅极无法冲到高电位，导致第五晶体管T5无法打开，垂直同步信号STV无法正常输入到第一驱动电路10，此时由正常工作的第二驱动电路20驱动显示面板40显示。
综上，第一自检中断电路31能够在第一驱动电路10反馈的信号为直流信号或多脉冲异常信号时，自动中断第一驱动电路10对显示面板40的驱动，由正常工作的第二驱动电路20驱动显示面板40显示，提高驱动有效性和可靠性。可选的，第一晶体管T1的栅极和第三晶体管T3的栅极均可以连接第一驱动电路10的最后一级输出端。在其中一个实施例中，第一自检中断电路还包括第二电容C2，第二电容C2串接在第二晶体管T2和公共电极之间。其中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管可以为N沟道型场效应管，也可以是其他类型的晶体管，只要是符合上述工作逻辑的晶体管均为本申请所保护的范围。
在其中一个实施例中，如图5所示，第二自检中断电路32包括与第一自检中断电路31结构相同的电路，第二自检中断电路32中的第五晶体管T5的第二极与第二驱动电路20的输入端连接。上述第二自检中断电路32包括与第一自检中断电路31结构相同的电路，是指第一自检中断电路31的内部电路结构与第二自检中断电路32的内部电路结构一 致，但各器件的外接端口，随着自检中断的控制对象不同而相应变化，其中第二自检中断电路32中的第五晶体管T5的第二极就与第二驱动电路20的输入端连接，用于控制第二驱动电路20的驱动状态。且第一晶体管T1的栅极和第三晶体管T3的栅极均与第二驱动电路20的输出端连接，用于采集第二驱动电路20的反馈信号FB1，以判断第二驱动电路20是否发生异常。可选的，第一晶体管T1的栅极和第三晶体管T3的栅极均与第二驱动电路20的最后一级输出端连接。可选的，第二自检中断电路还包括第二电容C2，第二电容C2串接在第二晶体管T2和公共电极之间。
本申请实施例还提供了一种显示器，如图1和图2所示，包括显示面板40和上述显示控制装置。本申请实施例提供的这种显示器，在第一驱动电路10和第二驱动电路20均正常时，由第一驱动电路10和第二驱动电路20从第二侧和第二侧分别驱动显示面板40进行显示。自检中断模块30根据获取的第一驱动电路10反馈的信号判定第一驱动电路10异常时，则切断垂直同步信号通向第一驱动电路10的通路，使得第一驱动电路10无法进行驱动工作，由第二驱动电路20单边驱动显示面板40显示。同理，若自检中断模块30根据获取的第二驱动电路20反馈的信号判定第二驱动电路20异常时，则切断垂直同步信号通向第二驱动电路20的通路，使得第二驱动电路20无法进行驱动工作，由第一驱动电路10单边驱动显示面板40显示，以提高显示器的驱动可靠性和有效性。在其中一个实施例中，显示面板40可以是液晶显示面板。
如图6所示，本申请实施例还提供了一种应用于上述显示控制装置的自检中断方法，包括：
S20：获取第一驱动电路反馈的信号和第二驱动电路反馈的信号；
S40：在检测第一驱动电路反馈的信号异常时，则断开垂直同步信号到第一驱动电路的输入通路，
或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路。
第一驱动电路等释义与上述实施例中相同，在此不做赘述。首先，获取第一驱动电路反馈的信号和第二驱动电路反馈的信号，通过判断第一驱动电路反馈的信号是否异常，可以判断第一驱动电路是否故障，若第一驱动电路故障，则断开垂直同步信号到第一驱动电 路的输入通路，由第二驱动电路驱动显示面板显示。或者，在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路，由第一驱动电路驱动显示面板进行显示。本申请实施例提供的自检中断方法，通过检测两边驱动电路的反馈信号来判断两侧的驱动电路是否故障，若一侧驱动电路发生故障，则中断故障侧的驱动电路的驱动工作，由正常侧的驱动电路对显示面板进行显示驱动，由双边驱动模式切换为单边驱动模式，以保证在单侧驱动电路故障时，任可以正常驱动显示面板的显示，提高驱动可靠性和有效性。
在其中一个实施例中，如图7所示，判断第一驱动电路反馈的信号异常的步骤包括：
S41：检测第一驱动电路反馈的信号是否为直流信号或多脉冲信号；
S42：若检测到第一驱动电路反馈的信号为直流信号或多脉冲信号，则判定第一驱动电路反馈的信号异常。
在工程实践中，常见的第一驱动电路异常有两种情况。第一种是第一驱动电路反馈的信号为直流电位，即驱动信号无法通过第一驱动电路正常传递；第二种是第一驱动电路中的输出部分异常，此时第一驱动电路的反馈信号和其对用的时序一致，为多脉冲信号。所以判断第一驱动电路反馈的信号异常的步骤可以是检测第一驱动电路反馈的信号是否为直流信号或多脉冲信号，若第一驱动电路反馈的信号为两种信号中的其中一种，则判定第一驱动电路反馈的信号异常。
在其中一个实施例中，如图8所示，判断第二驱动电路反馈的信号异常的步骤包括：
S43：检测第二驱动电路反馈的信号是否为直流信号或多脉冲信号；
S44：若检测到第二驱动电路反馈的信号为直流信号或多脉冲信号，则判定第二驱动电路反馈的信号异常。
同上述第一驱动电路反馈的信号异常的判断过程，第二驱动电路反馈的信号异常的判断步骤可以是，检测第二驱动电路反馈的信号是否为直流信号或多脉冲信号，若为二者中的其中一种情况，则判定第二驱动电路反馈的信号异常。
应该理解的是，虽然图6-8的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图6-8中的至少一 部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本申请实施例还提供了一种自检中断装置，如图9所示，包括：
反馈信号获取单元1，设置为获取第一驱动电路反馈的信号和第二驱动电路反馈的信号；
中断控制单元2，设置为在检测第一驱动电路反馈的信号异常时，则断开垂直同步信号到第一驱动电路的输入通路，
或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路。
关于第一驱动电路等的释义与上述实施例中相同，在此不做赘述。反馈信号获取单元1获取第一驱动电路反馈的信号和第二驱动电路反馈的信号并发送至中断控制单元2，然后中断控制单元2检测第一驱动电路反馈的信号是否异常，若判定第一驱动电路反馈的信号异常，则断开垂直同步信号到第一驱动电路的输入通路，或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路。本申请实施例提供的这种自检中断装置，可以在单侧驱动电路故障时，由双边驱动模式自动切换到单边驱动模式，提高显示面板显示驱动的可靠性和良率。
关于自检中断装置的具体限定可以参见上文中对于自检中断方法的限定，在此不再赘述。上述自检中断装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。
在一个实施例中，提供了一种计算机设备，该计算机设备可以是中断，其内部结构图可以如图10所示。该计算机设备包括通过系统总线连接的处理器、存储器、网络接口、显示面板和输入装置。其中，该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作系统和计算机程序。该内存储器为非易失性存储介质中的操作系统和计算机程序的运行提供环 境。该计算机设备的网络接口用于与外部的中断通过网络连接通信。该计算机程序被处理器执行时以实现一种自检中断方法。该计算机设备的显示面板可以是液晶显示面板或者电子墨水显示面板，该计算机设备的输入装置可以是显示屏上覆盖的触摸层，也可以是计算机设备外壳上设置的按键、轨迹球或触控板，还可以是外接的键盘、触控板或鼠标等。
本领域技术人员可以理解，图10中示出的结构，仅仅是与本申请方案相关的部分结构的框图，并不构成对本申请方案所应用于其上的计算机设备的限定，计算机设备可以包括比图中所示更多或更少的部件，或者组合某些部件，或者具有不同的部件布置。
一种计算机设备，包括存储器和处理器，存储器存储有计算机程序，处理器执行计算机程序时实现如图6所示的步骤：
S20：获取第一驱动电路反馈的信号和第二驱动电路反馈的信号；
S40：在检测第一驱动电路反馈的信号异常时，则断开垂直同步信号到第一驱动电路的输入通路，
或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路。
本申请提供的计算机设备，其上的处理器在工作时，可以调取存储器中存储的计算机程序，执行该程序过程中，可以实现对第一驱动电路和第二驱动电路的异常检测，并根据检测结果，自动中断异常侧的驱动电路的驱动，由正常侧的驱动电路对显示面板进行显示驱动，提高驱动的可靠性和有效性。
一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现如图6所示的步骤：
S20：获取第一驱动电路反馈的信号和第二驱动电路反馈的信号；
S40：在检测第一驱动电路反馈的信号异常时，则断开垂直同步信号到第一驱动电路的输入通路，
或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到第二驱动电路的输入通路。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读 取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种显示控制装置，包括：第一驱动电路，第二驱动电路和自检中断模块；
    所述第一驱动电路设置为从第一侧驱动显示面板，所述第一驱动电路的输出端与所述自检中断模块的第一输入端连接；
    所述第二驱动电路设置为从第二侧驱动所述显示面板，所述第二驱动电路的输出端与所述自检中断模块的第二输入端连接；
    所述自检中断模块的第一输出端与所述第一驱动电路的输入端连接，所述自检中断模块的第二输出端与所述第二驱动电路的输入端连接，所述自检中断模块的开始信号接线端用于接入垂直同步信号；
    所述自检中断模块设置为在所述第一驱动电路的输出端反馈的信号异常时断开所述垂直同步信号到所述第一驱动电路的输入通路或在所述第二驱动电路的输出端反馈的信号异常时断开所述垂直同步信号到所述第二驱动电路的输入通路。
  2. 根据权利要求1所述的显示控制装置，其中，所述自检中断模块包括第一自检中断电路和第二自检中断电路；所述第一驱动电路包括输入端和多级输出端，第二驱动电路包括输入端和多级输出端；
    所述第一自检中断电路的输入端与所述第一驱动电路的后级输出端相连，所述第一自检中断电路的输出端与所述第一驱动电路连接；
    所述第二自检中断电路的输入端与所述第二驱动电路的后级输出端相连，所述第二自检中断电路的输出端与所述第二驱动电路连接。
  3. 根据权利要求2所述的显示控制装置，其中，所述显示面板包括正电源输入端，负电源输入端和公共电极，所述正电源输入端用于连接栅极开启电源，所述负电源输入端用于连接栅极关断电源，所述公共电极用于接入公共电压；所述第一自检中断电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第一电容；
    所述第一晶体管的第一极用于接所述正电源输入端，所述第一晶体管的控制极与所述第一驱动电路的输出端连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述第二晶体管的控制极用于接入数据使能信号，所述第二晶体管的第二极用于接所 述公共电极，且与所述第四晶体管的控制极；
    所述第三晶体管的第一极用于接所述正电源输入端，所述第三晶体管的控制极与所述第一驱动电路的输出端连接，所述第三晶体管的第二极分别与所述第四晶体管的第一极、所述第五晶体管的控制极和所述第六晶体管的第一极连接；
    所述第四晶体管的第二极用于接所述负电源输入端；
    所述第五晶体管的第一极用于接入所述垂直同步信号，所述第五晶体管的第二极与所述第一驱动电路的输入端连接；
    所述第六晶体管的控制极用于接入扫描信号，所述扫描信号用于对所述显示面板进行行扫描；
    所述第六晶体管的第二极用于接所述负电源输入端，所述第一电容的一端连接所述第五晶体管的控制极，所述第一电容的另一端连接所述第五晶体管的第二极。
  4. 根据权利要求3所述的显示控制装置，其中，所述第一自检中断电路还包括第二电容，所述第二电容的一端与所述第二晶体管的第二极连接，另一端与所述公共电压输入端连接。
  5. 根据权利要求3所述的显示控制装置，其中，所述第二自检中断电路包括与所述第一自检中断电路结构相同的电路，所述第二自检中断电路中的第五晶体管的第二极与所述第二驱动电路的输入端连接，所述第二自检中断电路中的第一晶体管的栅极和第三晶体管的栅极均与所述第二驱动电路的输出端连接。
  6. 根据权利要求4所述的显示控制装置，其中，所述第二自检中断电路包括与所述第一自检中断电路结构相同的电路，所述第二自检中断电路中的第五晶体管的第二极与所述第二驱动电路的输入端连接，所述第二自检中断电路中的第一晶体管的栅极和第三晶体管的栅极均与所述第二驱动电路的输出端连接。
  7. 根据权利要求3所述的显示控制装置，其中，所述第一晶体管第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为N沟道型场效应管。
  8. 一种显示器，包括所述显示面板和显示控制装置，所述显示控制装置包括：第一驱动电路，第二驱动电路和自检中断模块；
    所述第一驱动电路设置为从第一侧驱动显示面板，所述第一驱动电路的输出端与所述 自检中断模块的第一输入端连接；
    所述第二驱动电路设置为从第二侧驱动所述显示面板，所述第二驱动电路的输出端与所述自检中断模块的第二输入端连接；
    所述自检中断模块的第一输出端与所述第一驱动电路的输入端连接，所述自检中断模块的第二输出端与所述第二驱动电路的输入端连接，所述自检中断模块的开始信号接线端用于接入垂直同步信号；
    所述自检中断模块设置为在所述第一驱动电路的输出端反馈的信号异常时断开所述垂直同步信号到所述第一驱动电路的输入通路或在所述第二驱动电路的输出端反馈的信号异常时断开所述垂直同步信号到所述第二驱动电路的输入通路。
  9. 根据权利要求8所述的显示器，其中，所述自检中断模块包括第一自检中断电路和第二自检中断电路；所述第一驱动电路包括输入端和多级输出端，第二驱动电路包括输入端和多级输出端；
    所述第一自检中断电路的输入端与所述第一驱动电路的后级输出端相连，所述第一自检中断电路的输出端与所述第一驱动电路连接；
    所述第二自检中断电路的输入端与所述第二驱动电路的后级输出端相连，所述第二自检中断电路的输出端与所述第二驱动电路连接。
  10. 根据权利要求9所述的显示器，其中，所述显示面板包括正电源输入端，负电源输入端和公共电极，所述正电源输入端用于连接栅极开启电源，所述负电源输入端用于连接栅极关断电源，所述公共电极用于接入公共电压；所述第一自检中断电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第一电容；
    所述第一晶体管的第一极用于接所述正电源输入端，所述第一晶体管的控制极与所述第一驱动电路的输出端连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述第二晶体管的控制极用于接入数据使能信号，所述第二晶体管的第二极用于接所述公共电极，且与所述第四晶体管的控制极；
    所述第三晶体管的第一极用于接所述正电源输入端，所述第三晶体管的控制极与所述第一驱动电路的输出端连接，所述第三晶体管的第二极分别与所述第四晶体管的第一极、所述第五晶体管的控制极和所述第六晶体管的第一极连接；
    所述第四晶体管的第二极用于接所述负电源输入端；
    所述第五晶体管的第一极用于接入所述垂直同步信号，所述第五晶体管的第二极与所述第一驱动电路的输入端连接；
    所述第六晶体管的控制极用于接入扫描信号，所述扫描信号用于对所述显示面板进行行扫描；
    所述第六晶体管的第二极用于接所述负电源输入端，所述第一电容的一端连接所述第五晶体管的控制极，所述第一电容的另一端连接所述第五晶体管的第二极。
  11. 根据权利要求10所述的显示器，其中，所述第一自检中断电路还包括第二电容，所述第二电容的一端与所述第二晶体管的第二极连接，另一端与所述公共电压输入端连接。
  12. 根据权利要求10所述的显示器，其中，所述第二自检中断电路包括与所述第一自检中断电路结构相同的电路，所述第二自检中断电路中的第五晶体管的第二极与所述第二驱动电路的输入端连接，所述第二自检中断电路中的第一晶体管的栅极和第三晶体管的栅极均与所述第二驱动电路的输出端连接。
  13. 根据权利要求11所述的显示器，其中，所述第二自检中断电路包括与所述第一自检中断电路结构相同的电路，所述第二自检中断电路中的第五晶体管的第二极与所述第二驱动电路的输入端连接，所述第二自检中断电路中的第一晶体管的栅极和第三晶体管的栅极均与所述第二驱动电路的输出端连接。
  14. 根据权利要求10所述的显示器，其中，所述第一晶体管第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为N沟道型场效应管。
  15. 根据权利要求7所述的显示器，其中，所述显示面板为液晶显示面板。
  16. 一种显示控制装置的自检中断方法，显示控制装置包括：第一驱动电路，第二驱动电路和自检中断模块；所述第一驱动电路设置为从第一侧驱动显示面板，所述第一驱动电路的输出端与所述自检中断模块的第一输入端连接；所述第二驱动电路设置为从第二侧驱动所述显示面板，所述第二驱动电路的输出端与所述自检中断模块的第二输入端连接；所述自检中断模块的第一输出端与所述第一驱动电路的输入端连接，所述自检中断模块的第二输出端与所述第二驱动电路的输入端连接，所述自检中断模块的开始信号接线端用于 接入垂直同步信号；自检中断方法包括：
    获取所述第一驱动电路反馈的信号和所述第二驱动电路反馈的信号；以及
    在检测所述第一驱动电路反馈的信号异常时，则断开垂直同步信号到所述第一驱动电路的输入通路，
    或在检测第二驱动电路反馈的信号异常时，则断开垂直同步信号到所述第二驱动电路的输入通路。
  17. 根据权利要求16所述的自检中断方法，其中，判断第一驱动电路反馈的信号异常的步骤包括：
    检测所述第一驱动电路反馈的信号是否为直流信号；以及
    若检测到所述第一驱动电路反馈的信号为直流信号，则判定所述第一驱动电路反馈的信号异常。
  18. 根据权利要求16所述的自检中断方法，其中，判断第一驱动电路反馈的信号异常的步骤包括：
    检测所述第一驱动电路反馈的信号是否为多脉冲信号；以及
    若检测到所述第一驱动电路反馈的信号为多脉冲信号，则判定所述第一驱动电路反馈的信号异常。
  19. 根据权利要求16所述的自检中断方法，其中，判断第二驱动电路反馈的信号异常的步骤包括：
    检测所述第二驱动电路反馈的信号是否为直流信号；以及
    若检测到所述第二驱动电路反馈的信号为直流信号，则判定所述第二驱动电路反馈的信号异常。
  20. 根据权利要求16所述的自检中断方法，其中，判断第二驱动电路反馈的信号异常的步骤包括：
    检测所述第二驱动电路反馈的信号是否为多脉冲信号；以及
    若检测到所述第二驱动电路反馈的信号为多脉冲信号，则判定所述第二驱动电路反馈的信号异常。
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