WO2020059199A1 - Piezoelectric device - Google Patents

Piezoelectric device Download PDF

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Publication number
WO2020059199A1
WO2020059199A1 PCT/JP2019/017431 JP2019017431W WO2020059199A1 WO 2020059199 A1 WO2020059199 A1 WO 2020059199A1 JP 2019017431 W JP2019017431 W JP 2019017431W WO 2020059199 A1 WO2020059199 A1 WO 2020059199A1
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Prior art keywords
layer
base
piezoelectric device
present
piezoelectric
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PCT/JP2019/017431
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French (fr)
Japanese (ja)
Inventor
諭卓 岸本
伸介 池内
藤本　克己
木村　哲也
文弥 黒川
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株式会社村田製作所
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Priority to DE112019004721.3T priority Critical patent/DE112019004721T5/en
Publication of WO2020059199A1 publication Critical patent/WO2020059199A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02086—Means for compensation or elimination of undesirable effects
    • H03H9/02149—Means for compensation or elimination of undesirable effects of ageing changes of characteristics, e.g. electro-acousto-migration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/173—Air-gaps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/174—Membranes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type

Definitions

  • the present invention relates to piezoelectric devices.
  • Non-Patent Document 1 As a prior document describing the configuration of a piezoelectric device, there is, for example, the following Non-Patent Document 1.
  • the piezoelectric device described in Non-Patent Document 1 includes an SOI substrate having a cavity, a piezoelectric layer disposed at least above the cavity, an upper electrode layer provided above the piezoelectric layer, and a piezoelectric layer. And a lower electrode layer provided on the opposite side to the upper electrode layer.
  • a piezoelectric layer is formed on the Si layer of the SOI substrate by sputtering or the like.
  • the piezoelectric layer grows in a direction perpendicular to the surface of the Si layer. Therefore, when the portion of the Si layer of the SOI substrate located on the concave portion forming the cavity is bent, the crystal growth directions of the piezoelectric layers formed on the bent portion of the Si layer intersect with each other. Are formed unevenly. In this case, the piezoelectric characteristics in the piezoelectric layer deteriorate.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a piezoelectric device that can improve the piezoelectric characteristics by making the portion of the piezoelectric layer located on the concave portion uniform.
  • a piezoelectric device includes a base and a laminated portion.
  • the base includes one main surface and the other main surface located on the opposite side to the one main surface, and has a concave portion formed on the one main surface.
  • the laminated portion is laminated on one main surface of the base so as to cover the recess from above.
  • the laminated portion includes a single crystal piezoelectric layer, an upper electrode layer, and a lower electrode layer at least above the recess.
  • the upper electrode layer is disposed above the single-crystal piezoelectric layer.
  • the lower electrode layer is disposed so as to face at least a part of the upper electrode layer with the single-crystal piezoelectric layer interposed therebetween.
  • the portion of the piezoelectric layer located on the concave portion can be made uniform, and the piezoelectric characteristics of the piezoelectric device can be improved.
  • FIG. 2 is a cross-sectional view of the piezoelectric device shown in FIG. 1 as viewed from the direction of arrows II-II.
  • FIG. 3 is a partially enlarged view of a section III in the cross-sectional view of the piezoelectric device shown in FIG. 2.
  • FIG. 4 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 1 is a cross-sectional view of the piezoelectric device shown in FIG. 1 as viewed from the direction of arrows II-II.
  • FIG. 3 is a partially enlarged view of a section III in the cross-sectional view of the piezoelectric device shown in FIG. 2.
  • FIG. 4 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single-crystal pie
  • FIG. 4 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a state where the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 3 is a cross-sectional view showing a state before a concave portion is formed in a base in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 4 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 4 is
  • FIG. 4 is a cross-sectional view showing a state in which a concave portion is formed in the base in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 7 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 6 in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a state where the base is joined to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 4 is a cross-sectional view showing a state in which the upper surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 4 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 9 is a cross-sectional view showing a state in which a single-crystal piezoelectric layer is joined to a support substrate in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a state in which the upper surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which a single-crystal piezoelectric layer is bonded to a support substrate in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a state in which the lower surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a state in which the lower surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which a lower electrode layer is provided on a lower surface of a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modified example of Embodiment 1 of the present invention.
  • FIG. 11 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of a lower electrode layer and a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of a lower electrode layer and a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention.
  • FIG. 19 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 18 in the method for manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which a base is joined to a lower surface of an intermediate layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • FIG. 19 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 18 in the method for manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which a base is joined
  • FIG. 9 is a cross-sectional view illustrating a state in which a support substrate is removed in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. It is sectional drawing of the piezoelectric device which concerns on Embodiment 2 of this invention.
  • FIG. 9 is a cross-sectional view illustrating a state before a release layer is formed on a sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. It is sectional drawing which shows the state which formed the peeling layer in the sealing layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which a support substrate is removed in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. It is sectional drawing of the piezoelectric device which concerns on Embodiment 2 of this invention.
  • FIG. 9 is
  • FIG. 7 is a cross-sectional view showing a state in which a sealing layer having a release layer formed thereon is joined to a plurality of layers shown in FIG. 6 in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. It is sectional drawing which shows the state which joined the sealing layer to the lower surface of the intermediate
  • FIG. 9 is a cross-sectional view illustrating a state in which a sealing layer 270 is polished from a lower surface side after a release layer is removed in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • FIG. 29 is a cross-sectional view showing a state where the base shown in FIG. 29 is joined to the plurality of layers shown in FIG. 27 in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a state in which the upper surface of a single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of a single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • FIG. 1 is a plan view of a piezoelectric device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view of the piezoelectric device shown in FIG. 1 as seen from the direction of arrows II-II.
  • FIG. 3 is a partially enlarged view of a section III in the cross-sectional view of the piezoelectric device shown in FIG. In FIG. 1, the internal configuration of the piezoelectric device is indicated by a dotted line.
  • the piezoelectric device 100 includes a base 110 and a stacked unit 120.
  • the base 110 includes one main surface 111 and the other main surface 112 located on the opposite side of the one main surface 111.
  • the base 110 has a concave portion 113 formed on one main surface 111.
  • the width of the opening located on the one main surface 111 side of the recess 113 is smaller than the width of the bottom of the recess 113.
  • the width of the opening may be equal to the width of the bottom, or the width of the opening may be wider than the width of the bottom.
  • a region located above the opening of the recess 113 may be referred to as above the recess 113 in some cases.
  • the concave portion 113 is covered by a laminated portion 120 laminated on one main surface 111.
  • the inside of the concave portion 113 in the piezoelectric device 100 is a closed space.
  • the pressure inside the recess 113 is a negative pressure.
  • the pressure inside the recess 113 may be atmospheric pressure or positive pressure.
  • the material forming the base 110 is not particularly limited.
  • the base 110 is made of Si.
  • the laminated portion 120 is laminated on the one main surface 111 of the base 110 so as to cover the recess 113 from above.
  • the laminated section 120 includes a single-crystal piezoelectric layer 130, an upper electrode layer 140, a lower electrode layer 150, and an intermediate layer 160.
  • the single crystal piezoelectric layer 130 is located above the base 110.
  • Single-crystal piezoelectric layer 130 is arranged such that at least a portion of single-crystal piezoelectric layer 130 is located above recess 113.
  • the single crystal piezoelectric layer 130 is curved in a convex shape toward the base 110 in a region located above the concave portion 113.
  • Single-crystal piezoelectric layer 130 is flat in a region not located above recess 113.
  • the single crystal piezoelectric layer 130 has a hole 131.
  • the hole 131 is formed so as to vertically penetrate the single crystal piezoelectric layer 130.
  • the hole 131 is located on one main surface 111 of the base 110, and is not located above the recess 113.
  • the single crystal piezoelectric layer 130 is made of lithium tantalate or lithium niobate.
  • the single crystal piezoelectric layer 130 made of lithium tantalate or lithium niobate has a uniform polarization state.
  • the upper electrode layer 140 is disposed above the single crystal piezoelectric layer 130.
  • the upper electrode layer 140 is arranged such that at least a part of the upper electrode layer 140 is located above the recess 113.
  • the upper electrode layer 140 is disposed above a part of the single crystal piezoelectric layer 130.
  • an adhesive layer made of Ti or the like may be disposed between the upper electrode layer 140 and the single-crystal piezoelectric layer 130.
  • the lower electrode layer 150 is disposed so as to face at least a part of the upper electrode layer 140 with the single-crystal piezoelectric layer 130 interposed therebetween.
  • the lower electrode layer 150 is arranged such that at least a part of the lower electrode layer 150 is located above the recess 113.
  • the lower electrode layer 150 is disposed above the recess 113 so as to face at least a part of the upper electrode layer 140 with the single crystal piezoelectric layer 130 interposed therebetween.
  • a part of the lower electrode layer 150 is arranged below the hole 131 formed in the single crystal piezoelectric layer 130.
  • the lower electrode layer 150 is formed so as to cover below the hole 131 of the single-crystal piezoelectric layer 130.
  • a two-layer wiring may be stacked on the lower electrode layer 150.
  • the lower electrode layer 150 may be formed so as to cover below the hole 131 of the single-crystal piezoelectric layer 130 via an adhesive layer.
  • the material of the adhesion layer is not particularly limited as long as the material has conductivity and adhesion.
  • the adhesion layer is made of, for example, Ti, Cr, Ni or NiCr.
  • the intermediate layer 160 is laminated so as to cover the lower electrode layer 150 from below.
  • the intermediate layer 160 is provided so as to be in contact with the lower surface of the lower electrode layer 150 and the portion of the lower surface of the single-crystal piezoelectric layer 130 that is not covered with the lower electrode layer 150.
  • the lower surface 161 of the intermediate layer 160 is connected to one main surface 111 of the base 110.
  • the laminated portion 120 is convexly curved toward the other main surface 112.
  • the lower surface 161 of the intermediate layer 160 located above the concave portion 113 is curved convexly toward the other main surface 112.
  • the lower surface 161 of the intermediate layer 160 is flat.
  • the intermediate layer 160 and the base 110 are directly connected to each other. Note that the intermediate layer 160 and the base 110 may not be directly connected to each other. The intermediate layer 160 and the base 110 may be connected to each other via a metal layer.
  • the material of the intermediate layer 160 is not particularly limited as long as it is an insulator.
  • the intermediate layer 160 is made of SiO 2 .
  • the intermediate layer 160 may be made of an organic material having electric insulation and heat insulation.
  • the stacked unit 120 includes the single-crystal piezoelectric layer 130, the upper electrode layer 140, the lower electrode layer 150, and the intermediate layer 160 at least above the recess 113.
  • the upper electrode layer 140 is disposed above the single crystal piezoelectric layer 130 above the recess 113.
  • the lower electrode layer 150 is arranged so as to face at least a part of the upper electrode layer 140 with the single-crystal piezoelectric layer 130 interposed therebetween.
  • the stacked portion 120 is formed in a region located above the concave portion 113 in accordance with expansion and contraction of the single crystal piezoelectric layer 130. Vibrates vertically.
  • FIG. 4 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • the thickness of the single-crystal piezoelectric layer 130 at the time of formation is larger than the thickness of the single-crystal piezoelectric layer 130 finally included in the piezoelectric device 100 according to the present embodiment.
  • the lower electrode layer 150 is provided on the lower surface of the single-crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
  • FIG. 5 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • an intermediate layer 160 is provided on the lower surface of each of the lower electrode layer 150 and the single-crystal piezoelectric layer 130 by a CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • FIG. 6 is a cross-sectional view showing a state in which the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. As shown in FIG. 6, the lower surface of the intermediate layer 160 is flattened by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • FIG. 7 is a cross-sectional view showing a state before the concave portion is formed in the base in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing a state in which a concave portion is formed in the base in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • a recess 113 is formed in the base 110 from the one main surface 111 side of the base 110 by, for example, deep reactive ion etching (Deep Reactive Ion). Form.
  • FIG. 9 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 6 in the method of manufacturing the piezoelectric device according to the first embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a state where the base is joined to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • one main surface 111 of the base 110 is joined to the lower surface 161 of the intermediate layer 160. Thereby, the inside of the concave portion 113 becomes a closed space.
  • the intermediate layer 160 and the base 110 are joined under a vacuum pressure in order to suppress entry of foreign matter into the recess 113.
  • the vacuum pressure may be any of a low vacuum, a medium vacuum, a high vacuum, and an ultra-high vacuum. Since the intermediate layer 160 and the base 110 are joined as described above, the pressure inside the concave portion 113 becomes a negative pressure. Further, since the pressure inside the concave portion 113 becomes a negative pressure, the lower surface 161 of the intermediate layer 160 is convexly curved toward the other main surface 112 above the concave portion 113.
  • the atmosphere for joining the intermediate layer 160 and the base 110 is not limited to a vacuum pressure.
  • the intermediate layer 160 may be joined to the base 110 under atmospheric pressure, or may be joined to the base 110 under high pressure.
  • the lower surface 161 of the intermediate layer 160 may be a flat surface, or may be convex on the side opposite to the other main surface 112 side. It may be curved.
  • FIG. 11 is a cross-sectional view showing a state where the upper surface of the single-crystal piezoelectric layer has been cut off in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • the upper surface of the single-crystal piezoelectric layer 130 is shaved by CMP or the like so that the single-crystal piezoelectric layer 130 has a desired thickness.
  • the thickness of the single-crystal piezoelectric layer 130 is adjusted so that a desired amount of expansion and contraction of the single-crystal piezoelectric layer 130 due to application of a voltage is obtained.
  • lower surface 161 of intermediate layer 160 curves more.
  • a release layer may be formed on the upper surface side of the single crystal piezoelectric layer 130 by ion implantation in advance.
  • the thickness of the single-crystal piezoelectric layer 130 can be easily adjusted by removing the release layer before the upper surface of the single-crystal piezoelectric layer 130 is shaved by CMP or the like.
  • FIG. 12 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
  • an upper electrode layer 140 is provided on a part of the upper surface of the single crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
  • the laminated portion 120 is laminated on the one main surface 111 of the base 110.
  • the laminated portion 120 is curved in a convex shape above the recess 113 toward the other main surface 112.
  • a hole 131 is provided in a part of the upper surface of the single-crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
  • the piezoelectric device 100 according to the first embodiment of the present invention as shown in FIG. 2 is manufactured.
  • the stacked unit 120 includes the single-crystal piezoelectric layer 130, the upper electrode layer 140, and the lower electrode layer 150 at least above the recess 113.
  • a plurality of layers including the single crystal piezoelectric layer 130, the upper electrode layer 140, and the lower electrode layer 150 are joined to the base 110, unlike the case where the polycrystalline piezoelectric layer is formed by film formation.
  • a piezoelectric layer can be provided on the recess 113.
  • the portion of the piezoelectric layer located on the concave portion 113 can be made uniform, and the piezoelectric characteristics of the piezoelectric device 100 can be improved.
  • the intermediate layer 160 is stacked so as to cover the lower electrode layer 150 from below. Accordingly, since the lower surface of the lower electrode layer 150 is not exposed to the outside and the concave portion 113, the deterioration of the lower electrode layer 150 can be suppressed.
  • the lower surface 161 of the intermediate layer 160 is flat in a region that is not located above the concave portion 113. Thereby, the intermediate layer 160 and the base 110 are brought into close contact with each other, and the occurrence of delamination between the intermediate layer 160 and the base 110 can be suppressed.
  • the laminated portion 120 is curved above the concave portion 113 so as to protrude toward the other main surface 112. Since the laminated portion 120 includes the single-crystal piezoelectric layer 130, even when the laminated portion 120 is convexly curved toward the other main surface 112, the portion located on the concave portion 113 of the piezoelectric layer can be removed. It is possible to improve the uniformity and improve the piezoelectric characteristics.
  • the recess 113 is sealed, and the pressure inside the recess 113 is a negative pressure.
  • the intrusion of foreign matter into the recess 113 can be suppressed.
  • the piezoelectric device 100 according to the present embodiment may be manufactured using a support substrate.
  • a method for manufacturing a piezoelectric device according to a modification of the present embodiment will be described.
  • FIG. 13 is a cross-sectional view illustrating a state in which a single-crystal piezoelectric layer is bonded to a support substrate in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • FIG. 14 is a cross-sectional view illustrating a state in which a single-crystal piezoelectric layer is bonded to a support substrate in a piezoelectric device manufacturing method according to a modification of the first embodiment of the present invention.
  • the single-crystal piezoelectric layer 130 is bonded to the lower surface of the support substrate 10.
  • the material forming the support substrate 10 is not particularly limited.
  • the support substrate 10 is made of Si.
  • an intermediate layer made of SiO 2 or the like may be provided on the lower surface of the support substrate 10, and the single-crystal piezoelectric layer 130 may be joined to the lower surface of the intermediate layer.
  • FIG. 15 is a cross-sectional view showing a state in which the lower surface of the single-crystal piezoelectric layer is shaved in the method of manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention.
  • the lower surface of the single-crystal piezoelectric layer 130 is shaved by CMP or the like so that the single-crystal piezoelectric layer 130 has a desired thickness.
  • the thickness of the single-crystal piezoelectric layer 130 is adjusted so that a desired amount of expansion and contraction of the single-crystal piezoelectric layer 130 due to application of a voltage is obtained.
  • FIG. 16 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention.
  • the lower electrode layer 150 is provided on the lower surface of the single crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
  • FIG. 17 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention.
  • an intermediate layer 160 is provided on the lower surface of each of the lower electrode layer 150 and the single crystal piezoelectric layer 130 by a CVD method or a PVD method.
  • FIG. 18 is a cross-sectional view showing a state where the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention. As shown in FIG. 18, the lower surface of the intermediate layer 160 is flattened by CMP or the like.
  • FIG. 19 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 18 in the method of manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention.
  • FIG. 20 is a cross-sectional view showing a state where the base is joined to the lower surface of the intermediate layer in the method of manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention.
  • one main surface 111 of the base 110 is joined to the lower surface 161 of the intermediate layer 160.
  • FIG. 21 is a cross-sectional view showing a state in which the supporting substrate has been removed in the piezoelectric device manufacturing method according to the modification of the first embodiment of the present invention.
  • the support substrate 10 is removed by wet etching.
  • a hole 131 is provided in a part of the upper surface of the single-crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
  • Embodiment 2 a piezoelectric device according to Embodiment 2 of the present invention will be described.
  • the piezoelectric device according to the second embodiment of the present invention is different from the piezoelectric device 100 according to the first embodiment in the configuration of each of the laminated portion and the base. Therefore, the description of the same configuration as that of the piezoelectric device 100 according to the first embodiment of the present invention will not be repeated.
  • FIG. 22 is a sectional view of a piezoelectric device according to Embodiment 2 of the present invention.
  • the sectional view of the piezoelectric device 200 shown in FIG. 22 is shown in the same sectional view as the sectional view of the piezoelectric device 100 shown in FIG.
  • the piezoelectric device 200 includes a base 210 and a laminated part 220.
  • the base 210 includes one main surface 211 and the other main surface 212 located on the opposite side to the one main surface 211.
  • the base 210 has a concave portion 213 formed on one main surface 211.
  • the base 210 includes a lower base 210a and an upper base 210b. On one main surface 211 side of the lower base 210a, an inner concave portion is formed along the concave portion 213.
  • An upper base 210b is provided on the lower base 210a along each of the upper surface located on the one main surface 211 side of the lower base 210a and the inner surface of the inner concave portion. That is, the upper surface of the upper base 210b constitutes one main surface 211 of the base 210.
  • the material forming the base 210 is not particularly limited.
  • the lower base 210a is made of Si.
  • the upper base portion 210b is constituted by SiO 2.
  • the laminated portion 220 is laminated on one main surface 211 of the base 210 so as to cover the concave portion 213 from above.
  • the laminated section 220 includes a single-crystal piezoelectric layer 230, an upper electrode layer 240, a lower electrode layer 250, an intermediate layer 260, and a sealing layer 270.
  • a sealing layer 270 is laminated on the lower surface 261 of the intermediate layer 260.
  • the lower surface of sealing layer 270 is connected to one main surface 111 of base 210.
  • the laminated portion 220 is curved convexly toward the other main surface 212.
  • the lower surface 271 of the sealing layer 270 located above the concave portion 213 is curved convexly toward the other main surface 112. In a region that is not located above the concave portion 213, the lower surface 271 of the sealing layer 270 is flat.
  • the sealing layer 270 and the base 210 are directly connected to each other.
  • the sealing layer 270 and the base 210 need not be directly connected to each other.
  • the sealing layer 270 and the base 210 may be connected to each other via a metal layer.
  • a layer such as a metal layer made of a material different from the material forming each of the sealing layer 270 and the intermediate layer 260 may be arranged.
  • the thickness of the sealing layer 270 in this embodiment is not less than 500 nm and not more than 2 ⁇ m.
  • the material forming the sealing layer 270 is not particularly limited.
  • the sealing layer 270 is made of Si. That is, a Cavity SOI (Silicon On Insulator) substrate is constituted by the base 210 and the sealing layer 270.
  • the stacked portion 220 includes the single crystal piezoelectric layer 230, the upper electrode layer 240, the lower electrode layer 250, the intermediate layer 260, and the sealing layer 270 at least above the concave portion 213. Contains.
  • the upper electrode layer 240 is arranged above the single-crystal piezoelectric layer 230.
  • the lower electrode layer 250 is disposed so as to face at least a part of the upper electrode layer 240 with the single-crystal piezoelectric layer 230 interposed therebetween.
  • the laminated portion 220 is bent up and down above the concave portion 213 in accordance with expansion and contraction of the single crystal piezoelectric layer 230. Vibrate.
  • FIG. 23 is a cross-sectional view showing a state before a release layer is formed on the sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • FIG. 24 is a cross-sectional view showing a state where a release layer is formed on a sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • ion implantation is performed from the lower surface side of the sealing layer 270 to form a peeling layer 272 on the lower surface side of the sealing layer 270.
  • FIG. 25 is a cross-sectional view showing a state in which a sealing layer provided with a release layer is joined to the plurality of layers shown in FIG. 6 in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present embodiment.
  • FIG. 26 is a cross-sectional view showing a state in which a sealing layer is joined to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • the upper surface of the sealing layer 270 is joined to the lower surface 261 of the intermediate layer.
  • an SiO 2 layer may be formed on the upper surface of the sealing layer 270 in advance.
  • the intermediate layer 260 is bonded to the upper surface of the SiO 2 layer provided on the upper surface of the sealing layer 270.
  • FIG. 27 is a cross-sectional view showing a state in which the sealing layer 270 is polished from the lower surface side after the release layer is removed in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • the sealing layer 270 is further shaved from the lower surface side by CMP or the like, so that the sealing layer 270 has a desired thickness.
  • the release layer 272 may not be formed.
  • FIG. 28 is a cross-sectional view showing a state before the upper base and the lower base are formed on the base in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • FIG. 29 is a cross-sectional view showing a state in which an upper base and a lower base are formed on a base in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the concave portion 213 is formed in the base 210 in the same manner as in the method for manufacturing the piezoelectric device 100 according to the first embodiment of the present invention.
  • each of the one main surface 211 of the base 210 and the inner surface of the concave portion 213 is thermally oxidized.
  • the portion of the base 210 that has been thermally oxidized becomes the upper base 210b
  • the portion of the base 210 that has not been thermally oxidized becomes the lower base 210a.
  • FIG. 30 is a cross-sectional view showing a state where the base shown in FIG. 29 is joined to the plurality of layers shown in FIG. 27 in the method of manufacturing the piezoelectric device according to Embodiment 2 of the present invention.
  • FIG. 31 is a cross-sectional view showing a state where the base is joined to the lower surface of the sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • one main surface 211 of the base 210 is joined to the lower surface 271 of the sealing layer 270. Thereby, the inside of the concave portion 213 becomes a closed space.
  • the sealing layer 270 and the base 210 are joined under a vacuum pressure in order to prevent foreign matter from entering the inside of the recess 213.
  • the vacuum pressure may be any of a low vacuum, a medium vacuum, a high vacuum, and an ultra-high vacuum. Since the sealing layer 270 and the base 210 are joined as described above, the pressure inside the concave portion 213 becomes a negative pressure. Further, since the pressure inside the concave portion 213 becomes a negative pressure, the lower surface 271 of the sealing layer 270 is convexly curved toward the other main surface 212 above the concave portion 213.
  • the atmosphere for joining the sealing layer 270 and the base 210 is not limited to a vacuum pressure.
  • the sealing layer 270 may be joined to the base 210 under atmospheric pressure, or may be joined to the base 210 under high pressure.
  • the lower surface 271 of the sealing layer 270 may be flat, or may be convex on the opposite side to the other main surface 212 side. It may be curved.
  • FIG. 32 is a cross-sectional view showing a state in which the upper surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • the upper surface of the single-crystal piezoelectric layer 230 is shaved by CMP or the like so that the single-crystal piezoelectric layer 230 has a desired thickness.
  • the thickness of the single-crystal piezoelectric layer 230 is adjusted so that a desired amount of expansion and contraction of the single-crystal piezoelectric layer 230 due to application of a voltage is obtained.
  • FIG. 33 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of a single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
  • an upper electrode layer 240 is provided on a part of the upper surface of the single-crystal piezoelectric layer 230 by a lift-off method, a plating method, an etching method, or the like.
  • the laminated portion 220 is laminated on the one main surface 211 of the base 210.
  • the sealing layer 270 and the base 210 are joined under a vacuum pressure, the laminated portion 220 is curved in a convex shape toward the other main surface 212.
  • a hole 231 is provided in a part of the upper surface of the single-crystal piezoelectric layer 230 by a lift-off method, a plating method, an etching method, or the like.
  • the piezoelectric device 200 according to the second embodiment of the present invention as shown in FIG. 22 is manufactured.
  • the stacked unit 220 includes the single-crystal piezoelectric layer 230, the upper electrode layer 240, and the lower electrode layer 250 at least above the recess 213. I have.
  • a plurality of layers including the single crystal piezoelectric layer 230, the upper electrode layer 240, and the lower electrode layer 250 are joined to the base 210, unlike the case where the polycrystalline piezoelectric layer is formed by film formation.
  • a piezoelectric layer can be provided on the concave portion 213.
  • the portion of the piezoelectric layer located on the concave portion 213 can be made uniform, and the piezoelectric characteristics of the piezoelectric device 200 can be improved.
  • 10 support substrate 100, 200 piezoelectric device, 110, 210 base, 111, 211 one main surface, 112, 212 the other main surface, 113,213 recess, 120, 220 lamination, 130, 230 single crystal piezoelectric layer , 131,231 holes, 140,240 upper electrode layer, 150,250 lower electrode layer, 160,260 intermediate layer, 161, 261,271 lower surface, 210a lower base, 210b upper base, 270 sealing layer, 272 release layer .

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Abstract

The present invention is equipped with a base section (110) and a layered section (120). The base section (110) includes one main surface (111) and another main surface (112) positioned on the opposite side from the one main surface (111), and has a recess (113) formed in the one main surface (111). The layered section (120) is layered on the one main surface (111) of the base section so as to cover the recess (113) from above. At least above the recess (113), the layered section (120) includes a piezoelectric single-crystal layer (130), an upper electrode layer (140), and a lower electrode layer (150). The upper electrode layer (140) is positioned on top of the piezoelectric single-crystal layer (130). The lower electrode layer (150) is positioned so as to face at least part of the upper electrode layer (140) with the piezoelectric single-crystal layer (130) sandwiched therebetween.

Description

圧電デバイスPiezo device
　本発明は、圧電デバイスに関する。 The present invention relates to piezoelectric devices.
　圧電デバイスの構成を記載した先行文献として、たとえば下記の非特許文献１がある。非特許文献１に記載された圧電デバイスは、キャビティを有するＳＯＩ基板と、少なくともキャビティの上方に配置された圧電体層と、圧電体層の上側に設けられた上部電極層と、圧電体層を挟んで上部電極層とは反対側に設けられた下部電極層とを備えている。 先行 As a prior document describing the configuration of a piezoelectric device, there is, for example, the following Non-Patent Document 1. The piezoelectric device described in Non-Patent Document 1 includes an SOI substrate having a cavity, a piezoelectric layer disposed at least above the cavity, an upper electrode layer provided above the piezoelectric layer, and a piezoelectric layer. And a lower electrode layer provided on the opposite side to the upper electrode layer.
　非特許文献１に記載された圧電デバイスにおいては、ＳＯＩ基板のＳｉ層上に、圧電体層がスパッタリングなどにより成膜される。成膜時には、圧電体層は、Ｓｉ層の表面に直交する方向に結晶成長する。そのため、ＳＯＩ基板のＳｉ層においてキャビティを構成する凹部上に位置する部分が撓んでいる場合、Ｓｉ層の撓み部分上に成膜される圧電体層の結晶成長方向が交差するため、圧電体層が不均一に形成される。この場合、圧電体層中の圧電特性が低下する。 In the piezoelectric device described in Non-Patent Document 1, a piezoelectric layer is formed on the Si layer of the SOI substrate by sputtering or the like. During film formation, the piezoelectric layer grows in a direction perpendicular to the surface of the Si layer. Therefore, when the portion of the Si layer of the SOI substrate located on the concave portion forming the cavity is bent, the crystal growth directions of the piezoelectric layers formed on the bent portion of the Si layer intersect with each other. Are formed unevenly. In this case, the piezoelectric characteristics in the piezoelectric layer deteriorate.
　本発明は上記の問題点に鑑みてなされたものであって、圧電体層の凹部上に位置する部分を均一化して、圧電特性を向上できる、圧電デバイスを提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a piezoelectric device that can improve the piezoelectric characteristics by making the portion of the piezoelectric layer located on the concave portion uniform.
　本発明に基づく圧電デバイスは、基部と、積層部とを備えている。基部は、一方の主面と、一方の主面とは反対側に位置する他方の主面とを含み、かつ、一方の主面に形成された凹部を有している。積層部は、凹部を上方から覆うように基部の一方の主面上に積層されている。積層部は、少なくとも凹部の上方において、単結晶圧電体層と、上部電極層と、下部電極層とを含んでいる。上部電極層は、単結晶圧電体層の上側に配置されている。下部電極層は、単結晶圧電体層を挟んで上部電極層の少なくとも一部に対向するように配置されている。 圧 電 A piezoelectric device according to the present invention includes a base and a laminated portion. The base includes one main surface and the other main surface located on the opposite side to the one main surface, and has a concave portion formed on the one main surface. The laminated portion is laminated on one main surface of the base so as to cover the recess from above. The laminated portion includes a single crystal piezoelectric layer, an upper electrode layer, and a lower electrode layer at least above the recess. The upper electrode layer is disposed above the single-crystal piezoelectric layer. The lower electrode layer is disposed so as to face at least a part of the upper electrode layer with the single-crystal piezoelectric layer interposed therebetween.
　本発明によれば、圧電体層の凹部上に位置する部分を均一化して、圧電デバイスの圧電特性を向上することができる。 According to the present invention, the portion of the piezoelectric layer located on the concave portion can be made uniform, and the piezoelectric characteristics of the piezoelectric device can be improved.
本発明の実施形態１に係る圧電デバイスの平面図である。It is a top view of the piezoelectric device concerning Embodiment 1 of the present invention. 図１に示した圧電デバイスについてＩＩ－ＩＩ線矢印方向から見た断面図である。FIG. 2 is a cross-sectional view of the piezoelectric device shown in FIG. 1 as viewed from the direction of arrows II-II. 図２に示した圧電デバイスの断面図におけるＩＩＩ部の部分拡大図である。FIG. 3 is a partially enlarged view of a section III in the cross-sectional view of the piezoelectric device shown in FIG. 2. 本発明の実施形態１に係る圧電デバイスの製造方法において、単結晶圧電体層の下面に下部電極層を設けた状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、下部電極層および単結晶圧電体層の各々の下面に中間層を設けた状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、中間層の下面を平坦にした状態を示す断面図である。FIG. 4 is a cross-sectional view illustrating a state where the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、基部に凹部を形成する前の状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state before a concave portion is formed in a base in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、基部に凹部を形成した状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which a concave portion is formed in the base in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、図６に示す複数の層に基部を接合させる状態を示す断面図である。FIG. 7 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 6 in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、中間層の下面に基部を接合させた状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state where the base is joined to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、単結晶圧電体層の上面を削った状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which the upper surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、支持基板に単結晶圧電体層を接合させる状態を示す断面図である。FIG. 9 is a cross-sectional view showing a state in which a single-crystal piezoelectric layer is joined to a support substrate in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、支持基板に単結晶圧電体層を接合させた状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which a single-crystal piezoelectric layer is bonded to a support substrate in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、単結晶圧電体層の下面を削った状態を示す断面図である。FIG. 11 is a cross-sectional view showing a state in which the lower surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、単結晶圧電体層の下面に下部電極層を設けた状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which a lower electrode layer is provided on a lower surface of a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modified example of Embodiment 1 of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、下部電極層および単結晶圧電体層の各々の下面に中間層を設けた状態を示す断面図である。FIG. 11 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of a lower electrode layer and a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、中間層の下面を平坦にした状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、図１８に示す複数の層に基部を接合させる状態を示す断面図である。FIG. 19 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 18 in the method for manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、中間層の下面に基部を接合させた状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which a base is joined to a lower surface of an intermediate layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. 本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、支持基板を除去した状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which a support substrate is removed in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. 本発明の実施形態２に係る圧電デバイスの断面図である。It is sectional drawing of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、シーリング層に剥離層を形成する前の状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state before a release layer is formed on a sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、シーリング層に剥離層を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the peeling layer in the sealing layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本実施形態の実施形態２に係る圧電デバイスの製造方法において、図６に示す複数の層に、剥離層が形成されたシーリング層を接合させる状態を示す断面図である。FIG. 7 is a cross-sectional view showing a state in which a sealing layer having a release layer formed thereon is joined to a plurality of layers shown in FIG. 6 in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、中間層の下面にシーリング層を接合させた状態を示す断面図である。It is sectional drawing which shows the state which joined the sealing layer to the lower surface of the intermediate | middle layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、剥離層を除去したあと、シーリング層２７０を下面側から研磨した状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which a sealing layer 270 is polished from a lower surface side after a release layer is removed in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、基部に上側基部および下側基部の各々を形成する前の状態を示す断面図である。It is sectional drawing which shows the state before forming each of an upper base and a lower base in a base in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、基部に上側基部および下側基部の各々を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed each of the upper base and the lower base in the base in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、図２７に示す複数の層に、図２９に示す基部を接合させる状態を示す断面図である。FIG. 29 is a cross-sectional view showing a state where the base shown in FIG. 29 is joined to the plurality of layers shown in FIG. 27 in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、シーリング層の下面に基部を接合させた状態を示す断面図である。It is sectional drawing which shows the state which joined the base to the lower surface of the sealing layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、単結晶圧電体層の上面を削った状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which the upper surface of a single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. 本発明の実施形態２に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。FIG. 9 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of a single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
　以下、本発明の各実施形態に係る圧電デバイスについて図面を参照して説明する。以下の実施形態の説明においては、図中の同一または相当部分には同一符号を付して、その説明は繰り返さない。 Hereinafter, a piezoelectric device according to each embodiment of the present invention will be described with reference to the drawings. In the following description of the embodiments, the same or corresponding portions in the drawings have the same reference characters allotted, and description thereof will not be repeated.
　（実施形態１）
　図１は、本発明の実施形態１に係る圧電デバイスの平面図である。図２は、図１に示した圧電デバイスについてＩＩ－ＩＩ線矢印方向から見た断面図である。図３は、図２に示した圧電デバイスの断面図におけるＩＩＩ部の部分拡大図である。図１においては、圧電デバイスの内部の構成を点線で示している。 (Embodiment 1)
FIG. 1 is a plan view of a piezoelectric device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of the piezoelectric device shown in FIG. 1 as seen from the direction of arrows II-II. FIG. 3 is a partially enlarged view of a section III in the cross-sectional view of the piezoelectric device shown in FIG. In FIG. 1, the internal configuration of the piezoelectric device is indicated by a dotted line.
　図１および図２に示すように、本発明の実施形態１に係る圧電デバイス１００は、基部１１０と、積層部１２０とを備えている。 As shown in FIGS. 1 and 2, the piezoelectric device 100 according to the first embodiment of the present invention includes a base 110 and a stacked unit 120.
　基部１１０は、一方の主面１１１と、一方の主面１１１とは反対側に位置する他方の主面１１２とを含んでいる。基部１１０は、一方の主面１１１に形成された凹部１１３を有している。 The base 110 includes one main surface 111 and the other main surface 112 located on the opposite side of the one main surface 111. The base 110 has a concave portion 113 formed on one main surface 111.
　本実施形態において、凹部１１３において一方の主面１１１側に位置する開口部の幅は、凹部１１３の底部の幅より狭くなっている。なお、凹部１１３において、開口部の幅が底部の幅と等しくてもよく、開口部の幅が底部の幅より広くてもよい。以下、凹部１１３の開口部の上方に位置する領域を、凹部１１３の上方という場合がある。 In the present embodiment, the width of the opening located on the one main surface 111 side of the recess 113 is smaller than the width of the bottom of the recess 113. In the recess 113, the width of the opening may be equal to the width of the bottom, or the width of the opening may be wider than the width of the bottom. Hereinafter, a region located above the opening of the recess 113 may be referred to as above the recess 113 in some cases.
　図２に示すように、凹部１１３は、一方の主面１１１上に積層された積層部１２０により覆われている。圧電デバイス１００における凹部１１３の内部は、密閉空間となっている。 凹 部 As shown in FIG. 2, the concave portion 113 is covered by a laminated portion 120 laminated on one main surface 111. The inside of the concave portion 113 in the piezoelectric device 100 is a closed space.
　本実施形態に係る圧電デバイス１００においては、凹部１１３の内部の圧力が負圧である。なお、凹部１１３の内部の圧力は、大気圧であってもよいし、正圧であってもよい。 に お い て In the piezoelectric device 100 according to the present embodiment, the pressure inside the recess 113 is a negative pressure. Note that the pressure inside the recess 113 may be atmospheric pressure or positive pressure.
　基部１１０を構成する材料は特に限定されない。本実施形態において、基部１１０はＳｉで構成されている。 材料 The material forming the base 110 is not particularly limited. In the present embodiment, the base 110 is made of Si.
　上記のように、積層部１２０は、凹部１１３を上方から覆うように基部１１０の一方の主面１１１上に積層されている。積層部１２０は、単結晶圧電体層１３０と、上部電極層１４０と、下部電極層１５０と、中間層１６０とを含んでいる。 積 層 As described above, the laminated portion 120 is laminated on the one main surface 111 of the base 110 so as to cover the recess 113 from above. The laminated section 120 includes a single-crystal piezoelectric layer 130, an upper electrode layer 140, a lower electrode layer 150, and an intermediate layer 160.
　単結晶圧電体層１３０は、基部１１０より上側に位置している。単結晶圧電体層１３０は、単結晶圧電体層１３０の少なくとも一部が凹部１１３の上方に位置するように配置されている。単結晶圧電体層１３０は、凹部１１３の上方に位置する領域においては、基部１１０側に凸状に湾曲している。単結晶圧電体層１３０は、凹部１１３の上方に位置していない領域においては、平坦である。 The single crystal piezoelectric layer 130 is located above the base 110. Single-crystal piezoelectric layer 130 is arranged such that at least a portion of single-crystal piezoelectric layer 130 is located above recess 113. The single crystal piezoelectric layer 130 is curved in a convex shape toward the base 110 in a region located above the concave portion 113. Single-crystal piezoelectric layer 130 is flat in a region not located above recess 113.
　単結晶圧電体層１３０は、孔部１３１を有している。孔部１３１は、単結晶圧電体層１３０を上下に貫通するように形成されている。本実施形態において、孔部１３１は、基部１１０の一方の主面１１１上に位置しており、凹部１１３の上方には位置していない。 The single crystal piezoelectric layer 130 has a hole 131. The hole 131 is formed so as to vertically penetrate the single crystal piezoelectric layer 130. In the present embodiment, the hole 131 is located on one main surface 111 of the base 110, and is not located above the recess 113.
　単結晶圧電体層１３０は、タンタル酸リチウムまたはニオブ酸リチウムで構成されている。タンタル酸リチウムまたはニオブ酸リチウムで構成された単結晶圧電体層１３０は、分極状態が一様である。 The single crystal piezoelectric layer 130 is made of lithium tantalate or lithium niobate. The single crystal piezoelectric layer 130 made of lithium tantalate or lithium niobate has a uniform polarization state.
　上部電極層１４０は、単結晶圧電体層１３０の上側に配置されている。上部電極層１４０は、上部電極層１４０の少なくとも一部が凹部１１３の上方に位置するように配置されている。 The upper electrode layer 140 is disposed above the single crystal piezoelectric layer 130. The upper electrode layer 140 is arranged such that at least a part of the upper electrode layer 140 is located above the recess 113.
　本実施形態において、上部電極層１４０は単結晶圧電体層１３０の一部の上側に配置されている。なお、上部電極層１４０と単結晶圧電体層１３０との間に、Ｔｉなどで構成された密着層が配置されていてもよい。 In the present embodiment, the upper electrode layer 140 is disposed above a part of the single crystal piezoelectric layer 130. Note that an adhesive layer made of Ti or the like may be disposed between the upper electrode layer 140 and the single-crystal piezoelectric layer 130.
　下部電極層１５０は、単結晶圧電体層１３０を挟んで上部電極層１４０の少なくとも一部に対向するように配置されている。下部電極層１５０は、下部電極層１５０の少なくとも一部が凹部１１３の上方に位置するように配置されている。下部電極層１５０は、凹部１１３の上方において、単結晶圧電体層１３０を挟んで上部電極層１４０の少なくとも一部と対向するように配置されている。 (4) The lower electrode layer 150 is disposed so as to face at least a part of the upper electrode layer 140 with the single-crystal piezoelectric layer 130 interposed therebetween. The lower electrode layer 150 is arranged such that at least a part of the lower electrode layer 150 is located above the recess 113. The lower electrode layer 150 is disposed above the recess 113 so as to face at least a part of the upper electrode layer 140 with the single crystal piezoelectric layer 130 interposed therebetween.
　下部電極層１５０の一部は、単結晶圧電体層１３０に形成された孔部１３１より下方に位置するように配置されている。本実施形態においては、下部電極層１５０は、単結晶圧電体層１３０の孔部１３１の下方を覆うように形成されている。孔部１３１内においては、下部電極層１５０上に二層配線が積層されていてもよい。 一部 A part of the lower electrode layer 150 is arranged below the hole 131 formed in the single crystal piezoelectric layer 130. In the present embodiment, the lower electrode layer 150 is formed so as to cover below the hole 131 of the single-crystal piezoelectric layer 130. In the hole 131, a two-layer wiring may be stacked on the lower electrode layer 150.
　なお、下部電極層１５０は、単結晶圧電体層１３０の孔部１３１の下方を、密着層を介して覆うように形成されていてもよい。密着層の材料は、導電性および密着性を有する材料であれば特に限定されない。密着層は、たとえばＴｉ、Ｃｒ、ＮｉまたはＮｉＣｒで構成される。 The lower electrode layer 150 may be formed so as to cover below the hole 131 of the single-crystal piezoelectric layer 130 via an adhesive layer. The material of the adhesion layer is not particularly limited as long as the material has conductivity and adhesion. The adhesion layer is made of, for example, Ti, Cr, Ni or NiCr.
　中間層１６０は、下部電極層１５０を下方から覆うように積層されている。本実施形態において、中間層１６０は、下部電極層１５０の下面、および、単結晶圧電体層１３０の下面のうち下部電極層１５０に覆われていない部分の、各々と接するように設けられている。また、中間層１６０の下面１６１は、基部１１０の一方の主面１１１と接続している。 The intermediate layer 160 is laminated so as to cover the lower electrode layer 150 from below. In the present embodiment, the intermediate layer 160 is provided so as to be in contact with the lower surface of the lower electrode layer 150 and the portion of the lower surface of the single-crystal piezoelectric layer 130 that is not covered with the lower electrode layer 150. . Further, the lower surface 161 of the intermediate layer 160 is connected to one main surface 111 of the base 110.
　本実施形態においては、凹部１１３の上方において、積層部１２０は、他方の主面１１２側に凸状に湾曲している。図３に示すように、凹部１１３の上方に位置する中間層１６０の下面１６１は、他方の主面１１２側に凸状に湾曲している。凹部１１３の上方に位置していない領域において、中間層１６０の下面１６１は、平坦である。 に お い て In the present embodiment, above the concave portion 113, the laminated portion 120 is convexly curved toward the other main surface 112. As shown in FIG. 3, the lower surface 161 of the intermediate layer 160 located above the concave portion 113 is curved convexly toward the other main surface 112. In a region that is not located above the concave portion 113, the lower surface 161 of the intermediate layer 160 is flat.
　凹部１１３の上方に位置していない領域において、中間層１６０と基部１１０とは互いに直接接続されている。なお、中間層１６０と基部１１０とは互いに直接接続されていなくてもよい。中間層１６０と基部１１０とは、金属層を介して互いに接続されていてもよい。 (4) In a region that is not located above the concave portion 113, the intermediate layer 160 and the base 110 are directly connected to each other. Note that the intermediate layer 160 and the base 110 may not be directly connected to each other. The intermediate layer 160 and the base 110 may be connected to each other via a metal layer.
　中間層１６０の材料は、絶縁物であれば特に限定されない。本実施形態において、中間層１６０は、ＳｉＯ2で構成されている。また、中間層１６０は、電気絶縁性および断熱性を有する有機材料で構成されていてもよい。 The material of the intermediate layer 160 is not particularly limited as long as it is an insulator. In the present embodiment, the intermediate layer 160 is made of SiO 2 . Further, the intermediate layer 160 may be made of an organic material having electric insulation and heat insulation.
　このように、本実施形態において、積層部１２０は、少なくとも凹部１１３の上方において、単結晶圧電体層１３０と、上部電極層１４０と、下部電極層１５０と、中間層１６０とを含んでいる。 As described above, in the present embodiment, the stacked unit 120 includes the single-crystal piezoelectric layer 130, the upper electrode layer 140, the lower electrode layer 150, and the intermediate layer 160 at least above the recess 113.
　図２に示すように、凹部１１３の上方において、上部電極層１４０は、単結晶圧電体層１３０の上側に配置されている。凹部１１３の上方において、下部電極層１５０は、単結晶圧電体層１３０を挟んで上部電極層１４０の少なくとも一部に対向するように配置されている。 上部 As shown in FIG. 2, the upper electrode layer 140 is disposed above the single crystal piezoelectric layer 130 above the recess 113. Above the recess 113, the lower electrode layer 150 is arranged so as to face at least a part of the upper electrode layer 140 with the single-crystal piezoelectric layer 130 interposed therebetween.
　上記の構成により、上部電極層１４０と下部電極層１５０との間に電圧が印加されることによって、単結晶圧電体層１３０の伸縮に応じて、凹部１１３の上方に位置する領域において積層部１２０が上下に屈曲振動する。 With the above configuration, when a voltage is applied between the upper electrode layer 140 and the lower electrode layer 150, the stacked portion 120 is formed in a region located above the concave portion 113 in accordance with expansion and contraction of the single crystal piezoelectric layer 130. Vibrates vertically.
　以下、本発明の実施形態１に係る圧電デバイスの製造方法について説明する。
　図４は、本発明の実施形態１に係る圧電デバイスの製造方法において、単結晶圧電体層の下面に下部電極層を設けた状態を示す断面図である。形成時の単結晶圧電体層１３０の厚みは、本実施形態に係る圧電デバイス１００に最終的に含まれる単結晶圧電体層１３０の厚みより厚い。 Hereinafter, a method for manufacturing the piezoelectric device according to the first embodiment of the present invention will be described.
FIG. 4 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. The thickness of the single-crystal piezoelectric layer 130 at the time of formation is larger than the thickness of the single-crystal piezoelectric layer 130 finally included in the piezoelectric device 100 according to the present embodiment.
　図４に示すように、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層１３０の下面に下部電極層１５０を設ける。 (4) As shown in FIG. 4, the lower electrode layer 150 is provided on the lower surface of the single-crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
　図５は、本発明の実施形態１に係る圧電デバイスの製造方法において、下部電極層および単結晶圧電体層の各々の下面に中間層を設けた状態を示す断面図である。図５に示すように、ＣＶＤ(Chemical　Vapor　Deposition)法またはＰＶＤ(Physical　Vapor　Deposition)法などにより、下部電極層１５０および単結晶圧電体層１３０の各々の下面に、中間層１６０を設ける。 FIG. 5 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. As shown in FIG. 5, an intermediate layer 160 is provided on the lower surface of each of the lower electrode layer 150 and the single-crystal piezoelectric layer 130 by a CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method.
　図６は、本発明の実施形態１に係る圧電デバイスの製造方法において、中間層の下面を平坦にした状態を示す断面図である。図６に示すように、中間層１６０の下面を化学機械研磨(ＣＭＰ：Chemical　Mechanical　Polishing)などにより、平坦にする。 FIG. 6 is a cross-sectional view showing a state in which the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. As shown in FIG. 6, the lower surface of the intermediate layer 160 is flattened by chemical mechanical polishing (CMP).
　図７は、本発明の実施形態１に係る圧電デバイスの製造方法において、基部に凹部を形成する前の状態を示す断面図である。図８は、本発明の実施形態１に係る圧電デバイスの製造方法において、基部に凹部を形成した状態を示す断面図である。 FIG. 7 is a cross-sectional view showing a state before the concave portion is formed in the base in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view showing a state in which a concave portion is formed in the base in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
　図７および図８に示すように、基部１１０の一方の主面１１１側から基部１１０に対して、深掘反応性イオンエッチング（Ｄｅｅｐ　ＲＩＥ：Deep　Reactive　Ion　Etching）などにより、基部１１０に凹部１１３を形成する。 As shown in FIGS. 7 and 8, a recess 113 is formed in the base 110 from the one main surface 111 side of the base 110 by, for example, deep reactive ion etching (Deep Reactive Ion). Form.
　図９は、本発明の実施形態１に係る圧電デバイスの製造方法において、図６に示す複数の層に基部を接合させる状態を示す断面図である。図１０は、本発明の実施形態１に係る圧電デバイスの製造方法において、中間層の下面に基部を接合させた状態を示す断面図である。 FIG. 9 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 6 in the method of manufacturing the piezoelectric device according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view showing a state where the base is joined to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention.
　図９および図１０に示すように、中間層１６０の下面１６１に、基部１１０の一方の主面１１１を接合させる。これにより、凹部１１３の内部が、密閉空間となる。 As shown in FIGS. 9 and 10, one main surface 111 of the base 110 is joined to the lower surface 161 of the intermediate layer 160. Thereby, the inside of the concave portion 113 becomes a closed space.
　本実施形態においては、凹部１１３の内部に異物が侵入することを抑制するため、真空圧下で中間層１６０と基部１１０とを接合させる。この場合、上記真空圧は、低真空、中真空、高真空および超高真空のいずれであってもよい。このように中間層１６０と基部１１０とを接合するため、凹部１１３の内部の圧力は負圧となる。さらに、凹部１１３の内部の圧力が負圧になるため、凹部１１３の上方において、中間層１６０の下面１６１は、他方の主面１１２側に凸状に湾曲する。 In the present embodiment, the intermediate layer 160 and the base 110 are joined under a vacuum pressure in order to suppress entry of foreign matter into the recess 113. In this case, the vacuum pressure may be any of a low vacuum, a medium vacuum, a high vacuum, and an ultra-high vacuum. Since the intermediate layer 160 and the base 110 are joined as described above, the pressure inside the concave portion 113 becomes a negative pressure. Further, since the pressure inside the concave portion 113 becomes a negative pressure, the lower surface 161 of the intermediate layer 160 is convexly curved toward the other main surface 112 above the concave portion 113.
　なお、中間層１６０と基部１１０とを接合させる際の雰囲気は、真空圧下に限定されない。中間層１６０は、大気圧下で基部１１０と接合されてもよいし、高圧下で基部１１０と接合されてもよい。これらの雰囲気下で中間層１６０と基部１１０とが接合されることにより、中間層１６０の下面１６１が、平坦面になってもよいし、他方の主面１１２側とは反対側に凸状に湾曲してもよい。 The atmosphere for joining the intermediate layer 160 and the base 110 is not limited to a vacuum pressure. The intermediate layer 160 may be joined to the base 110 under atmospheric pressure, or may be joined to the base 110 under high pressure. By joining the intermediate layer 160 and the base 110 under these atmospheres, the lower surface 161 of the intermediate layer 160 may be a flat surface, or may be convex on the side opposite to the other main surface 112 side. It may be curved.
　図１１は、本発明の実施形態１に係る圧電デバイスの製造方法において、単結晶圧電体層の上面を削った状態を示す断面図である。図１１に示すように、単結晶圧電体層１３０の上面をＣＭＰなどにより削って、単結晶圧電体層１３０を所望の厚さにする。この場合、単結晶圧電体層１３０の厚さは、電圧の印加による単結晶圧電体層１３０の所望の伸縮量が得られるように調整される。単結晶圧電体層１３０の厚さが薄くなるに従って、中間層１６０の下面１６１は、より大きく湾曲する。 FIG. 11 is a cross-sectional view showing a state where the upper surface of the single-crystal piezoelectric layer has been cut off in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. As shown in FIG. 11, the upper surface of the single-crystal piezoelectric layer 130 is shaved by CMP or the like so that the single-crystal piezoelectric layer 130 has a desired thickness. In this case, the thickness of the single-crystal piezoelectric layer 130 is adjusted so that a desired amount of expansion and contraction of the single-crystal piezoelectric layer 130 due to application of a voltage is obtained. As the thickness of single-crystal piezoelectric layer 130 decreases, lower surface 161 of intermediate layer 160 curves more.
　なお、単結晶圧電体層１３０の上面側に、予めイオン注入することにより、剥離層を形成していてもよい。この場合、単結晶圧電体層１３０の上面をＣＭＰなどにより削る前に、剥離層を剥離させることにより、単結晶圧電体層１３０の厚さ調整が容易になる。 Note that a release layer may be formed on the upper surface side of the single crystal piezoelectric layer 130 by ion implantation in advance. In this case, the thickness of the single-crystal piezoelectric layer 130 can be easily adjusted by removing the release layer before the upper surface of the single-crystal piezoelectric layer 130 is shaved by CMP or the like.
　図１２は、本発明の実施形態１に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。図１２に示すように、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層１３０の上面の一部に、上部電極層１４０を設ける。このようにして、積層部１２０が基部１１０の一方の主面１１１上に積層される。また、真空圧下で中間層１６０と基部１１０とが接合されるため、積層部１２０は、凹部１１３の上方において、他方の主面１１２側に凸状に湾曲する。 FIG. 12 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 1 of the present invention. As shown in FIG. 12, an upper electrode layer 140 is provided on a part of the upper surface of the single crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like. In this way, the laminated portion 120 is laminated on the one main surface 111 of the base 110. In addition, since the intermediate layer 160 and the base 110 are joined under vacuum pressure, the laminated portion 120 is curved in a convex shape above the recess 113 toward the other main surface 112.
　最後に、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層１３０の上面の一部に、孔部１３１を設ける。 Finally, a hole 131 is provided in a part of the upper surface of the single-crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
　上記の工程により、図２に示すような本発明の実施形態１に係る圧電デバイス１００が製造される。 に よ り Through the above steps, the piezoelectric device 100 according to the first embodiment of the present invention as shown in FIG. 2 is manufactured.
　上記のように、本実施形態に係る圧電デバイス１００においては、積層部１２０が、少なくとも凹部１１３の上方において、単結晶圧電体層１３０と、上部電極層１４０と、下部電極層１５０とを含んでいる。この構成の場合、多結晶圧電体層を成膜して形成する場合とは異なり、単結晶圧電体層１３０と上部電極層１４０と下部電極層１５０とを含む複数の層を基部１１０に接合することで凹部１１３上に圧電体層を設けることができる。これにより、圧電体層の凹部１１３上に位置する部分を均一化して、圧電デバイス１００の圧電特性を向上することができる。 As described above, in the piezoelectric device 100 according to the present embodiment, the stacked unit 120 includes the single-crystal piezoelectric layer 130, the upper electrode layer 140, and the lower electrode layer 150 at least above the recess 113. I have. In the case of this configuration, a plurality of layers including the single crystal piezoelectric layer 130, the upper electrode layer 140, and the lower electrode layer 150 are joined to the base 110, unlike the case where the polycrystalline piezoelectric layer is formed by film formation. Thus, a piezoelectric layer can be provided on the recess 113. Thereby, the portion of the piezoelectric layer located on the concave portion 113 can be made uniform, and the piezoelectric characteristics of the piezoelectric device 100 can be improved.
　本実施形態に係る圧電デバイス１００においては、中間層１６０が、下部電極層１５０を下方から覆うように積層されている。これにより、下部電極層１５０の下面が外部および凹部１１３に露出しないため、下部電極層１５０の劣化を抑制することができる。 中間 In the piezoelectric device 100 according to the present embodiment, the intermediate layer 160 is stacked so as to cover the lower electrode layer 150 from below. Accordingly, since the lower surface of the lower electrode layer 150 is not exposed to the outside and the concave portion 113, the deterioration of the lower electrode layer 150 can be suppressed.
　本実施形態に係る圧電デバイス１００においては、凹部１１３の上方に位置していない領域において、中間層１６０の下面１６１が平坦である。これにより、中間層１６０と基部１１０とを密着させて、中間層１６０と基部１１０との間での層間剥離の発生を抑制することができる。 In the piezoelectric device 100 according to the present embodiment, the lower surface 161 of the intermediate layer 160 is flat in a region that is not located above the concave portion 113. Thereby, the intermediate layer 160 and the base 110 are brought into close contact with each other, and the occurrence of delamination between the intermediate layer 160 and the base 110 can be suppressed.
　本実施形態に係る圧電デバイス１００においては、凹部１１３の上方において、積層部１２０が、他方の主面１１２側に凸状に湾曲している。積層部１２０は単結晶圧電体層１３０を含んでいるため、積層部１２０が他方の主面１１２側に凸状に湾曲している場合においても、圧電体層の凹部１１３上に位置する部分を均一化して、圧電特性を向上することができる。 積 層 In the piezoelectric device 100 according to the present embodiment, the laminated portion 120 is curved above the concave portion 113 so as to protrude toward the other main surface 112. Since the laminated portion 120 includes the single-crystal piezoelectric layer 130, even when the laminated portion 120 is convexly curved toward the other main surface 112, the portion located on the concave portion 113 of the piezoelectric layer can be removed. It is possible to improve the uniformity and improve the piezoelectric characteristics.
　本実施形態に係る圧電デバイス１００においては、凹部１１３は密閉されており、凹部１１３の内部の圧力は負圧である。これにより、凹部１１３の内部への異物の混入を抑制することができる。 凹 部 In the piezoelectric device 100 according to the present embodiment, the recess 113 is sealed, and the pressure inside the recess 113 is a negative pressure. Thus, the intrusion of foreign matter into the recess 113 can be suppressed.
　なお、本実施形態に係る圧電デバイス１００は、支持基板を用いて製造されてもよい。ここで、本実施形態の変形例に係る圧電デバイスの製造方法について説明する。 Note that the piezoelectric device 100 according to the present embodiment may be manufactured using a support substrate. Here, a method for manufacturing a piezoelectric device according to a modification of the present embodiment will be described.
　図１３は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、支持基板に単結晶圧電体層を接合させる状態を示す断面図である。図１４は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、支持基板に単結晶圧電体層を接合させた状態を示す断面図である。 FIG. 13 is a cross-sectional view illustrating a state in which a single-crystal piezoelectric layer is bonded to a support substrate in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. FIG. 14 is a cross-sectional view illustrating a state in which a single-crystal piezoelectric layer is bonded to a support substrate in a piezoelectric device manufacturing method according to a modification of the first embodiment of the present invention.
　図１３および図１４に示すように、支持基板１０の下面に、単結晶圧電体層１３０を接合させる。支持基板１０を構成する材料は特に限定されない。本変形例において、支持基板１０はＳｉで構成されている。なお、支持基板１０の下面にＳｉＯ2などからなる中間層を設け、この中間層の下面に単結晶圧電体層１３０を接合させてもよい。 As shown in FIGS. 13 and 14, the single-crystal piezoelectric layer 130 is bonded to the lower surface of the support substrate 10. The material forming the support substrate 10 is not particularly limited. In this modification, the support substrate 10 is made of Si. Note that an intermediate layer made of SiO 2 or the like may be provided on the lower surface of the support substrate 10, and the single-crystal piezoelectric layer 130 may be joined to the lower surface of the intermediate layer.
　図１５は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、単結晶圧電体層の下面を削った状態を示す断面図である。図１５に示すように、単結晶圧電体層１３０の下面をＣＭＰなどにより削って、単結晶圧電体層１３０を所望の厚さにする。この場合、単結晶圧電体層１３０の厚さは、電圧の印加による単結晶圧電体層１３０の所望の伸縮量が得られるように調整される。 FIG. 15 is a cross-sectional view showing a state in which the lower surface of the single-crystal piezoelectric layer is shaved in the method of manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention. As shown in FIG. 15, the lower surface of the single-crystal piezoelectric layer 130 is shaved by CMP or the like so that the single-crystal piezoelectric layer 130 has a desired thickness. In this case, the thickness of the single-crystal piezoelectric layer 130 is adjusted so that a desired amount of expansion and contraction of the single-crystal piezoelectric layer 130 due to application of a voltage is obtained.
　図１６は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、単結晶圧電体層の下面に下部電極層を設けた状態を示す断面図である。図１６に示すように、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層１３０の下面に下部電極層１５０を設ける。 FIG. 16 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of a single-crystal piezoelectric layer in a method for manufacturing a piezoelectric device according to a modification of the first embodiment of the present invention. As shown in FIG. 16, the lower electrode layer 150 is provided on the lower surface of the single crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
　図１７は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、下部電極層および単結晶圧電体層の各々の下面に中間層を設けた状態を示す断面図である。図１７に示すように、ＣＶＤ法またはＰＶＤ法などにより、下部電極層１５０および単結晶圧電体層１３０の各々の下面に、中間層１６０を設ける。 FIG. 17 is a cross-sectional view showing a state in which an intermediate layer is provided on the lower surface of each of the lower electrode layer and the single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention. As shown in FIG. 17, an intermediate layer 160 is provided on the lower surface of each of the lower electrode layer 150 and the single crystal piezoelectric layer 130 by a CVD method or a PVD method.
　図１８は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、中間層の下面を平坦にした状態を示す断面図である。図１８に示すように、中間層１６０の下面をＣＭＰなどにより、平坦にする。 FIG. 18 is a cross-sectional view showing a state where the lower surface of the intermediate layer is flattened in the method for manufacturing a piezoelectric device according to the modification of the first embodiment of the present invention. As shown in FIG. 18, the lower surface of the intermediate layer 160 is flattened by CMP or the like.
　図１９は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、図１８に示す複数の層に基部を接合させる状態を示す断面図である。図２０は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、中間層の下面に基部を接合させた状態を示す断面図である。 FIG. 19 is a cross-sectional view showing a state where the base is joined to the plurality of layers shown in FIG. 18 in the method of manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention. FIG. 20 is a cross-sectional view showing a state where the base is joined to the lower surface of the intermediate layer in the method of manufacturing the piezoelectric device according to the modification of the first embodiment of the present invention.
　図１９および図２０に示すように、中間層１６０の下面１６１に、基部１１０の一方の主面１１１を接合する。 。As shown in FIGS. 19 and 20, one main surface 111 of the base 110 is joined to the lower surface 161 of the intermediate layer 160.
　図２１は、本発明の実施形態１の変形例に係る圧電デバイスの製造方法において、支持基板を除去した状態を示す断面図である。図２１に示すように、図２０に示した積層体において、支持基板１０を上面側から研磨して薄くした後、支持基板１０をウェットエッチングにより除去する。 FIG. 21 is a cross-sectional view showing a state in which the supporting substrate has been removed in the piezoelectric device manufacturing method according to the modification of the first embodiment of the present invention. As shown in FIG. 21, in the stacked body shown in FIG. 20, after the support substrate 10 is polished from the upper surface side to make it thin, the support substrate 10 is removed by wet etching.
　最後に、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層１３０の上面の一部に、孔部１３１を設ける。 Finally, a hole 131 is provided in a part of the upper surface of the single-crystal piezoelectric layer 130 by a lift-off method, a plating method, an etching method, or the like.
　上記の変形例の工程によっても、図２に示すような本発明の実施形態１に係る圧電デバイス１００を製造することができる。 圧 電 The piezoelectric device 100 according to the first embodiment of the present invention as shown in FIG.
　（実施形態２）
　以下、本発明の実施形態２に係る圧電デバイスについて説明する。本発明の実施形態２に係る圧電デバイスは、積層部および基部の各々の構成が、実施形態１に係る圧電デバイス１００と異なる。よって、本発明の実施形態１に係る圧電デバイス１００と同様である構成については説明を繰り返さない。 (Embodiment 2)
Hereinafter, a piezoelectric device according to Embodiment 2 of the present invention will be described. The piezoelectric device according to the second embodiment of the present invention is different from the piezoelectric device 100 according to the first embodiment in the configuration of each of the laminated portion and the base. Therefore, the description of the same configuration as that of the piezoelectric device 100 according to the first embodiment of the present invention will not be repeated.
　図２２は、本発明の実施形態２に係る圧電デバイスの断面図である。図２２に示す圧電デバイス２００の断面図は、図２に示す圧電デバイス１００の断面図と同一の断面視にて図示している。 FIG. 22 is a sectional view of a piezoelectric device according to Embodiment 2 of the present invention. The sectional view of the piezoelectric device 200 shown in FIG. 22 is shown in the same sectional view as the sectional view of the piezoelectric device 100 shown in FIG.
　図２２に示すように、本発明の実施形態２に係る圧電デバイス２００は、基部２１０と、積層部２２０とを備えている。 圧 電 As shown in FIG. 22, the piezoelectric device 200 according to the second embodiment of the present invention includes a base 210 and a laminated part 220.
　基部２１０は、一方の主面２１１と、一方の主面２１１とは反対側に位置する他方の主面２１２とを含んでいる。基部２１０は、一方の主面２１１に形成された凹部２１３を有している。 The base 210 includes one main surface 211 and the other main surface 212 located on the opposite side to the one main surface 211. The base 210 has a concave portion 213 formed on one main surface 211.
　本実施形態において、基部２１０は、下側基部２１０ａと、上側基部２１０ｂとからなる。下側基部２１０ａの一方の主面２１１側においては、凹部２１３に沿って内側凹部が形成されている。下側基部２１０ａの一方の主面２１１側に位置する上面および内側凹部の内面の各々に沿って、下側基部２１０ａ上に上側基部２１０ｂが設けられている。すなわち、上側基部２１０ｂの上面は、基部２１０の一方の主面２１１を構成している。 In the present embodiment, the base 210 includes a lower base 210a and an upper base 210b. On one main surface 211 side of the lower base 210a, an inner concave portion is formed along the concave portion 213. An upper base 210b is provided on the lower base 210a along each of the upper surface located on the one main surface 211 side of the lower base 210a and the inner surface of the inner concave portion. That is, the upper surface of the upper base 210b constitutes one main surface 211 of the base 210.
　基部２１０を構成する材料は特に限定されない。本実施形態において、下側基部２１０ａはＳｉで構成されている。上側基部２１０ｂはＳｉＯ2で構成されている。 The material forming the base 210 is not particularly limited. In the present embodiment, the lower base 210a is made of Si. The upper base portion 210b is constituted by SiO 2.
　図２２に示すように、積層部２２０は、凹部２１３を上方から覆うように基部２１０の一方の主面２１１上に積層されている。積層部２２０は、単結晶圧電体層２３０と、上部電極層２４０と、下部電極層２５０と、中間層２６０と、シーリング層２７０とを含んでいる。本実施形態においては、中間層２６０の下面２６１上に、シーリング層２７０が積層されている。シーリング層２７０の下面は、基部２１０の一方の主面１１１と接続されている。 積 層 As shown in FIG. 22, the laminated portion 220 is laminated on one main surface 211 of the base 210 so as to cover the concave portion 213 from above. The laminated section 220 includes a single-crystal piezoelectric layer 230, an upper electrode layer 240, a lower electrode layer 250, an intermediate layer 260, and a sealing layer 270. In the present embodiment, a sealing layer 270 is laminated on the lower surface 261 of the intermediate layer 260. The lower surface of sealing layer 270 is connected to one main surface 111 of base 210.
　本実施形態においては、凹部２１３の上方において、積層部２２０は、他方の主面２１２側に凸状に湾曲している。凹部２１３の上方に位置するシーリング層２７０の下面２７１は、他方の主面１１２側に凸状に湾曲している。凹部２１３の上方に位置していない領域において、シーリング層２７０の下面２７１は、平坦である。 に お い て In the present embodiment, above the concave portion 213, the laminated portion 220 is curved convexly toward the other main surface 212. The lower surface 271 of the sealing layer 270 located above the concave portion 213 is curved convexly toward the other main surface 112. In a region that is not located above the concave portion 213, the lower surface 271 of the sealing layer 270 is flat.
　凹部２１３の上方に位置していない領域において、シーリング層２７０と基部２１０とは互いに直接接続されている。なお、シーリング層２７０と基部２１０とは互いに直接接続されていなくてもよい。シーリング層２７０と基部２１０とは、金属層を介して互いに接続されていてもよい。また、シーリング層２７０と中間層２６０との間に、金属層などの、シーリング層２７０および中間層２６０の各々を構成する材料とは異なる材料で構成された層が、配置されていてもよい。 (4) In a region that is not located above the concave portion 213, the sealing layer 270 and the base 210 are directly connected to each other. Note that the sealing layer 270 and the base 210 need not be directly connected to each other. The sealing layer 270 and the base 210 may be connected to each other via a metal layer. Further, between the sealing layer 270 and the intermediate layer 260, a layer such as a metal layer made of a material different from the material forming each of the sealing layer 270 and the intermediate layer 260 may be arranged.
　本実施形態におけるシーリング層２７０の厚さは、５００ｎｍ以上２μｍ以下である。シーリング層２７０を構成する材料は特に限定されない。本実施形態において、シーリング層２７０はＳｉで構成されている。すなわち、基部２１０およびシーリング層２７０によって、Ｃａｖｉｔｙ　ＳＯＩ(Silicon　on　Insulator)基板が構成されている。 厚 The thickness of the sealing layer 270 in this embodiment is not less than 500 nm and not more than 2 μm. The material forming the sealing layer 270 is not particularly limited. In the present embodiment, the sealing layer 270 is made of Si. That is, a Cavity SOI (Silicon On Insulator) substrate is constituted by the base 210 and the sealing layer 270.
　このように、本実施形態において、積層部２２０は、少なくとも凹部２１３の上方において、単結晶圧電体層２３０と、上部電極層２４０と、下部電極層２５０と、中間層２６０と、シーリング層２７０とを含んでいる。 As described above, in the present embodiment, the stacked portion 220 includes the single crystal piezoelectric layer 230, the upper electrode layer 240, the lower electrode layer 250, the intermediate layer 260, and the sealing layer 270 at least above the concave portion 213. Contains.
　図２２に示すように、凹部２１３の上方において、上部電極層２４０は、単結晶圧電体層２３０の上側に配置されている。凹部２１３の上方において、下部電極層２５０は、単結晶圧電体層２３０を挟んで上部電極層２４０の少なくとも一部に対向するように配置されている。 上部 As shown in FIG. 22, above the recess 213, the upper electrode layer 240 is arranged above the single-crystal piezoelectric layer 230. Above the concave portion 213, the lower electrode layer 250 is disposed so as to face at least a part of the upper electrode layer 240 with the single-crystal piezoelectric layer 230 interposed therebetween.
　上記の構成により、上部電極層２４０と下部電極層２５０との間に電圧が印加されることによって、単結晶圧電体層２３０の伸縮に応じて、凹部２１３の上方において積層部２２０が上下に屈曲振動する。 With the above configuration, when a voltage is applied between the upper electrode layer 240 and the lower electrode layer 250, the laminated portion 220 is bent up and down above the concave portion 213 in accordance with expansion and contraction of the single crystal piezoelectric layer 230. Vibrate.
　以下、本発明の実施形態２に係る圧電デバイスの製造方法について説明する。
　図２３は、本発明の実施形態２に係る圧電デバイスの製造方法において、シーリング層に剥離層を形成する前の状態を示す断面図である。図２４は、本発明の実施形態２に係る圧電デバイスの製造方法において、シーリング層に剥離層を形成した状態を示す断面図である。 Hereinafter, a method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention will be described.
FIG. 23 is a cross-sectional view showing a state before a release layer is formed on the sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. FIG. 24 is a cross-sectional view showing a state where a release layer is formed on a sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
　図２３および図２４に示すように、シーリング層２７０の下面側からイオン注入を行ない、シーリング層２７０の下面側に剥離層２７２を形成する。 イ オ ン As shown in FIGS. 23 and 24, ion implantation is performed from the lower surface side of the sealing layer 270 to form a peeling layer 272 on the lower surface side of the sealing layer 270.
　図２５は、本実施形態の実施形態２に係る圧電デバイスの製造方法において、図６に示す複数の層に、剥離層が形成されたシーリング層を接合させる状態を示す断面図である。図２６は、本発明の実施形態２に係る圧電デバイスの製造方法において、中間層の下面にシーリング層を接合させた状態を示す断面図である。 FIG. 25 is a cross-sectional view showing a state in which a sealing layer provided with a release layer is joined to the plurality of layers shown in FIG. 6 in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present embodiment. FIG. 26 is a cross-sectional view showing a state in which a sealing layer is joined to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
　図２５および図２６に示すように、中間層の下面２６１に、シーリング層２７０の上面を接合させる。なお、シーリング層２７０の上面には、予めＳｉＯ2層が形成されてもよい。この場合、中間層２６０は、シーリング層２７０の上面に設けられたＳｉＯ2層の上面と接合される。 As shown in FIGS. 25 and 26, the upper surface of the sealing layer 270 is joined to the lower surface 261 of the intermediate layer. Note that an SiO 2 layer may be formed on the upper surface of the sealing layer 270 in advance. In this case, the intermediate layer 260 is bonded to the upper surface of the SiO 2 layer provided on the upper surface of the sealing layer 270.
　図２７は、本発明の実施形態２に係る圧電デバイスの製造方法において、剥離層を除去したあと、シーリング層２７０を下面側から研磨した状態を示す断面図である。 FIG. 27 is a cross-sectional view showing a state in which the sealing layer 270 is polished from the lower surface side after the release layer is removed in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
　図２６および図２７に示すように、シーリング層２７０の下面側に形成された剥離層２７２を除去したあと、さらに、シーリング層２７０を下面側からＣＭＰなどにより削って、シーリング層２７０を所望の厚さにする。なお、本実施形態の製造方法において、剥離層２７２は形成されていなくてもよい。 As shown in FIGS. 26 and 27, after removing the release layer 272 formed on the lower surface side of the sealing layer 270, the sealing layer 270 is further shaved from the lower surface side by CMP or the like, so that the sealing layer 270 has a desired thickness. To Note that, in the manufacturing method of the present embodiment, the release layer 272 may not be formed.
　図２８は、本発明の実施形態２に係る圧電デバイスの製造方法において、基部に上側基部および下側基部の各々を形成する前の状態を示す断面図である。図２９は、本発明の実施形態２に係る圧電デバイスの製造方法において、基部に上側基部および下側基部の各々を形成した状態を示す断面図である。 FIG. 28 is a cross-sectional view showing a state before the upper base and the lower base are formed on the base in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. FIG. 29 is a cross-sectional view showing a state in which an upper base and a lower base are formed on a base in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
　図２８に示すように、本発明の実施形態１に係る圧電デバイス１００の製造方法と同様にして、基部２１０に凹部２１３を形成する。次に、図２９に示すように、基部２１０の一方の主面２１１および凹部２１３の内面の各々を熱酸化させる。これにより、基部２１０において熱酸化された部分が上側基部２１０ｂになり、基部２１０において熱酸化されなかった部分が下側基部２１０ａになる。 凹 部 As shown in FIG. 28, the concave portion 213 is formed in the base 210 in the same manner as in the method for manufacturing the piezoelectric device 100 according to the first embodiment of the present invention. Next, as shown in FIG. 29, each of the one main surface 211 of the base 210 and the inner surface of the concave portion 213 is thermally oxidized. Thus, the portion of the base 210 that has been thermally oxidized becomes the upper base 210b, and the portion of the base 210 that has not been thermally oxidized becomes the lower base 210a.
　図３０は、本発明の実施形態２に係る圧電デバイスの製造方法において、図２７に示す複数の層に、図２９に示す基部を接合させる状態を示す断面図である。図３１は、本発明の実施形態２に係る圧電デバイスの製造方法において、シーリング層の下面に基部を接合させた状態を示す断面図である。 FIG. 30 is a cross-sectional view showing a state where the base shown in FIG. 29 is joined to the plurality of layers shown in FIG. 27 in the method of manufacturing the piezoelectric device according to Embodiment 2 of the present invention. FIG. 31 is a cross-sectional view showing a state where the base is joined to the lower surface of the sealing layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention.
　図３０および図３１に示すように、シーリング層２７０の下面２７１に、基部２１０の一方の主面２１１を接合させる。これにより、凹部２１３の内部が、密閉空間となる。 As shown in FIGS. 30 and 31, one main surface 211 of the base 210 is joined to the lower surface 271 of the sealing layer 270. Thereby, the inside of the concave portion 213 becomes a closed space.
　本実施形態においては、凹部２１３の内部に異物が侵入することを抑制するため、真空圧下でシーリング層２７０と基部２１０とを接合させる。この場合、上記真空圧は、低真空、中真空、高真空および超高真空のいずれであってもよい。このようにシーリング層２７０と基部２１０とを接合するため、凹部２１３の内部の圧力は負圧となる。さらに、凹部２１３の内部の圧力が負圧になるため、凹部２１３の上方において、シーリング層２７０の下面２７１は、他方の主面２１２側に凸状に湾曲する。 In the present embodiment, the sealing layer 270 and the base 210 are joined under a vacuum pressure in order to prevent foreign matter from entering the inside of the recess 213. In this case, the vacuum pressure may be any of a low vacuum, a medium vacuum, a high vacuum, and an ultra-high vacuum. Since the sealing layer 270 and the base 210 are joined as described above, the pressure inside the concave portion 213 becomes a negative pressure. Further, since the pressure inside the concave portion 213 becomes a negative pressure, the lower surface 271 of the sealing layer 270 is convexly curved toward the other main surface 212 above the concave portion 213.
　なお、シーリング層２７０と基部２１０とを接合させるときの雰囲気は、真空圧下に限定されない。シーリング層２７０は、大気圧下で基部２１０と接合されてもよいし、高圧下で基部２１０と接合されてもよい。これらの雰囲気下でシーリング層２７０と基部２１０とが接合されることにより、シーリング層２７０の下面２７１が、平坦面になってもよいし、他方の主面２１２側とは反対側に凸状に湾曲してもよい。 The atmosphere for joining the sealing layer 270 and the base 210 is not limited to a vacuum pressure. The sealing layer 270 may be joined to the base 210 under atmospheric pressure, or may be joined to the base 210 under high pressure. By joining the sealing layer 270 and the base 210 under these atmospheres, the lower surface 271 of the sealing layer 270 may be flat, or may be convex on the opposite side to the other main surface 212 side. It may be curved.
　図３２は、本発明の実施形態２に係る圧電デバイスの製造方法において、単結晶圧電体層の上面を削った状態を示す断面図である。図３２に示すように、単結晶圧電体層２３０の上面をＣＭＰなどにより削って、単結晶圧電体層２３０を所望の厚さにする。この場合、単結晶圧電体層２３０の厚さは、電圧の印加による単結晶圧電体層２３０の所望の伸縮量が得られるように調整される。 FIG. 32 is a cross-sectional view showing a state in which the upper surface of the single-crystal piezoelectric layer is shaved in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. As shown in FIG. 32, the upper surface of the single-crystal piezoelectric layer 230 is shaved by CMP or the like so that the single-crystal piezoelectric layer 230 has a desired thickness. In this case, the thickness of the single-crystal piezoelectric layer 230 is adjusted so that a desired amount of expansion and contraction of the single-crystal piezoelectric layer 230 due to application of a voltage is obtained.
　図３３は、本発明の実施形態２に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。図３３に示すように、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層２３０の上面の一部に、上部電極層２４０を設ける。このようにして、積層部２２０が基部２１０の一方の主面２１１上に積層される。また、真空圧下でシーリング層２７０と基部２１０とが接合されるため、積層部２２０は、他方の主面２１２側に凸状に湾曲する。 FIG. 33 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of a single-crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to Embodiment 2 of the present invention. As shown in FIG. 33, an upper electrode layer 240 is provided on a part of the upper surface of the single-crystal piezoelectric layer 230 by a lift-off method, a plating method, an etching method, or the like. In this way, the laminated portion 220 is laminated on the one main surface 211 of the base 210. Further, since the sealing layer 270 and the base 210 are joined under a vacuum pressure, the laminated portion 220 is curved in a convex shape toward the other main surface 212.
　最後に、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層２３０の上面の一部に、孔部２３１を設ける。 Finally, a hole 231 is provided in a part of the upper surface of the single-crystal piezoelectric layer 230 by a lift-off method, a plating method, an etching method, or the like.
　上記の工程により、図２２に示すような本発明の実施形態２に係る圧電デバイス２００が製造される。 に よ り Through the above steps, the piezoelectric device 200 according to the second embodiment of the present invention as shown in FIG. 22 is manufactured.
　上記のように、本実施形態に係る圧電デバイス２００においては、積層部２２０が、少なくとも凹部２１３の上方において、単結晶圧電体層２３０と、上部電極層２４０と、下部電極層２５０とを含んでいる。この構成の場合、多結晶圧電体層を成膜して形成する場合とは異なり、単結晶圧電体層２３０と上部電極層２４０と下部電極層２５０とを含む複数の層を基部２１０に接合することで凹部２１３上に圧電体層を設けることができる。これにより、圧電体層の凹部２１３上に位置する部分を均一化して、圧電デバイス２００の圧電特性を向上することができる。 As described above, in the piezoelectric device 200 according to the present embodiment, the stacked unit 220 includes the single-crystal piezoelectric layer 230, the upper electrode layer 240, and the lower electrode layer 250 at least above the recess 213. I have. In the case of this configuration, a plurality of layers including the single crystal piezoelectric layer 230, the upper electrode layer 240, and the lower electrode layer 250 are joined to the base 210, unlike the case where the polycrystalline piezoelectric layer is formed by film formation. Thus, a piezoelectric layer can be provided on the concave portion 213. Thereby, the portion of the piezoelectric layer located on the concave portion 213 can be made uniform, and the piezoelectric characteristics of the piezoelectric device 200 can be improved.
　上述した実施形態の説明において、組み合わせ可能な構成を相互に組み合わせてもよい。 In the description of the above-described embodiment, combinations that can be combined may be combined with each other.
　今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 実 施 The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　１０　支持基板、１００，２００　圧電デバイス、１１０，２１０　基部、１１１，２１１　一方の主面、１１２，２１２　他方の主面、１１３，２１３　凹部、１２０，２２０　積層部、１３０，２３０　単結晶圧電体層、１３１，２３１　孔部、１４０，２４０　上部電極層、１５０，２５０　下部電極層、１６０，２６０　中間層、１６１，２６１，２７１　下面、２１０ａ　下側基部、２１０ｂ　上側基部、２７０　シーリング層、２７２　剥離層。 10 support substrate, 100, 200 piezoelectric device, 110, 210 base, 111, 211 one main surface, 112, 212 the other main surface, 113,213 recess, 120, 220 lamination, 130, 230 single crystal piezoelectric layer , 131,231 holes, 140,240 upper electrode layer, 150,250 lower electrode layer, 160,260 intermediate layer, 161, 261,271 lower surface, 210a lower base, 210b upper base, 270 sealing layer, 272 release layer .

Claims (5)

  1. 　一方の主面と、該一方の主面とは反対側に位置する他方の主面とを含み、かつ、前記一方の主面に形成された凹部を有する基部と、
    　前記凹部を上方から覆うように前記基部の前記一方の主面上に積層された積層部とを備え、
    　前記積層部は、少なくとも前記凹部の上方において、単結晶圧電体層と、該単結晶圧電体層の上側に配置された上部電極層と、前記単結晶圧電体層を挟んで前記上部電極層の少なくとも一部に対向するように配置された下部電極層とを含む、圧電デバイス。     A base including one main surface and the other main surface located on the opposite side to the one main surface, and having a recess formed in the one main surface;
    A laminated portion laminated on the one main surface of the base portion so as to cover the concave portion from above,
    The laminated portion is, at least above the concave portion, a single-crystal piezoelectric layer, an upper electrode layer disposed above the single-crystal piezoelectric layer, and an upper electrode layer sandwiching the single-crystal piezoelectric layer. A lower electrode layer disposed so as to face at least a part of the piezoelectric device.
  2. 　前記積層部は、前記下部電極層を下方から覆うように積層された中間層をさらに含んでいる、請求項１に記載の圧電デバイス。 The piezoelectric device according to claim 1, wherein the stacked unit further includes an intermediate layer stacked so as to cover the lower electrode layer from below.
  3. 　前記凹部の上方に位置していない領域において、前記中間層の下面が平坦である、請求項２に記載の圧電デバイス。 The piezoelectric device according to claim 2, wherein a lower surface of the intermediate layer is flat in a region not located above the concave portion.
  4. 　前記凹部の上方において、前記積層部は、他方の主面側に凸状に湾曲している、請求項１から請求項３のいずれか１項に記載の圧電デバイス。 4. The piezoelectric device according to claim 1, wherein, above the concave portion, the laminated portion is convexly curved toward the other main surface. 5.
  5. 　前記凹部の内部の圧力が負圧である、請求項１から請求項４のいずれか１項に記載の圧電デバイス。 (5) The piezoelectric device according to any one of (1) to (4), wherein the pressure inside the recess is a negative pressure.
PCT/JP2019/017431 2018-09-21 2019-04-24 Piezoelectric device WO2020059199A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309302A (en) * 2002-04-18 2003-10-31 Canon Inc Piezoelectric film type element structure, liquid injection head, and their manufacturing method
JP2010214633A (en) * 2009-03-13 2010-09-30 Ricoh Co Ltd Piezoelectric actuator, liquid droplet delivering head, liquid droplet head cartridge, liquid droplet delivering apparatus, micro-pump, and method for manufacturing piezoelectric actuator
JP2012049584A (en) * 2010-08-24 2012-03-08 Nippon Dempa Kogyo Co Ltd Piezoelectric device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309302A (en) * 2002-04-18 2003-10-31 Canon Inc Piezoelectric film type element structure, liquid injection head, and their manufacturing method
JP2010214633A (en) * 2009-03-13 2010-09-30 Ricoh Co Ltd Piezoelectric actuator, liquid droplet delivering head, liquid droplet head cartridge, liquid droplet delivering apparatus, micro-pump, and method for manufacturing piezoelectric actuator
JP2012049584A (en) * 2010-08-24 2012-03-08 Nippon Dempa Kogyo Co Ltd Piezoelectric device and method of manufacturing the same

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