WO2021053892A1 - Piezoelectric device and method for manufacturing same - Google Patents

Piezoelectric device and method for manufacturing same Download PDF

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Publication number
WO2021053892A1
WO2021053892A1 PCT/JP2020/022109 JP2020022109W WO2021053892A1 WO 2021053892 A1 WO2021053892 A1 WO 2021053892A1 JP 2020022109 W JP2020022109 W JP 2020022109W WO 2021053892 A1 WO2021053892 A1 WO 2021053892A1
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Prior art keywords
layer
single crystal
electrode layer
groove
piezoelectric device
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PCT/JP2020/022109
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French (fr)
Japanese (ja)
Inventor
文弥 黒川
伸介 池内
勝之 鈴木
諭卓 岸本
青司 梅澤
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株式会社村田製作所
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Publication of WO2021053892A1 publication Critical patent/WO2021053892A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02NELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
    • H02N2/00Electric machines in general using piezoelectric effect, electrostriction or magnetostriction
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R17/00Piezoelectric transducers; Electrostrictive transducers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/06Forming electrodes or interconnections, e.g. leads or terminals
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/80Constructional details
    • H10N30/87Electrodes or interconnections, e.g. leads or terminals

Definitions

  • the present invention relates to a piezoelectric device and a method for manufacturing the same.
  • Patent Document 1 is a document that discloses the configuration of the piezoelectric device.
  • the piezoelectric device described in Patent Document 1 includes a substrate and a membrane portion.
  • the substrate has an opening formed to penetrate.
  • the membrane portion is formed of at least one elastic layer and at least one piezoelectric layer sandwiched between the upper electrode layer and the lower electrode layer.
  • the membrane portion is attached to the substrate above the opening.
  • a through groove is formed by etching.
  • the piezoelectric layer is exposed in the through groove of the membrane portion.
  • the surface of the piezoelectric layer may be roughened, and the electrical characteristics of the piezoelectric device may be deteriorated. Therefore, there is room for improving the environmental resistance of the piezoelectric device by protecting the cross section forming the through groove of the piezoelectric layer.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a piezoelectric device capable of improving environmental resistance.
  • the piezoelectric device based on the present invention includes a base portion and a membrane portion.
  • the membrane portion is indirectly supported by the base portion, is located above the base portion, and is composed of a plurality of layers.
  • the membrane portion does not overlap the base portion.
  • the membrane portion includes a single crystal piezoelectric layer, an upper electrode layer, and a lower electrode layer.
  • the upper electrode layer is arranged above the single crystal piezoelectric layer.
  • the lower electrode layer is arranged so as to face at least a part of the upper electrode layer via the single crystal piezoelectric layer.
  • the membrane portion is provided with a through groove that penetrates in the vertical direction.
  • the first cross section of the single crystal piezoelectric layer facing the through groove is covered with a first protective portion located with the through groove in between.
  • the method for manufacturing a piezoelectric device based on the present invention includes a step of arranging a lower electrode layer below the single crystal piezoelectric layer and a step of forming a groove for a first protective portion penetrating in the vertical direction in the single crystal piezoelectric layer.
  • a step of filling the groove for the first protective portion with the first protective portion a step of forming a first laminated body including at least a single crystal piezoelectric layer, and a second laminated body under the first laminated body.
  • a step of arranging the above a step of forming a through groove, and a step of forming a recess.
  • a through groove that penetrates at least the first laminated body in the vertical direction is formed so as to divide the first protective portion.
  • the upper electrode layer and the lower electrode layer overlap with each other via the single crystal piezoelectric layer and the portion where the through groove is located.
  • a recess is formed which is opened on the lower side of the second laminated body and communicates with the through groove.
  • the environmental resistance of the piezoelectric device can be improved.
  • FIG. 5 is a cross-sectional view of the piezoelectric device of FIG. 1 as viewed from the direction of the arrow along line II-II. It is sectional drawing which shows the state which provided the lower electrode layer on the lower surface of the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the state which formed the groove for the 1st protection part in the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention.
  • FIG. 5 is a cross-sectional view showing a state in which the lower surface of the intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. It is sectional drawing which shows the state which prepared the 2nd laminated body in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention.
  • FIG. 5 is a cross-sectional view showing a state in which a groove is formed in a single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a state in which a first external electrode is provided on an upper electrode layer and a second external electrode is provided on a lower electrode layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. It is sectional drawing of the piezoelectric device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the state which formed the groove for the 1st protection part and the groove for the 2nd protection part in the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention.
  • a first intermediate layer is provided on the lower surface of each of the single crystal piezoelectric layers, in the groove for the first protective portion, and in the groove for the second protective portion. It is sectional drawing which shows the state. It is sectional drawing which shows the state which the lower surface of the 1st intermediate layer was shaved in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the state which provided the lower electrode layer on the lower surface of the 1st intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention.
  • FIG. 5 is a cross-sectional view showing a state in which a first external electrode is provided on an upper electrode layer and a second external electrode is provided on a semiconductor layer which is a lower electrode layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention. ..
  • FIG. 1 is a plan view of the piezoelectric device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the piezoelectric device of FIG. 1 as viewed from the direction of the arrow along line II-II.
  • the piezoelectric device 100 includes a base portion 110 and a membrane portion 120.
  • the base 110 includes a lower base 110a and an upper base 110b located above the lower base 110a.
  • the base 110 has an upper main surface 111 and a lower main surface 112 located on the opposite side of the upper main surface 111.
  • the upper surface of the upper base 110b is the upper main surface 111
  • the lower surface of the lower base 110a is the lower main surface 112.
  • the base 110 is formed with a recess 113 that penetrates the lower base 110a and the upper base 110b in the vertical direction.
  • the material constituting the base 110 is not particularly limited.
  • the lower base 110a is made of Si.
  • the upper base 110b is made of SiO 2 .
  • a plurality of layers 130 are laminated on the upper main surface 111 of the base 110.
  • the membrane portion 120 is a portion of the plurality of layers located above the recess 113. That is, the membrane portion 120 is composed of a plurality of layers 130.
  • the plurality of layers 130 extend from the membrane portion 120 to the upper side of the base portion 110.
  • the membrane portion 120 Since the membrane portion 120 is located above the recess 113 of the base 110, it does not overlap the base 110. That is, the membrane portion 120 is indirectly supported by the base portion 110 and is located above the base portion 110.
  • the membrane portion 120 is provided with a through groove 121 penetrating in the vertical direction.
  • the width of the through groove 121 is substantially constant from the upper end to the lower end.
  • the width of the through groove 121 is preferably 10 ⁇ m or less.
  • the membrane portion 120 includes a single crystal piezoelectric layer 140, an upper electrode layer 150, a lower electrode layer 160, an intermediate layer 170, a semiconductor layer 180, and a first protective portion 190. .. That is, the plurality of layers 130 constituting the membrane portion 120 include the single crystal piezoelectric layer 140, the upper electrode layer 150, the lower electrode layer 160, the intermediate layer 170, the semiconductor layer 180, and the first protective portion 190. have.
  • the single crystal piezoelectric layer 140 is located above the base 110.
  • the single crystal piezoelectric layer 140 has a first cross section 141 and a second cross section 142.
  • the distance between the first cross sections 141 increases from the upper electrode layer 150 side to the lower electrode layer 160 side.
  • the distance between the second cross sections 142 is substantially constant from the upper electrode layer 150 side to the lower electrode layer 160 side.
  • the single crystal piezoelectric layer 140 is formed with a groove portion 143 that penetrates the single crystal piezoelectric layer 140 in the vertical direction.
  • the second cross section 142 faces the groove portion 143.
  • the thickness of the single crystal piezoelectric layer 140 is, for example, 5 ⁇ m or less.
  • the single crystal piezoelectric layer 140 is made of lithium tantalate or lithium niobate.
  • the single crystal piezoelectric layer 140 composed of lithium tantalate or lithium niobate has a uniform polarization state, and the direction parallel to the plane on the base 110 side of the single crystal piezoelectric layer 140 is the in-plane direction. In addition, it has the property of being easy to cleave while forming a cleavage plane in a specific in-plane direction and out-of-plane direction.
  • the upper electrode layer 150 is arranged above the single crystal piezoelectric layer 140.
  • An adhesion layer may be arranged between the upper electrode layer 150 and the single crystal piezoelectric layer 140.
  • the lower electrode layer 160 is arranged in the membrane portion 120 so as to face at least a part of the upper electrode layer 150 via the single crystal piezoelectric layer 140.
  • the lower electrode layer 160 is arranged below the single crystal piezoelectric layer 140.
  • An adhesion layer may be arranged between the lower electrode layer 160 and the single crystal piezoelectric layer 140.
  • the lower electrode layer 160 has an etching stop layer 161.
  • the etching stop layer 161 is located at a portion of the lower electrode layer 160 on the base 110 side.
  • the etching stop layer 161 may be located at a portion of the lower electrode layer 160 opposite to the base 110 side.
  • the lower electrode layer 160 is arranged above the base 110 and below the groove 143 formed in the single crystal piezoelectric layer 140.
  • the lower electrode layer 160 is located so as to cover the lower part of the groove portion 143.
  • the etching stop layer 161 of the lower electrode layer 160 is located so as to cover the lower part of the groove portion 143.
  • the upper electrode layer 150 is continuously formed on the upper side of the single crystal piezoelectric layer 140 when viewed from above and below. ing.
  • the lower electrode layer 160 is also continuously formed under the single crystal piezoelectric layer 140 when viewed from above and below.
  • the outer edges of the upper electrode layer 150 and the lower electrode layer 160 are preferably located non-parallel to the cleavage direction of the single crystal piezoelectric layer 140. .. Further, when the piezoelectric device 100 according to the present embodiment includes a semiconductor layer made of Si, the outer edges of the upper electrode layer 150 and the lower electrode layer 160 are set with respect to the opening direction of the semiconductor layer. It is preferable that they are located non-parallel.
  • each of the upper electrode layer 150 and the lower electrode layer 160 is made of a conductive material such as Pt, Ni, or Au.
  • the etching stop layer 161 is preferably a material that has conductivity and is not etched when the single crystal piezoelectric 140 layer is etched. It is composed of an etching stop layer 161 such as Ni.
  • the material of the adhesion layer is not particularly limited as long as it is a material having conductivity and adhesion.
  • the adhesion layer is composed of, for example, a Ti, Cr, Ni or NiCr alloy.
  • the adhesion layer is preferably made of a NiCr alloy that is less likely to diffuse atoms into the single crystal piezoelectric layer 140 as compared with Ti.
  • the piezoelectric device 100 further includes a first external electrode 155 and a second external electrode 165.
  • the first external electrode 155 is electrically connected to the upper electrode layer 150, and specifically, is arranged on the upper electrode layer 150 above the base 110.
  • the second external electrode 165 is electrically connected to the lower electrode layer 160.
  • the second external electrode 165 is provided on the lower electrode layer 160, on the second cross section 142 which is the inner side surface of the groove portion 143, and on the upper surface of the single crystal piezoelectric layer 140.
  • the material constituting each of the first external electrode 155 and the second external electrode 165 is not particularly limited as long as it is a conductive material such as metal.
  • the intermediate layer 170 is arranged below the single crystal piezoelectric layer 140.
  • the intermediate layer 170 includes the lower surface of the lower electrode layer 160, the lower surface of the single crystal piezoelectric layer 140 that is not covered by the lower electrode layer 160, and the lower surface of the first protective portion 190. It is provided so that it touches.
  • the intermediate layer 170 is composed of a dielectric layer such as SiO 2.
  • the semiconductor layer 180 is arranged below the intermediate layer 170.
  • the semiconductor layer 180 is provided so as to be in contact with the lower surface of the intermediate layer 170.
  • the semiconductor layer 180 may be provided on the lower surface of the intermediate layer 170 via the metal layer.
  • the lower surface of the semiconductor layer 180 is exposed in the recess 113.
  • the semiconductor layer 180 is made of, for example, Si.
  • the first protection unit 190 is located on the first cross section 141.
  • the first protective portion 190 is provided with a through groove 121. That is, the first cross section 141 of the single crystal piezoelectric layer 140 facing the through groove 121 is covered with the first protective portion 190 located with the through groove 121 in between.
  • the first protection unit 190 is composed of a member integrated with the intermediate layer 170. That is, the lower surface of the first protective portion 190 is connected to the intermediate layer 170. With the above configuration, the first protective portion 190 and the intermediate layer 170 can be laminated at the same time, and the manufacturing process of the piezoelectric device 100 can be simplified. Further, when the first protective portion 190 is made of the same material as the material constituting the intermediate layer 170, it is possible to suppress the formation of a crystal boundary between the lower surface of the first protective portion 190 and the intermediate layer 170. .. Therefore, it is possible to suppress the occurrence of cracks from the crystal boundary.
  • the first protection unit 190 is made of a dielectric material such as SiO 2.
  • the single crystal piezoelectric layer 140 expands and contracts when a voltage is applied between the upper electrode layer 150 and the lower electrode layer 160.
  • the members other than the single crystal piezoelectric layer 140 are not deformed by the application of voltage. Therefore, the membrane portion 120 bends and vibrates up and down in response to the expansion and contraction of the single crystal piezoelectric layer 140 due to the application of the voltage.
  • FIG. 3 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • the lower electrode layer 160 is arranged below the single crystal piezoelectric layer 140.
  • the thickness of the single crystal piezoelectric layer 140 is, for example, 200 ⁇ m or more and 500 ⁇ m or less.
  • the lower electrode layer 160 is provided on the lower surface of the single crystal piezoelectric layer 140 by a lift-off method, a plating method, an etching method, or the like. More specifically, after providing the portion of the lower electrode layer 160 other than the etching stop layer 161, the etching stop layer 161 is provided. After the etching stop layer 161 is provided, a portion of the lower electrode layer 160 other than the etching stop layer 161 may be provided.
  • the lower electrode layer 160 is preferably provided by epitaxial growth. As a result, the fatigue characteristics of the membrane portion 120 due to the driving of the single crystal piezoelectric layer 140 are improved.
  • FIG. 4 is a cross-sectional view showing a state in which a groove for a first protective portion is formed in a single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • a groove 141A for the first protective portion is formed on the lower surface of the single crystal piezoelectric layer 140 from the lower side of the single crystal piezoelectric layer 140 by an etching method or the like.
  • the depth of the groove 141A for the first protective portion may be, for example, about 10 ⁇ m.
  • FIG. 5 shows a state in which the lower surfaces of the single crystal piezoelectric layer and the lower electrode layer and the intermediate layer are provided in the groove for the first protective portion in the method for manufacturing the piezoelectric device according to the first embodiment of the present invention. It is a sectional view. As shown in FIGS. 4 and 5, each of the lower electrode layer 160 and the single crystal piezoelectric layer 140 in the groove 141A for the first protective portion by the CVD (Chemical Vapor Deposition) method or the PVD (Physical Vapor Deposition) method or the like. An intermediate layer 170 is provided on the lower surface of the. At this time, the intermediate layer 170 is provided so as to fill the inside of the groove 141A for the first protective portion.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • FIG. 6 is a cross-sectional view showing a state in which the lower surface of the intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • the lower surface of the intermediate layer 170 is flattened by chemical mechanical polishing (CMP) or the like.
  • CMP chemical mechanical polishing
  • the groove 141A for the first protective portion is filled with the first protective portion 190 made of the same member as the intermediate layer 170.
  • the first laminated body 10 including at least the single crystal piezoelectric layer 140 is formed by the above steps. Specifically, the first laminated body 10 in the present embodiment further includes a lower electrode layer 160, an intermediate layer 170, and a first protective portion 190.
  • FIG. 7 is a cross-sectional view showing a state in which a second laminated body is prepared in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • the second laminated body 20 is joined to the lower side of the first laminated body 10.
  • the second laminated body 20 is composed of a base portion 110 in which the recess 113 is not formed, and a semiconductor layer 180 joined on the upper main surface 111 of the base portion 110.
  • the second laminated body 20 is an SOI (Silicon on Insulator) substrate.
  • FIG. 10 is a cross-sectional view showing a state in which the upper surfaces of the single crystal piezoelectric layer and the first protective portion are scraped in the method for manufacturing the piezoelectric device according to the first embodiment of the present invention.
  • the thickness of the single crystal piezoelectric layer 140 is adjusted. Specifically, the upper surfaces of the single crystal piezoelectric layer 140 and the first protective portion 190 are each scraped by CMP or the like to make the single crystal piezoelectric layer 140 a desired thickness, and the first protective portion 190 is exposed. Let me. In this case, the thickness of the single crystal piezoelectric layer 140 is adjusted so that a desired amount of expansion and contraction of the single crystal piezoelectric layer 140 can be obtained by applying a voltage.
  • a release layer may be formed by implanting ions in advance on the upper surface side of the single crystal piezoelectric layer 140.
  • the thickness of the single crystal piezoelectric layer 140 can be easily adjusted by peeling the peeling layer before the upper surface of the single crystal piezoelectric layer 140 is scraped by CMP or the like.
  • the peeling layer may be scraped by CMP or the like.
  • FIG. 11 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • a lower electrode is formed on the upper side of the single crystal piezoelectric layer 140 by a lift-off method (photolithography method), a plating method, an etching method, or the like, at least partially via the single crystal piezoelectric layer 140.
  • the upper electrode layer 150 is arranged so as to face the layer 160.
  • the upper electrode layer 150 is patterned by the lift-off method (photolithography method).
  • the upper electrode layer 150 is preferably provided by epitaxial growth. As a result, the fatigue characteristics of the membrane portion 120 due to the driving of the single crystal piezoelectric layer 140 are improved.
  • FIG. 12 is a cross-sectional view showing a state in which a through groove is formed from the first protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • a through groove 121 is formed in the first protective portion 190 by etching from the upper side.
  • a through groove 121 that penetrates at least the first laminated body 10 in the vertical direction is formed so as to divide the first protective portion 190.
  • the through groove 121 is formed so as to further penetrate the semiconductor layer 180.
  • the through groove 121 may be formed so as to be located below the lower surface of the semiconductor layer 180.
  • FIG. 13 is a cross-sectional view showing a state in which a groove is formed in the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
  • the groove portion 143 is formed by etching the single crystal piezoelectric layer 140 above the base portion 110.
  • the upper portion of the etching stop layer 161 of the lower electrode layer 160 may be etched.
  • FIG. 14 is a cross-sectional view showing a state in which the first external electrode is provided on the upper electrode layer and the second external electrode is provided on the lower electrode layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. ..
  • a first external electrode 155 is provided on the upper electrode layer 150 and a second external electrode 165 is provided on the lower electrode layer 160 by a lift-off method, a plating method, an etching method, or the like.
  • the second external electrode 165 is provided on the etching stop layer 161 of the lower electrode layer 160.
  • the recess 113 is formed. Specifically, when viewed from the vertical direction, the upper electrode layer 150 and the lower electrode layer 160 face each other via the single crystal piezoelectric layer 140, and the portion where the through groove 121 is located. A recess 113 that opens to the lower side of the second laminated body 20 and communicates with the through groove 121 is formed so as to overlap each other.
  • the second laminated body 20 is subjected to deep reactive ion etching (Deep Reactive Ion Etching) to form a recess 113 in the base 110.
  • the piezoelectric device 100 according to the first embodiment of the present invention as shown in FIG. 2 is manufactured.
  • the membrane portion 120 is provided with a through groove 121 penetrating in the vertical direction.
  • the first cross section 141 of the single crystal piezoelectric layer 140 facing the through groove 121 is covered with a first protective portion 190 located with the through groove 121 in between.
  • the distance between the first cross sections 141 increases from the upper electrode layer 150 side to the lower electrode layer 160 side.
  • the first protective portion 190 having good covering property can be obtained by laminating the first protective portion 190 from the lower side of the single crystal piezoelectric layer 140. Can be provided. As a result, in the single crystal piezoelectric layer 140, the internal stress caused by the first protective portion 190 is relaxed, so that cracks are less likely to occur and the reliability of the piezoelectric device 100 is improved.
  • the method for manufacturing the piezoelectric device 100 according to the first embodiment of the present invention includes a step of arranging the lower electrode layer 160 below the single crystal piezoelectric layer 140 and a first method of penetrating the single crystal piezoelectric layer 140 in the vertical direction.
  • the recess 113 when viewed from the vertical direction, a portion where the upper electrode layer 150 and the lower electrode layer 160 face each other via the single crystal piezoelectric layer 140, and a through groove 121 are formed.
  • a recess 113 that opens to the lower side of the second laminated body 20 and communicates with the through groove 121 is formed so as to overlap the located portion.
  • the environmental resistance of the piezoelectric device 100 can be improved. Further, since the through groove 121 is formed by processing the first protective portion 190 which is easier to etch than the single crystal piezoelectric layer 140 made of a difficult-to-etch material, the shape of the through groove 121 is stabilized. be able to.
  • the piezoelectric device according to the second embodiment of the present invention is different from the piezoelectric device 100 according to the first embodiment of the present invention mainly in that a second protective portion is provided. Therefore, the description of the configuration similar to that of the piezoelectric device 100 according to the first embodiment of the present invention will not be repeated.
  • FIG. 15 is a cross-sectional view of the piezoelectric device according to the second embodiment of the present invention.
  • the cross-sectional view of the piezoelectric device 200 shown in FIG. 15 is shown in the same cross-sectional view as the cross-sectional view of the piezoelectric device 100 shown in FIG.
  • the membrane portion 120 includes the first intermediate layer 270 as an intermediate layer located between the lower electrode layer 260 and the single crystal piezoelectric layer 140. ..
  • the stress generated in the membrane portion 120 can be relaxed, and the peeling of the lower electrode layer 260 from the single crystal piezoelectric layer 140 can be suppressed.
  • the membrane portion 120 includes a first intermediate layer 270 and a second intermediate layer 275 as intermediate layers, and the plurality of layers 130 constituting the membrane portion 120 are
  • the intermediate layer includes a first intermediate layer 270 and a second intermediate layer 275.
  • the first intermediate layer 270 is provided so as to be in contact with each of the lower surface of the single crystal piezoelectric layer 140, the lower surface of the first protective portion 190, and the lower surface of the second protective portion described later. Is composed of a dielectric layer such as SiO 2.
  • the lower electrode layer 260 is arranged below the first intermediate layer 270.
  • the first protective portion 190 is composed of a member integrated with the first intermediate layer 270.
  • the second intermediate layer 275 is provided so as to be in contact with each of the lower surface of the lower electrode layer 260 and the lower surface of the first intermediate layer 270 that are not covered by the lower electrode layer 260.
  • the second intermediate layer 275 is preferably made of the same material as the material constituting the first intermediate layer 270.
  • the second intermediate layer 275 is composed of a dielectric layer such as SiO 2.
  • the semiconductor layer 180 is provided so as to be in contact with the lower surface of the first intermediate layer 270.
  • the single crystal piezoelectric layer 140 has a second cross section 242 above the base 110 and facing each other with a groove 143 in between. I have more.
  • the second cross section 242 is covered with a second protective portion 291 located with the groove portion 143 in between.
  • the lower electrode layer 260 is located below the second protective portion 291.
  • the second external electrode 165 is provided on the lower electrode layer 260, the inner side surface of the groove portion 143, and the upper side of the second protective portion 291 and is separated from the single crystal piezoelectric layer 140.
  • the metal atoms constituting the second external electrode 165 it is possible to prevent the metal atoms constituting the second external electrode 165 from diffusing into the single crystal piezoelectric layer 140.
  • the second external electrode 165 is made of Ti and the single crystal piezoelectric layer 140 is made of lithium niobate, the Ti atom is a single crystal piezoelectric layer due to the above configuration. It is possible to suppress the diffusion within 140.
  • the groove portion 143 is formed not in the single crystal piezoelectric layer 140 but in the second protective portion 291.
  • the second cross section 242 is not exposed to the groove portion 143.
  • the groove portion 143 is formed so as to reach the upper surface of the lower electrode layer 260. The distance between the second cross sections 242 increases from the upper electrode layer 150 side to the lower electrode layer 160 side.
  • the second protective portion 291 is composed of a member integrated with the first intermediate layer 270.
  • the lower surface of the second protective portion 291 is connected to the first intermediate layer 270.
  • the second protective portion 291 is made of a dielectric material such as SiO 2.
  • FIG. 16 is a cross-sectional view showing a state in which a groove for a first protective portion and a groove for a second protective portion are formed in a single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to a second embodiment of the present invention.
  • the groove 141A for the first protective portion is formed, and the groove 242A for the second protective portion is formed on the lower surface of the single crystal piezoelectric layer 140 by an etching method or the like.
  • FIG. 17 shows the first intermediate in each of the lower surface of each single crystal piezoelectric layer, the inside of the groove for the first protection portion, and the inside of the groove for the second protection portion in the method for manufacturing the piezoelectric device according to the second embodiment of the present invention. It is sectional drawing which shows the state which provided the layer. As shown in FIGS. 16 and 17, the first protective portion groove 141A, the second protective portion groove 242A, and the lower surface of the single crystal piezoelectric layer 140 are formed by a CVD method, a PVD method, or the like. An intermediate layer 270 is provided.
  • FIG. 18 is a cross-sectional view showing a state in which the lower surface of the first intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the lower surface of the first intermediate layer 270 is scraped to be flat by CMP or the like.
  • the first protective portion groove 141A is filled with the first protective portion 190 made of the same member as the first intermediate layer 270
  • the second protective portion groove 242A is filled with the first intermediate layer 270. It is filled with the second protective portion 291 made of the same member as the above.
  • FIG. 19 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the first intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the lower electrode layer 260 is provided on the lower surface of the first intermediate layer 270.
  • the specific method for providing the lower electrode layer 260 is the same as the method for providing the lower electrode layer 160 in the first embodiment of the present invention.
  • FIG. 20 is a cross-sectional view showing a state in which a second intermediate layer is provided on the lower surfaces of each of the first intermediate layer and the lower electrode layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • a second intermediate layer 275 is provided on the lower surfaces of each of the first intermediate layer 270 and the lower electrode layer 260 by a CVD method, a PVD method, or the like.
  • FIG. 21 is a cross-sectional view showing a state in which the lower surface of the second intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 21, the lower surface of the second intermediate layer 275 is flattened by CMP or the like.
  • the first laminated body 10 is formed by the above steps. Specifically, the first laminated body 10 in the present embodiment includes a first intermediate layer 270 and a second intermediate layer 275 as intermediate layers, and further includes a second protective portion 291.
  • FIG. 22 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the second intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • FIG. 23 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the second intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the second laminated body 20 used in the first embodiment of the present invention is joined to the lower side of the first laminated body 10.
  • FIG. 24 is a cross-sectional view showing a state in which the upper surfaces of the single crystal piezoelectric layer, the first protective portion, and the second protective portion are scraped in the method for manufacturing the piezoelectric device according to the second embodiment of the present invention.
  • the upper surfaces of the single crystal piezoelectric layer 140, the first protective portion 190, and the second protective portion 291 are each scraped by CMP or the like to make the single crystal piezoelectric layer 140 a desired thickness.
  • Each of the first protection unit 190 and the second protection unit 291 is exposed.
  • FIG. 25 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the upper electrode layer 150 is arranged on the upper surface of the single crystal piezoelectric layer 140 in the same manner as the upper electrode layer 150 in the first embodiment of the present invention.
  • FIG. 26 is a cross-sectional view showing a state in which a through groove is formed from the first protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the through groove 121 is formed in the same manner as the through groove 121 in the first embodiment of the present invention.
  • the through groove 121 is formed so as to penetrate the first intermediate layer 270 and the second intermediate layer 275.
  • FIG. 27 is a cross-sectional view showing a state in which a groove portion is formed from the second protective portion to the first intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention.
  • the groove portion 143 is formed by etching the second protective portion 291 and the first intermediate layer 270 above the base portion 110.
  • FIG. 28 is a cross-sectional view showing a state in which the first external electrode is provided on the upper electrode layer and the second external electrode is provided on the lower electrode layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. .. As shown in FIG. 28, the first external electrode 155 and the second external electrode 165 are provided in the same manner as the first external electrode 155 and the second external electrode 165 in the first embodiment of the present invention.
  • the recess 113 is formed in the same manner as the recess 113 of the first embodiment of the present invention.
  • the piezoelectric device 200 according to the second embodiment of the present invention as shown in FIG. 15 is manufactured.
  • the piezoelectric device according to the third embodiment of the present invention is different from the piezoelectric device 200 according to the second embodiment of the present invention mainly in that it does not have the first intermediate layer 270 in the second embodiment of the present invention. Therefore, the description of the configuration similar to that of the piezoelectric device 200 according to the second embodiment of the present invention will not be repeated.
  • FIG. 29 is a cross-sectional view of the piezoelectric device according to the third embodiment of the present invention.
  • the cross-sectional view of the piezoelectric device 300 shown in FIG. 29 is shown in the same cross-sectional view as the cross-sectional view of the piezoelectric device 200 shown in FIG.
  • the membrane portion 120 includes only the second intermediate layer 275 as the intermediate layer.
  • the lower electrode layer 260 is provided on the lower surface of the single crystal piezoelectric layer 140, the lower surface of the second external electrode 165, and the lower surface of the second protective portion 291.
  • the upper electrode layer 150 and the lower electrode layer 260 face each other with only the single crystal piezoelectric layer 140 interposed therebetween, so that the piezoelectric device 200 is compared with the piezoelectric device 200 according to the second embodiment of the present invention.
  • the piezoelectric characteristics of the device 300 can be improved.
  • the second intermediate layer 275 is provided on the lower surface of the single crystal piezoelectric layer 140, the lower surface of the lower electrode layer 260, and the lower surface of the first protective portion 190.
  • FIGS. 16 and 17 in the same manner as in the manufacturing method of the piezoelectric device 200 according to the second embodiment of the present invention, the inside of the first protective portion groove 141A, the inside of the second protective portion groove 242A, and the single.
  • a first intermediate layer 270 is provided on the lower surface of each of the crystalline piezoelectric layers 140.
  • FIG. 30 is a cross-sectional view showing a state in which the first intermediate layer is scraped from the lower side in the method for manufacturing a piezoelectric device according to the third embodiment of the present invention.
  • the first intermediate layer 270 is scraped from the lower side by CMP or the like to completely remove the first intermediate layer 270 located below the lower surface of the single crystal piezoelectric layer 140.
  • the lower surface of the single crystal piezoelectric layer 140 may be scraped at the same time.
  • FIG. 31 is a cross-sectional view showing a state in which the lower electrode layer is provided on the lower surface of the single crystal piezoelectric layer and the second protective portion in the method for manufacturing the piezoelectric device according to the third embodiment of the present invention.
  • the lower electrode layer 260 is provided on the lower surface of the single crystal piezoelectric layer 140 and the lower surface of the second protective portion 291.
  • the specific method for providing the lower electrode layer 260 is the same as the method for providing the lower electrode layer 160 in the first embodiment of the present invention.
  • FIG. 32 is a cross-sectional view showing a state in which a second intermediate layer is provided on the lower surfaces of each of the first protective portion and the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the third embodiment of the present invention.
  • a second intermediate layer 275 is provided on the lower surfaces of each of the single crystal piezoelectric layer 140, the lower electrode layer 260, and the first protective portion 190 by a CVD method, a PVD method, or the like.
  • the book as shown in FIG. 29 is similar to the method for manufacturing the piezoelectric device 200 according to the second embodiment of the present invention shown in FIGS. 21 to 28.
  • the piezoelectric device 300 according to the third embodiment of the present invention can be manufactured.
  • the piezoelectric device according to the fourth embodiment of the present invention is different from the piezoelectric device 200 according to the second embodiment of the present invention mainly in that the lower electrode layer is a semiconductor layer. Therefore, the description of the configuration similar to that of the piezoelectric device 200 according to the second embodiment of the present invention will not be repeated.
  • FIG. 33 is a cross-sectional view of the piezoelectric device according to the fourth embodiment of the present invention.
  • the cross-sectional view of the piezoelectric device 400 shown in FIG. 33 is shown in the same cross-sectional view as the cross-sectional view of the piezoelectric device 200 shown in FIG.
  • the lower electrode layer 460 is a semiconductor layer 180. That is, as shown in FIG. 15, the lower electrode layer 260 and the second intermediate layer 275 made of members different from the semiconductor layer 180 in the second embodiment of the present invention are the piezoelectric device 400 according to the fourth embodiment of the present invention. Not provided in. As shown in FIG. 33, in the present embodiment, the semiconductor layer 180 is provided on the lower surface of the first intermediate layer 270.
  • the step of providing the lower electrode layer made of a member different from the semiconductor layer 180 can be omitted when manufacturing the piezoelectric device 400. As a result, the manufacturing method of the piezoelectric device 400 can be simplified.
  • the electrical resistivity of the material constituting the semiconductor layer 180 is preferably 20 m ⁇ ⁇ cm or less from the viewpoint of functioning as the lower electrode layer 460.
  • the groove portion 443 is located below the upper surface of the semiconductor layer 180.
  • the contact area between the second external electrode 165 and the semiconductor layer 180, which is the lower electrode layer 460 increases. Therefore, the contact resistance between the second external electrode 165 and the semiconductor layer 180 can be reduced.
  • the groove 141A for the first protective portion is filled with the first protective portion 190, and the second protective portion is formed.
  • the groove 242A is filled with the second protective portion 291.
  • the laminate shown in FIG. 18 is the first laminate 10.
  • FIG. 34 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the first intermediate layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention.
  • FIG. 35 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the first intermediate layer in the method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention.
  • the second laminated body 20 used in the first embodiment of the present invention is joined to the lower side of the first laminated body 10.
  • FIG. 36 is a cross-sectional view showing a state in which the upper surfaces of the single crystal piezoelectric layer, the first protective portion, and the second protective portion are scraped in the method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention.
  • the upper surfaces of the single crystal piezoelectric layer 140, the first protective portion 190, and the second protective portion 291 are each scraped by CMP or the like to make the single crystal piezoelectric layer 140 a desired thickness.
  • Each of the first protective portion 190 and the second protective portion 291 is exposed.
  • FIG. 37 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention.
  • the upper electrode layer 150 is arranged on the upper surface of the single crystal piezoelectric layer 140 in the same manner as the upper electrode layer 150 in the first embodiment of the present invention.
  • FIG. 38 is a cross-sectional view showing a state in which a through groove is formed from the first protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention.
  • the through groove 121 is formed in the same manner as the through groove 121 in the first embodiment of the present invention.
  • FIG. 39 is a cross-sectional view showing a state in which a groove portion is formed from the second protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention.
  • the groove portion 443 is formed by etching the second protective portion 291 and the first intermediate layer 270 and a part of the semiconductor layer 180 above the base portion 110.
  • FIG. 40 shows a state in which the first external electrode is provided on the upper electrode layer and the second external electrode is provided on the semiconductor layer which is the lower electrode layer in the method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention. It is a sectional view. As shown in FIG. 40, the first external electrode 155 and the second external electrode 165 are provided in the same manner as the first external electrode 155 and the second external electrode 165 in the first embodiment of the present invention. That is, in the fourth embodiment of the present invention, the second external electrode 165 is provided on the semiconductor layer 180, which is the lower electrode layer 460.
  • the recess 113 is formed in the same manner as the recess 113 of the first embodiment of the present invention.
  • the piezoelectric device 400 according to the fourth embodiment of the present invention as shown in FIG. 33 is manufactured.

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Abstract

Provided is a piezoelectric device (100) in which a membrane part (120) is indirectly supported by a base part (110), is located on the upper side relative to the base part (110), and is formed of a plurality of layers (130). The membrane part (120) does not overlap with the base part (110). The membrane part (120) includes a single crystal piezoelectric layer (140), an upper electrode layer (150), and a lower electrode layer (160). The upper electrode layer (150) is disposed on the upper side of the single crystal piezoelectric layer (140). The lower electrode layer (160) is disposed so as to face at least part of the upper electrode layer (150) with the single crystal piezoelectric layer (140) interposed therebetween. The membrane part (120) is provided with a through-groove (121) vertically penetrating therethrough. A first cross-section (141) of the single crystal piezoelectric layer (140) facing the through-groove (121) is covered by a first protection part (190) which is located with the through-groove (121) sandwiched therebetween.

Description

圧電デバイスおよびその製造方法Piezoelectric device and its manufacturing method
 本発明は、圧電デバイスおよびその製造方法に関する。 The present invention relates to a piezoelectric device and a method for manufacturing the same.
 圧電デバイスの構成を開示した文献として、国際公開第2017/218299号(特許文献1)がある。特許文献1に記載された圧電デバイスは、基板と、メンブレン部とを備えている。基板は、貫通するように形成された開口部を有している。メンブレン部は、少なくとも1つの弾性層と、上部電極層および下部電極層の間に挟まれた少なくとも1つの圧電層とから形成されている。メンブレン部は、開口部より上方において基板に取り付けられている。メンブレン部においては、エッチングされることにより貫通溝が形成されている。 International Publication No. 2017/218299 (Patent Document 1) is a document that discloses the configuration of the piezoelectric device. The piezoelectric device described in Patent Document 1 includes a substrate and a membrane portion. The substrate has an opening formed to penetrate. The membrane portion is formed of at least one elastic layer and at least one piezoelectric layer sandwiched between the upper electrode layer and the lower electrode layer. The membrane portion is attached to the substrate above the opening. In the membrane portion, a through groove is formed by etching.
国際公開第2017/218299号International Publication No. 2017/218299
 メンブレン部の貫通溝においては、圧電体層が露出している。この貫通溝を構成している断面において、圧電体層の表面が荒れて、圧電デバイスの電気特性が劣化するおそれがある。このため、圧電体層の貫通溝を構成している断面を保護することで、圧電デバイスの耐環境性を向上できる余地がある。 The piezoelectric layer is exposed in the through groove of the membrane portion. In the cross section forming the through groove, the surface of the piezoelectric layer may be roughened, and the electrical characteristics of the piezoelectric device may be deteriorated. Therefore, there is room for improving the environmental resistance of the piezoelectric device by protecting the cross section forming the through groove of the piezoelectric layer.
 本発明は上記の課題に鑑みてなされたものであり、耐環境性を向上できる圧電デバイスを提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a piezoelectric device capable of improving environmental resistance.
 本発明に基づく圧電デバイスは、基部と、メンブレン部とを備えている。メンブレン部は、基部に間接的に支持されて、基部より上側に位置し、複数の層からなる。メンブレン部は、基部に重なっていない。メンブレン部は、単結晶圧電体層と、上部電極層と、下部電極層とを含んでいる。上部電極層は、単結晶圧電体層の上側に配置されている。下部電極層は、単結晶圧電体層を介して、上部電極層の少なくとも一部に対向するように配置されている。メンブレン部には、上下方向に貫通する貫通溝が設けられている。単結晶圧電体層の貫通溝と面する第1断面は、貫通溝を間に挟んで位置する第1保護部に覆われている。 The piezoelectric device based on the present invention includes a base portion and a membrane portion. The membrane portion is indirectly supported by the base portion, is located above the base portion, and is composed of a plurality of layers. The membrane portion does not overlap the base portion. The membrane portion includes a single crystal piezoelectric layer, an upper electrode layer, and a lower electrode layer. The upper electrode layer is arranged above the single crystal piezoelectric layer. The lower electrode layer is arranged so as to face at least a part of the upper electrode layer via the single crystal piezoelectric layer. The membrane portion is provided with a through groove that penetrates in the vertical direction. The first cross section of the single crystal piezoelectric layer facing the through groove is covered with a first protective portion located with the through groove in between.
 本発明に基づく圧電デバイスの製造方法は、単結晶圧電体層の下方に下部電極層を配置する工程と、単結晶圧電体層に、上下方向に貫通する第1保護部用溝を形成する工程と、第1保護部用溝を第1保護部で埋める工程と、少なくとも単結晶圧電体層を含む第1積層体を形成する工程と、第1積層体の下側に、第2積層体を接合する工程と、単結晶圧電体層の厚さを調整する工程と、単結晶圧電体層の上側に、少なくとも一部が単結晶圧電体層を介して下部電極層と対向する、上部電極層を配置する工程と、貫通溝を形成する工程と、凹部を形成する工程とを備える工程とを備えている。貫通溝を形成する工程においては、第1保護部を分割するように、少なくとも第1積層体を上下方向に貫通する貫通溝を形成する。凹部を形成する工程においては、上下方向から見たときに、上部電極層と、下部電極層とが単結晶圧電体層を介して対向している部分、および、貫通溝が位置する部分と重なるように、第2積層体の下側に開口して貫通溝と連通する凹部を形成する。 The method for manufacturing a piezoelectric device based on the present invention includes a step of arranging a lower electrode layer below the single crystal piezoelectric layer and a step of forming a groove for a first protective portion penetrating in the vertical direction in the single crystal piezoelectric layer. A step of filling the groove for the first protective portion with the first protective portion, a step of forming a first laminated body including at least a single crystal piezoelectric layer, and a second laminated body under the first laminated body. The step of joining, the step of adjusting the thickness of the single crystal piezoelectric layer, and the upper electrode layer on the upper side of the single crystal piezoelectric layer, at least a part of which faces the lower electrode layer via the single crystal piezoelectric layer. It is provided with a step of arranging the above, a step of forming a through groove, and a step of forming a recess. In the step of forming the through groove, a through groove that penetrates at least the first laminated body in the vertical direction is formed so as to divide the first protective portion. In the step of forming the recess, when viewed from above and below, the upper electrode layer and the lower electrode layer overlap with each other via the single crystal piezoelectric layer and the portion where the through groove is located. As described above, a recess is formed which is opened on the lower side of the second laminated body and communicates with the through groove.
 本発明によれば、圧電デバイスの耐環境性を向上できる。 According to the present invention, the environmental resistance of the piezoelectric device can be improved.
本発明の実施形態1に係る圧電デバイスの平面図である。It is a top view of the piezoelectric device which concerns on Embodiment 1 of this invention. 図1の圧電デバイスをII-II線矢印方向から見た断面図である。FIG. 5 is a cross-sectional view of the piezoelectric device of FIG. 1 as viewed from the direction of the arrow along line II-II. 本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層の下面に下部電極層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the lower electrode layer on the lower surface of the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層に第1保護部用溝を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the groove for the 1st protection part in the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層および下部電極層の各々の下面と、第1保護部用溝内に中間層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the lower surface of each of the single crystal piezoelectric layer and the lower electrode layer, and the intermediate layer in the groove for the 1st protection part in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. .. 本発明の実施形態1に係る圧電デバイスの製造方法において、中間層の下面を削った状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state in which the lower surface of the intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、第2積層体を準備した状態を示す断面図である。It is sectional drawing which shows the state which prepared the 2nd laminated body in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、中間層の下面に第2積層体を接合させる状態を示す断面図である。It is sectional drawing which shows the state which the 2nd laminated body is bonded to the lower surface of the intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、中間層の下面に第2積層体を接合させた状態を示す断面図である。It is sectional drawing which shows the state which the 2nd laminated body was bonded to the lower surface of the intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層および第1保護部の各々の上面を削った状態を示す断面図である。It is sectional drawing which shows the state which the upper surface of each of the single crystal piezoelectric layer and the 1st protection part was shaved in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the upper electrode layer on the upper surface of the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、第1保護部から半導体層まで貫通溝を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the through groove from the 1st protection part to the semiconductor layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層に溝部を形成した状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state in which a groove is formed in a single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. 本発明の実施形態1に係る圧電デバイスの製造方法において、上部電極層上に第1外部電極を設け、下部電極層上に第2外部電極を設けた状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state in which a first external electrode is provided on an upper electrode layer and a second external electrode is provided on a lower electrode layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. 本発明の実施形態2に係る圧電デバイスの断面図である。It is sectional drawing of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層に第1保護部用溝および第2保護部用溝を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the groove for the 1st protection part and the groove for the 2nd protection part in the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層の各々の下面、第1保護部用溝内および第2保護部用溝内の各々に第1中間層を設けた状態を示す断面図である。In the method for manufacturing a piezoelectric device according to the second embodiment of the present invention, a first intermediate layer is provided on the lower surface of each of the single crystal piezoelectric layers, in the groove for the first protective portion, and in the groove for the second protective portion. It is sectional drawing which shows the state. 本発明の実施形態2に係る圧電デバイスの製造方法において、第1中間層の下面を削った状態を示す断面図である。It is sectional drawing which shows the state which the lower surface of the 1st intermediate layer was shaved in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第1中間層の下面に下部電極層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the lower electrode layer on the lower surface of the 1st intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第1中間層および下部電極層の各々の下面に、第2中間層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the 2nd intermediate layer on the lower surface of each of the 1st intermediate layer and the lower electrode layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第2中間層の下面を削った状態を示す断面図である。It is sectional drawing which shows the state which the lower surface of the 2nd intermediate layer was shaved in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第2中間層の下面に第2積層体を接合させる状態を示す断面図である。It is sectional drawing which shows the state which the 2nd laminated body is bonded to the lower surface of the 2nd intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第2中間層の下面に第2積層体を接合させた状態を示す断面図である。It is sectional drawing which shows the state which the 2nd laminated body was bonded to the lower surface of the 2nd intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層、第1保護部および第2保護部の各々の上面を削った状態を示す断面図である。It is sectional drawing which shows the state which the upper surface of each of the single crystal piezoelectric layer, the 1st protection part and the 2nd protection part was cut in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the upper electrode layer on the upper surface of the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第1保護部から半導体層まで貫通溝を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the through groove from the 1st protection part to the semiconductor layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、第2保護部から第1中間層まで溝部を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the groove part from the 2nd protection part to the 1st intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る圧電デバイスの製造方法において、上部電極層上に第1外部電極を設け、下部電極層上に第2外部電極を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the 1st external electrode on the upper electrode layer, and provided the 2nd external electrode on the lower electrode layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 2 of this invention. 本発明の実施形態3に係る圧電デバイスの断面図である。It is sectional drawing of the piezoelectric device which concerns on Embodiment 3 of this invention. 本発明の実施形態3に係る圧電デバイスの製造方法において、第1中間層を下側から削った状態を示す断面図である。It is sectional drawing which shows the state which the 1st intermediate layer was cut from the lower side in the manufacturing method of the piezoelectric device which concerns on Embodiment 3 of this invention. 本発明の実施形態3に係る圧電デバイスの製造方法において、単結晶圧電体層および第2保護部の下面に下部電極層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the lower electrode layer on the lower surface of the single crystal piezoelectric layer and the 2nd protection part in the manufacturing method of the piezoelectric device which concerns on Embodiment 3 of this invention. 本発明の実施形態3に係る圧電デバイスの製造方法において、第1保護部および単結晶圧電体層の各々の下面に第2中間層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the 2nd intermediate layer on the lower surface of each of the 1st protection part and the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 3 of this invention. 本発明の実施形態4に係る圧電デバイスの断面図である。It is sectional drawing of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法において、第1中間層の下面に第2積層体を接合させる状態を示す断面図である。It is sectional drawing which shows the state which the 2nd laminated body is bonded to the lower surface of the 1st intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法おいて、第1中間層の下面に第2積層体を接合させた状態を示す断面図である。It is sectional drawing which shows the state which the 2nd laminated body was bonded to the lower surface of the 1st intermediate layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法において、単結晶圧電体層、第1保護部および第2保護部の各々の上面を削った状態を示す断面図である。It is sectional drawing which shows the state which the upper surface of each of the single crystal piezoelectric layer, the 1st protection part and the 2nd protection part was cut in the manufacturing method of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。It is sectional drawing which shows the state which provided the upper electrode layer on the upper surface of the single crystal piezoelectric layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法において、第1保護部から半導体層まで貫通溝を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the through groove from the 1st protection part to the semiconductor layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法において、第2保護部から半導体層まで溝部を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the groove part from the 2nd protection part to the semiconductor layer in the manufacturing method of the piezoelectric device which concerns on Embodiment 4 of this invention. 本発明の実施形態4に係る圧電デバイスの製造方法において、上部電極層上に第1外部電極を設け、下部電極層である半導体層上に第2外部電極を設けた状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state in which a first external electrode is provided on an upper electrode layer and a second external electrode is provided on a semiconductor layer which is a lower electrode layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention. ..
 以下、本発明の各実施形態に係る圧電デバイスについて図面を参照して説明する。以下の実施形態の説明においては、図中の同一または相当部分には同一符号を付して、その説明は繰り返さない。また、以下の説明において、上または下の概念に言及する際には、絶対的な上または下を意味するとは限らず、図示された姿勢の中での相対的な上または下を意味する場合がある。 Hereinafter, the piezoelectric device according to each embodiment of the present invention will be described with reference to the drawings. In the following description of the embodiment, the same or corresponding parts in the drawings are designated by the same reference numerals, and the description thereof will not be repeated. Also, in the following description, when referring to the concept of up or down, it does not necessarily mean absolute up or down, but rather relative up or down in the illustrated posture. There is.
 (実施形態1)
 図1は、本発明の実施形態1に係る圧電デバイスの平面図である。図2は、図1の圧電デバイスをII-II線矢印方向から見た断面図である。
(Embodiment 1)
FIG. 1 is a plan view of the piezoelectric device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the piezoelectric device of FIG. 1 as viewed from the direction of the arrow along line II-II.
 図1および図2に示すように、本発明の実施形態1に係る圧電デバイス100は、基部110と、メンブレン部120とを備えている。 As shown in FIGS. 1 and 2, the piezoelectric device 100 according to the first embodiment of the present invention includes a base portion 110 and a membrane portion 120.
 図2に示すように、本実施形態において、基部110は、下側基部110aと、下側基部110aの上側に位置する上側基部110bとを含んでいる。基部110は、上側主面111、および、上側主面111とは反対側に位置する下側主面112を有している。本実施形態において、上側基部110bの上面が上側主面111であり、下側基部110aの下面が下側主面112である。基部110には、上下方向に下側基部110aと上側基部110bとを貫通する凹部113が形成されている。 As shown in FIG. 2, in the present embodiment, the base 110 includes a lower base 110a and an upper base 110b located above the lower base 110a. The base 110 has an upper main surface 111 and a lower main surface 112 located on the opposite side of the upper main surface 111. In the present embodiment, the upper surface of the upper base 110b is the upper main surface 111, and the lower surface of the lower base 110a is the lower main surface 112. The base 110 is formed with a recess 113 that penetrates the lower base 110a and the upper base 110b in the vertical direction.
 基部110を構成する材料は特に限定されない。本実施形態において、下側基部110aはSiで構成されている。上側基部110bはSiO2で構成されている。 The material constituting the base 110 is not particularly limited. In this embodiment, the lower base 110a is made of Si. The upper base 110b is made of SiO 2 .
 基部110の上側主面111上には、複数の層130が積層されている。メンブレン部120は、上記複数の層のうち、凹部113の上側に位置する部分である。すなわち、メンブレン部120は、複数の層130からなる。複数の層130は、メンブレン部120から、基部110の上側に延在している。 A plurality of layers 130 are laminated on the upper main surface 111 of the base 110. The membrane portion 120 is a portion of the plurality of layers located above the recess 113. That is, the membrane portion 120 is composed of a plurality of layers 130. The plurality of layers 130 extend from the membrane portion 120 to the upper side of the base portion 110.
 メンブレン部120は、基部110の凹部113の上側に位置しているため、基部110に重なっていない。すなわち、メンブレン部120は、基部110に間接的に支持されて、基部110より上側に位置している。 Since the membrane portion 120 is located above the recess 113 of the base 110, it does not overlap the base 110. That is, the membrane portion 120 is indirectly supported by the base portion 110 and is located above the base portion 110.
 メンブレン部120には、上下方向に貫通する貫通溝121が設けられている。本実施形態において、貫通溝121は、上端から下端まで幅が略一定である。貫通溝121の幅は、10μm以下であることが好ましい。 The membrane portion 120 is provided with a through groove 121 penetrating in the vertical direction. In the present embodiment, the width of the through groove 121 is substantially constant from the upper end to the lower end. The width of the through groove 121 is preferably 10 μm or less.
 本実施形態において、メンブレン部120は、単結晶圧電体層140と、上部電極層150と、下部電極層160と、中間層170と、半導体層180と、第1保護部190とを含んでいる。すなわち、メンブレン部120を構成する複数の層130は、単結晶圧電体層140と、上部電極層150と、下部電極層160と、中間層170と、半導体層180と、第1保護部190とを有している。 In the present embodiment, the membrane portion 120 includes a single crystal piezoelectric layer 140, an upper electrode layer 150, a lower electrode layer 160, an intermediate layer 170, a semiconductor layer 180, and a first protective portion 190. .. That is, the plurality of layers 130 constituting the membrane portion 120 include the single crystal piezoelectric layer 140, the upper electrode layer 150, the lower electrode layer 160, the intermediate layer 170, the semiconductor layer 180, and the first protective portion 190. have.
 単結晶圧電体層140は、基部110より上側に位置している。単結晶圧電体層140は、第1断面141と第2断面142とを有している。第1断面141同士の距離は、上部電極層150側から下部電極層160側に行くにしたがって長くなっている。第2断面142同士の距離は、上部電極層150側から下部電極層160側まで略一定である。 The single crystal piezoelectric layer 140 is located above the base 110. The single crystal piezoelectric layer 140 has a first cross section 141 and a second cross section 142. The distance between the first cross sections 141 increases from the upper electrode layer 150 side to the lower electrode layer 160 side. The distance between the second cross sections 142 is substantially constant from the upper electrode layer 150 side to the lower electrode layer 160 side.
 本実施形態において、単結晶圧電体層140には、単結晶圧電体層140を上下方向に貫通する溝部143が形成されている。第2断面142は、溝部143に面している。 In the present embodiment, the single crystal piezoelectric layer 140 is formed with a groove portion 143 that penetrates the single crystal piezoelectric layer 140 in the vertical direction. The second cross section 142 faces the groove portion 143.
 単結晶圧電体層140の厚さは、たとえば5μm以下である。また、単結晶圧電体層140は、タンタル酸リチウムまたはニオブ酸リチウムで構成されている。タンタル酸リチウムまたはニオブ酸リチウムで構成された単結晶圧電体層140は、分極状態が一様であり、単結晶圧電体層140の基部110側の面に平行な方向を面内方向としたときに、ある特定の面内方向および面外方向に劈開面を形成しつつ劈開しやすいという性質を有している。 The thickness of the single crystal piezoelectric layer 140 is, for example, 5 μm or less. The single crystal piezoelectric layer 140 is made of lithium tantalate or lithium niobate. The single crystal piezoelectric layer 140 composed of lithium tantalate or lithium niobate has a uniform polarization state, and the direction parallel to the plane on the base 110 side of the single crystal piezoelectric layer 140 is the in-plane direction. In addition, it has the property of being easy to cleave while forming a cleavage plane in a specific in-plane direction and out-of-plane direction.
 上部電極層150は、当該単結晶圧電体層140の上側に配置されている。上部電極層150と単結晶圧電体層140との間に、密着層が配置されていてもよい。 The upper electrode layer 150 is arranged above the single crystal piezoelectric layer 140. An adhesion layer may be arranged between the upper electrode layer 150 and the single crystal piezoelectric layer 140.
 下部電極層160は、メンブレン部120において、単結晶圧電体層140を介して、上部電極層150の少なくとも一部に対向するように配置されている。本実施形態においては、下部電極層160は、単結晶圧電体層140の下側に配置されている。下部電極層160と単結晶圧電体層140との間には、密着層が配置されていてもよい。 The lower electrode layer 160 is arranged in the membrane portion 120 so as to face at least a part of the upper electrode layer 150 via the single crystal piezoelectric layer 140. In the present embodiment, the lower electrode layer 160 is arranged below the single crystal piezoelectric layer 140. An adhesion layer may be arranged between the lower electrode layer 160 and the single crystal piezoelectric layer 140.
 本実施形態においては、下部電極層160はエッチングストップ層161を有している。エッチングストップ層161は、下部電極層160の基部110側の部分に位置している。なお、エッチングストップ層161は、下部電極層160の基部110側とは反対側の部分に位置していてもよい。 In the present embodiment, the lower electrode layer 160 has an etching stop layer 161. The etching stop layer 161 is located at a portion of the lower electrode layer 160 on the base 110 side. The etching stop layer 161 may be located at a portion of the lower electrode layer 160 opposite to the base 110 side.
 下部電極層160は、基部110の上方において、単結晶圧電体層140に形成された溝部143の下方に位置するように配置されている。下部電極層160は、溝部143の下方を覆うように位置している。本実施形態においては、下部電極層160のうちエッチングストップ層161が、溝部143の下方を覆うように位置している。 The lower electrode layer 160 is arranged above the base 110 and below the groove 143 formed in the single crystal piezoelectric layer 140. The lower electrode layer 160 is located so as to cover the lower part of the groove portion 143. In the present embodiment, the etching stop layer 161 of the lower electrode layer 160 is located so as to cover the lower part of the groove portion 143.
 なお、図2においては、上部電極層150の有する複数の断面が示されているが、上下方向から見たときに、上部電極層150は単結晶圧電体層140の上側において連続して形成されている。下部電極層160も、上下方向から見たときには、単結晶圧電体層140の下側において連続して形成されている。 Although a plurality of cross sections of the upper electrode layer 150 are shown in FIG. 2, the upper electrode layer 150 is continuously formed on the upper side of the single crystal piezoelectric layer 140 when viewed from above and below. ing. The lower electrode layer 160 is also continuously formed under the single crystal piezoelectric layer 140 when viewed from above and below.
 本実施形態において、上下方向から見たときに、上部電極層150および下部電極層160の各々の外縁は、単結晶圧電体層140の劈開方向に対して非平行に位置していることが好ましい。また、本実施形態に係る圧電デバイス100が、Siで構成される半導体層を備えている場合には、上部電極層150および下部電極層160の各々の外縁は、上記半導体層の劈開方向に対して非平行に位置していることが好ましい。 In the present embodiment, when viewed from the vertical direction, the outer edges of the upper electrode layer 150 and the lower electrode layer 160 are preferably located non-parallel to the cleavage direction of the single crystal piezoelectric layer 140. .. Further, when the piezoelectric device 100 according to the present embodiment includes a semiconductor layer made of Si, the outer edges of the upper electrode layer 150 and the lower electrode layer 160 are set with respect to the opening direction of the semiconductor layer. It is preferable that they are located non-parallel.
 本実施形態において、上部電極層150および下部電極層160の各々は、Pt、NiまたはAuなどの導電性材料で構成されている。エッチングストップ層161は、導電性を有し、かつ、単結晶圧電体140層をエッチングする際においてエッチングされない材料であることが好ましい。エッチングストップ層161、たとえばNiで構成される。密着層の材料は、導電性および密着性を有する材料であれば特に限定されない。密着層は、たとえばTi、Cr、NiまたはNiCr合金で構成される。単結晶圧電体層140がニオブ酸リチウムで構成されている場合には、密着層は、Tiと比較して単結晶圧電体層140へ原子拡散しにくいNiCr合金で構成されていることが好ましい。 In the present embodiment, each of the upper electrode layer 150 and the lower electrode layer 160 is made of a conductive material such as Pt, Ni, or Au. The etching stop layer 161 is preferably a material that has conductivity and is not etched when the single crystal piezoelectric 140 layer is etched. It is composed of an etching stop layer 161 such as Ni. The material of the adhesion layer is not particularly limited as long as it is a material having conductivity and adhesion. The adhesion layer is composed of, for example, a Ti, Cr, Ni or NiCr alloy. When the single crystal piezoelectric layer 140 is made of lithium niobate, the adhesion layer is preferably made of a NiCr alloy that is less likely to diffuse atoms into the single crystal piezoelectric layer 140 as compared with Ti.
 本実施形態に係る圧電デバイス100は、第1外部電極155および第2外部電極165をさらに備えている。第1外部電極155は、上部電極層150と電気的に接続されており、具体的には、基部110の上方において上部電極層150上に配置されている。第2外部電極165は、下部電極層160と電気的に接続されている。本実施形態においては、第2外部電極165は、下部電極層160上と、溝部143の内側面である第2断面142上と、単結晶圧電体層140の上面とにわたって設けられている。第1外部電極155および第2外部電極165の各々を構成する材料は、金属などの導電性を有する材料であれば、特に限定されない。 The piezoelectric device 100 according to the present embodiment further includes a first external electrode 155 and a second external electrode 165. The first external electrode 155 is electrically connected to the upper electrode layer 150, and specifically, is arranged on the upper electrode layer 150 above the base 110. The second external electrode 165 is electrically connected to the lower electrode layer 160. In the present embodiment, the second external electrode 165 is provided on the lower electrode layer 160, on the second cross section 142 which is the inner side surface of the groove portion 143, and on the upper surface of the single crystal piezoelectric layer 140. The material constituting each of the first external electrode 155 and the second external electrode 165 is not particularly limited as long as it is a conductive material such as metal.
 中間層170は、単結晶圧電体層140より下方に配置されている。本実施形態においては、中間層170は、下部電極層160の下面、単結晶圧電体層140の下面のうち下部電極層160に覆われていない部分、および第1保護部190の下面の各々と接するように設けられている。中間層170は、たとえばSiO2などの誘電体層で構成されている。 The intermediate layer 170 is arranged below the single crystal piezoelectric layer 140. In the present embodiment, the intermediate layer 170 includes the lower surface of the lower electrode layer 160, the lower surface of the single crystal piezoelectric layer 140 that is not covered by the lower electrode layer 160, and the lower surface of the first protective portion 190. It is provided so that it touches. The intermediate layer 170 is composed of a dielectric layer such as SiO 2.
 半導体層180は、中間層170の下側に配置されている。半導体層180は、中間層170の下面と接するように設けられている。半導体層180は、金属層を介して中間層170の下面に設けられていてもよい。本実施形態においては、メンブレン部120において、半導体層180の下面が凹部113に露出している。半導体層180は、たとえばSiで構成されている。 The semiconductor layer 180 is arranged below the intermediate layer 170. The semiconductor layer 180 is provided so as to be in contact with the lower surface of the intermediate layer 170. The semiconductor layer 180 may be provided on the lower surface of the intermediate layer 170 via the metal layer. In the present embodiment, in the membrane portion 120, the lower surface of the semiconductor layer 180 is exposed in the recess 113. The semiconductor layer 180 is made of, for example, Si.
 第1保護部190は、第1断面141上に位置している。第1保護部190には、貫通溝121が設けられている。すなわち、単結晶圧電体層140の貫通溝121と面する第1断面141は、貫通溝121を間に挟んで位置する第1保護部190に覆われている。 The first protection unit 190 is located on the first cross section 141. The first protective portion 190 is provided with a through groove 121. That is, the first cross section 141 of the single crystal piezoelectric layer 140 facing the through groove 121 is covered with the first protective portion 190 located with the through groove 121 in between.
 本実施形態において、第1保護部190は、中間層170と一体の部材で構成されている。すなわち、第1保護部190の下面が、中間層170と互いに接続している。上記の構成により、第1保護部190と中間層170とを同時に積層することができ、圧電デバイス100の製造工程を簡素化できる。また、第1保護部190が中間層170を構成する材料と同一の材料で構成される場合には、第1保護部190の下面と中間層170との間に結晶境界が生じることを抑制できる。よって、結晶境界からクラックが生じることを抑制できる。第1保護部190は、たとえばSiO2などの誘電体材料で構成されている。 In the present embodiment, the first protection unit 190 is composed of a member integrated with the intermediate layer 170. That is, the lower surface of the first protective portion 190 is connected to the intermediate layer 170. With the above configuration, the first protective portion 190 and the intermediate layer 170 can be laminated at the same time, and the manufacturing process of the piezoelectric device 100 can be simplified. Further, when the first protective portion 190 is made of the same material as the material constituting the intermediate layer 170, it is possible to suppress the formation of a crystal boundary between the lower surface of the first protective portion 190 and the intermediate layer 170. .. Therefore, it is possible to suppress the occurrence of cracks from the crystal boundary. The first protection unit 190 is made of a dielectric material such as SiO 2.
 上記の構成により、本実施形態に係る圧電デバイス100においては、上部電極層150と下部電極層160との間に電圧が印加されることによって、単結晶圧電体層140が伸縮する。一方、メンブレン部120においては、単結晶圧電体層140以外の部材は電圧の印加によって変形しない。よって、上記電圧の印加による単結晶圧電体層140の伸縮に応じて、メンブレン部120が上下に屈曲振動する。 With the above configuration, in the piezoelectric device 100 according to the present embodiment, the single crystal piezoelectric layer 140 expands and contracts when a voltage is applied between the upper electrode layer 150 and the lower electrode layer 160. On the other hand, in the membrane portion 120, the members other than the single crystal piezoelectric layer 140 are not deformed by the application of voltage. Therefore, the membrane portion 120 bends and vibrates up and down in response to the expansion and contraction of the single crystal piezoelectric layer 140 due to the application of the voltage.
 以下、本発明の実施形態1に係る圧電デバイスの製造方法について説明する。
 図3は、本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層の下面に下部電極層を設けた状態を示す断面図である。図3に示すように、単結晶圧電体層140の下方に下部電極層160を配置する。このとき、単結晶圧電体層140の厚さは、たとえば200μm以上500μm以下である。本実施形態においては、リフトオフ法、めっき法、または、エッチング法などにより、単結晶圧電体層140の下面に、下部電極層160を設ける。より具体的には、下部電極層160のエッチングストップ層161以外の部分を設けた後、エッチングストップ層161を設ける。なお、エッチングストップ層161を設けた後、下部電極層160のエッチングストップ層161以外の部分を設けてもよい。
Hereinafter, a method for manufacturing the piezoelectric device according to the first embodiment of the present invention will be described.
FIG. 3 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 3, the lower electrode layer 160 is arranged below the single crystal piezoelectric layer 140. At this time, the thickness of the single crystal piezoelectric layer 140 is, for example, 200 μm or more and 500 μm or less. In the present embodiment, the lower electrode layer 160 is provided on the lower surface of the single crystal piezoelectric layer 140 by a lift-off method, a plating method, an etching method, or the like. More specifically, after providing the portion of the lower electrode layer 160 other than the etching stop layer 161, the etching stop layer 161 is provided. After the etching stop layer 161 is provided, a portion of the lower electrode layer 160 other than the etching stop layer 161 may be provided.
 下部電極層160は、エピタキシャル成長により設けることが好ましい。これにより、単結晶圧電体層140の駆動によるメンブレン部120の疲労特性が向上する。 The lower electrode layer 160 is preferably provided by epitaxial growth. As a result, the fatigue characteristics of the membrane portion 120 due to the driving of the single crystal piezoelectric layer 140 are improved.
 図4は、本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層に第1保護部用溝を形成した状態を示す断面図である。図4に示すように、エッチング法などにより、単結晶圧電体層140の下側から、単結晶圧電体層140の下面に、第1保護部用溝141Aを形成する。第1保護部用溝141Aの深さは、たとえば10μm程度であればよい。 FIG. 4 is a cross-sectional view showing a state in which a groove for a first protective portion is formed in a single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 4, a groove 141A for the first protective portion is formed on the lower surface of the single crystal piezoelectric layer 140 from the lower side of the single crystal piezoelectric layer 140 by an etching method or the like. The depth of the groove 141A for the first protective portion may be, for example, about 10 μm.
 図5は、本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層および下部電極層の各々の下面と、第1保護部用溝内に中間層を設けた状態を示す断面図である。図4および図5に示すように、CVD(Chemical Vapor Deposition)法またはPVD(Physical Vapor Deposition)法などにより、第1保護部用溝141A内、下部電極層160および単結晶圧電体層140の各々の下面に、中間層170を設ける。このとき、第1保護部用溝141A内を埋めるように、中間層170を設ける。 FIG. 5 shows a state in which the lower surfaces of the single crystal piezoelectric layer and the lower electrode layer and the intermediate layer are provided in the groove for the first protective portion in the method for manufacturing the piezoelectric device according to the first embodiment of the present invention. It is a sectional view. As shown in FIGS. 4 and 5, each of the lower electrode layer 160 and the single crystal piezoelectric layer 140 in the groove 141A for the first protective portion by the CVD (Chemical Vapor Deposition) method or the PVD (Physical Vapor Deposition) method or the like. An intermediate layer 170 is provided on the lower surface of the. At this time, the intermediate layer 170 is provided so as to fill the inside of the groove 141A for the first protective portion.
 図6は、本発明の実施形態1に係る圧電デバイスの製造方法において、中間層の下面を削った状態を示す断面図である。図6に示すように、中間層170の下面を化学機械研磨(CMP:Chemical Mechanical Polishing)などにより、平坦にする。このようにして、第1保護部用溝141Aを、中間層170と同一の部材で構成された第1保護部190で埋める。 FIG. 6 is a cross-sectional view showing a state in which the lower surface of the intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 6, the lower surface of the intermediate layer 170 is flattened by chemical mechanical polishing (CMP) or the like. In this way, the groove 141A for the first protective portion is filled with the first protective portion 190 made of the same member as the intermediate layer 170.
 本実施形態においては、以上の工程により、少なくとも単結晶圧電体層140を含む第1積層体10を形成する。具体的には、本実施形態における第1積層体10は、下部電極層160、中間層170および第1保護部190をさらに含んでいる。 In the present embodiment, the first laminated body 10 including at least the single crystal piezoelectric layer 140 is formed by the above steps. Specifically, the first laminated body 10 in the present embodiment further includes a lower electrode layer 160, an intermediate layer 170, and a first protective portion 190.
 図7は、本発明の実施形態1に係る圧電デバイスの製造方法において、第2積層体を準備した状態を示す断面図である。図8は、本発明の実施形態1に係る圧電デバイスの製造方法において、中間層の下面に第2積層体を接合させる状態を示す断面図である。図9は、本発明の実施形態1に係る圧電デバイスの製造方法において、中間層の下面に第2積層体を接合させた状態を示す断面図である。 FIG. 7 is a cross-sectional view showing a state in which a second laminated body is prepared in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the intermediate layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention.
 図7から図9に示すように、第1積層体10の下側に、第2積層体20を接合する。第2積層体20は、凹部113が形成されていない基部110と、基部110の上側主面111上に接合された半導体層180とから構成されている。本実施形態において、第2積層体20はSOI(Silicon on Insulator)基板である。 As shown in FIGS. 7 to 9, the second laminated body 20 is joined to the lower side of the first laminated body 10. The second laminated body 20 is composed of a base portion 110 in which the recess 113 is not formed, and a semiconductor layer 180 joined on the upper main surface 111 of the base portion 110. In the present embodiment, the second laminated body 20 is an SOI (Silicon on Insulator) substrate.
 図10は、本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層および第1保護部の各々の上面を削った状態を示す断面図である。図10に示すように、単結晶圧電体層140の厚さを調整する。具体的には、単結晶圧電体層140および第1保護部190の各々の上面をCMPなどにより削って、単結晶圧電体層140を所望の厚さにするとともに、第1保護部190を露出させる。この場合、単結晶圧電体層140の厚さは、電圧の印加による単結晶圧電体層140の所望の伸縮量が得られるように調整される。 FIG. 10 is a cross-sectional view showing a state in which the upper surfaces of the single crystal piezoelectric layer and the first protective portion are scraped in the method for manufacturing the piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 10, the thickness of the single crystal piezoelectric layer 140 is adjusted. Specifically, the upper surfaces of the single crystal piezoelectric layer 140 and the first protective portion 190 are each scraped by CMP or the like to make the single crystal piezoelectric layer 140 a desired thickness, and the first protective portion 190 is exposed. Let me. In this case, the thickness of the single crystal piezoelectric layer 140 is adjusted so that a desired amount of expansion and contraction of the single crystal piezoelectric layer 140 can be obtained by applying a voltage.
 なお、単結晶圧電体層140の上面側に、予めイオン注入することにより、剥離層を形成していてもよい。この場合、単結晶圧電体層140の上面をCMPなどにより削る前に、剥離層を剥離させることにより、単結晶圧電体層140の厚さ調整が容易になる。上記剥離層をCMPなどにより削ってもよい。 A release layer may be formed by implanting ions in advance on the upper surface side of the single crystal piezoelectric layer 140. In this case, the thickness of the single crystal piezoelectric layer 140 can be easily adjusted by peeling the peeling layer before the upper surface of the single crystal piezoelectric layer 140 is scraped by CMP or the like. The peeling layer may be scraped by CMP or the like.
 図11は、本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。図11に示すように、リフトオフ法(フォトリソグラフィ法)、めっき法、または、エッチング法などにより、単結晶圧電体層140の上側に、少なくとも一部が単結晶圧電体層140を介して下部電極層160と対向する、上部電極層150を配置する。本実施形態においては、リフトオフ法(フォトリソグラフィ法)により、上部電極層150をパターニングする。 FIG. 11 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 11, a lower electrode is formed on the upper side of the single crystal piezoelectric layer 140 by a lift-off method (photolithography method), a plating method, an etching method, or the like, at least partially via the single crystal piezoelectric layer 140. The upper electrode layer 150 is arranged so as to face the layer 160. In the present embodiment, the upper electrode layer 150 is patterned by the lift-off method (photolithography method).
 上部電極層150は、エピタキシャル成長により設けることが好ましい。これにより、単結晶圧電体層140の駆動によるメンブレン部120の疲労特性が向上する。 The upper electrode layer 150 is preferably provided by epitaxial growth. As a result, the fatigue characteristics of the membrane portion 120 due to the driving of the single crystal piezoelectric layer 140 are improved.
 図12は、本発明の実施形態1に係る圧電デバイスの製造方法において、第1保護部から半導体層まで貫通溝を形成した状態を示す断面図である。図12に示すように、上側からエッチングすることにより、第1保護部190に、貫通溝121を形成する。具体的には、第1保護部190を分割するように、少なくとも第1積層体10を上下方向に貫通する貫通溝121を形成する。本実施形態においては、貫通溝121は、半導体層180をさらに貫通するように形成されている。貫通溝121は、半導体層180の下面より下方に位置するように形成されてもよい。 FIG. 12 is a cross-sectional view showing a state in which a through groove is formed from the first protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 12, a through groove 121 is formed in the first protective portion 190 by etching from the upper side. Specifically, a through groove 121 that penetrates at least the first laminated body 10 in the vertical direction is formed so as to divide the first protective portion 190. In the present embodiment, the through groove 121 is formed so as to further penetrate the semiconductor layer 180. The through groove 121 may be formed so as to be located below the lower surface of the semiconductor layer 180.
 図13は、本発明の実施形態1に係る圧電デバイスの製造方法において、単結晶圧電体層に溝部を形成した状態を示す断面図である。図13に示すように、基部110の上方において単結晶圧電体層140をエッチングすることにより、溝部143を形成する。このとき、図13に示すように、下部電極層160のうちエッチングストップ層161の上側の部分がエッチングされてもよい。 FIG. 13 is a cross-sectional view showing a state in which a groove is formed in the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. As shown in FIG. 13, the groove portion 143 is formed by etching the single crystal piezoelectric layer 140 above the base portion 110. At this time, as shown in FIG. 13, the upper portion of the etching stop layer 161 of the lower electrode layer 160 may be etched.
 図14は、本発明の実施形態1に係る圧電デバイスの製造方法において、上部電極層上に第1外部電極を設け、下部電極層上に第2外部電極を設けた状態を示す断面図である。図14に示すように、リフトオフ法、めっき法またはエッチング法などにより、上部電極層150上に第1外部電極155を設け、下部電極層160上に第2外部電極165を設ける。本実施形態においては、下部電極層160のエッチングストップ層161上に、第2外部電極165を設ける。 FIG. 14 is a cross-sectional view showing a state in which the first external electrode is provided on the upper electrode layer and the second external electrode is provided on the lower electrode layer in the method for manufacturing a piezoelectric device according to the first embodiment of the present invention. .. As shown in FIG. 14, a first external electrode 155 is provided on the upper electrode layer 150 and a second external electrode 165 is provided on the lower electrode layer 160 by a lift-off method, a plating method, an etching method, or the like. In the present embodiment, the second external electrode 165 is provided on the etching stop layer 161 of the lower electrode layer 160.
 最後に、図14および図2に示すように、凹部113を形成する。具体的には、上下方向から見たときに、上部電極層150と、下部電極層160とが単結晶圧電体層140を介して対向している部分、および、貫通溝121が位置する部分と重なるように、第2積層体20の下側に開口して貫通溝121と連通する凹部113を形成する。本実施形態においては、第2積層体20に対して、深掘反応性イオンエッチング(Deep RIE:Deep Reactive Ion Etching)することにより、基部110に凹部113を形成する。 Finally, as shown in FIGS. 14 and 2, the recess 113 is formed. Specifically, when viewed from the vertical direction, the upper electrode layer 150 and the lower electrode layer 160 face each other via the single crystal piezoelectric layer 140, and the portion where the through groove 121 is located. A recess 113 that opens to the lower side of the second laminated body 20 and communicates with the through groove 121 is formed so as to overlap each other. In the present embodiment, the second laminated body 20 is subjected to deep reactive ion etching (Deep Reactive Ion Etching) to form a recess 113 in the base 110.
 上記の工程により、図2に示すような本発明の実施形態1に係る圧電デバイス100が製造される。 By the above steps, the piezoelectric device 100 according to the first embodiment of the present invention as shown in FIG. 2 is manufactured.
 上記のように、本発明の実施形態1に係る圧電デバイス100において、メンブレン部120には、上下方向に貫通する貫通溝121が設けられている。単結晶圧電体層140の貫通溝121と面する第1断面141は、貫通溝121を間に挟んで位置する第1保護部190に覆われている。これにより、圧電デバイス100の耐環境性を向上できる。 As described above, in the piezoelectric device 100 according to the first embodiment of the present invention, the membrane portion 120 is provided with a through groove 121 penetrating in the vertical direction. The first cross section 141 of the single crystal piezoelectric layer 140 facing the through groove 121 is covered with a first protective portion 190 located with the through groove 121 in between. Thereby, the environmental resistance of the piezoelectric device 100 can be improved.
 本実施形態においては、第1断面141同士の距離は、上部電極層150側から下部電極層160側に行くにしたがって長くなっている。 In the present embodiment, the distance between the first cross sections 141 increases from the upper electrode layer 150 side to the lower electrode layer 160 side.
 これにより、第1断面同士の距離が一定である場合と比較して、単結晶圧電体層140の下側から第1保護部190を積層させることで、被覆性の良い第1保護部190を設けることができる。ひいては、単結晶圧電体層140において、第1保護部190による内部応力が緩和されるため、クラックが発生しにくくなり、圧電デバイス100の信頼性が向上する。 As a result, as compared with the case where the distance between the first cross sections is constant, the first protective portion 190 having good covering property can be obtained by laminating the first protective portion 190 from the lower side of the single crystal piezoelectric layer 140. Can be provided. As a result, in the single crystal piezoelectric layer 140, the internal stress caused by the first protective portion 190 is relaxed, so that cracks are less likely to occur and the reliability of the piezoelectric device 100 is improved.
 本発明の実施形態1に係る圧電デバイス100の製造方法は、単結晶圧電体層140の下方に下部電極層160を配置する工程と、単結晶圧電体層140に、上下方向に貫通する第1保護部用溝141Aを形成する工程と、第1保護部用溝141Aを第1保護部190で埋める工程と、少なくとも単結晶圧電体層140を含む第1積層体10を形成する工程と、第1積層体10の下側に、第2積層体20を接合する工程と、単結晶圧電体層140の厚さを調整する工程と、単結晶圧電体層140の上側に、少なくとも一部が単結晶圧電体層140を介して下部電極層160と対向する、上部電極層150を配置する工程と、貫通溝121を形成する工程と、凹部113を形成する工程とを備える工程とを備えている。貫通溝121を形成する工程においては、第1保護部190を分割するように、少なくとも第1積層体10を上下方向に貫通する貫通溝121を形成する。凹部113を形成する工程においては、上下方向から見たときに、上部電極層150と、下部電極層160とが単結晶圧電体層140を介して対向している部分、および、貫通溝121が位置する部分と重なるように、第2積層体20の下側に開口して貫通溝121と連通する凹部113を形成する。 The method for manufacturing the piezoelectric device 100 according to the first embodiment of the present invention includes a step of arranging the lower electrode layer 160 below the single crystal piezoelectric layer 140 and a first method of penetrating the single crystal piezoelectric layer 140 in the vertical direction. A step of forming the groove 141A for the protective portion, a step of filling the groove 141A for the first protective portion with the first protective portion 190, a step of forming the first laminated body 10 including at least the single crystal piezoelectric layer 140, and the first step. A step of joining the second laminated body 20 to the lower side of the 1 laminated body 10, a step of adjusting the thickness of the single crystal piezoelectric layer 140, and at least a part of the upper side of the single crystal piezoelectric layer 140. It includes a step of arranging the upper electrode layer 150 facing the lower electrode layer 160 via the crystalline piezoelectric layer 140, a step of forming a through groove 121, and a step of forming a recess 113. .. In the step of forming the through groove 121, the through groove 121 that penetrates at least the first laminated body 10 in the vertical direction is formed so as to divide the first protective portion 190. In the step of forming the recess 113, when viewed from the vertical direction, a portion where the upper electrode layer 150 and the lower electrode layer 160 face each other via the single crystal piezoelectric layer 140, and a through groove 121 are formed. A recess 113 that opens to the lower side of the second laminated body 20 and communicates with the through groove 121 is formed so as to overlap the located portion.
 これにより、圧電デバイス100の耐環境性を向上できる。さらには、貫通溝121が、難エッチング材で構成される単結晶圧電体層140よりエッチングが容易な第1保護部190を加工することで形成されるため、貫通溝121の形状を安定化することができる。 Thereby, the environmental resistance of the piezoelectric device 100 can be improved. Further, since the through groove 121 is formed by processing the first protective portion 190 which is easier to etch than the single crystal piezoelectric layer 140 made of a difficult-to-etch material, the shape of the through groove 121 is stabilized. be able to.
 (実施形態2)
 以下、本発明の実施形態2に係る圧電デバイスについて説明する。本発明の実施形態2に係る圧電デバイスは、第2保護部が設けられている点が主に、本発明の実施形態1に係る圧電デバイス100と異なる。よって、本発明の実施形態1に係る圧電デバイス100と同様である構成については説明を繰り返さない。
(Embodiment 2)
Hereinafter, the piezoelectric device according to the second embodiment of the present invention will be described. The piezoelectric device according to the second embodiment of the present invention is different from the piezoelectric device 100 according to the first embodiment of the present invention mainly in that a second protective portion is provided. Therefore, the description of the configuration similar to that of the piezoelectric device 100 according to the first embodiment of the present invention will not be repeated.
 図15は、本発明の実施形態2に係る圧電デバイスの断面図である。図15に示す圧電デバイス200の断面図は、図2に示す圧電デバイス100の断面図と同一の断面視にて図示している。 FIG. 15 is a cross-sectional view of the piezoelectric device according to the second embodiment of the present invention. The cross-sectional view of the piezoelectric device 200 shown in FIG. 15 is shown in the same cross-sectional view as the cross-sectional view of the piezoelectric device 100 shown in FIG.
 図15に示すように、本発明の実施形態2において、メンブレン部120は、下部電極層260と、単結晶圧電体層140との間に位置する中間層として第1中間層270を含んでいる。これにより、メンブレン部120内に生じる応力を緩和して、単結晶圧電体層140から下部電極層260が剥離することを抑制することができる。 As shown in FIG. 15, in the second embodiment of the present invention, the membrane portion 120 includes the first intermediate layer 270 as an intermediate layer located between the lower electrode layer 260 and the single crystal piezoelectric layer 140. .. As a result, the stress generated in the membrane portion 120 can be relaxed, and the peeling of the lower electrode layer 260 from the single crystal piezoelectric layer 140 can be suppressed.
 本実施形態に係る圧電デバイス200においては、メンブレン部120は、中間層として、第1中間層270と、第2中間層275とを含んでおり、メンブレン部120を構成する複数の層130は、中間層として、第1中間層270と、第2中間層275とを含んでいる。 In the piezoelectric device 200 according to the present embodiment, the membrane portion 120 includes a first intermediate layer 270 and a second intermediate layer 275 as intermediate layers, and the plurality of layers 130 constituting the membrane portion 120 are The intermediate layer includes a first intermediate layer 270 and a second intermediate layer 275.
 第1中間層270は、単結晶圧電体層140の下面、第1保護部190の下面、および、後述する第2保護部の下面の各々と接するように設けられている、第1中間層270は、たとえばSiO2などの誘電体層で構成されている。下部電極層260は、第1中間層270の下側に配置されている。第1保護部190は、第1中間層270と一体の部材で構成されている。 The first intermediate layer 270 is provided so as to be in contact with each of the lower surface of the single crystal piezoelectric layer 140, the lower surface of the first protective portion 190, and the lower surface of the second protective portion described later. Is composed of a dielectric layer such as SiO 2. The lower electrode layer 260 is arranged below the first intermediate layer 270. The first protective portion 190 is composed of a member integrated with the first intermediate layer 270.
 第2中間層275は、下部電極層260の下面、第1中間層270の下面のうち下部電極層260に覆われていない部分の各々と接するように設けられている。第2中間層275は、第1中間層270を構成する材料と同じ材料で構成されていることが好ましい。第2中間層275は、たとえばSiO2などの誘電体層で構成されている。本実施形態において、半導体層180は、第1中間層270の下面と接するように設けられている。 The second intermediate layer 275 is provided so as to be in contact with each of the lower surface of the lower electrode layer 260 and the lower surface of the first intermediate layer 270 that are not covered by the lower electrode layer 260. The second intermediate layer 275 is preferably made of the same material as the material constituting the first intermediate layer 270. The second intermediate layer 275 is composed of a dielectric layer such as SiO 2. In the present embodiment, the semiconductor layer 180 is provided so as to be in contact with the lower surface of the first intermediate layer 270.
 図15に示すように、本発明の実施形態2に係る圧電デバイス200においては、単結晶圧電体層140は、基部110の上方において、溝部143を間に挟んで互いに面する第2断面242をさらに有している。第2断面242は、溝部143を間に挟んで位置する第2保護部291に覆われている。下部電極層260は、第2保護部291の下方に位置している。第2外部電極165は、下部電極層260上と、溝部143の内側面と、第2保護部291の上側とにわたって設けられており、かつ、単結晶圧電体層140とは離間している。 As shown in FIG. 15, in the piezoelectric device 200 according to the second embodiment of the present invention, the single crystal piezoelectric layer 140 has a second cross section 242 above the base 110 and facing each other with a groove 143 in between. I have more. The second cross section 242 is covered with a second protective portion 291 located with the groove portion 143 in between. The lower electrode layer 260 is located below the second protective portion 291. The second external electrode 165 is provided on the lower electrode layer 260, the inner side surface of the groove portion 143, and the upper side of the second protective portion 291 and is separated from the single crystal piezoelectric layer 140.
 これにより、第2外部電極165を構成する金属原子が、単結晶圧電体層140内に拡散することを抑制することができる。たとえば、第2外部電極165がTiで構成されており、単結晶圧電体層140が、ニオブ酸リチウムで構成されている場合であっても、上記の構成により、Ti原子が単結晶圧電体層140内に拡散することを抑制できる。 As a result, it is possible to prevent the metal atoms constituting the second external electrode 165 from diffusing into the single crystal piezoelectric layer 140. For example, even when the second external electrode 165 is made of Ti and the single crystal piezoelectric layer 140 is made of lithium niobate, the Ti atom is a single crystal piezoelectric layer due to the above configuration. It is possible to suppress the diffusion within 140.
 すなわち、本実施形態においては、溝部143は、単結晶圧電体層140ではなく第2保護部291に形成されている。第2断面242は、溝部143に露出していない。本実施形態において、溝部143は、下部電極層260の上面にまで達するように形成されている。第2断面242同士の距離は、上部電極層150側から下部電極層160側に行くにしたがって長くなっている。 That is, in the present embodiment, the groove portion 143 is formed not in the single crystal piezoelectric layer 140 but in the second protective portion 291. The second cross section 242 is not exposed to the groove portion 143. In the present embodiment, the groove portion 143 is formed so as to reach the upper surface of the lower electrode layer 260. The distance between the second cross sections 242 increases from the upper electrode layer 150 side to the lower electrode layer 160 side.
 第2保護部291は、第1中間層270と一体の部材で構成されている。第2保護部291の下面は、第1中間層270と互いに接続している。第2保護部291は、たとえばSiO2などの誘電体材料で構成されている。 The second protective portion 291 is composed of a member integrated with the first intermediate layer 270. The lower surface of the second protective portion 291 is connected to the first intermediate layer 270. The second protective portion 291 is made of a dielectric material such as SiO 2.
 以下、本発明の実施形態2に係る圧電デバイス200の製造方法について説明する。
 図16は、本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層に第1保護部用溝および第2保護部用溝を形成した状態を示す断面図である。図16に示すように、第1保護部用溝141Aを形成するとともに、エッチング法などにより、単結晶圧電体層140の下面に、第2保護部用溝242Aを形成する。
Hereinafter, a method for manufacturing the piezoelectric device 200 according to the second embodiment of the present invention will be described.
FIG. 16 is a cross-sectional view showing a state in which a groove for a first protective portion and a groove for a second protective portion are formed in a single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to a second embodiment of the present invention. As shown in FIG. 16, the groove 141A for the first protective portion is formed, and the groove 242A for the second protective portion is formed on the lower surface of the single crystal piezoelectric layer 140 by an etching method or the like.
 図17は、本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層の各々の下面、第1保護部用溝内および第2保護部用溝内の各々に第1中間層を設けた状態を示す断面図である。図16および図17に示すように、CVD法またはPVD法などにより、第1保護部用溝141A内、第2保護部用溝242A内および単結晶圧電体層140の各々の下面に、第1中間層270を設ける。 FIG. 17 shows the first intermediate in each of the lower surface of each single crystal piezoelectric layer, the inside of the groove for the first protection portion, and the inside of the groove for the second protection portion in the method for manufacturing the piezoelectric device according to the second embodiment of the present invention. It is sectional drawing which shows the state which provided the layer. As shown in FIGS. 16 and 17, the first protective portion groove 141A, the second protective portion groove 242A, and the lower surface of the single crystal piezoelectric layer 140 are formed by a CVD method, a PVD method, or the like. An intermediate layer 270 is provided.
 図18は、本発明の実施形態2に係る圧電デバイスの製造方法において、第1中間層の下面を削った状態を示す断面図である。図18に示すように、CMPなどにより、第1中間層270の下面を削って平坦にする。このようにして、第1保護部用溝141Aを、第1中間層270と同一の部材で構成された第1保護部190で埋めるとともに、第2保護部用溝242Aを、第1中間層270と同一の部材で構成された第2保護部291で埋める。 FIG. 18 is a cross-sectional view showing a state in which the lower surface of the first intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 18, the lower surface of the first intermediate layer 270 is scraped to be flat by CMP or the like. In this way, the first protective portion groove 141A is filled with the first protective portion 190 made of the same member as the first intermediate layer 270, and the second protective portion groove 242A is filled with the first intermediate layer 270. It is filled with the second protective portion 291 made of the same member as the above.
 図19は、本発明の実施形態2に係る圧電デバイスの製造方法において、第1中間層の下面に下部電極層を設けた状態を示す断面図である。図19に示すように、第1中間層270の下面に、下部電極層260を設ける。本実施形態において、下部電極層260を設ける具体的な方法は、本発明の実施形態1における下部電極層160を設ける方法と同様である。 FIG. 19 is a cross-sectional view showing a state in which a lower electrode layer is provided on the lower surface of the first intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 19, the lower electrode layer 260 is provided on the lower surface of the first intermediate layer 270. In the present embodiment, the specific method for providing the lower electrode layer 260 is the same as the method for providing the lower electrode layer 160 in the first embodiment of the present invention.
 図20は、本発明の実施形態2に係る圧電デバイスの製造方法において、第1中間層および下部電極層の各々の下面に、第2中間層を設けた状態を示す断面図である。図20に示すように、CVD法またはPVD法などにより、第1中間層270および下部電極層260の各々の下面に、第2中間層275を設ける。 FIG. 20 is a cross-sectional view showing a state in which a second intermediate layer is provided on the lower surfaces of each of the first intermediate layer and the lower electrode layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 20, a second intermediate layer 275 is provided on the lower surfaces of each of the first intermediate layer 270 and the lower electrode layer 260 by a CVD method, a PVD method, or the like.
 図21は、本発明の実施形態2に係る圧電デバイスの製造方法において、第2中間層の下面を削った状態を示す断面図である。図21に示すように、第2中間層275の下面をCMPなどにより平坦にする。 FIG. 21 is a cross-sectional view showing a state in which the lower surface of the second intermediate layer is scraped in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 21, the lower surface of the second intermediate layer 275 is flattened by CMP or the like.
 本実施形態においては、以上の工程により、第1積層体10を形成する。具体的には、本実施形態における第1積層体10は、中間層として第1中間層270と第2中間層275とを含むと共に、第2保護部291をさらに含んでいる。 In the present embodiment, the first laminated body 10 is formed by the above steps. Specifically, the first laminated body 10 in the present embodiment includes a first intermediate layer 270 and a second intermediate layer 275 as intermediate layers, and further includes a second protective portion 291.
 図22は、本発明の実施形態2に係る圧電デバイスの製造方法において、第2中間層の下面に第2積層体を接合させる状態を示す断面図である。図23は、本発明の実施形態2に係る圧電デバイスの製造方法において、第2中間層の下面に第2積層体を接合させた状態を示す断面図である。図22および図23に示すように、第1積層体10の下側に、本発明の実施形態1において用いた第2積層体20を接合する。 FIG. 22 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the second intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. FIG. 23 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the second intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIGS. 22 and 23, the second laminated body 20 used in the first embodiment of the present invention is joined to the lower side of the first laminated body 10.
 図24は、本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層、第1保護部および第2保護部の各々の上面を削った状態を示す断面図である。図24に示すように、単結晶圧電体層140、第1保護部190および第2保護部291の各々の上面をCMPなどにより削って、単結晶圧電体層140を所望の厚さにするとともに、第1保護部190および第2保護部291の各々を露出させる。 FIG. 24 is a cross-sectional view showing a state in which the upper surfaces of the single crystal piezoelectric layer, the first protective portion, and the second protective portion are scraped in the method for manufacturing the piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 24, the upper surfaces of the single crystal piezoelectric layer 140, the first protective portion 190, and the second protective portion 291 are each scraped by CMP or the like to make the single crystal piezoelectric layer 140 a desired thickness. , Each of the first protection unit 190 and the second protection unit 291 is exposed.
 図25は、本発明の実施形態2に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。図25に示すように、本発明の実施形態1における上部電極層150と同様にして、単結晶圧電体層140の上面に上部電極層150を配置する。 FIG. 25 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 25, the upper electrode layer 150 is arranged on the upper surface of the single crystal piezoelectric layer 140 in the same manner as the upper electrode layer 150 in the first embodiment of the present invention.
 図26は、本発明の実施形態2に係る圧電デバイスの製造方法において、第1保護部から半導体層まで貫通溝を形成した状態を示す断面図である。図26に示すように、本発明の実施形態1における貫通溝121と同様にして、貫通溝121を形成する。本実施形態においては、貫通溝121は、第1中間層270および第2中間層275を貫通するように形成する。 FIG. 26 is a cross-sectional view showing a state in which a through groove is formed from the first protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 26, the through groove 121 is formed in the same manner as the through groove 121 in the first embodiment of the present invention. In the present embodiment, the through groove 121 is formed so as to penetrate the first intermediate layer 270 and the second intermediate layer 275.
 図27は、本発明の実施形態2に係る圧電デバイスの製造方法において、第2保護部から第1中間層まで溝部を形成した状態を示す断面図である。図27に示すように、基部110の上方において第2保護部291および第1中間層270をエッチングすることにより、溝部143を形成する。 FIG. 27 is a cross-sectional view showing a state in which a groove portion is formed from the second protective portion to the first intermediate layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. As shown in FIG. 27, the groove portion 143 is formed by etching the second protective portion 291 and the first intermediate layer 270 above the base portion 110.
 図28は、本発明の実施形態2に係る圧電デバイスの製造方法において、上部電極層上に第1外部電極を設け、下部電極層上に第2外部電極を設けた状態を示す断面図である。図28に示すように、本発明の実施形態1における第1外部電極155および第2外部電極165と同様にして、第1外部電極155および第2外部電極165を設ける。 FIG. 28 is a cross-sectional view showing a state in which the first external electrode is provided on the upper electrode layer and the second external electrode is provided on the lower electrode layer in the method for manufacturing a piezoelectric device according to the second embodiment of the present invention. .. As shown in FIG. 28, the first external electrode 155 and the second external electrode 165 are provided in the same manner as the first external electrode 155 and the second external electrode 165 in the first embodiment of the present invention.
 最後に、図28および図15に示すように、本発明の実施形態1の凹部113と同様に、凹部113を形成する。上記の工程により、図15に示すような本発明の実施形態2に係る圧電デバイス200が製造される。 Finally, as shown in FIGS. 28 and 15, the recess 113 is formed in the same manner as the recess 113 of the first embodiment of the present invention. By the above steps, the piezoelectric device 200 according to the second embodiment of the present invention as shown in FIG. 15 is manufactured.
 (実施形態3)
 以下、本発明の実施形態3に係る圧電デバイスについて説明する。本発明の実施形態3に係る圧電デバイスは、本発明の実施形態2における第1中間層270を有さない点が主に、本発明の実施形態2に係る圧電デバイス200と異なる。よって、本発明の実施形態2に係る圧電デバイス200と同様である構成については説明を繰り返さない。
(Embodiment 3)
Hereinafter, the piezoelectric device according to the third embodiment of the present invention will be described. The piezoelectric device according to the third embodiment of the present invention is different from the piezoelectric device 200 according to the second embodiment of the present invention mainly in that it does not have the first intermediate layer 270 in the second embodiment of the present invention. Therefore, the description of the configuration similar to that of the piezoelectric device 200 according to the second embodiment of the present invention will not be repeated.
 図29は、本発明の実施形態3に係る圧電デバイスの断面図である。図29に示す圧電デバイス300の断面図は、図15に示す圧電デバイス200の断面図と同一の断面視にて図示している。 FIG. 29 is a cross-sectional view of the piezoelectric device according to the third embodiment of the present invention. The cross-sectional view of the piezoelectric device 300 shown in FIG. 29 is shown in the same cross-sectional view as the cross-sectional view of the piezoelectric device 200 shown in FIG.
 図29に示すように、本発明の実施形態3において、メンブレン部120は、中間層として第2中間層275のみを含んでいる。下部電極層260は、単結晶圧電体層140の下面、第2外部電極165の下面、第2保護部291の下面に設けられている。これにより、メンブレン部120において上部電極層150と下部電極層260とが、単結晶圧電体層140のみを挟んで対向するため、本発明の実施形態2に係る圧電デバイス200と比較して、圧電デバイス300の圧電特性を向上することができる。 As shown in FIG. 29, in the third embodiment of the present invention, the membrane portion 120 includes only the second intermediate layer 275 as the intermediate layer. The lower electrode layer 260 is provided on the lower surface of the single crystal piezoelectric layer 140, the lower surface of the second external electrode 165, and the lower surface of the second protective portion 291. As a result, in the membrane portion 120, the upper electrode layer 150 and the lower electrode layer 260 face each other with only the single crystal piezoelectric layer 140 interposed therebetween, so that the piezoelectric device 200 is compared with the piezoelectric device 200 according to the second embodiment of the present invention. The piezoelectric characteristics of the device 300 can be improved.
 本実施形態においては、中間層として、第2中間層275が、単結晶圧電体層140の下面、下部電極層260の下面および第1保護部190の下面に設けられている。 In the present embodiment, as the intermediate layer, the second intermediate layer 275 is provided on the lower surface of the single crystal piezoelectric layer 140, the lower surface of the lower electrode layer 260, and the lower surface of the first protective portion 190.
 以下、本発明の実施形態3に係る圧電デバイスの製造方法について説明する。
 まず、図16および図17に示すように、本発明の実施形態2に係る圧電デバイス200の製造方法と同様にして、第1保護部用溝141A内、第2保護部用溝242A内および単結晶圧電体層140の各々の下面に、第1中間層270を設ける。
Hereinafter, a method for manufacturing the piezoelectric device according to the third embodiment of the present invention will be described.
First, as shown in FIGS. 16 and 17, in the same manner as in the manufacturing method of the piezoelectric device 200 according to the second embodiment of the present invention, the inside of the first protective portion groove 141A, the inside of the second protective portion groove 242A, and the single. A first intermediate layer 270 is provided on the lower surface of each of the crystalline piezoelectric layers 140.
 次に、第1中間層270を下側から削る。図30は、本発明の実施形態3に係る圧電デバイスの製造方法において、第1中間層を下側から削った状態を示す断面図である。図30に示すように、CMPなどにより、第1中間層270を下側から削って、単結晶圧電体層140の下面より下側に位置する第1中間層270を完全に除去する。このとき、単結晶圧電体層140の下面を同時に削ってもよい。 Next, scrape the first intermediate layer 270 from the bottom. FIG. 30 is a cross-sectional view showing a state in which the first intermediate layer is scraped from the lower side in the method for manufacturing a piezoelectric device according to the third embodiment of the present invention. As shown in FIG. 30, the first intermediate layer 270 is scraped from the lower side by CMP or the like to completely remove the first intermediate layer 270 located below the lower surface of the single crystal piezoelectric layer 140. At this time, the lower surface of the single crystal piezoelectric layer 140 may be scraped at the same time.
 図31は、本発明の実施形態3に係る圧電デバイスの製造方法において、単結晶圧電体層および第2保護部の下面に下部電極層を設けた状態を示す断面図である。図31に示すように、単結晶圧電体層140の下面および第2保護部291の下面に、下部電極層260を設ける。本実施形態において、下部電極層260を設ける具体的な方法は、本発明の実施形態1における下部電極層160を設ける方法と同様である。 FIG. 31 is a cross-sectional view showing a state in which the lower electrode layer is provided on the lower surface of the single crystal piezoelectric layer and the second protective portion in the method for manufacturing the piezoelectric device according to the third embodiment of the present invention. As shown in FIG. 31, the lower electrode layer 260 is provided on the lower surface of the single crystal piezoelectric layer 140 and the lower surface of the second protective portion 291. In the present embodiment, the specific method for providing the lower electrode layer 260 is the same as the method for providing the lower electrode layer 160 in the first embodiment of the present invention.
 図32は、本発明の実施形態3に係る圧電デバイスの製造方法において、第1保護部および単結晶圧電体層の各々の下面に第2中間層を設けた状態を示す断面図である。図32に示すように、CVD法またはPVD法などにより、単結晶圧電体層140、下部電極層260、第1保護部190の各々の下面に、第2中間層275を設ける。 FIG. 32 is a cross-sectional view showing a state in which a second intermediate layer is provided on the lower surfaces of each of the first protective portion and the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the third embodiment of the present invention. As shown in FIG. 32, a second intermediate layer 275 is provided on the lower surfaces of each of the single crystal piezoelectric layer 140, the lower electrode layer 260, and the first protective portion 190 by a CVD method, a PVD method, or the like.
 本実施形態においては、第2中間層275を設けた後、図21から図28に示した本発明の実施形態2に係る圧電デバイス200の製造方法と同様にして、図29に示すような本発明の実施形態3に係る圧電デバイス300を製造することができる。 In the present embodiment, after the second intermediate layer 275 is provided, the book as shown in FIG. 29 is similar to the method for manufacturing the piezoelectric device 200 according to the second embodiment of the present invention shown in FIGS. 21 to 28. The piezoelectric device 300 according to the third embodiment of the present invention can be manufactured.
 (実施形態4)
 以下、本発明の実施形態4に係る圧電デバイスについて説明する。本発明の実施形態4に係る圧電デバイスは、下部電極層が半導体層である点が主に、本発明の実施形態2に係る圧電デバイス200と異なる。よって、本発明の実施形態2に係る圧電デバイス200と同様である構成については説明を繰り返さない。
(Embodiment 4)
Hereinafter, the piezoelectric device according to the fourth embodiment of the present invention will be described. The piezoelectric device according to the fourth embodiment of the present invention is different from the piezoelectric device 200 according to the second embodiment of the present invention mainly in that the lower electrode layer is a semiconductor layer. Therefore, the description of the configuration similar to that of the piezoelectric device 200 according to the second embodiment of the present invention will not be repeated.
 図33は、本発明の実施形態4に係る圧電デバイスの断面図である。図33に示す圧電デバイス400の断面図は、図15に示す圧電デバイス200の断面図と同一の断面視にて図示している。 FIG. 33 is a cross-sectional view of the piezoelectric device according to the fourth embodiment of the present invention. The cross-sectional view of the piezoelectric device 400 shown in FIG. 33 is shown in the same cross-sectional view as the cross-sectional view of the piezoelectric device 200 shown in FIG.
 図33に示すように、本実施形態において、下部電極層460は、半導体層180である。すなわち、図15に示すように、本発明の実施形態2において半導体層180とは異なる部材で構成された下部電極層260および第2中間層275は、本発明の実施形態4に係る圧電デバイス400に設けられていない。図33に示すように、本実施形態において、半導体層180は、第1中間層270の下面に設けられている。 As shown in FIG. 33, in the present embodiment, the lower electrode layer 460 is a semiconductor layer 180. That is, as shown in FIG. 15, the lower electrode layer 260 and the second intermediate layer 275 made of members different from the semiconductor layer 180 in the second embodiment of the present invention are the piezoelectric device 400 according to the fourth embodiment of the present invention. Not provided in. As shown in FIG. 33, in the present embodiment, the semiconductor layer 180 is provided on the lower surface of the first intermediate layer 270.
 下部電極層460が、半導体層180であることにより、圧電デバイス400を製造する際においては、半導体層180と異なる部材で構成された下部電極層を設ける工程を省略できる。ひいては、圧電デバイス400の製造方法を簡素化することができる。 Since the lower electrode layer 460 is the semiconductor layer 180, the step of providing the lower electrode layer made of a member different from the semiconductor layer 180 can be omitted when manufacturing the piezoelectric device 400. As a result, the manufacturing method of the piezoelectric device 400 can be simplified.
 本実施形態において、半導体層180を構成する材料の電気抵抗率は、下部電極層460として機能させるという観点から、20mΩ・cm以下であることが好ましい。 In the present embodiment, the electrical resistivity of the material constituting the semiconductor layer 180 is preferably 20 mΩ · cm or less from the viewpoint of functioning as the lower electrode layer 460.
 本実施形態において、溝部443は、半導体層180の上面より下側まで位置している。これにより、第2外部電極165と、下部電極層460である半導体層180との接触面積が増加する。よって、第2外部電極165と半導体層180との接触抵抗を低減することができる。 In the present embodiment, the groove portion 443 is located below the upper surface of the semiconductor layer 180. As a result, the contact area between the second external electrode 165 and the semiconductor layer 180, which is the lower electrode layer 460, increases. Therefore, the contact resistance between the second external electrode 165 and the semiconductor layer 180 can be reduced.
 以下、本発明の実施形態4に係る圧電デバイスの製造方法について説明する。
 まず、図16から図18に示した本発明の実施形態2に係る圧電デバイス200の製造方法と同様にして、第1保護部用溝141Aを第1保護部190で埋めるとともに、第2保護部用溝242Aを第2保護部291で埋める。本発明の実施形態4に係る圧電デバイス400の製造方法においては、図18に示した積層体が、第1積層体10となる。
Hereinafter, a method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention will be described.
First, in the same manner as the manufacturing method of the piezoelectric device 200 according to the second embodiment of the present invention shown in FIGS. 16 to 18, the groove 141A for the first protective portion is filled with the first protective portion 190, and the second protective portion is formed. The groove 242A is filled with the second protective portion 291. In the method for manufacturing the piezoelectric device 400 according to the fourth embodiment of the present invention, the laminate shown in FIG. 18 is the first laminate 10.
 図34は、本発明の実施形態4に係る圧電デバイスの製造方法において、第1中間層の下面に第2積層体を接合させる状態を示す断面図である。図35は、本発明の実施形態4に係る圧電デバイスの製造方法おいて、第1中間層の下面に第2積層体を接合させた状態を示す断面図である。 FIG. 34 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the first intermediate layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention. FIG. 35 is a cross-sectional view showing a state in which the second laminated body is bonded to the lower surface of the first intermediate layer in the method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention.
 図34および図35に示すように、第1積層体10の下側に、本発明の実施形態1において用いた第2積層体20を接合する。 As shown in FIGS. 34 and 35, the second laminated body 20 used in the first embodiment of the present invention is joined to the lower side of the first laminated body 10.
 図36は、本発明の実施形態4に係る圧電デバイスの製造方法において、単結晶圧電体層、第1保護部および第2保護部の各々の上面を削った状態を示す断面図である。図36に示すように、単結晶圧電体層140、第1保護部190および第2保護部291の各々の上面をCMPなどにより削って、単結晶圧電体層140を所望の厚さにするとともに第1保護部190および第2保護部291の各々を露出させる。 FIG. 36 is a cross-sectional view showing a state in which the upper surfaces of the single crystal piezoelectric layer, the first protective portion, and the second protective portion are scraped in the method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention. As shown in FIG. 36, the upper surfaces of the single crystal piezoelectric layer 140, the first protective portion 190, and the second protective portion 291 are each scraped by CMP or the like to make the single crystal piezoelectric layer 140 a desired thickness. Each of the first protective portion 190 and the second protective portion 291 is exposed.
 図37は、本発明の実施形態4に係る圧電デバイスの製造方法において、単結晶圧電体層の上面に上部電極層を設けた状態を示す断面図である。図37に示すように、本発明の実施形態1における上部電極層150と同様にして、単結晶圧電体層140の上面に上部電極層150を配置する。 FIG. 37 is a cross-sectional view showing a state in which an upper electrode layer is provided on the upper surface of the single crystal piezoelectric layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention. As shown in FIG. 37, the upper electrode layer 150 is arranged on the upper surface of the single crystal piezoelectric layer 140 in the same manner as the upper electrode layer 150 in the first embodiment of the present invention.
 図38は、本発明の実施形態4に係る圧電デバイスの製造方法において、第1保護部から半導体層まで貫通溝を形成した状態を示す断面図である。図38に示すように、本発明の実施形態1における貫通溝121と同様にして、貫通溝121を形成する。 FIG. 38 is a cross-sectional view showing a state in which a through groove is formed from the first protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention. As shown in FIG. 38, the through groove 121 is formed in the same manner as the through groove 121 in the first embodiment of the present invention.
 図39は、本発明の実施形態4に係る圧電デバイスの製造方法において、第2保護部から半導体層まで溝部を形成した状態を示す断面図である。図39に示すように、基部110の上方において、第2保護部291と、第1中間層270と、半導体層180の一部をエッチングすることにより、溝部443を形成する。 FIG. 39 is a cross-sectional view showing a state in which a groove portion is formed from the second protective portion to the semiconductor layer in the method for manufacturing a piezoelectric device according to the fourth embodiment of the present invention. As shown in FIG. 39, the groove portion 443 is formed by etching the second protective portion 291 and the first intermediate layer 270 and a part of the semiconductor layer 180 above the base portion 110.
 図40は、本発明の実施形態4に係る圧電デバイスの製造方法において、上部電極層上に第1外部電極を設け、下部電極層である半導体層上に第2外部電極を設けた状態を示す断面図である。図40に示すように、本発明の実施形態1における第1外部電極155および第2外部電極165と同様にして、第1外部電極155および第2外部電極165を設ける。すなわち、本発明の実施形態4においては、下部電極層460である半導体層180上に、第2外部電極165を設ける。 FIG. 40 shows a state in which the first external electrode is provided on the upper electrode layer and the second external electrode is provided on the semiconductor layer which is the lower electrode layer in the method for manufacturing the piezoelectric device according to the fourth embodiment of the present invention. It is a sectional view. As shown in FIG. 40, the first external electrode 155 and the second external electrode 165 are provided in the same manner as the first external electrode 155 and the second external electrode 165 in the first embodiment of the present invention. That is, in the fourth embodiment of the present invention, the second external electrode 165 is provided on the semiconductor layer 180, which is the lower electrode layer 460.
 最後に、図40および図33に示すように、本発明の実施形態1の凹部113と同様にして、凹部113を形成する。上記の工程により、図33に示すような本発明の実施形態4に係る圧電デバイス400が製造される。 Finally, as shown in FIGS. 40 and 33, the recess 113 is formed in the same manner as the recess 113 of the first embodiment of the present invention. By the above steps, the piezoelectric device 400 according to the fourth embodiment of the present invention as shown in FIG. 33 is manufactured.
 上述した実施形態の説明において、組み合わせ可能な構成を相互に組み合わせてもよい。 In the above description of the embodiment, the configurations that can be combined may be combined with each other.
 今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the claims.
 10 第1積層体、20 第2積層体、100,200,300,400 圧電デバイス、110 基部、110a 下側基部、110b 上側基部、111 上側主面、112 下側主面、113 凹部、120 メンブレン部、121 貫通溝、130 複数の層、140 単結晶圧電体層、141 第1断面、141A 第1保護部用溝、142,242 第2断面、143,443 溝部、150 上部電極層、155 第1外部電極、160,260,460 下部電極層、161 エッチングストップ層、165 第2外部電極、170 中間層、180 半導体層、190 第1保護部、242A 第2保護部用溝、270 第1中間層、275 第2中間層、291 第2保護部。 10 1st laminate, 20 2nd laminate, 100, 200, 300, 400 piezoelectric device, 110 base, 110a lower base, 110b upper base, 111 upper main surface, 112 lower main surface, 113 recess, 120 membrane Part, 121 through groove, 130 multiple layers, 140 single crystal piezoelectric layer, 141 first cross section, 141A first protection groove, 142, 242 second cross section, 143, 443 groove, 150 upper electrode layer, 155th 1 external electrode, 160, 260, 460 lower electrode layer, 161 etching stop layer, 165 second external electrode, 170 intermediate layer, 180 semiconductor layer, 190 first protective part, 242A second protective part groove, 270 first intermediate Layer, 275, second intermediate layer, 291 second protection.

Claims (7)

  1.  基部と、
     前記基部に間接的に支持されて、前記基部より上側に位置し、複数の層からなるメンブレン部とを備え、
     前記メンブレン部は、前記基部に重なっておらず、かつ、単結晶圧電体層と、該単結晶圧電体層の上側に配置された上部電極層と、前記単結晶圧電体層を介して、前記上部電極層の少なくとも一部に対向するように配置された下部電極層とを含み、
     前記メンブレン部には、上下方向に貫通する貫通溝が設けられており、
     前記単結晶圧電体層の前記貫通溝と面する第1断面は、前記貫通溝を間に挟んで位置する第1保護部に覆われている、圧電デバイス。
    At the base,
    It is indirectly supported by the base portion, is located above the base portion, and includes a membrane portion composed of a plurality of layers.
    The membrane portion does not overlap the base portion, and the single crystal piezoelectric layer, an upper electrode layer arranged on the upper side of the single crystal piezoelectric layer, and the single crystal piezoelectric layer are interposed therein. Includes a lower electrode layer arranged to face at least a portion of the upper electrode layer.
    The membrane portion is provided with a through groove that penetrates in the vertical direction.
    A piezoelectric device in which a first cross section of the single crystal piezoelectric layer facing the through groove is covered with a first protective portion located with the through groove in between.
  2.  前記第1断面同士の距離は、上部電極層側から下部電極層側に行くにしたがって長くなっている、請求項1に記載の圧電デバイス。 The piezoelectric device according to claim 1, wherein the distance between the first cross sections increases from the upper electrode layer side to the lower electrode layer side.
  3.  前記メンブレン部は、前記下部電極層と、前記単結晶圧電体層との間に位置する中間層をさらに含んでいる、請求項1または請求項2に記載の圧電デバイス。 The piezoelectric device according to claim 1 or 2, wherein the membrane portion further includes an intermediate layer located between the lower electrode layer and the single crystal piezoelectric layer.
  4.  前記下部電極層と電気的に接続された第2外部電極をさらに備えており、
     前記複数の層は、前記基部の上側に延在しており、
     前記単結晶圧電体層は、前記基部の上方において、溝部を間に挟んで互いに面する第2断面をさらに有し、
     前記第2断面は、前記溝部を間に挟んで位置する第2保護部に覆われており、
     前記下部電極層は、前記第2保護部の下方に位置しており、
     前記第2外部電極は、前記下部電極層上と、前記溝部の内側面と、前記第2保護部の上側とにわたって設けられており、かつ、前記単結晶圧電体層とは離間している、請求項1から請求項3のいずれか1項に記載の圧電デバイス。
    Further, a second external electrode electrically connected to the lower electrode layer is provided.
    The plurality of layers extend above the base and extend over the base.
    The single crystal piezoelectric layer further has a second cross section above the base portion, which faces each other with a groove portion in between.
    The second cross section is covered with a second protective portion located with the groove portion in between.
    The lower electrode layer is located below the second protective portion.
    The second external electrode is provided on the lower electrode layer, the inner surface of the groove portion, and the upper side of the second protective portion, and is separated from the single crystal piezoelectric layer. The piezoelectric device according to any one of claims 1 to 3.
  5.  前記下部電極層が、半導体層である、請求項1から請求項4のいずれか1項に記載の圧電デバイス。 The piezoelectric device according to any one of claims 1 to 4, wherein the lower electrode layer is a semiconductor layer.
  6.  前記下部電極層が、半導体層であり、
     前記溝部は、前記半導体層の上面より下側まで位置している、請求項4に記載の圧電デバイス。
    The lower electrode layer is a semiconductor layer,
    The piezoelectric device according to claim 4, wherein the groove is located below the upper surface of the semiconductor layer.
  7.  単結晶圧電体層の下方に下部電極層を配置する工程と、
     前記単結晶圧電体層に、上下方向に貫通する第1保護部用溝を形成する工程と、
     前記第1保護部用溝を第1保護部で埋める工程と、
     少なくとも前記単結晶圧電体層を含む第1積層体を形成する工程と、
     前記第1積層体の下側に、第2積層体を接合する工程と、
     前記単結晶圧電体層の厚さを調整する工程と、
     前記単結晶圧電体層の上側に、少なくとも一部が前記単結晶圧電体層を介して前記下部電極層と対向する、上部電極層を配置する工程と、
     前記第1保護部を分割するように、少なくとも前記第1積層体を上下方向に貫通する貫通溝を形成する工程と、
     上下方向から見たときに、前記上部電極層と、前記下部電極層とが前記単結晶圧電体層を介して対向している部分、および、前記貫通溝が位置する部分と重なるように、前記第2積層体の下側に開口して前記貫通溝と連通する凹部を形成する工程とを備える、圧電デバイスの製造方法。
    The process of arranging the lower electrode layer below the single crystal piezoelectric layer,
    A step of forming a groove for a first protective portion penetrating in the vertical direction in the single crystal piezoelectric layer, and
    The step of filling the groove for the first protective portion with the first protective portion and
    The step of forming the first laminated body including at least the single crystal piezoelectric layer, and
    A step of joining the second laminated body to the lower side of the first laminated body,
    The step of adjusting the thickness of the single crystal piezoelectric layer and
    A step of arranging an upper electrode layer on the upper side of the single crystal piezoelectric layer, at least a part of which faces the lower electrode layer via the single crystal piezoelectric layer.
    A step of forming a through groove that penetrates at least the first laminated body in the vertical direction so as to divide the first protective portion.
    When viewed from the vertical direction, the upper electrode layer and the lower electrode layer overlap with each other through the single crystal piezoelectric layer and the portion where the through groove is located. A method for manufacturing a piezoelectric device, comprising a step of forming a recess that opens on the lower side of the second laminated body and communicates with the through groove.
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