WO2020052431A1 - 信息调制解调方法与装置 - Google Patents

信息调制解调方法与装置 Download PDF

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Publication number
WO2020052431A1
WO2020052431A1 PCT/CN2019/102826 CN2019102826W WO2020052431A1 WO 2020052431 A1 WO2020052431 A1 WO 2020052431A1 CN 2019102826 W CN2019102826 W CN 2019102826W WO 2020052431 A1 WO2020052431 A1 WO 2020052431A1
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WO
WIPO (PCT)
Prior art keywords
bit
information
bit information
sequence
soft
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PCT/CN2019/102826
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English (en)
French (fr)
Inventor
牛凯
周德坤
董超
于天航
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华为技术有限公司
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Publication of WO2020052431A1 publication Critical patent/WO2020052431A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H04L1/0008—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length by supplementing frame payload, e.g. with padding bits

Definitions

  • Embodiments of the present application relate to the field of communications, and in particular, to an information modulation and demodulation method and device.
  • Polar codes (Polar Codes) is a constructable channel coding method that can achieve the capacity of binary input discrete memoryless channels.
  • polar code coding by using channel combining and segmentation operations, the resulting subchannels are noiseless or Full Noise Channel.
  • the polarization coding and modulation framework is mainly bit-interleaved polar coded modulation (BIPCM).
  • BIPCM bit-interleaved polar coded modulation
  • the transmitting device eliminates the correlation between bits by introducing a bit interleaver, and then encodes
  • the modulator and the modulator are simply cascaded, and then the bit stream of the same encoding code block is sent to the receiving device with the same transmission symbol.
  • the receiving device obtains the receiving symbol from the transmitting device, the bit stream of the same encoding code block is demodulated in parallel. Then, the demodulated bit stream is sent to a polar code decoder for decoding, and a decoding result is obtained.
  • the receiving device applies parallel demodulation to the bit stream of the same encoding code block, and then sends the demodulated bit stream to the polar code decoder for decoding to obtain the decoding result, wherein the bits of the same encoding code block are decoded.
  • Parallel demodulation of streams will cause mutual information loss between bit streams, which will cause the degradation of system performance.
  • Embodiments of the present application provide an information modulation and demodulation method and apparatus, which are used by a receiving device to serially demodulate undemodulated bit information by using a decoded codeword sequence to reduce the mutual information between bit streams. Loss and improve the performance of the communication system.
  • a first aspect of the embodiments of the present application provides an information modulation method, including:
  • the sending device modulates a first target bit stream to obtain a first target symbol, where the first target symbol includes first M-bit information, the first target bit stream includes a first bit stream of a first coded block, and
  • the first M-bit information includes first bit information of the first bit stream, and at least one padding bit information, the padding bit information is known bit information, the M is an integer greater than 1,
  • the transmitting device modulates A second target bit stream to obtain a second target symbol, where the second target symbol includes second M-bit information, and the second target bit stream includes a second bit stream of the first coded block and a second code
  • the third bit stream of the code block, the second M bit information includes at least the second bit information of the second bit stream, and the third bit information of the third bit stream; the sending device at the first time Sending the first target symbol to a receiving device and sending the second target symbol at a second time, the first time being before the second time.
  • the second target symbol includes at least two bit information from different coded code blocks, so that the receiving device can use the information bit sequence corresponding to the decoded bit information to demodulate the softness of the undecoded bit information.
  • Information reducing the loss of mutual information between bit information.
  • the method before the transmitting device modulates a first target bit stream, the method includes: the transmitting device applies the first The codeword sequences corresponding to the coded code blocks are divided with the same length to obtain a first divided stream, where the first divided stream includes the first bit stream and the second bit stream.
  • the sending device divides a codeword sequence corresponding to the second coded code block by the same length to obtain a second divided stream, where the second divided stream includes the third bit stream.
  • the second M-bit information includes the padding bit information.
  • the second M-bit information may further include padding bit information, and the soft information of the bit information of the first coded code block may be demodulated based on the padding bit information. The accuracy of soft information of demodulated bit information is improved.
  • the first M-bit information further includes fourth bit information, and the fourth bit information corresponds to a fourth bit stream of the second encoded code block.
  • the first M-bit information further includes fourth bit information, and the soft information of the fourth bit information can be demodulated based on the decoded first codeword sequence. Reduce the loss of mutual information between bit information.
  • all The first M-bit information and the second M-bit information respectively correspond to M coded code blocks; or, the first M-bit information and the second M-bit information correspond to M / 2 coded code blocks, respectively, when When the first M-bit information and the second M-bit information correspond to M / 2 coded code blocks, respectively, the M is an even number.
  • the first M-bit information and the second M-bit information respectively correspond to M coding code blocks, or respectively correspond to M / 2 coding codes. Block, which improves the accuracy of the soft information of the demodulated bit information.
  • a second aspect of the embodiments of the present application provides an information demodulation method, including:
  • the receiving device receives a first target symbol sent by the sending device at a first moment, the first target symbol includes first M-bit information, and the first M-bit information includes a first bit stream of a first bit stream of a first code block. Bit information and at least one padding bit information, the padding bit information is known bit information, and the M is an integer greater than 1; the receiving device demodulates the first bit information based on the at least one padding bit information The soft information of the first bit information is included in the soft information sequence of the first encoded code block; the receiving device receives the second target symbol sent by the sending device at a second moment, and the first The two target symbols include second M-bit information, and the second M-bit information includes at least second bit information of a second bit stream of the first encoded code block, and second bit information of a third bit stream of the second encoded code block.
  • the receiving device demodulates the soft information of the second bit information, and the soft information of the second bit information is included in the soft information sequence of the first encoded code block;
  • Device for the first soft information sequence encoded code block is decoded to obtain a first information bit sequence, the first information bit sequence for the third bit soft information demodulating information. It can be seen from the second aspect that the receiving device uses the information bit sequence corresponding to the decoded bit information to demodulate the soft information of the undecoded bit information, thereby reducing the loss of mutual information between the bit information.
  • the method further includes: the receiving device performs polarization code encoding on the first information bit sequence to obtain A first codeword sequence; the receiving device demodulates the soft information of the third bit information based on the first codeword sequence, and the soft information of the third bit information is included in the softness of the second coded code block Information sequence.
  • the soft information of the undecoded third bit information can be demodulated based on the decoded first encoded code block, which reduces the interaction between the bit information. Loss of information.
  • the second M-bit information includes the padding bit information
  • the The soft information of the receiving device demodulating the third bit information based on the first codeword sequence includes: the receiving device demodulating the third bit information based on the padding bit information and the first codeword sequence.
  • Soft information As can be seen from the second implementation manner of the second aspect, in the embodiments of the present application, the soft information of the undecoded third bit information can be demodulated based on the stuffed bit information and the decoded codeword sequence, reducing the bit information. Loss of mutual information.
  • the first M-bit information further includes fourth-bit information
  • the method further includes: the receiving device demodulates the soft information of the fourth-bit information based on the padding bit information and the first codeword sequence.
  • the fourth bit information is included in a fourth bit stream of the second encoded code block.
  • the soft information of the undecoded third bit information can be demodulated based on the stuffing bit information and the decoded codeword sequence, thereby reducing the bit information. Loss of mutual information.
  • the second M-bit information includes fifth bit information, the fifth bit information corresponds to a third coded code block, and the method further includes: the receiving device decodes the code based on the first codeword sequence and the second codeword sequence.
  • the soft information of the fifth bit information is adjusted, the fifth bit information and the second bit information have the same sequence number in the bit stream to which they belong, and the second codeword sequence is the second information bit sequence.
  • a codeword sequence obtained by encoding a code, and the second information bit sequence is an information bit sequence corresponding to the second encoded code block.
  • the soft information of the bit information to be decoded subsequently can be demodulated based on the decoded codeword sequence, which reduces the mutual information between the bit information. loss.
  • the second M-bit information includes padding bit information
  • the receiving device demodulates the soft information of the fifth bit information based on the first codeword sequence and the second codeword sequence includes: the receiving device is based on the first codeword sequence A codeword sequence, the second codeword sequence, and the stuffing bit information demodulate the soft information of the fifth bit information.
  • the soft information of the bit information to be decoded subsequently can be demodulated based on the stuffing bit information and the decoded codeword sequence, reducing the bit information. Loss of mutual information.
  • the method further includes: the receiving device softening the soft code of the second coded code block. Decode the information sequence to obtain the second information bit sequence; the receiving device performs polarization code encoding on the second information bit sequence to obtain the second codeword sequence.
  • the receiving device decodes the soft information sequence of the first encoded code block to obtain a first information bit sequence includes: the receiving device uses a sequence continuous deletion algorithm SCL or a cyclic redundancy check auxiliary sequence continuous deletion algorithm CA -SCL decodes the soft information sequence of the first encoded code block to obtain the first information bit sequence.
  • all The first M-bit information and the second M-bit information respectively correspond to M coded code blocks; or, the first M-bit information and the second M-bit information correspond to M / 2 coded code blocks, respectively, when When the first M-bit information and the second M-bit information correspond to M / 2 coded code blocks, respectively, the M is an even number.
  • the first M-bit information and the second M-bit information respectively correspond to M coding code blocks, or respectively correspond to M / 2 coding codes. Block, which improves the accuracy of the soft information of the demodulated bit information.
  • a third aspect of the embodiments of the present application provides a sending device, where the sending device includes: a memory, a transceiver, and at least one processor, and the memory stores instructions; the memory, the transceiver, and the at least one Processors are connected via lines;
  • the at least one processor invokes the instruction to perform a message processing or control operation performed on the sending device side by the first aspect.
  • a fourth aspect of the embodiments of the present application provides a receiving device.
  • the receiving device includes: a memory, a transceiver, and at least one processor, and the memory stores instructions; the memory, the transceiver, and the at least one Processors are connected via lines;
  • the at least one processor invokes the instruction to perform a message processing or control operation performed on the receiving device side by the second aspect.
  • a fifth aspect of the embodiments of the present application provides a computer-readable storage medium, which is characterized by including instructions that, when the instructions are run on a computer, cause the computer to execute the method of the first aspect or any possible implementation manner of the first aspect .
  • a sixth aspect of the embodiments of the present application provides a computer-readable storage medium, which is characterized in that it includes instructions that, when the instructions run on a computer, cause the computer to execute the method of the second aspect or any possible implementation manner of the second aspect .
  • a seventh aspect of the embodiments of the present application provides a computer program product including instructions, which is characterized in that when it is run on a computer, the computer is caused to execute the method of the first aspect or any possible implementation manner of the first aspect.
  • An eighth aspect of the embodiments of the present application provides a computer program product including instructions, which is characterized in that when it is run on a computer, the computer is caused to execute the method of the second aspect or any possible implementation manner of the second aspect.
  • the transmitting device separately modulates the first target bit stream and the second target bit stream to obtain first M bit information and second M bit information, wherein the first M bit information includes a first bit stream of the first bit stream.
  • Bit information, and at least one padding bit information the second M bit information includes at least the second bit information of the second bit stream and the third bit information of the third bit stream, and the receiving device encodes the first bit information corresponding to the first bit information.
  • the soft information of the code block is decoded to obtain a first information bit sequence, and then the soft information of the third bit information of the second coded code block is demodulated based on the first information bit sequence.
  • the second target symbol includes at least two pieces of bit information from different coded code blocks, so that the information bits corresponding to the decoded bit information can be used to demodulate the soft information of the undecoded bit information. To reduce the loss of mutual information between bit information.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application
  • FIG. 2 is a system framework diagram provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an information modulation and demodulation method according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an embodiment provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another embodiment provided by this embodiment.
  • FIG. 6 is a schematic diagram of another embodiment of an information modulation and demodulation method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another embodiment provided by an embodiment of the present application.
  • FIG. 8 is a schematic block diagram of a sending device according to an embodiment of the present application.
  • FIG. 9 is a schematic block diagram of a receiving device according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a hardware structure of a sending device according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a hardware structure of a receiving device according to an embodiment of the present application.
  • Embodiments of the present application provide an information modulation and demodulation method and apparatus, which are used by a receiving device to serially demodulate undemodulated bit information by using a decoded codeword sequence to reduce the mutual information between bit streams. Loss and improve the performance of the communication system.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • the schematic diagram of the application scenario may include a terminal device 101 and a network device 102.
  • the terminal device 101 may include various handheld devices with wireless communication functions, vehicle-mounted devices, wearable devices, computing devices, or other processing devices connected to a wireless modem.
  • the terminal device 101 may be a mobile station (MS), a subscriber unit, a cellular phone, a smart phone, a wireless data card, or a personal digital assistant. : PDA) computer, tablet computer, wireless modem (modem), handheld device (handset), laptop (laptop computer), machine type communication (machine type communication (MTC) terminal, etc.).
  • the network device 102 provided in the embodiment of the present application may be a device that is deployed in a wireless access network to provide a wireless communication function for the terminal device 101.
  • the network device 102 may include various forms of macro base stations, micro base stations (also referred to as small stations), relay stations, access points, and the like.
  • macro base stations also referred to as small stations
  • micro base stations also referred to as small stations
  • relay stations access points
  • the names of devices with base station functions may be different.
  • eNB or eNodeB evolved NodeB
  • eNB evolved NodeB
  • Node B Node B
  • 5G fifth generation
  • the terminal device 101 can send information to the network device 102 as a sending device.
  • the network device 102 can receive information sent by the terminal device 101 as a receiving device.
  • the network device 102 can also be used as a sending device.
  • the device sends information to the terminal device 101.
  • the terminal device 101 can also function as a receiving device to receive the information sent by the network device 102.
  • the embodiment of the present application only uses the terminal device 101 as a sending device and the network device 102 as a receiving device as an example to describe the sending device and the network device involved in the embodiment of the present application.
  • FIG. 2 is a system framework diagram provided by an embodiment of the present application.
  • the system framework diagram includes a sending device and a receiving device.
  • the sending equipment includes polarization encoder, serial-to-parallel converter, interleaver, bit delayer, and modulator.
  • a polar encoder may be a device that polarizes a source bit stream or data
  • a serial-to-parallel converter may be a device that converts a codeword sequence into multiple parallel bit streams
  • an interleaver may be used to A device that interleaves streams
  • a bit delayer can delay the bit stream and send the delayed bit stream to the modulator respectively
  • the modulator can modulate the bit information in the bit stream and then send it to the receiving device through the channel .
  • the receiving equipment includes demodulator, inverse bit delay, deinterleaver, parallel-to-serial converter and polarization decoder.
  • the demodulator can demodulate the bit information in the bit stream;
  • the inverse delayer can inverse delay the demodulated bit stream soft information sequence;
  • the deinterleaver can deinterleave the bit stream soft information sequence;
  • a parallel-to-serial converter can convert multiple parallel bitstream soft information sequences into one bitstream soft information sequence that can be decoded;
  • a polar decoder can be a device that decodes a bitstream or data.
  • FIG. 3 is a schematic diagram of an embodiment of an information modulation and demodulation method provided by an embodiment of the present application.
  • the information modulation and demodulation method provided by the embodiment of the present application may include the following steps:
  • a polarization encoder performs polarization code encoding on a source bit sequence.
  • the polarization encoder obtains M source bit sequences from the source device, where M is an integer greater than 1. It should be noted that, in this embodiment, the M source bit sequences may be different source bit sequences.
  • the polarization encoder separately performs polarization code encoding on the M source bit sequences to obtain M coded code blocks; for example, the polarization encoder performs the first source bit sequence u 1: N of the M source bit sequences. , 1 performs polar code encoding to obtain a first encoded code block, where the codeword sequence of the first encoded code block is b 1: N, 1 .
  • the code length of each of the M coded code blocks is N and the information bit length is Q.
  • the codeword sequence b 1: N, 2 of the second coded code block to the codeword sequence b 1: N, M corresponding to the Mth coded code block is similar to the foregoing codeword sequence b 1: N, 1 . I will not repeat them here.
  • the second coded code block corresponds to the second source bit sequence u 1: N, 2 of the M source bit sequences
  • the Mth coded block corresponds to the M source source bit sequence u 1: of the M source bit sequences . N, M.
  • the serial-to-parallel converter divides the M coded code blocks and sends the divided bit stream to the interleaver.
  • codeword sequence b 1: N, 1 of the first coded code block is used as an example to describe the division of the coded code block in this embodiment:
  • the corresponding 4 bit streams can be shown in Table 3-1.
  • the corresponding 4 bit streams can also be shown in Table 3-2.
  • codeword sequence b 1: N, 1 of the first encoded code block in this embodiment may also be divided in other manners, and details are not described herein again.
  • the division method of 1: N, 1 is similar and will not be repeated here.
  • the serial-to-parallel converter divides the bit sequence corresponding to each coded code block into m bit streams of length N / m, and sends the divided bit streams to the interleaver.
  • the serial-to-parallel converter determines the i-th bit stream of each coded code block from the segmented bit stream. And the i-th bitstream Send to the i-th interleaver. For example, the bit stream of the first encoded code block Send to the first interleaver, and the bit stream of the second coded block Send to the first interleaver, and so on.
  • the serial-to-parallel converter may also send m bit streams of the same code block to the same interleaver, which is not limited herein.
  • This embodiment and subsequent embodiments are described only by using an example in which an i-th bit stream of each coded code block is transmitted to a corresponding i-th interleaver.
  • the interleaver interleaves the bit stream.
  • the interleaver obtains the divided bit stream from the serial-parallel converter; specifically, the i-th interleaver obtains the i-th bit stream of each coded block, and the i-th interleaver converts the i-th bit of each coded block
  • the bit streams are interleaved separately, and the interleaved bit stream of each coded code block is output.
  • the following uses the first interleaver and the second interleaver to interleave the bit stream as an example.
  • the first interleaver converts the first bit stream of the first encoded code block. Interleaving to output the interleaved bit stream
  • the first interleaver converts the first bit stream of the second coded block Interleaving to output the interleaved bit stream And so on.
  • the second interleaver converts the second bit stream of the first coded block Interleaving to output the interleaved bit stream
  • the second interleaver converts the second bit stream of the second coded block Interleaving to output the interleaved bit stream And so on.
  • the bit delayer delays the bit stream.
  • the bit delayer delays the bit stream obtained from the interleaver. Among them, the delay of the i-th bit stream of each coded code block is the same, and the delayed bit stream is sent to the modulator at different times. send.
  • the bit delayer sends a first target bit stream to the modulator at a first moment.
  • the first target bit stream includes at least a first bit stream of a first coded block, where the first bit stream may be a first coded block. Any of the m bit streams.
  • the bit delayer sends a second target bit stream to the modulator at a second moment.
  • the second target bit stream includes the second bit stream of the first encoded code block and the third bit stream of the second encoded code block.
  • the second bit stream is any one of the m bit streams of the first coded code block
  • the third bit stream is any one of the m bit streams of the second coded code block.
  • step 303 and step 304 may be performed first, and step 304 and step 303 may be performed first, which is not limited herein.
  • the modulator modulates a first target bit stream and a second target bit stream.
  • the modulator obtains the first target bit stream and the second target bit stream sent by the bit delayer, and modulates the first target bit stream and the second target bit stream, respectively.
  • the modulator modulates the first target bit stream to obtain a first target symbol, where the first target symbol includes first M-bit information, the first M-bit information includes first bit information of the first bit stream, and at least one padding bit Information, it should be noted that the padding bit information is known bit information.
  • the modulator modulates the second target bit stream to obtain a second target symbol, where the second target symbol includes second M-bit information, the second M-bit information includes at least the second bit information of the second bit stream, and the third bit stream Three-bit information, that is, the second M-bit information includes at least two bits of information, where the two bits of information correspond to different coding code blocks, respectively.
  • the following describes the modulation bit stream involved in this implementation with 16 quadrature amplitude modulation (QAM), four coding code blocks, and a code length of each coding code block as N.
  • the four code blocks are A code block, B code block, C code block, and D code block.
  • FIG. 4 is a schematic diagram of an embodiment provided by an embodiment of the present application.
  • the modulator obtains a first target bit stream sent by a bit delayer at a first moment, where the first target bit stream
  • the first bitstream included may be (A 1 A 2 ... A N / 4 ), and the modulator modulates (A 1 A 2 ... A N / 4 ) and the stuffing bit information (XXX... X) to obtain N / 4 First target symbols, where each first target symbol includes first M-bit information.
  • the modulator combines the first bit stream (A 1 A 2 ... A N / 4 ) and the j-bit information in each padding bit information to form a binary bit sequence.
  • the modulator converts (A 1 A 2 ... A N / 4 ), the bit information A 1 with sequence number 1 and the X with sequence number 1 in each padding bit information are modulated into a first target symbol, and the first M bit information of the first target symbol is (X X X A 1 ), X is stuffing bit information. And modulate bit information A 2 with serial number 2 and X with serial number 2 in each padding bit information into another second target symbol, the first M bit information of the second target symbol is (X X X A 2 ), and so on , N / 4 first target symbols can be obtained, and each first target symbol includes first M-bit information.
  • the modulator obtains a second target bit stream sent by the bit delayer at a second moment, where the second target bit stream includes a second bit stream that may be (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ), the third bit stream may be (B 1 B 2 ... B N / 4 ).
  • the modulator modulates (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ), (B 1 B 2 ... B N / 4 ), and (XXX... X) to obtain N / 4 second A target symbol, where the second target symbol includes second M-bit information.
  • the modulator divides the second bit stream (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ) and the third bit stream (B 1 B 2 ... B N / 4 ) and each padding bit
  • the bit information with serial number j in the message constitutes a binary bit sequence.
  • the modulator sets the serial number in (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ), (B 1 B 2 ... B N / 4 ), and each padding bit information (XXX ...
  • the second target symbol includes second M-bit information (X X A N / 4 + 1 B 1 ), and a sequence number 2 A N / 4 + 2 , B 2 and X are modulated into another second target symbol, the second target symbol is (X X A N / 4 + 2 B 2 ), and so on, and N / 4 second target symbols can be obtained
  • Each second target symbol includes second M-bit information.
  • the modulation method of the target symbol obtained at the third time, the fourth time, and the subsequent time in FIG. 4 is similar to the modulation method of the first target bit stream corresponding to the first time in FIG. 4 described above, and is not repeated here. .
  • the first target bitstream may further include a fourth bitstream (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ), where the fourth bit stream corresponds to the second coded code block. It should be noted that the fourth bit stream may also correspond to other encoding code blocks.
  • the modulator pairs the first bit stream (A 1 A 2 ... A N / 4 ), the fourth bit stream (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ), and each padding bit information (XXX ... X ) To obtain one of the first target symbols.
  • the first M-bit information of the first target symbol is (XXA 1 B 3N / 4 + 1 ), and the first M-bit information of the other first target symbol (X X A 2 B 3N / 4 + 2 ), and so on, to obtain N / 4 first target symbols, and each first target symbol includes first M-bit information.
  • the second target bit stream also includes a fifth bit stream (C 3N / 4 + 1 C 3N / 4 + 2 ... C N ), where the fifth bit stream corresponds to the third coded block.
  • the modulator performs the second bit stream (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ), the third bit stream (B 1 B 2 ... B N / 4 ), and the fifth bit stream Modulation (C 3N / 4 + 1 C 3N / 4 + 2 ... C N ) and stuffing bit information (XXX... X) to perform modulation to obtain one of the second target symbols, where the second target symbol is second M-bit information ( XA N / 4 + 1 B 1 C 3N / 4 + 1 ), another second M-bit information (X A N / 4 + 2 B 2 C 3N / 4 + 2 ), and so on, can get N / 4th Two target symbols, each of which includes second M-bit information.
  • the modulation method of the target symbol obtained at the third time, the fourth time, and the subsequent time in FIG. 5 is similar to the modulation method of the first target bit stream corresponding to the first time in FIG. 5 described above, and details are not described herein.
  • the sending device sends a first target symbol and a second target symbol.
  • the transmitting device transmits N / m first target symbols at a first moment and N / m second target symbols at a second moment, respectively.
  • the sending device may send the first target symbol and the second target symbol through a wireless channel, respectively.
  • steps 301 to 306 in this embodiment are performed by the sending device.
  • the receiving device receives the first target symbol and the second target symbol sent by the sending device.
  • the receiving device respectively receives N / m first target symbols sent by the sending device at a first moment, wherein each first target symbol includes first M-bit information, and the first M-bit information includes a first The first bit information of the bitstream, and at least one padding bit information.
  • each second target symbol includes second M-bit information
  • the second M-bit information includes the The second bit information and the third bit information of the second coded code block, that is, each second M bit information includes two bit information, and the two bit information respectively correspond to different coded code blocks.
  • the receiving device may receive the first target symbol and the second target symbol respectively sent by the sending device through a wireless channel.
  • the demodulator demodulates the soft information of the first bit information.
  • the demodulator receives a first target symbol and a second target symbol to be demodulated.
  • the demodulator acquires the first M-bit information, and the demodulator demodulates the soft information of the first bit information based on the padding information in the first M-bit information. For example, when the first M-bit information obtained by the demodulator is (X X X A 1 ), the demodulator demodulates the soft information of the first bit information A 1 based on the stuffing bit information (X X X), and the first M-bit information is ( XXXA 2 ), the demodulator demodulates soft information of A 2 based on stuffing bit information (X X X), and so on.
  • the demodulator demodulates (A 1 to A N / 4 ) respectively to obtain soft information of the bit sequence (A 1 A 2 ... A N / 4 ).
  • the demodulator After the demodulator acquires the second M-bit information, the demodulator demodulates the soft information of the second-bit information of the second M-bit information. For example, when the second M-bit information obtained by the demodulator is (X X A N / 4 + 1 B 1 ), the demodulator demodulates the software of the second bit information A N / 4 + 1 based on the stuffing bit information (X X). information.
  • the demodulator demodulates the soft information of A N / 4 + 2 based on the stuffing bit information (X X), and so on to obtain the bit sequence (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ).
  • the demodulator can demodulate the bit sequence (A 1 A 2 ... A N / 4 ) of the first bit stream of the first coded code block from the first M bit information and the second M bit information. And the soft information of the bit sequence (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ) of the second bit stream. The demodulator can also demodulate the bit sequence (A N / 2 + 1 A N / 2 + 2 ... A 3N / 4 ) of the third bit stream of the first coded code block from the third M-bit information.
  • the demodulator demodulates the soft information of the first bit information A 1 based on the stuffing bit information (X X), and analogy.
  • the demodulator demodulates the soft information (A 1 to A N / 4 ) respectively, so as to obtain the soft information of the bit sequence (A 1 A 2 ... A N / 4 ).
  • the demodulator demodulates the soft information of the first bit information A N / 4 + 1 based on the stuffing bit information (X), and so on.
  • the demodulator demodulates the soft information (A N / 4 + 1 to A N / 2 ) respectively, so as to obtain the soft information of the bit sequence (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ).
  • the inverse bit delayer performs inverse delay on the soft information of the bit sequence of the first encoded code block.
  • the inverse bit delayer obtains the soft information of the bit sequences corresponding to the m bit streams of the first encoded code block from the demodulator. Then, the soft information of the bit sequence corresponding to the ith bit stream of the first coded code block is inversely delayed, and then sent to the deinterleaver respectively. For example, the inverse bit delayer sends the soft information of the bit sequence (A 1 A 2 ... A N / 4 ) corresponding to the first bit stream to the first deinterleaver, and sends the bit sequence corresponding to the second bit stream (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ) is sent to the second deinterleaver, and so on.
  • the deinterleaver deinterleaves the soft information of the bit sequence of the first encoded code block.
  • the deinterleaver After the deinterleaver obtains the soft information of the bit sequence corresponding to each bit stream of the first encoded code block from the inverse bit delayer. De-interleave the soft information of each bit sequence separately to obtain the soft information of the m bit streams of the first coded block. For example, the first deinterleaver deinterleaves the soft information of the first bit sequence to obtain the soft information of the first bit stream, and the second deinterleaver deinterleaves the soft information of the second bit sequence to obtain the first Soft information of 2 bit streams, and so on.
  • step 309 may be performed first, and then step 310 may be performed, or step 310 may be performed first, and then step 309 may be performed, which is not limited herein.
  • the parallel-to-serial converter performs serial conversion on the soft information of the first encoded code block.
  • the parallel-to-serial converter obtains the soft information of the m bit streams of the first encoded code block from the deinterleaver, and then converts the soft information of the m bit streams into a serial soft information sequence, that is, obtains the first encoded code. Soft information sequence of the block.
  • the polarization decoder decodes the soft information sequence of the first encoded code block.
  • the polarization decoder obtains the soft information sequence of the first encoded code block from the parallel-to-serial converter, and decodes the soft information sequence of the first encoded code block to obtain a first source bit sequence.
  • the polarization decoder may use a sequence continuous deletion algorithm (SCL) or a cyclic redundancy check auxiliary sequence continuous deletion algorithm (cyclic-redundancy check-aided-SCL, CA-SCL) to encode the first code.
  • SCL sequence continuous deletion algorithm
  • CA-SCL cyclic redundancy check auxiliary sequence continuous deletion algorithm
  • the soft information sequence of the code block is decoded to obtain the first information bit sequence.
  • the polar decoder can also use other algorithms to decode the soft information sequence of the first coded code block. limited.
  • the polarization encoder performs polarization code encoding on the first information bit sequence.
  • the polarization encoder re-polarizes the first information bit sequence to obtain a first codeword sequence.
  • the first codeword sequence may be (A 1 A 2 ... A N ).
  • the demodulator demodulates the soft information of the third bit information.
  • the demodulator demodulates the soft information of the third bit information based on the decoded first codeword sequence.
  • the demodulator determines the third bit information of the second encoded code block from the second target symbol, and demodulates the soft information of the third bit information based on the first codeword sequence and the padding bit information. For example, when the second M-bit information is (X X A N / 4 + 1 B 1 ), the demodulator demodulates the third bit information B based on A N / 4 + 1 in the first codeword sequence and the stuffing bit information X.
  • the soft information of 1 that is, the soft information of B 1 is demodulated based on (X X A N / 4 + 1 ).
  • the demodulator is based on A N / 4 + 2 in the first codeword sequence and the soft-bit information X to demodulate the softness of B 2 .
  • the demodulator demodulates the soft information of B N / 4 + 1 based on (X A N / 2 + 1 ), and so on. To obtain the soft information of (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ).
  • the demodulator is also based on (A 3N / 4 + 1 ) demodulation (B N / 2 +1 ) soft information, so as to obtain (B N / 2 + 1 B N / 2 + 2 ... B 3N / 4 ).
  • the demodulator can demodulate the soft information sequence corresponding to the second coded code block based on the first codeword sequence of the first coded code block that has been decoded and the padding information, that is, based on the The first codeword sequence of the coded code block is demodulated to obtain (B 1 B 2 ... B N / 4 ), (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ), (B N / 2 + 1 B N / 2 + 2 ... B 3N / 4 ) and (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ) respectively correspond to soft information.
  • each bit information in the bit sequence (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ) in this embodiment may be obtained by parallel demodulation.
  • the demodulator may further demodulate the soft information of the fourth bit information based on the first codeword sequence and the padding bit information, such as a first M-bit information
  • the fourth bit information is B 3N / 4 + 1
  • the demodulator can also demodulate the soft information of B 3N / 4 + 1 based on (X X A 1 )
  • the demodulator can also demodulate the soft information of B 3N / 4 + 2 based on (X X A 2 ).
  • the soft information of (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ) can be obtained.
  • demodulation (B 1 B 2 ... B N / 4 ), (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ), and (B N / 2 + 1 B N / 2 + 2 ... B
  • the soft information corresponding to 3N / 4 ) is similar to the foregoing, and is not repeated here.
  • the demodulator may demodulate the soft information of the bit information corresponding to the second coded code block based on the first codeword sequence of the first coded code block that has been decoded, so as to obtain the second code. Soft information of the bit sequence of each bit stream of the code block.
  • the inverse bit delayer performs inverse delay on the soft information of the bit sequence of the second encoded code block.
  • the deinterleaver deinterleaves the soft information of the bit sequence of the second coded code block.
  • the parallel-to-serial converter performs serial conversion on the soft information of the second coded code block.
  • the polarization decoder decodes the soft information sequence of the second encoded code block.
  • steps 315 to 318 are similar to the foregoing steps 319 to 312, and details are not described herein again.
  • the polarization encoder performs polarization code encoding on the second information bit sequence.
  • the polarization encoder re-polarizes the second information bit sequence of the second encoding code block to obtain a second codeword sequence.
  • the second codeword sequence may be (B 1 B 2 ... B N ). It should be noted that the second information bit sequence is obtained by decoding the soft information sequence of the second encoded code block.
  • the demodulator demodulates the soft information of the fifth bit information.
  • the demodulator demodulates the soft information of the fifth bit information based on the decoded first codeword sequence and the second codeword sequence.
  • the second M-bit information may further include fifth bit information of the third coded block, where the fifth bit information and the second bit information have the same sequence number in the bit stream to which they belong.
  • a second M bit information is (X A N / 4 + 1 B 1 C 3N / 4 + 1 )
  • C 3N / 4 + 1 is the fifth bit information
  • the demodulator is based on the first codeword sequence A N / 4 + 1
  • X demodulate the soft information of the fifth bit information C 3N / 4 + 1 , that is, based on (X A N / 4 + 1 B 1 ) demodulation C 3N / 4 + 1 soft information.
  • the soft information of other bit information of the third encoding code block can also be demodulated based on the first codeword sequence of the first encoding code block and the second codeword sequence of the second encoding code block. Therefore, soft information of a bit sequence corresponding to each bit stream of the third encoded code block can be obtained.
  • the demodulator may demodulate the soft information of the bit information of the currently coded code block to be decoded based on the codeword sequence corresponding to the coded code block that has been decoded, thereby obtaining M coded codes. A sequence of soft information for each coded block in the block.
  • steps 307 to 320 in this embodiment are performed by the receiving device.
  • the sending device separately encodes different information bit streams to generate different coded code blocks, divides each coded code block into several bit streams, and respectively passes corresponding delays, and then divides the different coded code blocks into The bit stream that has undergone the same delay is modulated on the target symbol, so that the target symbol includes bit information from at least two different coded code blocks.
  • the receiving device After receiving the target symbol, the receiving device performs serial demodulation on the bit information to be decoded according to the decoded codeword sequence and padding bit information. Therefore, in this embodiment, the already decoded codeword sequence is used to demodulate the soft information of the bit information of the code block that is currently to be decoded, so that the loss of mutual information between the bit information can be reduced.
  • FIG. 6 is a schematic diagram of another embodiment of an information modulation and demodulation method according to an embodiment of the present application.
  • the information modulation and demodulation method provided by the embodiment of the present application may include the following steps:
  • a polarization encoder performs polarization code encoding on a source bit sequence.
  • the polar encoder obtains K source bit sequences from the source device, where K is M / 2.
  • the polarization encoder performs polarization code encoding on the K source bit sequences and the polarization encoder described in step 301 of FIG. 3 performs polarization on the M source bit sequences respectively.
  • the encoding codes are similar and will not be repeated here.
  • K may also be M / 3, or is not limited herein. This embodiment only uses K as M / 2 as an example for description.
  • the serial-to-parallel converter divides the K coded code blocks and sends the divided bit stream to the interleaver.
  • the serial-to-parallel converter obtains K codeword sequences corresponding to the K coded code blocks from the polar encoder.
  • serial-to-parallel converter divides each codeword sequence of K codeword sequences into m bit streams of length N / m.
  • the serial-to-parallel converter described in step 302 of FIG. 3 divides each codeword sequence of the M codeword sequence into m bit streams of length N / m, respectively. Similar, will not repeat them here.
  • serial-to-parallel converter sends the segmented bit stream to the interleaver similar to that described in step 302 of FIG. 3, and is not repeated here.
  • the interleaver interleaves the bit stream.
  • the bit delayer delays the bit stream.
  • steps 603 to 604 are similar to steps 303 to 304 corresponding to the foregoing FIG. 3, and details are not described herein again.
  • step 603 and step 604 may be performed first, and step 604 and step 603 may be performed first, which is not limited herein.
  • the modulator modulates the first target bit stream and the second target bit stream.
  • the modulator obtains a first target bit stream and a second target bit stream sent by the bit delayer, and modulates the first target bit stream and the second target bit stream.
  • the modulator modulates the first target bit stream to obtain a first target symbol, where the first target symbol includes first M-bit information, the first M-bit information includes first bit information of the first bit stream, and at least one padding bit information.
  • the modulator modulates the second target bit stream to obtain a second target symbol, where the second target symbol includes second M-bit information, the second M-bit information includes at least the second bit information of the second bit stream, and the third bit stream Three-bit information, that is, the second M-bit information includes at least two bits of information, where the two bits of information correspond to different coding code blocks, respectively.
  • the following describes the modulation bit stream involved in this implementation with 16QAM, two encoding code blocks, and a code length of each encoding code block being N.
  • the two coded code blocks are an A coded code block and a B coded code block, respectively.
  • FIG. 7 is a schematic diagram of another embodiment provided by the embodiment of the present application.
  • the modulator obtains a first target bit stream sent by a bit delayer at a first moment, where the first target bit The stream includes a bit stream (A 1 A 2 ... A N / 4 ) and (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ) of the first coded code block.
  • the modulator modulates (A 1 A 2 ... A N / 4 ), (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ) and stuffing bit information (XXX... X) to obtain N / 4 First target symbols, where each first target symbol includes first M-bit information. Specifically, the modulator adds (A 1 A 2 ... A N / 4 ), (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ), and bit information of sequence number j in each padding bit information. Make up a binary bit sequence.
  • the modulator divides the bit stream (A 1 A 2 ... A N / 4 ), (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ), and A with the serial number 1 in (X X X... X) 1 , A N / 4 + 1 and X modulation into a first target symbol, the first M-bit information included in the first target symbol is (X X A 1 A N / 4 + 1 ), and A 2 with a serial number of 2 , A N / 4 + 2 and X modulation are another first target symbol, and the first M-bit information included in the first target symbol is (X X A 2 A N / 4 + 2 ), and so on, and N / 4 can be obtained.
  • First target symbols, each first target symbol includes first M-bit information.
  • the modulator obtains a second target bitstream at a second moment, where the second target bitstream includes a second bitstream of the first coded code block (A N / 2 + 1 A N / 2 + 2 ... A 3N / 4 ) And (A 3N / 4 + 1 A 3N / 4 + 2 ... A N ), and the third bit stream (B 1 B 2 ... B N / 4 ) and (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ).
  • Modulator pair (A N / 2 + 1 A N / 2 + 2 ... A 3N / 4 ), (A 3N / 4 + 1 A 3N / 4 + 2 ... A N ), (B 1 B 2 ... B N / 4 ) and (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ) to obtain N / 4 second target symbols, where the second target symbol includes second M-bit information.
  • the modulator will be (A N / 2 + 1 A N / 2 + 2 ... A 3N / 4 ), (A 3N / 4 + 1 A 3N / 4 + 2 ... A N ), (B 1 B 2 ... B N / 4 ) and (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ) bit information with a sequence number j constitute a binary bit sequence.
  • the modulator will be (A N / 2 + 1 A N / 2 + 2 ... A 3N / 4 ), (A 3N / 4 + 1 A 3N / 4 + 2 ... A N ), (B 1 B 2 ... B N / 4 ) and (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ) A N / 2 + 1 , A 3N / 4 + 1 , B 1 and B N / 4 +1 modulation into a second target symbol, where the second target symbol includes the second M-bit information (A N / 2 + 1 A 3N / 4 + 1 B 1 B N / 4 + 1 ), and the serial number is 2 A N / 2 + 2 A 3N / 4 + 2 B 2 and B N / 4 + 2 are modulated into another second target symbol, where the second target symbol includes second M-bit information (A N / 2 + 2 A 3N / 4 + 2 B 2 B N / 4 + 2 ), and so on, to
  • the modulator may also obtain the third target bit stream from the bit delayer at the third moment, and the target bit stream obtained from the bit delayer at other times and the aforementioned modulated first target bit stream. The method is similar and will not be repeated here.
  • bit stream (B N / 2 + 1 B N / 2 + 2 ... B 3N / 4 ), (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ), it also includes the bit stream or termination padding bits of other coded blocks.
  • the sending device sends the first target symbol and the second target symbol to the receiving device.
  • steps 601 to 606 in this embodiment are executed by the sending device.
  • the receiving device receives the first target symbol and the second target symbol sent by the sending device.
  • steps 606 to 607 are similar to steps 306 to 307 corresponding to the foregoing FIG. 3, and details are not described herein again.
  • the demodulator demodulates the soft information of the first bit information.
  • the demodulator receives a first target symbol and a second target symbol to be demodulated.
  • the demodulator acquires the first M-bit information, and the demodulator demodulates the soft information of the first bit information based on the padding information in the first M-bit information. For example, when the first M-bit information obtained by the demodulator is (X X A 1 A N / 4 + 1 ), the demodulator demodulates the soft information of the first bit information A 1 based on the stuffing bit information (X X), and based on The stuffing bit information (XX) demodulates the soft information of the first bit information A N / 4 + 1 .
  • the demodulator demodulates the soft information of A 2 based on the stuffing bit information (X X), and demodulates A N / 4 based on the stuffing bit information (X X). +2 soft information, and so on.
  • the demodulator demodulates the soft information of (A 1 to A N / 4 ) respectively, so as to obtain the bit sequence (A 1 A 2 ... A N / 4 ) and (A N / 4 + 1 A N / 4 + 2 ... A N / 2 ) respectively corresponding soft information.
  • the demodulator After the demodulator acquires the second M-bit information, the demodulator demodulates the soft information of the second-bit information of the second M-bit information.
  • the demodulator can demodulate the soft information of the bit information belonging to the first coded code block in the second M-bit information based on the parallel demodulation algorithm to obtain a bit sequence (A N / 2 + 1 A N / 2 + 2 ... A 3N / 4 ) and (A 3N / 4 + 1 A 3N / 4 + 2 ... A N ) respectively.
  • the inverse bit delayer performs inverse delay on the soft information of the bit sequence of the first encoded code block.
  • the deinterleaver deinterleaves the soft information of the bit sequence of the first encoded code block.
  • step 609 and step 610 may be performed first, and step 610 and step 609 may be performed first, which is not limited herein.
  • the parallel-to-serial converter performs serial conversion on the soft information of the first encoded code block.
  • the polarization decoder decodes the soft information sequence of the first encoded code block.
  • the polarization encoder performs polarization code encoding on the first information bit sequence.
  • steps 609 to 613 are similar to steps 309 to 313 corresponding to the foregoing FIG. 3, and details are not described herein again.
  • the demodulator demodulates the soft information of the third bit information.
  • the demodulator demodulates the soft information of the third bit information based on the decoded first codeword sequence.
  • the demodulator demodulates the soft information of the third bit information of the second coded code block based on the first codeword sequence. For example, when the second M-bit information is (A N / 2 + 1 A 3N / 4 + 1 B 1 B N / 4 + 1 ), the demodulator is based on A N / 2 + 1 and A 3N / 4 + 1 demodulates the soft information of the third bit information B 1 and the soft information of B N / 4 + 1 . That is, soft information based on (A N / 2 + 1 A 3N / 4 + 1 ) to demodulate B 1 and soft software based on (A N / 2 + 1 A 3N / 4 + 1 ) to demodulate B N / 4 + 1 information.
  • the demodulator is based on the first codeword sequence A N / 2 + 2 and A 3N / 4 + 2 demodulate the third bit information B 2 and B N / 4 + 2 , that is, based on (A N / 2 + 1 A 3N / 4 + 1 ) demodulated soft information of B 2 , and based on (A N / 2 +1 A 3N / 4 + 1 ) demodulate the soft information of B N / 4 + 2 .
  • the soft information corresponding to the bit sequence (B 1 B 2 ... B N / 4 ) and (B N / 4 + 1 B N / 4 + 2 ... B N / 2 ) can be demodulated. It can be understood that, in this embodiment, (B N / 2 + 1 B N / 2 + 2 ... B 3N / 4 ) and (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ) respectively Information can be demodulated in parallel. That is, (B 1 B 2 ... B N / 4 ), (B N / 4 + 1 B N / 4 + 2 ...) of the second encoded code block are demodulated based on the bit sequence of the first encoded code block that has been decoded. B N / 2 ), (B N / 2 + 1 B N / 2 + 2 ... B 3N / 4 ), and (B 3N / 4 + 1 B 3N / 4 + 2 ... B N ) respectively correspond to soft information.
  • the demodulator may perform serial demodulation on the bit information of the currently coded code block to be decoded based on the codeword sequence corresponding to the decoded code block, thereby obtaining M codes.
  • steps 607 to 614 in this embodiment are performed by the receiving device.
  • the sending device separately encodes different information bit streams to generate different coded code blocks, divides each coded code block into several bit streams, and respectively passes corresponding delays, and then divides the different coded code blocks into The bit stream that has undergone the same delay is modulated on the target symbol, so that the target symbol includes bit information from at least two different coded code blocks.
  • the receiving device After receiving the target symbol, the receiving device performs serial demodulation on the bit information to be decoded according to the decoded codeword sequence and padding bit information. Therefore, in this embodiment, the already decoded codeword sequence is used to demodulate the soft information of the bit information of the code block that is currently to be decoded, so that the loss of mutual information between the bit information can be reduced.
  • FIG. 8 is a schematic block diagram of a sending device according to an embodiment of the present application.
  • the sending device includes:
  • a modulation unit 801 is configured to modulate a first target bit stream to obtain a first target symbol.
  • the first target symbol includes first M-bit information
  • the first target bit stream includes a first bit of a first encoded code block.
  • a stream, the first M bit information includes first bit information of the first bit stream, and at least one padding bit information, the padding bit information is known bit information, and M is an integer greater than 1;
  • the modulation unit 801 is further configured to modulate a second target bit stream to obtain a second target symbol.
  • the second target symbol includes second M-bit information
  • the second target bit stream includes the first encoded code block.
  • a second bit stream of the second bit stream and a third bit stream of the second code block, the second M bit information includes at least the second bit information of the second bit stream and the third bit information of the third bit stream ;
  • the sending unit 802 is configured to send the first target symbol to the receiving device at a first time and the second target symbol at a second time, where the first time is before the second time.
  • the sending device further includes:
  • a dividing unit 803 configured to divide a codeword sequence corresponding to the first coded code block by the same length to obtain a first divided stream, where the first divided stream includes the first bit stream and the second bit stream Bitstream.
  • the dividing unit 803 is further configured to divide the codeword sequence corresponding to the second encoded code block by the same length to obtain a second divided stream, where the second divided stream includes the third bit stream.
  • the second M-bit information includes the padding bit information.
  • the first M-bit information further includes fourth bit information, and the fourth bit information corresponds to a fourth bit stream of the second encoded code block.
  • the first M-bit information and the second M-bit information correspond to M coding code blocks, respectively;
  • the first M-bit information and the second M-bit information respectively correspond to M / 2 encoded code blocks, and when the first M-bit information and the second M-bit information correspond to M / 2 encoded code blocks, respectively , M is an even number.
  • the modulation unit 801 modulates the first target bit stream and the second target bit stream, respectively, to obtain first M bit information and second M bit information, where the first M bit information includes the first M bit information and the second M bit information.
  • One bit of information, and at least one stuffing bit the second M-bit information includes at least the second bit information of the second bit stream, and the third bit information of the third bit stream, wherein the second target symbol includes at least two data from Bit information of different coding code blocks, so that the receiving device decodes the soft information of the first coding code block corresponding to the first bit information to obtain a first information bit sequence, and then demodulate the second coding code based on the first information bit sequence Soft information of the third bit information of the block. Therefore, the information bit sequence corresponding to the decoded bit information can be used to demodulate the soft information of the undecoded bit information and reduce the loss of mutual information between the bit information.
  • the sending device provided in the embodiment of the present application is described above, and the receiving device provided in the embodiment of the present application is described below.
  • FIG. 9 is a schematic block diagram of a receiving device according to an embodiment of the present application.
  • the receiving device includes:
  • the receiving unit 901 is configured to receive a first target symbol sent by a sending device at a first moment, where the first target symbol includes first M-bit information, and the first M-bit information includes a first bit of a first encoding code block.
  • the first bit information of the stream, and at least one padding bit information, the padding bit information is known bit information, and M is an integer greater than 1;
  • a demodulation unit 902 is configured to demodulate the soft information of the first bit information based on the at least one padding bit information, and the soft information of the first bit information is included in a soft information sequence of the first encoded code block;
  • the receiving unit 901 is further configured to receive a second target symbol sent by the sending device at a second moment.
  • the second target symbol includes second M-bit information, and the second M-bit information includes at least the first M-bit information.
  • the demodulation unit 902 is further configured to demodulate the soft information of the second bit information, and the soft information of the second bit information is included in a soft information sequence of the first encoded code block;
  • a decoding unit 903 is configured to decode the soft information sequence of the first encoded code block to obtain a first information bit sequence, where the first information bit sequence is used to demodulate the soft information of the third bit information. information.
  • the receiving device further includes:
  • An encoding unit 904 configured to perform polarization code encoding on the first information bit sequence to obtain a first codeword sequence
  • the demodulation unit 902 is further configured to demodulate the soft information of the third bit information based on the first codeword sequence.
  • the soft information of the third bit information is included in the soft information of the second encoded code block. sequence.
  • the second M-bit information includes the padding bit information
  • the demodulation unit 902 is specifically configured to demodulate the third bit based on the padding bit information and the first codeword sequence. Soft information of bit information.
  • the first M-bit information further includes fourth bit information
  • the demodulation unit 902 is specifically configured to demodulate the information based on the padding bit information and the first codeword sequence.
  • Soft information of fourth bit information the fourth bit information being included in a fourth bit stream of the second encoded code block.
  • the second M-bit information includes fifth bit information
  • the fifth bit information corresponds to a third coded code block
  • the demodulation unit 902 is further configured to be based on the first code
  • the word sequence and the second codeword sequence demodulate the soft information of the fifth bit information, where the fifth bit information and the second bit information have the same sequence number in the bit stream to which they belong, and the second code
  • the word sequence is a codeword sequence obtained by polar code encoding of a second information bit sequence
  • the second information bit sequence is an information bit sequence corresponding to the second encoded code block.
  • the second M-bit information includes padding bit information
  • the demodulation unit 902 is specifically configured to be based on the first codeword sequence, the second codeword sequence, and the padding.
  • the bit information demodulates the soft information of the fifth bit information.
  • the decoding unit 903 is further configured to decode the soft information sequence of the second encoded code block to obtain the second information bit sequence;
  • the encoding unit 904 is further configured to perform polarization code encoding on the second information bit sequence to obtain the second codeword sequence.
  • the decoding unit 903 is specifically configured to decode the soft information sequence of the first encoded code block by using a sequence continuous deletion algorithm SCL or a cyclic redundancy check auxiliary sequence continuous deletion algorithm CA-SCL to obtain the first An information bit sequence.
  • the first M-bit information and the second M-bit information respectively correspond to M coding code blocks; or, the first M-bit information and the second M-bit information are respectively Corresponding to M / 2 encoded code blocks, when the first M-bit information and the second M-bit information correspond to M / 2 encoded code blocks, respectively, the M is an even number.
  • the receiving unit 901 receives a first target symbol and a second target symbol, respectively.
  • the first target symbol includes first M-bit information
  • the second target symbol includes second M-bit information.
  • the first M-bit information includes The first bit information of the first bit stream and at least one padding bit information.
  • the second M bit information includes at least the second bit information of the second bit stream and the third bit information of the third bit stream.
  • the decoding unit 903 pairs The soft information of the first encoded code block corresponding to the first bit information is decoded to obtain a first information bit sequence, and the encoding unit 904 performs polarization code encoding on the first information bit sequence to obtain a first codeword sequence. Therefore, in the embodiment of the present application, the demodulation unit 902 may use the first codeword sequence corresponding to the decoded bit information to demodulate the soft information of the undecoded bit information, and reduce the loss of mutual information between the bit information. .
  • FIG. 10 is a schematic diagram of a hardware structure of a sending device according to an embodiment of the present application.
  • the sending device includes:
  • the transceiver may include a receiver and a transmitter, and the memory 1050 may include a read-only memory and / or a random access memory, and provide operation instructions and data to the processor 1010.
  • a part of the memory 1050 may further include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory and the processor may be independently connected through a bus or an interface, or may be integrated together.
  • the memory 1050 stores the following elements, executable modules or data structures, or their subsets, or their extended sets.
  • a corresponding operation is performed by calling an operation instruction stored in the memory 1050 (the operation instruction may be stored in an operating system).
  • the processor 1010 controls operations of the sending device, and the processor 1010 may also be referred to as a CPU (Central Processing Unit).
  • the memory 1050 may include a read-only memory and a random access memory, and provide instructions and data to the processor 1010.
  • a part of the memory 1050 may further include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • various components of the transmitting device are coupled together through a bus system 1020.
  • the bus system 1020 may include a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, various buses are marked as the bus system 1020 in the figure.
  • the method disclosed in the foregoing embodiment of the present application may be applied to the processor 1010, or implemented by the processor 1010.
  • the processor 1010 may be an integrated circuit chip and has a signal processing capability. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in the processor 1010 or an instruction in the form of software.
  • the processor 1010 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware. Components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA off-the-shelf programmable gate array
  • Various methods, steps, and logical block diagrams disclosed in the embodiments of the present application can be implemented or executed.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the steps of the method disclosed in combination with the embodiments of the present application may be directly implemented by a hardware decoding processor, or may be performed by using a combination of hardware and software modules in the decoding processor.
  • the software module may be located in a mature storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, and the like.
  • the storage medium is located in the memory 1050.
  • the memory 1050 may be a physically independent unit or integrated with the processor 1010.
  • the processor 1010 reads information in the memory 1050 and completes the steps of the foregoing method in combination with its hardware.
  • the transceiver 1030 may be respectively configured to perform the operation steps related to receiving and sending on the sending device side of the embodiment corresponding to FIG. 3 and the embodiment corresponding to FIG. 6. Or it is used to perform the steps of sending and receiving data on the sending device side in other optional embodiments.
  • the processor 1010 may be respectively configured to execute the steps of the data processing on the sending device side in the embodiment corresponding to FIG. 3 and the embodiment corresponding to FIG. 6. Or it is used to perform the steps of processing data on the sending device side in other optional embodiments.
  • FIG. 11 is a schematic diagram of a hardware structure of a receiving device according to an embodiment of the present application.
  • the receiving device includes at least one processor 1110, a memory 1150, and a transceiver 1130.
  • the transceiver may include a receiver and a transmitter, and the memory 1150 may include a read-only memory and / or a random access memory, and provide operation instructions and data to the processor 1110.
  • a part of the memory 1150 may further include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory and the processor may be independently connected through a bus or an interface, or may be integrated together.
  • the corresponding functional structures of at least one processor 1110, memory 1150, and transceiver 1130 are similar to those described in the foregoing embodiment corresponding to FIG. 10, and are not repeated here.
  • the transceiver 1130 may be respectively configured to perform the operation steps related to receiving and sending on the receiving device side of the embodiment corresponding to FIG. 3 and the embodiment corresponding to FIG. 6. Or used to perform the steps of sending and receiving data on the receiving device side in other optional embodiments.
  • the processor 1110 may be respectively configured to execute the steps of receiving device-side data processing in the embodiment corresponding to FIG. 3 and the embodiment corresponding to FIG. 6. Or it is used to perform the steps of receiving device-side data processing in other optional embodiments.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the integrated unit When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially a part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium. , Including a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.
  • the foregoing storage media include: U disks, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or compact discs, and other media that can store program codes .

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Abstract

本申请实施例提供一种信息调制解调方法与装置，本申请实施例方法包括：发送设备调制第一目标比特流，以得到第一目标符号，第一目标符号包括第一M比特信息，第一M比特信息包括第一比特流的第一比特信息，以及至少一个填充比特信息；发送设备调制第二目标比特流，以得到第二目标符号，第二目标符号包括第二M比特信息，第二M比特信息至少包括第二比特流的第二比特信息，以及第三比特流的第三比特信息；发送设备向接收设备发送第一目标符号和第二目标符号，第一比特信息的软信息和第二比特信息的软信息包含于第一编码码块的软信息序列，第一编码码块的软信息序列用于译码得到第一信息比特序列，第一信息比特序列用于解调第三比特信息的软信息。

Description

信息调制解调方法与装置
本申请要求于2018年09月11日提交中国专利局、申请号为201811058027.0、发明名称为“信息调制解调方法与装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，尤其涉及一种信息调制解调方法与装置。
背景技术
极化码(Polar Codes)是一种可达二进制输入离散无记忆信道容量的可构造性信道编码方式，在极化码编码中，通过采用信道合并和分割操作，所得子信道均为无噪或者全噪信道。
目前极化编码调制框架主要是比特交织极化编码调制(bit interleaver polar coded modulation，BIPCM)，比特交织极化编码调制中，发送设备通过引入比特交织器消除比特之间的相关性，再将编码器与调制器简单级联，然后将同一编码码块的比特流附和在同一个发送符号向接收设备发送，接收设备从发送设备获取到接收符号之后，采用并行解调相同编码码块的比特流，然后将解调后的比特流送入极化码译码器进行译码，得到译码结果。
在接收设备对同一编码码块的比特流采用并行解调，然后将解调后的比特流送入极化码译码器进行译码，得到译码结果，其中，对同一编码码块的比特流进行并行解调会造成比特流之间的互信息损失，从而造成系统性能的下降。
发明内容
本申请实施例提供了一种信息调制解调方法与装置，用于接收设备使用已译码的码字序列对未解调的比特信息进行串行解调，减小比特流之间互信息的损失，提升通信系统的性能。
本申请实施例第一方面提供一种信息调制方法，包括：
发送设备调制第一目标比特流，以得到第一目标符号，所述第一目标符号包括第一M比特信息，所述第一目标比特流包括第一编码码块的第一比特流，所述第一M比特信息包括所述第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；所述发送设备调制第二目标比特流，以得到第二目标符号，所述第二目标符号包括第二M比特信息，所述第二目标比特流包括所述第一编码码块的第二比特流以及第二编码码块的第三比特流，所述第二M比特信息至少包括所述第二比特流的第二比特信息，以及所述第三比特流的第三比特信息；所述发送设备在第一时刻向接收设备发送所述第一目标符号以及在第二时刻发送所述第二目标符号，所述第一时刻在所述第二时刻之前。由第一方面可见，第二目标符号至少包括两个来自不同编码码块的比特信息，从而可以使得接收设备使用已译码的比特信息对应的信息比特序列解调未译码的比特信息的软信息，减小比特信息之间的互信息的损失。
基于本申请实施例第一方面，本申请实施例第一方面的第一种实现方式中，所述发送设备调制第一目标比特流之前，所述方法包括：所述发送设备将所述第一编码码块对应的码字序列进行相同长度的分割，以得到第一分割流，所述第一分割流包括所述第一比特流 以及所述第二比特流。所述发送设备将所述第二编码码块对应的码字序列进行相同长度的分割，以得到第二分割流，所述第二分割流包括所述第三比特流。
基于本申请实施例第一方面以及第一方面的第一种实现方式，本申请实施例第一方面的第二种实现方式中，所述第二M比特信息包括所述填充比特信息。由第一方面的第二种实现方式可见，本申请实施例中，第二M比特信息中还可以包括填充比特信息，可以基于填充比特信息解调第一编码码块的比特信息的软信息，提高了解调比特信息的软信息的准确性。
基于本申请实施例第一方面以及第一方面的第一种实现方式至第一方面的第二种实现方式中的任一项，本申请实施例第一方面的第三种实现方式中，所述第一M比特信息还包括第四比特信息，所述第四比特信息对应所述第二编码码块的第四比特流。由第一方面的第三种实现方式，本申请实施例中，第一M比特信息还包括第四比特信息，可以基于已译码的第一码字序列解调第四比特信息的软信息，减小比特信息之间的互信息的损失。
基于本申请实施例第一方面以及第一方面的第一种实现方式至第一方面的第三种实现方式中的任一项，本申请实施例第一方面的第四种实现方式中,所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。由第一方面的第四种实现方式可见，本申请实施例中，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块，或者分别对应M/2个编码码块，提高了解调比特信息的软信息的准确性。
本申请实施例第二方面提供一种信息解调方法，包括：
接收设备在第一时刻接收发送设备发送的第一目标符号，所述第一目标符号包括第一M比特信息，所述第一M比特信息包括第一编码码块的第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；所述接收设备基于所述至少一个填充比特信息解调所述第一比特信息的软信息，所述第一比特信息的软信息包含于所述第一编码码块的软信息序列；所述接收设备在第二时刻接收所述发送设备发送的第二目标符号，所述第二目标符号包括第二M比特信息，所述第二M比特信息至少包括所述第一编码码块的第二比特流的第二比特信息，以及第二编码码块的第三比特流的第三比特信息；所述接收设备解调所述第二比特信息的软信息，所述第二比特信息的软信息包含于所述第一编码码块的软信息序列；所述接收设备对所述第一编码码块的软信息序列进行译码，以得到第一信息比特序列，所述第一信息比特序列用于解调所述第三比特信息的软信息。由第二方面可见，接收设备使用已译码的比特信息对应的信息比特序列解调未译码的比特信息的软信息，减小比特信息之间互信息的损失。
基于本申请实施例第二方面，本申请实施例第二方面的第一种实现方式中，所述方法还包括：所述接收设备对所述第一信息比特序列进行极化码编码，以得到第一码字序列；所述接收设备基于所述第一码字序列解调所述第三比特信息的软信息，所述第三比特信息的软信息包含于所述第二编码码块的软信息序列。由第二方面的第一种实现方式可见，本申请实施例中，可以基于已译码的第一编码码块解调未译码第三比特信息的软信息，减小了比特信息之间互信息的损失。
基于本申请实施例第二方面以及第二方面的第一种实现方式，本申请实施例第二方面的第二种实现方式中，所述第二M比特信息包括所述填充比特信息，所述接收设备基于所述第一码字序列解调所述第三比特信息的软信息包括：所述接收设备基于所述填充比特信息以及所述第一码字序列解调所述第三比特信息的软信息。由第二方面的第二种实现方式可见，本申请实施例中，可以基于填充比特信息以及已译码的码字序列解调未译码第三比特信息的软信息，减小了比特信息之间互信息的损失。
基于本申请实施例第二方面以及第二方面的第一种实现方式至第二方面的第二种实现方式中的任一项，本申请实施例第二方面的第三种实现方式中，所述第一M比特信息还包括第四比特信息，所述方法还包括：所述接收设备基于所述填充比特信息以及所述第一码字序列解调所述第四比特信息的软信息，所述第四比特信息包含于所述第二编码码块的第四比特流。由第二方面的第三种实现方式可见，本申请实施例中，可以基于填充比特信息以及已译码的码字序列解调未译码的第三比特信息的软信息，减小了比特信息之间互信息的损失。
基于本申请实施例第二方面以及第二方面的第一种实现方式至第二方面的第三种实现方式中的任一项，本申请实施例第二方面的第四种实现方式中，所述第二M比特信息包括第五比特信息，所述第五比特信息对应第三编码码块，所述方法还包括：所述接收设备基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息，所述第五比特信息与所述第二比特信息在各自所属的比特流中的位置序号相同，所述第二码字序列为第二信息比特序列极化码编码得到的码字序列，所述第二信息比特序列为所述第二编码码块对应的信息比特序列。由第二方面的第四种实现方式可见，本申请实施例中，可以基于已译码的码字序列解调后续需要译码的比特信息的软信息，减小了比特信息之间互信息的损失。
基于本申请实施例第二方面以及第二方面的第一种实现方式至第二方面的第四种实现方式中的任一项，本申请实施例第二方面的第五种实现方式中，所述第二M比特信息包括填充比特信息，所述接收设备基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息包括：所述接收设备基于所述第一码字序列、所述第二码字序列以及所述填充比特信息解调所述第五比特信息的软信息。由第二方面的第五种实现方式可见，本申请实施例中，可以基于填充比特信息以及已译码的码字序列解调后续需要译码的比特信息的软信息，减小了比特信息之间互信息的损失。
基于本申请实施例第二方面以及第二方面的第一种实现方式至第二方面的第五种实现方式中的任一项，本申请实施例第二方面的第六种实现方式中，所述接收设备基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息之前，所述方法还包括：所述接收设备对所述第二编码码块的软信息序列进行译码，以得到所述第二信息比特序列；所述接收设备对所述第二信息比特序列进行极化码编码，以得到所述第二码字序列。
基于本申请实施例第二方面以及第二方面的第一种实现方式至第二方面的第六种实现方式中的任一项，本申请实施例第二方面的第七种实现方式中，所述接收设备对所述第一编码码块的软信息序列进行译码，以得到第一信息比特序列包括：所述接收设备使用序列连续删除算法SCL或者循环冗余校验辅助序列连续删除算法CA-SCL对所述第一编码码块的软信息序列进行译码，以得到所述第一信息比特序列。
基于本申请实施例第二方面以及第二方面的第一种实现方式至第二方面的第七种实现方式中的任一项，本申请实施例第二方面的第八种实现方式中，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。由第一方面的第四种实现方式可见，本申请实施例中，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块，或者分别对应M/2个编码码块，提高了解调比特信息的软信息的准确性。
本申请实施例第三方面提供一种发送设备，所述发送设备包括：存储器、收发器和至少一个处理器，所述存储器中存储有指令；所述存储器、所述收发器和所述至少一个处理器通过线路连接；
所述至少一个处理器调用所述指令，执行第一方面在所述发送设备侧进行的消息处理或控制操作。
本申请实施例第四方面提供一种接收设备，所述接收设备包括：存储器、收发器和至少一个处理器，所述存储器中存储有指令；所述存储器、所述收发器和所述至少一个处理器通过线路连接；
所述至少一个处理器调用所述指令，执行第二方面在所述接收设备侧进行的消息处理或控制操作。
本申请实施例第五方面提供一种计算机可读存储介质，其特征在于，包括指令，当所述指令在计算机上运行时，使得计算机执行第一方面或第一方面任一可能实现方式的方法。
本申请实施例第六方面提供一种计算机可读存储介质，其特征在于，包括指令，当所述指令在计算机上运行时，使得计算机执行第二方面或第二方面任一可能实现方式的方法。
本申请实施例第七方面提供一种包含指令的计算机程序产品，其特征在于，当其在计算机上运行时，使得所述计算机执行第一方面或第一方面任一可能实现方式的方法。
本申请实施例第八方面提供一种包含指令的计算机程序产品，其特征在于，当其在计算机上运行时，使得所述计算机执行第二方面或第二方面任一可能实现方式的方法。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例中，发送设备分别调制第一目标比特流以及第二目标比特流，分别得到第一M比特信息和第二M比特信息，其中第一M比特信息包括第一比特流的第一比特信息，以及至少一个填充比特信息，第二M比特信息至少包括第二比特流的第二比特信息，以及第三比特流的第三比特信息，接收设备对第一比特信息对应的第一编码码块的软信息进行译码以得到第一信息比特序列，然后基于第一信息比特序列解调第二编码码块的第三比特信息的软信息。因此，本申请实施例中，第二目标符号至少包括两个来自不同编码码块的比特信息，从而可以使用已译码的比特信息对应的信息比特序列解调未译码的比特信息的软信息，减小比特信息之间的互信息的损失。
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图1为本申请实施例提供的一种应用场景示意图；
图2为本申请实施例提供的一个系统框架图；
图3为本申请实施例提供的信息调制解调方法的一个实施例示意图；
图4为本申请实施例提供的一个实施例示意图；
图5为本实施例提供的另一个实施例示意图；
图6为本申请实施例提供的信息调制解调方法的另一个实施例示意图；
图7为本申请实施例提供的另一个实施例示意图；
图8为本申请实施例提供的发送设备的一个示意性框图；
图9为本申请实施例提供的接收设备的一个示意性框图；
图10为本申请实施例提供的发送设备的一个硬件结构示意图；
图11为本申请实施例提供的接收设备的一个硬件结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着新技术的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请实施例提供了一种信息调制解调方法与装置，用于接收设备使用已译码的码字序列对未解调的比特信息进行串行解调，减小比特流之间互信息的损失，提升通信系统的性能。
请参考图1，图1为本申请实施例提供的一种应用场景示意图，如图1所示，该应用场景示意图可以包括接终端设备101以及网络设备102。
其中，本申请实施例提供的终端设备101可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。所述终端设备101可以是移动站(mobile station，MS)、用户单元(subscriber unit)、蜂窝电话(cellular phone)、智能电话(smart phone)、无线数据卡、个人数字助理(personal digital assistant，简称：PDA)电脑、平板型电脑、无线调制解调器(modem)、手持设备(handset)、膝上型电脑(laptop computer)、机器类型通信(machine type communication,MTC)终端等。
本申请实施例提供的网络设备102可以是一种部署在无线接入网中为终端设备101提供无线通信功能的装置。其中，网络设备102可以包括各种形式的宏基站，微基站(也称为小站)，中继站，接入点等。在采用不同的无线接入技术的系统中，具备基站功能的设备的名称可能会有所不同，例如，在LTE系统中，称为演进的节点B(evolved NodeB，eNB或者eNodeB),在第三代(3rd Generation，3G)系统中，称为节点B(Node B)，在第五代(3rd Generation，5G)系统中成为无线网络接入设备等。
本申请实施例中，终端设备101可以作为发送设备向网络设备102发送信息，对应地，网络设备102可以作为接收设备接收终端设备101发送的信息；需要说明的是，网络设备102也可以作为发送设备向终端设备101发送信息，对应地，终端设备101也可以作为接收设备接收网络设备102发送的信息。
本申请实施例仅以终端设备101作为发送设备，网络设备102作为接收设备为例对本申请实施例所涉及的发送设备以及网络设备进行描述。
上面对本实施例中提供的应用场景示意图进行了描述，下面从发送设备以及接收设备 的角度对本实施例进行描述。
请参考图2，图2为本申请实施例提供的一个系统框架图，该系统框架图包括发送设备以及接收设备。
其中，发送设备包括极化编码器、串并转化器、交织器、比特延时器以及调制器等设备。其中，极化编码器可以是将信源比特流或数据进行极化编码的设备；串并转化器可以是将码字序列转换为多个并行比特流的设备；交织器可以是用于对比特流进行交织的设备；比特延时器可以将比特流进行延时，分别将延时后的比特流发送至调制器；调制器可以比特流中的比特信息进行调制，然后通过信道发送至接收设备。
接收设备包括解调器、逆比特延时器、解交织器、并串转换器以及极化译码器等设备。其中，解调器可以对比特流中的比特信息进行解调；逆延时器可以将解调的比特流软信息序列进行逆延时；解交织器可以对比特流软信息序列进行解交织；并串转化器可以将多个并行的比特流软信息序列转换为可以进行译码的一个比特流软信息序列；极化译码器可以是将比特流或数据进行译码的设备。
下面结合图2，对本申请实施例提供的信息调制解调方法进行描述。
请参考图3，图3为本申请实施例提供的信息调制解调方法的一个实施例示意图，如图3所示本申请实施例提供的信息调制解调方法可以包括以下步骤：
301、极化编码器对信源比特序列进行极化码编码。
极化编码器从信源设备中获取M个信源比特序列，其中，M为大于1的整数。需要说明的是，本实施例中该M个信源比特序列可以为不同的信源比特序列。
极化编码器对该M个信源比特序列分别进行极化码编码，得到M个编码码块；比如，极化编码器对M个信源比特序列的第一信源比特序列u 1:N,1进行极化码编码，得到第一编码码块，其中，第一编码码块的码字序列为b 1:N,1。需要说明的是，该M个编码码块的每个编码码块的码长为N，信息位长度为Q，对应地，每个编码码块的码率为R＝N/Q。
其中，b 1:N,1＝u 1:N,1 G N，G N为极化码编码矩阵，
Figure PCTCN2019102826-appb-000001
B N表示比特置换矩阵，
Figure PCTCN2019102826-appb-000002
表示为F 2的n次克罗内克积，
Figure PCTCN2019102826-appb-000003
本实施例中第二编码码块的码字序列b 1:N,2至第M编码码块对应的码字序列b 1:N,M与前述码字序列b 1:N,1类似，此处不再赘述。其中，第二编码码块对应M个信源比特序列的第二信源比特序列u 1:N,2，第M编码码块对应M个信源比特序列的第M信源比特序列u 1:N,M。
302、串并转化器将M个编码码块进行分割并将分割得到的比特流发送至交织器。
串并转换器从极化编码器编码获取M个编码码块分别对应的M个码字序列，串并转换器分别将M个码字序列的每个码字序列进行长度相同的分割。具体地，串并转换器分别将M个码字序列的每个码字序列分割成m个长度为N/m的比特流
Figure PCTCN2019102826-appb-000004
其中,i为比特流的序号，i＝1,2,...,m。
下面以第一编码码块的码字序列b 1:N,1为例对本实施例的编码码块的分割进行说明：
具体地，串并转换器将第一编码码块的码字序列b 1:N,1分割为M个长度相同的比特流
Figure PCTCN2019102826-appb-000005
i＝1,2,...,m。例如，串并转换器将第一编码码块的码字序列b 1:N,1分割为4个长度相同的比特流
Figure PCTCN2019102826-appb-000006
i＝1,2,3,4，对应得到的4个比特流可如表3-1所示。
表3-1.第一编码码块的比特流
Figure PCTCN2019102826-appb-000007
Figure PCTCN2019102826-appb-000008
本实施例中，串并转换器将第一编码码块的码字序列b 1:N,T分割为4个长度相同的比特流
Figure PCTCN2019102826-appb-000009
i＝1,2,3,4，对应得到的4个比特流还可以如表3-2所示。
表3-2.第一编码码块的比特流
Figure PCTCN2019102826-appb-000010
Figure PCTCN2019102826-appb-000011
需要说明的是，本实施例中第一编码码块的码字序列b 1:N,1还可以其他方式进行分割，此处不再赘述。
本实施例中，第二编码码块的码字序列b 1:N,2至第M编码码块的码字序列b 1:N,M的分割方式与第一编码码块的码字序列b 1:N,1的分割方式类似，此处不再赘述。
串并转换器将每个编码码块对应的比特序列分别分割为m个长度为N/m的比特流后，将分割得到的比特流发送至交织器。
具体地，串并转换器从分割后的比特流确定每个编码码块的第i个比特流
Figure PCTCN2019102826-appb-000012
并将第i个比特流
Figure PCTCN2019102826-appb-000013
发送至第i个交织器。例如，将第一编码码块的比特流
Figure PCTCN2019102826-appb-000014
发送至第1个交织器，以及将第二编码码块的比特流
Figure PCTCN2019102826-appb-000015
发送至第1个交织器，依次类推。
需要说明的是，本申请实施例中，串并转换器还可以将同一个编码码块的m个比特流发送至同一交织器中，此处不做限定。本实施例以及后续实施例仅以将每个编码码块的第i个比特流传输至对应的第i个交织器为例进行说明。
303、交织器对比特流进行交织。
交织器从串并转换器中获取分割后的比特流；具体地，第i个交织器获取每个编码码块的第i个比特流，第i个交织器将每个编码码块的第i个比特流分别进行交织，输出每个编码码块交织后的比特流。
下面以第1个交织器以及第2个交织器对比特流的交织进行举例说明，具体地，第1个交织器将第一编码码块的第1个比特流
Figure PCTCN2019102826-appb-000016
进行交织，输出交织后的比特流
Figure PCTCN2019102826-appb-000017
第1个交织器将第二编码码块的第1个比特流
Figure PCTCN2019102826-appb-000018
进行交织，输出交织后的比特流
Figure PCTCN2019102826-appb-000019
依次类推。
第2个交织器将第一编码码块的第2个比特流
Figure PCTCN2019102826-appb-000020
进行交织，输出交织后的比特流
Figure PCTCN2019102826-appb-000021
第2个交织器将第二编码码块的第2个比特流
Figure PCTCN2019102826-appb-000022
进行交织，输出交织后的比特流
Figure PCTCN2019102826-appb-000023
依次类推。
304、比特延时器对比特流进行延时。
比特延时器将从交织器中获取的比特流进行延时，其中，每个编码码块的第i个比特流的延时相同，将延时后的比特流分别以不同的时刻向调制器发送。
其中，比特延时器在第一时刻向调制器发送第一目标比特流，第一目标比特流至少包括第一编码码块的第一比特流，其中第一比特流可以是第一编码码块的m个比特流中的任意一个。
比特延时器在第二时刻向调制器发送第二目标比特流，第二目标比特流包括所述第一编码码块的第二比特流以及第二编码码块的第三比特流，其中第二比特流为第一编码码块的m个比特流中的任意一个，第三比特流为第二编码码块的m个比特流中的任意一个。
需要说明的是，本实施例可以先执行步骤303，再执行步骤304，也可以先执行步骤304，再执行步骤303，此处不做限定。
305、调制器调制第一目标比特流以及第二目标比特流。
调制器获取比特延时器发送的第一目标比特流以及第二目标比特流，并将第一目标比特流和第二目标比特流分别进行调制。
具体地，调制器调制第一目标比特流得到第一目标符号，其中第一目标符号包括第一M比特信息，第一M比特信息包括第一比特流的第一比特信息，以及至少一个填充比特信息，需要说明的是，填充比特信息为已知比特信息。
调制器调制第二目标比特流得到第二目标符号，其中第二目标符号包括第二M比特信息，第二M比特信息至少包括第二比特流的第二比特信息，以及第三比特流的第三比特信息，也就是说第二M比特信息至少包括两个比特信息，其中该两个比特信息分别对应不同的编码码块。
下面以16正交振幅调制(quadrature amplitude modulation，QAM)、4个编码码块以及每个编码码块的码长为N对本实施涉及的调制比特流进行描述。其中，4个编码码块分别为A编码码块、B编码码块、C编码码块以及D编码码块。
请参考图4，图4为本申请实施例提供的一个实施例示意图，如图4所示，调制器在第一时刻获取比特延时器发送的第一目标比特流，其中第一目标比特流包括的第一比特流可以是(A 1 A 2…A N/4)，调制器对(A 1 A 2…A N/4)和填充比特信息(X X X…X)进行调制，得到N/4个第一目标符号，其中每个第一目标符号包括第一M比特信息。具体地，调制器将第一比特流(A 1 A 2…A N/4)以及每个填充比特信息中序号为j比特信息组成二进制比特序列，例如，调制器将(A 1 A 2…A N/4)中序号为1的比特信息A 1和每个填充比特信息中序号为1的X调制成一个第一目标符号，该第一目标符号的第一M比特信息为(X X X A 1)，X为填充比特信息。以及将序号为2的比特信息A 2和每个填充比特信息中序号为2的X调制成另一个第二目标符号，该第二目标符号的第一M比特信息为(X X X A 2)，依次类推，可得到N/4个第一目标符号，每个第一目标符号包括第一M比特信息。
调制器在第二时刻获取比特延时器发送的第二目标比特流，其中第二目标比特流包括的第二比特流可以是(A N/4+1 A N/4+2…A N/2)，第三比特流可以是(B 1 B 2…B N/4)。调制器对(A N/4+1 A N/4+2…A N/2)、(B 1 B 2…B N/4)以及(X X X…X)进行调制，得到N/4个第二目标符号，其中第二目标符号包括第二M比特信息。具体地，调制器将第二比特流(A N/4+1 A N/4+2…A N/2)和第三比特流(B 1 B 2…B N/4)以及每个填充比特信息中序号为j的比特信息组成二进制比特序列。例如，调制器将(A N/4+1 A N/4+2…A N/2)、(B 1 B 2…B N/4)和每个填充比特信息(X X X…X)中序号为1的A N/4+1、B 1和X调制为一个第二目标符号，该第二目标符号包括第二M比特信息为(X X A N/4+1B 1),以及将序号为2的A N/4+2、B 2和X调制为另一个第二目标符号，该第二目标符号为(X X A N/4+2B 2),依次类推，可得到N/4个第二目标符号，每个第二目标符号包括第二M比特信息。
可以理解的是，图4对应第三时刻、第四时刻以及后续时刻获取的目标符号的调制方式与前述图4的第一时刻对应的第一目标比特流的调制方式类似，此处不再赘述。
可选地，请参考图5，图5为本实施例提供的另一个实施例示意图，如图5所示，第一目标比特流还可以包括第四比特流(B 3N/4+1 B 3N/4+2…B N)，其中，第四比特流对应第二编码码块。需要说明的是，第四比特流还可以对应其他编码码块。调制器对第一比特流(A 1 A 2…A N/4)、第四比特流(B 3N/4+1 B 3N/4+2…B N)以及每个填充比特信息(X X X…X)进行调制，得到其中一个第一目标符号，该第一目标符号的第一M比特信息为(X X A 1B 3N/4+1)，另一个第一目标符号的第一M比特信息(X X A 2 B 3N/4+2)，依次类推，可得到N/4个第一目标符号，每个第一目标符号包括第一M比特信息。
第二目标比特流还包括第五比特流(C 3N/4+1 C 3N/4+2…C N)，其中第五比特流对应第三编码码块。其中，调制器对第二比特流(A N/4+1 A N/4+2…A N/2)、第三比特流(B 1 B 2…B N/4)、第五比特流进行调制(C 3N/4+1 C 3N/4+2…C N)以及填充比特信息(X X X…X)进行调制，得到其中一个第二目标符号，该第二目标符号为第二M比特信息(X A N/4+1 B 1 C 3N/4+1)，另一个第二M比特信息(X A N/4+2 B 2 C 3N/4+2)，依次类推,可得到N/4个第二目标符号，每个第二目标符号包括第二M比特信息。
可以理解的是，图5第三时刻、第四时刻以及后续时刻获取的目标符号的调制方式与前述图5第一时刻对应的第一目标比特流的调制方式类似，此处不再赘述。
306、发送设备发送第一目标符号和第二目标符号。
发送设备分别在第一时刻发送N/m个第一目标符号和在第二时刻发送N/m个第二目标符号。
需要说明的是，本实施例中发送设备可以通过无线信道分别发送第一目标符号以及第二目标符号。
需要说明的是，本实施例的步骤301至步骤306由发送设备执行。
307、接收设备接收发送设备发送的第一目标符号和第二目标符号。
接收设备在第一时刻分别接收发送设备发送N/m个第一目标符号，其中，每个第一目标符号分别包括第一M比特信息，第一M比特信息包括第一编码码块的第一比特流的第一比特信息，以及至少一个填充比特信息。
以及接收设备在第二时刻分别接收发送设备发送的N/m个第二目标符号，其中，每个第二目标符号分别包括第二M比特信息，第二M比特信息包括第一编码码块的第二比特信息以及第二编码码块的第三比特信息，也就是说每个第二M比特信息包括两个比特信息，该两个比特信息分别对应不同的编码码块。
需要说明的是，接收设备可以通过无线信道接收发送设备分别发送的第一目标符号以及第二目标符号。
308、解调器解调第一比特信息的软信息。
解调器接收待解调的第一目标符号以及第二目标符号。
解调器获取第一M比特信息，解调器基于第一M比特信息中的填充比特信息解调第一比特信息的软信息。比如，解调器获取到的第一M比特信息为(X X X A 1)时，解调器基于填充比特信息(X X X)解调第一比特信息A 1的软信息，以及第一M比特信息为(X X X A 2)时，解调器基于填充比特信息(X X X)解调A 2的软信息，依次类推。解调器分别解调(A 1至A N/4)，从而得到比特序列(A 1 A 2…A N/4)的软信息。
解调器获取第二M比特信息后，解调器解调第二M比特信息的第二比特信息的软信息。比如，解调器获取到的第二M比特信息为(X X A N/4+1 B 1)时，解调器基于填充比特信息(X X)解调第二比特信息A N/4+1的软信息。以及第二M比特信息为(X X A N/4+2 B 2)时，解调器基于填充比特信息(X X)解调A N/4+2的软信息，依次类推，从而得到比特序列(A N/4+1 A N/4+2…A N/2)的软信息。
可以理解的是，解调器可以从第一M比特信息以及第二M比特信息中解调得到第一编码码块的第1个比特流的比特序列(A 1 A 2…A N/4)的软信息以及第2个比特流的比特序列(A N/4+1 A N/4+2…A N/2)的软信息。解调器还可以从第三M比特信息中解调得到第一编码码块的第3个比特流的比特序列(A N/2+1 A N/2+2…A 3N/4)的软信息，依次类推，从而可以解调得到第一编码码块的m个比特流分别对应的比特序列的软信息，即可以解调得到(A 1 A 2…A N/4)、(A N/4+1 A N/4+2…A N/2)、(A N/2+1 A N/2+2…A 3N/4)以及(A 3N/4+1 A 3N/4+2…A N)分别对应的软信息。
可选地，本实施例中，当第一M比特信息还包括第四比特信息以及第二M比特信息还包括第五比特信息时，比如第一M比特信息为(X X A 1 B 3N/4+1)，第二M比特信息为(X A N/4+1 B 1 C 3N/4+1)时，解调器基于填充比特信息(X X)解调第一比特信息A 1的软信息，依次类推。解调器分别解调(A 1至A N/4)的软信息，从而得到比特序列(A 1 A 2…A N/4)的软信息。解调器基于填充比特信息(X)解调第一比特信息A N/4+1的软信息，依次类推。解调器分别解调 (A N/4+1至A N/2)的软信息，从而得到比特序列(A N/4+1 A N/4+2…A N/2)的软信息。同样可以解调得到第一编码码块的(A 1 A 2…A N/4)、(A N/4+1 A N/4+2…A N/2)、(A N/2+1 A N/2+2…A 3N/4)以及(A 3N/4+1 A 3N/4+2…A N)分别对应的软信息。
309、逆比特延时器对第一编码码块的比特序列的软信息进行逆延时。
逆比特延时器从解调器中获取到第一编码码块的m个比特流分别对应的比特序列的软信息。然后分别将第一编码码块第i个比特流对应的比特序列的软信息进行逆延时之后，分别发送至解交织器。比如，逆比特延时器将第1个比特流对应的比特序列(A 1 A 2…A N/4)的软信息发送至第1个解交织器，将第2个比特流对应的比特序列(A N/4+1 A N/4+2…A N/2)的软信息发送至第2个解交织器，依次类推。
310、解交织器对第一编码码块的比特序列的软信息进行解交织。
解交织器从逆比特延时器中获取第一编码码块的每个比特流分别对应的比特序列的软信息之后。分别对每个比特序列的软信息进行解交织，分别得到第一编码码块的m个比特流的软信息。比如，第1个解交织器对第1个比特序列的软信息解交织，得到第1个比特流的软信息，第2个解交织器对第2个比特序列的软信息解交织，得到第2个比特流的软信息，依次类推。
对应地，本实施例可以先执行步骤309，再执行步骤310，也可以先执行步骤310，再执行步骤309，此处不做限定。
311、并串变换器对第一编码码块的软信息进行串行变换。
并串变换器分别从解交织器中获取第一编码码块的m个比特流的软信息，然后将该m个比特流的软信息变换为串行软信息序列，即变换得到第一编码码块的软信息序列。
312、极化译码器对第一编码码块的软信息序列进行译码。
极化译码器从并串变换器中获取第一编码码块的软信息序列，并对第一编码码块的软信息序列进行译码，从而得到第一信源比特序列。
本实施例中，极化译码器可以使用序列连续删除算法(successive cancellation list，SCL)或者循环冗余校验辅助序列连续删除算法(cyclic redundancy check aided-SCL，CA-SCL)对第一编码码块的软信息序列译码，以得到第一信息比特序列，需要说明的是，极化译码器还可以使用其他算法对第一编码码块的软信息序列进行译码，此处不做限定。
313、极化编码器对第一信息比特序列进行极化码编码。
极化编码器重新对第一信息比特序列进行极化码编码，得到第一码字序列。比如该第一码字序列可以为(A 1 A 2…A N)。
314、解调器解调第三比特信息的软信息。
解调器基于已经译码的第一码字序列解调第三比特信息的软信息。
具体地，解调器从第二目标符号中确定第二编码码块的第三比特信息，并基于第一码字序列以及填充比特信息解调第三比特信息的软信息。例如，当第二M比特信息为(X X A N/4+1 B 1)时，解调器基于第一码字序列中的A N/4+1以及填充比特信息X解调第三比特信息B 1的软信息，即基于(X X A N/4+1)解调B 1的软信息。另外,另一个第二M比特信息为(X X A N/4+2 B 2)时，解调器基于第一码字序列中的A N/4+2以及填充比特信息X解调B 2的软信息，依次类推，从而分别解调得到(B 1 B 2…B N/4)的软信息。当第二M比特信息为(X A N/2+1 B N/4+1 C 1)，解调 器基于(X A N/2+1)解调B N/4+1的软信息，依次类推，从而分别得到(B N/4+1 B N/4+2…B N/2)的软信息。当第二M比特信息为(A 3N/4+1 B N/2+1 C N/4+1 D 1)，解调器同样基于(A 3N/4+1)解调(B N/2+1)的软信息，从而得到(B N/2+1 B N/2+2…B 3N/4)的软信息。因此，解调器可以基于已经进行译码的第一编码码块的第一码字序列以及填充比特信息解调得到第二编码码块对应的软信息序列，即基于已经进行译码的第一编码码块的第一码字序列解调得到第二编码码块的(B 1 B 2…B N/4)、(B N/4+1 B N/4+2…B N/2)、(B N/2+1 B N/2+2…B 3N/4)以及(B 3N/4+1 B 3N/4+2…B N)分别对应的软信息。需要说明的是，本实施例中比特序列(B 3N/4+1 B 3N/4+2…B N)中的每个比特信息可以通过并行解调得到。
可选地，当第一M比特信息还包括第四比特信息时，解调器还可以基于第一码字序列以及填充比特信息解调第四比特信息的软信息，比如一个第一M比特信息为(X X A 1 B 3N/4+1)时，第四比特信息为B 3N/4+1，解调器还可以基于(X X A 1)解调B 3N/4+1的软信息，以及另一第一M比特信息为(X X A 2 B 3N/4+2)时，解调器还可以基于(X X A 2)解调B 3N/4+2的软信息。从而可以得到(B 3N/4+1 B 3N/4+2…B N)的软信息。其中解调(B 1 B 2…B N/4)、(B N/4+1 B N/4+2…B N/2)以及(B N/2+1 B N/2+2…B 3N/4)分别对应的软信息与前述类似，此处不再赘述。
可以理解的是，本实施例中，解调器可以基于已经译码的第一编码码块的第一码字序列解调第二编码码块对应的比特信息的软信息，从而得到第二编码码块的每个比特流的比特序列的软信息。
315、逆比特延时器对第二编码码块的比特序列的软信息进行逆延时。
316、解交织器对第二编码码块的比特序列的软信息进行解交织。
317、并串变换器对第二编码码块的软信息进行串行变换。
318、极化译码器对第二编码码块的软信息序列进行译码。
本实施例中，步骤315至步骤318与前述步骤319至步骤312类似，此处不再赘述。
319、极化编码器对第二信息比特序列进行极化码编码。
极化编码器重新对第二编码码块的第二信息比特序列进行极化码编码，得到第二码字序列。比如该第二码字序列可以为(B 1 B 2…B N)。需要说明的是，第二信息比特序列由第二编码码块的软信息序列译码得到。
320、解调器解调第五比特信息的软信息。
解调器基于已经译码的第一码字序列以及第二码字序列解调第五比特信息的软信息。
具体地，第二M比特信息还可以包括第三编码码块的第五比特信息，其中，第五比特信息与第二比特信息在各自所属的比特流中的位置序号相同。比如，当一个第二M比特信息为(X A N/4+1 B 1 C 3N/4+1)时，其中C 3N/4+1为第五比特信息，解调器基于第一码字序列的A N/4+1、第二码字序列B 1以及填充比特信息X解调第五比特信息C 3N/4+1的软信息，即基于(X A N/4+1 B 1)解调C 3N/4+1的软信息。当另一个第二M比特信息为(X A N/4+2 B 2 C 3N/4+2)时，解调器基于(X A N/4+2 B 2)解调C 3N/4+2的软信息，依次类推，从而可以解调得到第三编码码块的其中一个比特流的比特序列(C 3N/4+1 C 3N/4+2 C 3N/4+3…C N)的软信息。可以理解的是，第三编码码块的其他比特信息的软信息同样可以基于已经译码的第一编码码块的第一码字序列以及第二编码码块的第二码字序列解调得到，从而可以得到第三编码码块每个比特流分别对应的比特序列的软信息。
可以理解的是，本实施例中，解调器可以基于已经译码的编码码块对应的码字序列解调当前需要译码的编码码块的比特信息的软信息，从而得到M个编码码块中的每个编码码块的软信息序列。
需要说明的是，本实施例的步骤307至步骤320由接收设备执行。
本实施例中，发送设备分别对不同的信息比特流进行编码生成不同的编码码块，将每个编码码块分割成数个比特流并分别经过相应的延时，然后将不同编码码块中经过相同延时的比特流调制于目标符号，从而使得目标符号包括来自于至少两个不同编码码块的比特信息。接收设备在接收到目标符号之后，根据已译码完成的码字序列以及填充比特信息，对当前要译码的比特信息进行串行解调。因此，本实施例中，使用已经译码的码字序列解调当前需要译码的编码码块的比特信息的软信息，可以减小比特信息之间互信息的损失。
上面描述了本申请实施例提供的一个实施例，下面对本申请实施例提供的另一个实施例进行描述。
请参考图6，图6为本申请实施例提供的信息调制解调方法的另一个实施例示意图，如图6所示本申请实施例提供的信息调制解调方法可以包括以下步骤：
601、极化编码器对信源比特序列进行极化码编码。
极化编码器从信源设备中获取K个信源比特序列，其中，K为M/2。
需要说明的是，本实施例中极化编码器对K个信源比特序列分别进行极化码编码与前述图3步骤301所描述的极化编码器对该M个信源比特序列分别进行极化码编码类似，此处不再赘述。
需要说明的是，K还可以是M/3，或者其他此处不做限定，本实施例仅以K为M/2作为例子进行说明。
602、串并转化器将K个编码码块进行分割并将分割得到的比特流发送至交织器。
串并转换器从极化编码器编码获取K个编码码块分别对应的K个码字序列，串并转换器分别将K个码字序列的每个码字序列进行长度相同的分割。具体地，串并转换器分别将K个码字序列的每个码字序列分割成m个长度为N/m的比特流
Figure PCTCN2019102826-appb-000024
其中i为比特流的序号，i＝1,2,...,m。
需要说明的是，串并转换器分别将K个码字序列的每个码字序列分割成m个长度为N/m的比特流
Figure PCTCN2019102826-appb-000025
与前述图3步骤302所描述的串并转换器分别将M码字序列的每个码字序列分割成m个长度为N/m的比特流
Figure PCTCN2019102826-appb-000026
类似，此处不再赘述。
需要说明的是，串并转换器将分割得到的比特流发送至交织器前述图3步骤302所描述的类似，此处不再赘述。
603、交织器对比特流进行交织。
604、比特延时器对比特流进行延时。
本实施例中，步骤603至步骤604与前述图3对应的步骤303至步骤304类似，此处不再赘述。
需要说明的是，本实施例可以先执行步骤603，再执行步骤604，也可以先执行步骤604，再执行步骤603，此处不做限定。
605、调制器调制第一目标比特流以及第二目标比特流。
调制器获取比特延时器发送的第一目标比特流以及第二目标比特流，并将第一目标比特流和第二目标比特流进行调制。
具体地，调制器调制第一目标比特流得到第一目标符号，其中第一目标符号包括第一M比特信息，第一M比特信息包括第一比特流的第一比特信息，以及至少一个填充比特信息。
调制器调制第二目标比特流得到第二目标符号，其中第二目标符号包括第二M比特信息，第二M比特信息至少包括第二比特流的第二比特信息，以及第三比特流的第三比特信息，也就是说第二M比特信息至少包括两个比特信息，其中该两个比特信息分别对应不同的编码码块。
下面以16QAM、2个编码码块以及每个编码码块的码长为N对本实施涉及的调制比特流进行描述。其中，该2个编码码块分别为A编码码块、B编码码块。
请参考图7，图7为本申请实施例提供的另一个实施例示意图，如图7所示，调制器在第一时刻获取比特延时器发送的第一目标比特流，其中第一目标比特流包括第一编码码块的比特流(A 1 A 2…A N/4)和(A N/4+1 A N/4+2…A N/2)。调制器对(A 1 A 2…A N/4)、(A N/4+1 A N/4+2…A N/2)以及填充比特信息(X X X…X)进行调制，得到N/4个第一目标符号，其中每个第一目标符号包括第一M比特信息。具体地，调制器将(A 1 A 2…A N/4)、(A N/4+1 A N/4+2…A N/2)和每个填充比特信息中序号为j的比特信息组成二进制比特序列。例如，调制器将比特流(A 1 A 2…A N/4)、(A N/4+1 A N/4+2…A N/2)以及(X X X…X)中序号为1的A 1、A N/4+1和X调制为一个第一目标符号，该第一目标符号包括的第一M比特信息为(X X A 1 A N/4+1),以及将序号为2的A 2、A N/4+2和X调制为另一个第一目标符号，该第一目标符号包括的第一M比特信息为(X X A 2 A N/4+2),依次类推，可得到N/4个第一目标符号，每个第一目标符号包括第一M比特信息。
调制器在第二时刻获取到第二目标比特流，其中，第二目标比特流包括第一编码码块的第二比特流(A N/2+1 A N/2+2…A 3N/4)和(A 3N/4+1 A 3N/4+2…A N)，以及第二编码码块的第三比特流(B 1 B 2…B N/4)和(B N/4+1 B N/4+2…B N/2)。调制器对(A N/2+1 A N/2+2…A 3N/4)、(A 3N/4+1 A 3N/4+2…A N)、(B 1 B 2…B N/4)和(B N/4+1 B N/4+2…B N/2)进行调制，得到N/4个第二目标符号，其中第二目标符号包括第二M比特信息。具体地，调制器将(A N/2+1 A N/2+2…A 3N/4)、(A 3N/4+1 A 3N/4+2…A N)、(B 1 B 2…B N/4)和(B N/4+1 B N/4+2…B N/2)中序号为j的比特信息组成二进制比特序列。例如，调制器将(A N/2+1 A N/2+2…A 3N/4)、(A 3N/4+1 A 3N/4+2…A N)、(B 1 B 2…B N/4)和(B N/4+1 B N/4+2…B N/2)中序号为1的A N/2+1、A 3N/4+1、B 1和B N/4+1调制为一个第二目标符号，其中第二目标符号包括第二M比特信息(A N/2+1 A 3N/4+1 B 1 B N/4+1),以及将序号为2的A N/2+2 A 3N/4+2 B 2和B N/4+2调制为另一个第二目标符号，其中第二目标符号包括第二M比特信息(A N/2+2 A 3N/4+2 B 2 B N/4+2),依次类推，可得到N/4个第二目标符号，其中第二目标符号包括第二M比特信息。
需要说明的是，本实施例中调制器在第三时刻还可以从比特延时器获取第三目标比特流以及在其他时刻从比特延时器获取的目标比特流与前述调制第一目标比特流的方法类似，此处不再赘述。
需要说明的是，如图7所示，第三时刻从比特延时器中获取到比特流(B N/2+1 B N/2+2…B 3N/4)、(B 3N/4+1 B 3N/4+2…B N)外，还包括其他编码码块的比特流或者终止填充比特。
606、发送设备向接收设备发送第一目标符号和第二目标符号。
需要说明的是，本实施例的步骤601至步骤606由发送设备执行。
607、接收设备接收发送设备发送的第一目标符号以及第二目标符号。
本实施例中，步骤606至步骤607与前述图3对应的步骤306至步骤307类似，此处不再赘述。
608、解调器解调第一比特信息的软信息。
解调器接收待解调的第一目标符号以及第二目标符号。
解调器获取第一M比特信息，解调器基于第一M比特信息中的填充比特信息解调第一比特信息的软信息。比如，解调器获取到的第一M比特信息为(X X A 1 A N/4+1)时，解调器基于填充比特信息(X X)解调第一比特信息A 1的软信息，以及基于填充比特信息(X X)解调第一比特信息A N/4+1的软信息。当第一M比特信息为(X X A 2 A N/4+2)，解调器基于填充比特信息(X X)解调A 2的软信息，以及基于填充比特信息(X X)解调A N/4+2的软信息，依次类推，解调器分别解调(A 1至A N/4)的软信息，从而得到比特序列(A 1 A 2…A N/4)和(A N/4+1 A N/4+2…A N/2)分别对应的软信息。
解调器获取第二M比特信息后，解调器解调第二M比特信息的第二比特信息的软信息。解调器可以基于并行解调算法解调第二M比特信息中属于第一编码码块的比特信息的软信息，从而得到比特序列(A N/2+1 A N/2+2…A 3N/4)和(A 3N/4+1 A 3N/4+2…A N)分别对应的软信息。
609、逆比特延时器对第一编码码块的比特序列的软信息进行逆延时。
610、解交织器对第一编码码块的比特序列的软信息进行解交织。
对应地，本实施例可以先执行步骤609，再执行步骤610，也可以先执行步骤610，再执行步骤609，此处不做限定。
611、并串变换器对第一编码码块的软信息进行串行变换。
612、极化译码器对第一编码码块的软信息序列进行译码。
613、极化编码器对第一信息比特序列进行极化码编码。
本实施例中，步骤609至步骤613与前述图3对应的步骤309至步骤313类似，此处不再赘述。
614、解调器解调第三比特信息的软信息。
解调器基于已经译码的第一码字序列解调第三比特信息的软信息。
解调器基于第一码字序列解调第二编码码块的第三比特信息的软信息。例如，当第二M比特信息为(A N/2+1 A 3N/4+1 B 1 B N/4+1)，解调器基于第一码字序列中的A N/2+1和A 3N/4+1解调第三比特信息B 1的软信息以及B N/4+1的软信息。即基于(A N/2+1 A 3N/4+1)解调B 1的软信息，以及基于(A N/2+1 A 3N/4+1)解调B N/4+1的软信息。当第二M比特信息为(A N/2+2 A 3N/4+2 B 2 B N/4+2)时，解调器基于第一码字序列A N/2+2和A 3N/4+2解调第三比特信息B 2和B N/4+2，即基于(A N/2+1 A 3N/4+1)解调B 2的软信息，以及基于(A N/2+1 A 3N/4+1)解调B N/4+2的软信息。依次类推，从而可以解调得到比特序列(B 1 B 2…B N/4)以及(B N/4+1 B N/4+2…B N/2)分别对应的软信息。可以理解的是，本实施例中(B N/2+1 B N/2+2…B 3N/4)以及(B 3N/4+1 B 3N/4+2…B N)分别对应的软信息可以进行并行解调。即基 于已经进行译码的第一编码码块的比特序列解调得到第二编码码块的(B 1 B 2…B N/4)、(B N/4+1 B N/4+2…B N/2)、(B N/2+1 B N/2+2…B 3N/4)以及(B 3N/4+1 B 3N/4+2…B N)分别对应的软信息。
可以理解的是，本实施例中，解调器可以基于已经译码的编码码块对应的码字序列对当前需要译码的编码码块的比特信息进行串行解调，从而得到M个编码码块中的每个编码码块的软信息序列。
需要说明的是，本实施例的步骤607至步骤614由接收设备执行。
本实施例中，发送设备分别对不同的信息比特流进行编码生成不同的编码码块，将每个编码码块分割成数个比特流并分别经过相应的延时，然后将不同编码码块中经过相同延时的比特流调制于目标符号，从而使得目标符号包括来自于至少两个不同编码码块的比特信息。接收设备在接收到目标符号之后，根据已译码完成的码字序列以及填充比特信息，对当前要译码的比特信息进行串行解调。因此，本实施例中，使用已经译码的码字序列解调当前需要译码的编码码块的比特信息的软信息，可以减小比特信息之间互信息的损失。
上面对本申请实施例提供的信息调制解调方法进行描述，下面对本申请实施例挺提供的装置进行描述。
请参考图8，图8为本申请实施例提供的发送设备的一个示意性框图，该发送设备包括：
调制单元801，用于调制第一目标比特流，以得到第一目标符号，所述第一目标符号包括第一M比特信息，所述第一目标比特流包括第一编码码块的第一比特流，所述第一M比特信息包括所述第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；
所述调制单元801还用于调制第二目标比特流，以得到第二目标符号，所述第二目标符号包括第二M比特信息，所述第二目标比特流包括所述第一编码码块的第二比特流以及第二编码码块的第三比特流，所述第二M比特信息至少包括所述第二比特流的第二比特信息，以及所述第三比特流的第三比特信息；
发送单元802，用于在第一时刻向接收设备发送所述第一目标符号以及在第二时刻发送所述第二目标符号，所述第一时刻在所述第二时刻之前。
可选地，本实施例中，所述发送设备还包括：
分割单元803，用于将所述第一编码码块对应的码字序列进行相同长度的分割，以得到第一分割流，所述第一分割流包括所述第一比特流以及所述第二比特流。
所述分割单元803还用于将所述第二编码码块对应的码字序列进行相同长度的分割，以得到第二分割流，所述第二分割流包括所述第三比特流。
可选地，本实施例中，所述第二M比特信息包括所述填充比特信息。
可选地，本实施例中，所述第一M比特信息还包括第四比特信息，所述第四比特信息对应所述第二编码码块的第四比特流。
可选地，本实施例中，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，
所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。
本申请实施例中，调制单元801分别调制第一目标比特流以及第二目标比特流，分别 得到第一M比特信息和第二M比特信息，其中第一M比特信息包括第一比特流的第一比特信息，以及至少一个填充比特信息，第二M比特信息至少包括第二比特流的第二比特信息，以及第三比特流的第三比特信息，其中，第二目标符号至少包括两个来自不同编码码块的比特信息，使得接收设备对第一比特信息对应的第一编码码块的软信息进行译码以得到第一信息比特序列，然后基于第一信息比特序列解调第二编码码块的第三比特信息的软信息。从而可以使用已译码的比特信息对应的信息比特序列解调未译码的比特信息的软信息，减小比特信息之间的互信息的损失。
上面对本申请实施例提供的发送设备进行了描述，下面对本申请实施例提供的接收设备进行描述。
请参考图9，图9为本申请实施例提供的接收设备的一个示意性框图，该接收设备包括：
接收单元901，用于在第一时刻接收发送设备发送的第一目标符号，所述第一目标符号包括第一M比特信息，所述第一M比特信息包括第一编码码块的第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；
解调单元902，用于基于所述至少一个填充比特信息解调所述第一比特信息的软信息，所述第一比特信息的软信息包含于所述第一编码码块的软信息序列；
所述接收单元901还用于在第二时刻接收所述发送设备发送的第二目标符号，所述第二目标符号包括第二M比特信息，所述第二M比特信息至少包括所述第一编码码块的第二比特流的第二比特信息，以及第二编码码块的第三比特流的第三比特信息；
所述解调单元902还用于解调所述第二比特信息的软信息，所述第二比特信息的软信息包含于所述第一编码码块的软信息序列；
译码单元903，用于对所述第一编码码块的软信息序列进行译码，以得到第一信息比特序列，所述第一信息比特序列用于解调所述第三比特信息的软信息。
可选地，本实施例中，所述接收设备还包括：
编码单元904，用于对所述第一信息比特序列进行极化码编码，以得到第一码字序列；
所述解调单元902还用于基于所述第一码字序列解调所述第三比特信息的软信息，所述第三比特信息的软信息包含于所述第二编码码块的软信息序列。
可选地，本实施例中，第二M比特信息包括所述填充比特信息，所述解调单元902具体用于基于所述填充比特信息以及所述第一码字序列解调所述第三比特信息的软信息。
可选地，本实施例中，所述第一M比特信息还包括第四比特信息，所述解调单元902具体用于基于所述填充比特信息以及所述第一码字序列解调所述第四比特信息的软信息，所述第四比特信息包含于所述第二编码码块的第四比特流。
可选地，本实施例中，所述第二M比特信息包括第五比特信息，所述第五比特信息对应第三编码码块，所述解调单元902还用于基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息，所述第五比特信息与所述第二比特信息在各自所属的比特流中的位置序号相同，所述第二码字序列为第二信息比特序列极化码编码得到的码字序列，所述第二信息比特序列为所述第二编码码块对应的信息比特序列。
可选地，本实施例中，所述第二M比特信息包括填充比特信息，所述解调单元902具体用于基于所述第一码字序列、所述第二码字序列以及所述填充比特信息解调所述第五比特信息的软信息。
可选地，本实施例中，所述译码单元903还用于对所述第二编码码块的软信息序列进行译码，以得到所述第二信息比特序列；
所述编码单元904还用于对所述第二信息比特序列进行极化码编码，以得到所述第二码字序列。
所述译码单元903具体用于使用序列连续删除算法SCL或者循环冗余校验辅助序列连续删除算法CA-SCL对所述第一编码码块的软信息序列进行译码，以得到所述第一信息比特序列。
可选地，本实施例中，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。
本申请实施例中，接收单元901分别接收第一目标符号以及第二目标符号，第一目标符号包括第一M比特信息，第二目标符号包括第二M比特信息，其中第一M比特信息包括第一比特流的第一比特信息，以及至少一个填充比特信息，第二M比特信息至少包括第二比特流的第二比特信息，以及第三比特流的第三比特信息，译码单元903对第一比特信息对应的第一编码码块的软信息进行译码以得到第一信息比特序列，编码单元904对第一信息比特序列进行极化码编码得到第一码字序列。因此，本申请实施例中，解调单元902可以使用已译码的比特信息对应的第一码字序列解调未译码的比特信息的软信息，减小比特信息之间的互信息的损失。
请参考图10，图10为本申请实施例提供的发送设备的一个硬件结构示意图，该发送设备包括：
至少一个处理器1010、存储器1050和收发器1030。该收发器可包括接收机和发射机，该存储器1050可以包括只读存储器和/或随机存取存储器，并向处理器1010提供操作指令和数据。存储器1050的一部分还可以包括非易失性随机存取存储器(NVRAM)。存储器与处理器可以是各自独立通过总线或者接口连接，也可以集成在一起。
在一些实施方式中，存储器1050存储了如下的元素，可执行模块或者数据结构，或者他们的子集，或者他们的扩展集。
在本申请实施例中，通过调用存储器1050存储的操作指令(该操作指令可存储在操作系统中)，执行相应的操作。处理器1010控制发送设备的操作，处理器1010还可以称为CPU(Central Processing Unit，中央处理单元)。存储器1050可以包括只读存储器和随机存取存储器，并向处理器1010提供指令和数据。存储器1050的一部分还可以包括非易失性随机存取存储器(NVRAM)。具体的应用中发送设备的各个组件通过总线系统1020耦合在一起，其中总线系统1020除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统1020。
上述本申请实施例揭示的方法可以应用于处理器1010中，或者由处理器1010实现。处理器1010可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各 步骤可以通过处理器1010中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1010可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1050，该存储器1050可以是物理上独立的单元，也可以是与处理器1010集成在一起的，处理器1010读取存储器1050中的信息，结合其硬件完成上述方法的步骤。
本实施例中，收发器1030可以分别用于执行图3对应的实施例以及图6对应的实施例发送设备侧涉及到接收和发送的操作步骤。或用于执行其他可选实施例中的发送设备侧的数据发送以及接收的步骤。
处理器1010可以分别用于执行图3对应的实施例以及图6对应的实施例发送设备侧数据处理的步骤。或用于执行其他可选实施例中发送设备侧数据处理的步骤。
请参考图11，图11为本申请实施例提供的接收设备的一个硬件结构示意图，该接收设备包括：至少一个处理器1110、存储器1150和收发器1130。该收发器可包括接收机和发射机，该存储器1150可以包括只读存储器和/或随机存取存储器，并向处理器1110提供操作指令和数据。存储器1150的一部分还可以包括非易失性随机存取存储器(NVRAM)。存储器与处理器可以是各自独立通过总线或者接口连接，也可以集成在一起。
本实施例中，至少一个处理器1110、存储器1150和收发器1130分别对应功能结构与前述图10对应实施例所描述的类似，此处不再赘述。
其中，收发器1130可以分别用于执行图3对应的实施例以及图6对应的实施例接收设备侧涉及到接收和发送的操作步骤。或用于执行其他可选实施例中的接收设备侧的数据发送以及接收的步骤。
处理器1110可以分别用于执行图3对应的实施例以及图6对应的实施例接收设备侧数据处理的步骤。或用于执行其他可选实施例中接收设备侧数据处理的步骤。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，read-only memory)、随机存取存储器(RAM，random access memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (36)

  1. 一种信息调制方法，其特征在于，包括：
    发送设备调制第一目标比特流，以得到第一目标符号，所述第一目标符号包括第一M比特信息，所述第一目标比特流包括第一编码码块的第一比特流，所述第一M比特信息包括所述第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；
    所述发送设备调制第二目标比特流，以得到第二目标符号，所述第二目标符号包括第二M比特信息，所述第二目标比特流包括所述第一编码码块的第二比特流以及第二编码码块的第三比特流，所述第二M比特信息至少包括所述第二比特流的第二比特信息，以及所述第三比特流的第三比特信息；
    所述发送设备在第一时刻发送所述第一目标符号以及在第二时刻发送所述第二目标符号，所述第一时刻在所述第二时刻之前。
  2. 根据权利要求1所述的方法，其特征在于，所述发送设备调制第一目标比特流之前，所述方法包括：
    所述发送设备将所述第一编码码块对应的码字序列进行相同长度的分割，以得到第一分割流，所述第一分割流包括所述第一比特流以及所述第二比特流；
    所述发送设备将所述第二编码码块对应的码字序列进行相同长度的分割，以得到第二分割流，所述第二分割流包括所述第三比特流。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第二M比特信息包括所述填充比特信息。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，所述第一M比特信息还包括第四比特信息，所述第四比特信息对应所述第二编码码块的第四比特流。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，
    所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。
  6. 一种信息解调方法，其特征在于，包括：
    接收设备在第一时刻接收发送设备发送的第一目标符号，所述第一目标符号包括第一M比特信息，所述第一M比特信息包括第一编码码块的第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；
    所述接收设备基于所述至少一个填充比特信息解调所述第一比特信息的软信息，所述第一比特信息的软信息包含于所述第一编码码块的软信息序列；
    所述接收设备在第二时刻接收所述发送设备发送的第二目标符号，所述第二目标符号包括第二M比特信息，所述第二M比特信息至少包括所述第一编码码块的第二比特流的第二比特信息，以及第二编码码块的第三比特流的第三比特信息；
    所述接收设备解调所述第二比特信息的软信息，所述第二比特信息的软信息包含于所述第一编码码块的软信息序列；
    所述接收设备对所述第一编码码块的软信息序列进行译码，以得到第一信息比特序列， 所述第一信息比特序列用于解调所述第三比特信息的软信息。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    所述接收设备对所述第一信息比特序列进行极化码编码，以得到第一码字序列；
    所述接收设备基于所述第一码字序列解调所述第三比特信息的软信息，所述第三比特信息的软信息包含于所述第二编码码块的软信息序列。
  8. 根据权利要求7所述的方法，其特征在于，第二M比特信息包括所述填充比特信息，所述接收设备基于所述第一码字序列解调所述第三比特信息的软信息包括：
    所述接收设备基于所述填充比特信息以及所述第一码字序列解调所述第三比特信息的软信息。
  9. 根据权利要求7或8所述的方法，其特征在于，所述第一M比特信息还包括第四比特信息，所述方法还包括：
    所述接收设备基于所述填充比特信息以及所述第一码字序列解调所述第四比特信息的软信息，所述第四比特信息包含于所述第二编码码块的第四比特流。
  10. 根据权利要求6至9任一项所述的方法，其特征在于，所述第二M比特信息包括第五比特信息，所述第五比特信息对应第三编码码块，所述方法还包括：
    所述接收设备基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息，所述第五比特信息与所述第二比特信息在各自所属的比特流中的位置序号相同，所述第二码字序列为第二信息比特序列极化码编码得到的码字序列，所述第二信息比特序列为所述第二编码码块对应的信息比特序列。
  11. 根据权利要求10所述的方法，其特征在于，所述第二M比特信息包括填充比特信息，所述接收设备基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息包括：
    所述接收设备基于所述第一码字序列、所述第二码字序列以及所述填充比特信息解调所述第五比特信息的软信息。
  12. 根据权利要求10所述的方法，其特征在于，所述接收设备基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息之前，所述方法还包括：
    所述接收设备对所述第二编码码块的软信息序列进行译码，以得到所述第二信息比特序列；
    所述接收设备对所述第二信息比特序列进行极化码编码，以得到所述第二码字序列。
  13. 根据权利要求6所述的方法，其特征在于，所述接收设备对所述第一编码码块的软信息序列进行译码，以得到第一信息比特序列包括：
    所述接收设备使用序列连续删除算法SCL或者循环冗余校验辅助序列连续删除算法CA-SCL对所述第一编码码块的软信息序列进行译码，以得到所述第一信息比特序列。
  14. 根据权利要求6至13任一项所述的方法，其特征在于，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，
    所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。
  15. 一种发送设备，其特征在于，包括：
    调制单元，用于调制第一目标比特流，以得到第一目标符号，所述第一目标符号包括第一M比特信息，所述第一目标比特流包括第一编码码块的第一比特流，所述第一M比特信息包括所述第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；
    所述调制单元还用于调制第二目标比特流，以得到第二目标符号，所述第二目标符号包括第二M比特信息，所述第二目标比特流包括所述第一编码码块的第二比特流以及第二编码码块的第三比特流，所述第二M比特信息至少包括所述第二比特流的第二比特信息，以及所述第三比特流的第三比特信息；
    发送单元，用于在第一时刻发送所述第一目标符号以及在第二时刻发送所述第二目标符号，所述第一时刻在所述第二时刻之前。
  16. 根据权利要求15所述的发送设备，其特征在于，所述发送设备还包括：
    分割单元，用于将所述第一编码码块对应的码字序列进行相同长度的分割，以得到第一分割流，所述第一分割流包括所述第一比特流以及所述第二比特流；
    所述分割单元还用于将所述第二编码码块对应的码字序列进行相同长度的分割，以得到第二分割流，所述第二分割流包括所述第三比特流。
  17. 根据权利要求15或16所述的发送设备，其特征在于，所述第二M比特信息包括所述填充比特信息。
  18. 根据权利要求15至17任一项所述的发送设备，其特征在于，所述第一M比特信息还包括第四比特信息，所述第四比特信息对应所述第二编码码块的第四比特流。
  19. 根据权利要求15至18任一项所述的发送设备，其特征在于，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，
    所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。
  20. 一种接收设备，其特征在于，包括：
    接收单元，用于在第一时刻接收发送设备发送的第一目标符号，所述第一目标符号包括第一M比特信息，所述第一M比特信息包括第一编码码块的第一比特流的第一比特信息，以及至少一个填充比特信息，所述填充比特信息为已知比特信息，所述M为大于1的整数；
    解调单元，用于基于所述至少一个填充比特信息解调所述第一比特信息的软信息，所述第一比特信息的软信息包含于所述第一编码码块的软信息序列；
    所述接收单元还用于在第二时刻接收所述发送设备发送的第二目标符号，所述第二目标符号包括第二M比特信息，所述第二M比特信息至少包括所述第一编码码块的第二比特流的第二比特信息，以及第二编码码块的第三比特流的第三比特信息；
    所述解调单元还用于解调所述第二比特信息的软信息，所述第二比特信息的软信息包含于所述第一编码码块的软信息序列；
    译码单元，用于对所述第一编码码块的软信息序列进行译码，以得到第一信息比特序列，所述第一信息比特序列用于解调所述第三比特信息的软信息。
  21. 根据权利要求20所述的接收设备，其特征在于，所述接收设备还包括：
    编码单元，用于对所述第一信息比特序列进行极化码编码，以得到第一码字序列；
    所述解调单元还用于基于所述第一码字序列解调所述第三比特信息的软信息，所述第三比特信息的软信息包含于所述第二编码码块的软信息序列。
  22. 根据权利要求21所述的接收设备，其特征在于，第二M比特信息包括所述填充比特信息，所述解调单元具体用于基于所述填充比特信息以及所述第一码字序列解调所述第三比特信息的软信息。
  23. 根据权利要求21或22所述的接收设备，其特征在于，所述第一M比特信息还包括第四比特信息，所述解调单元具体用于基于所述填充比特信息以及所述第一码字序列解调所述第四比特信息的软信息，所述第四比特信息包含于所述第二编码码块的第四比特流。
  24. 根据权利要求20至23任一项所述的接收设备，其特征在于，所述第二M比特信息包括第五比特信息，所述第五比特信息对应第三编码码块，所述解调单元还用于基于所述第一码字序列和第二码字序列解调所述第五比特信息的软信息，所述第五比特信息与所述第二比特信息在各自所属的比特流中的位置序号相同，所述第二码字序列为第二信息比特序列极化码编码得到的码字序列，所述第二信息比特序列为所述第二编码码块对应的信息比特序列。
  25. 根据权利要求24所述的接收设备，其特征在于，所述第二M比特信息包括填充比特信息，所述解调单元具体用于基于所述第一码字序列、所述第二码字序列以及所述填充比特信息解调所述第五比特信息的软信息。
  26. 根据权利要求24所述的接收设备，其特征在于，所述译码单元还用于对所述第二编码码块的软信息序列进行译码，以得到所述第二信息比特序列；
    所述编码单元还用于对所述第二信息比特序列进行极化码编码，以得到所述第二码字序列。
  27. 根据权利要求20所述的接收设备，其特征在于，所述译码单元具体用于使用序列连续删除算法SCL或者循环冗余校验辅助序列连续删除算法CA-SCL对所述第一编码码块的软信息序列进行译码，以得到所述第一信息比特序列。
  28. 根据权利要求20至27任一项所述的接收设备，其特征在于，所述第一M比特信息和所述第二M比特信息分别对应M个编码码块；或者，
    所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块，当所述第一M比特信息和所述第二M比特信息分别对应M/2个编码码块时，所述M为偶数。
  29. 一种发送设备，其特征在于，所述发送设备包括处理器和存储器，所述存储器用于存储指令，所述处理器在执行所述指令时执行权利要求1至5中任一项所述的信息调制方法。
  30. 根据权利要求29所述的发送设备，其特征在于，所述发送设备还包括收发器，所述收发器用于在第一时刻发送所述第一目标符号以及在第二时刻发送所述第二目标符号，所述第一时刻在所述第二时刻之前。
  31. 根据权利要求29或30所述的发送设备，其特征在于，所述处理器和所述存储器集成在一起。
  32. 一种接收设备，其特征在于，所述接收设备包括处理器和存储器，所述存储器用于存储指令，所述处理器在执行所述指令时执行权利要求6至14中任一项所述的信息解调 方法。
  33. 根据权利要求32所述的接收设备，其特征在于，所述发送设备还包括收发器，所述收发器用于在第一时刻接收发送设备发送的第一目标符号以及在第二时刻接收所述发送设备发送的第二目标符号，所述第一时刻在所述第二时刻之前。
  34. 根据权利要求32或33所述的接收设备，其特征在于，所述处理器和所述存储器集成在一起。
  35. 一种计算机可读存储介质，其特征在于，包括指令，当所述指令在计算机上运行时，使得计算机执行权利要求1至14中任一项所述的方法。
  36. 一种包含指令的计算机程序产品，其特征在于，当其在计算机上运行时，使得所述计算机执行如权利要求1至14任一项所述的方法。
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