WO2020052127A1 - 显示面板及其驱动方法与显示装置 - Google Patents

显示面板及其驱动方法与显示装置 Download PDF

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WO2020052127A1
WO2020052127A1 PCT/CN2018/120611 CN2018120611W WO2020052127A1 WO 2020052127 A1 WO2020052127 A1 WO 2020052127A1 CN 2018120611 W CN2018120611 W CN 2018120611W WO 2020052127 A1 WO2020052127 A1 WO 2020052127A1
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voltage
turn
display panel
circuit
buffer circuit
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PCT/CN2018/120611
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English (en)
French (fr)
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黄笑宇
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Publication of WO2020052127A1 publication Critical patent/WO2020052127A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display, and in particular, to a display panel, a driving method thereof, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the driving of the pixel unit in the TFT-LCD needs to be implemented by driving the corresponding scanning lines and data lines through a gate driving circuit and a source driving circuit.
  • the falling edge of the gate-on voltage output changes too quickly, which will affect the reference voltage inside the display panel, and the degree of the effect is positively related to the change in voltage per unit time. Therefore, in the design of the circuit architecture of the display device, the output of the gate is chamfered by the design of the printed circuit board end, that is, the change time from 33V to -7V is lengthened to reduce the impact on the reference voltage. Gate output waveform.
  • the gate turn-on voltage VGH of the TFT needs to be cut.
  • the method of resistance ground discharge is used to achieve the purpose of chamfering.
  • some components of the chamfering structure are arranged on the non-display area printed circuit board. The heat dissipation area is small, which makes the temperature of the printed circuit board rise easily.
  • the chamfered structure also needs to occupy a part of the printed circuit board, which is not conducive to the integration of the display device.
  • the object of the present application is to provide a display panel, including but not limited to a part of a component for solving a chamfered structure, which is disposed on a printed circuit board in a non-display area, and has a small heat dissipation area, which easily increases the temperature of the printed circuit board.
  • the chamfered structure also needs to occupy a part of the printed circuit board, which is not conducive to the integration of the display device.
  • a display panel including: a display area and a non-display area; a control circuit including a turn-on voltage; a buffer circuit disposed in the non-display area and coupled to the control circuit; A driving circuit is disposed in the non-display area and is coupled to the buffer circuit; a pixel module is disposed in the display area and is coupled to the driving circuit; wherein the turn-on voltage passes through the buffer circuit and By using the buffering effect of the buffer circuit, the turning-on voltage is formed into a chamfer, and is turned on to the pixel module through the driving circuit.
  • the turn-on voltage is a square wave voltage.
  • the buffer circuit includes a plurality of pixel units arranged in an array, and the plurality of pixel units are connected in series.
  • the impedance effect of the pixel unit is used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit includes a plurality of capacitors and a plurality of resistors arranged in an array, and the plurality of capacitors and the plurality of resistors are connected in series or in parallel or a combination of both. .
  • the capacitor and the resistor are used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit forms an arc-shaped inclined portion at a rising edge and a falling edge of the turn-on voltage.
  • control circuit is connected to an end of the plurality of pixel units remote from the driving circuit through a wire.
  • Another object of the present application is to provide a method for driving a display panel, including:
  • the driving voltage is used to transmit the turned-on voltage of the chamfer to the pixel module.
  • the turn-on voltage is a square wave voltage.
  • the step of forming the turn-on voltage to be chamfered by a buffer circuit specifically includes:
  • the rising and falling edges of the turn-on voltage are slowed down to form a chamfer.
  • the buffer circuit includes a plurality of pixel units arranged in an array, and the plurality of pixel units are connected in series.
  • the impedance effect of the pixel unit is used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit includes a plurality of capacitors and a plurality of resistors arranged in an array, and the plurality of capacitors and the plurality of resistors are connected in series or in parallel or a combination of both. .
  • the capacitor and the resistor are used to slow the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit forms an arc-shaped inclined portion at a rising edge and a falling edge of the turn-on voltage.
  • control circuit is connected to an end of the plurality of pixel units remote from the driving circuit through a wire.
  • Another object of the present application is to provide a display device including: a display area and a non-display area;
  • Control circuit including turn-on voltage
  • a buffer circuit disposed in the non-display area and coupled to the control circuit
  • a driving circuit disposed in the non-display area and coupled to the buffer circuit
  • a pixel module disposed in the display area and coupled to the driving circuit
  • the turn-on voltage passes through the snubber circuit and uses the snubber effect of the snubber circuit to form a chamfer of the turn-on voltage and conducts to the pixel module through the driving circuit;
  • the buffer circuit includes a plurality of pixel units arranged in an array, and the plurality of pixel units are connected in series.
  • the impedance effect of the pixel units is used to slow the rising and falling edges of the turn-on voltage to form a chamfer ;
  • the buffer circuit includes a plurality of capacitors and a plurality of resistors arranged in an array, and the plurality of capacitors and the plurality of resistors are connected in series or in parallel or a combination of both, and the capacitors and the resistors are utilized. , Slowing the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit in the non-display area can save the cost of the chamfered circuit of the display device, reduce the area of the printed circuit board, and eliminate the problem of the high temperature of the printed circuit board caused by the chamfered circuit.
  • FIG. 1 is an exemplary display device
  • FIG. 2a is a schematic diagram of an exemplary chamfering circuit
  • FIG. 2b is a schematic diagram of an exemplary chamfered waveform
  • FIG. 3 is a block diagram of a display device according to an embodiment of the present application.
  • FIG. 4 is a waveform diagram of a driving circuit according to an embodiment of the present application.
  • FIG. 5 is a structural diagram of a display device according to an embodiment of the present application.
  • FIG. 6 is a flowchart of a driving method according to an embodiment of the present application.
  • FIG. 1 is an exemplary display device.
  • an exemplary display device 100 includes: a display panel 140 having a display area 141 and a non-display area 142; a system motherboard (not shown), the system The motherboard connects the R / G / B compression signal, control signal and power supply to the connector 111 on the printed circuit board (PCB) 110 through wires, and the data passes through the timing controller (on the printed circuit board 110).
  • Timing Controller (TCON) (not shown) processing, and then through the source-chip chip 120 (S-COF) and gate-chip chip 130 (G-COF) and display
  • TCON Timing Controller
  • S-COF source-chip chip 120
  • G-COF gate-chip chip 130
  • the falling edge of the gate-on voltage output changes too quickly (for example, it can fall from 33V to -7V), which will affect the reference voltage inside the panel, and the extent of the effect will be the same as the change in voltage per unit time.
  • the quantity is positively correlated.
  • FIG. 2a is a schematic diagram of an exemplary chamfering circuit
  • FIG. 2b is a schematic diagram of an exemplary chamfering waveform.
  • An exemplary chamfering structure 101 includes an integrated control chip 102 (Integrated Circuit, IC) and a chamfering resistor 103. One end of the chamfering resistor 103 is coupled to the integrated control chip 102, and the other end is grounded to GND.
  • a gate turn-on voltage VGH is generated by the integrated control chip 102, and after the gate turn-on voltage passes through the chamfer resistor 103, a chamfer ⁇ V (which is shown in FIG.
  • the chamfered structure is formed to ease the gate turn-on The voltage drops too fast and reduces the impact of voltage changes on the reference voltage.
  • some components of the chamfered structure are disposed in the non-display area of the display panel, and the heat dissipation area is relatively large, which may easily cause the temperature of the display panel or the display device to rise.
  • the chamfered structure also needs to occupy a part of the printed circuit board, which is not conducive to the integration of the display device.
  • FIG. 3 is a block diagram of a display device according to an embodiment of the present application.
  • a display device 200 includes: a display panel having a display area and a non-display area; and a control circuit 210 Has a turn-on voltage; a buffer circuit 220 is provided in the non-display area and is coupled to the control circuit 210; a gate driving circuit 230 is provided in the non-display area and is coupled to the buffer circuit 220; a pixel A module 240 is disposed in the display area and is coupled to the gate driving circuit 230.
  • the turn-on voltage passes through the buffer circuit 220 and uses the buffer effect of the buffer circuit to form the turn-on voltage. It is chamfered and turned on to the pixel module through the gate driving circuit.
  • the turn-on voltage is a square wave voltage.
  • the buffer circuit 220 includes a plurality of pixel units arranged in an array, and the connection manner between the plurality of pixel units is a series connection.
  • the impedance effect of the pixel unit is used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit 220 includes a plurality of capacitors and a plurality of resistors arranged in an array, and the connection manner between the plurality of capacitors and the plurality of resistors is series or parallel or both Combination.
  • the capacitor and the resistor are used to slow the rising and falling edges of the turn-on voltage to form a chamfer.
  • control circuit is connected to an end of the plurality of pixel units away from the gate driving circuit through a wire.
  • control circuit is connected to the middle ends of the plurality of pixel units through wires.
  • the number of pixel units between the connection point and the gate driving circuit can be adjusted appropriately.
  • the plurality of pixel units are non-display pixel units disposed in a non-display area.
  • FIG. 4 is a waveform diagram of a driving circuit according to an embodiment of the present application. Please refer to FIG. 3 and FIG. 4 at the same time.
  • the initial voltage of the gate is adjusted to a cut-off opening voltage by the buffer circuit.
  • the turn-on voltage is turned on to the gate driving circuit. Since the output voltage of the gate drive circuit is based on the turn-on voltage, the rising and falling edges of the output voltage output from the gate driving circuit to the display panel are also slowed down. .
  • the output voltages exemplified in FIG. 4 are the first output voltage, the second output voltage, and the third output voltage. However, there is no limitation to only three output voltages, which depends on the needs of the designer.
  • the turned-on voltage waveform after the chamfering in FIG. 4 is only an example, and is not used to limit the shape and the degree of chamfering.
  • the waveform depends on the number of pixel units or capacitors or resistors in the buffer circuit and the parameter changes. Moved.
  • FIG. 5 is a structural diagram of a display device according to an embodiment of the present application. Please refer to FIG. 3 to FIG. 5 at the same time.
  • a display device 300 includes: a display panel 140 having a display area 141 and a non-display area 142; a printed circuit board 110 and the display The panel 140 is connected, and the printed circuit board has a power chip 112; a plurality of non-display pixel units 242 are disposed in the non-display area 142 of the display panel, and one end is connected to the printed circuit board 110 through a wire.
  • the power chip 112 is connected, and the other end is connected to the gate driving chip 130 of the display panel.
  • a plurality of display pixel units 241 are disposed in the display area 141 of the display panel for displaying a display screen.
  • the printed circuit board 110 and the power chip 112 may be equivalent to a control circuit
  • the plurality of pixel units 242 may be equivalent to a buffer circuit.
  • the turn-on voltage passes through a plurality of pixel units 242 and the buffering effect of the pixel unit 242 is used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the gate driving chip 130 outputs a plurality of output voltages to the pixel units 241 in the display area.
  • the power chip 112 is connected to an end of the plurality of non-display pixel units 242 away from the gate driving chip 130 through a wire. This can fully take advantage of the mitigation effect of the non-display pixel unit 242.
  • the power chip 112 may also be connected to the middle ends of the plurality of non-display pixel units 242. According to design requirements, the number of pixel units 242 between the connection point and the gate driving chip 130 is appropriately adjusted.
  • the plurality of pixel units 242 are arranged in series. After the turn-on voltage passes through the pixel units 242, the turned-on voltage is formed after being chamfered, and is turned on to the display via the gate driving chip 130. Used pixel unit 241.
  • FIG. 6 is a flowchart of a driving method according to an embodiment of the present application. Please refer to FIG. 3 to FIG. 6 at the same time.
  • a method for driving a display panel includes the following steps:
  • S102 Form a chamfer of the turn-on voltage through a buffer circuit
  • the buffer circuit is a square wave voltage.
  • the step of forming the turn-on voltage to be chamfered by a buffer circuit specifically includes:
  • the rising and falling edges of the turn-on voltage are slowed down to form a chamfer.
  • the buffer circuit includes a plurality of pixel units arranged in an array, and the plurality of pixel units are connected in series.
  • the impedance effect of the pixel unit is used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit includes a plurality of capacitors and a plurality of resistors arranged in an array, and the plurality of capacitors and the plurality of resistors are connected in series or in parallel or a combination of both. .
  • the capacitor and the resistor are used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit forms an arc-shaped inclined portion at a rising edge and a falling edge of the turn-on voltage.
  • the buffer circuit 220 includes a plurality of pixel units arranged in an array, and the connection manner between the plurality of pixel units is a series connection.
  • the impedance effect of the pixel unit is used to slow down the rising and falling edges of the turn-on voltage to form a chamfer.
  • the buffer circuit 220 includes a plurality of capacitors and a plurality of resistors arranged in an array, and the connection manner between the plurality of capacitors and the plurality of resistors is series or parallel or both Combination.
  • the capacitor and the resistor are used to slow the rising and falling edges of the turn-on voltage to form a chamfer.
  • the pixel unit 242 in the non-display area can be fully utilized, which does not need to consume a large amount of design cost, and can also save the cost of the bevel circuit on the printed circuit board, which is beneficial to the integration of the display device Into.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but it is not limited thereto, and it may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, or a curved display panel. Or other types of display panels.
  • the present application can save the cost of the chamfered circuit of the display device, reduce the area of the printed circuit board, and eliminate the problem of excessive temperature of the printed circuit board caused by the chamfered circuit To further improve the stability of the display device.

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Abstract

一种显示面板（140）及其驱动方法与显示装置（200、300）；其中，显示面板（140）包括：显示区（141）和非显示区（142）；控制电路（210），包含开启电压；缓冲电路（220），设置于非显示区（142），并耦接控制电路（210）；驱动电路（230），设置于非显示区（142），并耦接缓冲电路（220）；像素模块（240），设置于显示区（141），并耦接驱动电路（230）；其中，开启电压通过缓冲电路（220），并利用缓冲电路（220）的缓冲作用，使开启电压形成削角，并通过驱动电路（230）导通至像素模块（240）。

Description

显示面板及其驱动方法与显示装置
本申请要求于2018年9月11日提交中国专利局，申请号为2018110585293，发明名称为“显示面板及其驱动方法与显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，特别涉及一种显示面板及其驱动方法与显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示装置)，具有低成本、低功耗和高性能的优点，在电子、数码产品等领域有着广泛的运用，是现代IT、视讯产品中重要的显示平台。TFT-LCD中像素单元的驱动，则需通过栅极驱动电路和源极驱动电路驱动相应的扫描线和数据线加以实现。随着面板尺寸，解析度，及大视角影像品质的需求提高，并进一步提高用户体验及节约成本，各产商开发了很多有关显示领域的制造技术。
在显示装置中，栅极开启电压输出的下降沿变化过快，其会影响显示面板内部的基准电压，影响的程度与单位时间内电压的变化成正相关。因此显示装置中电路架构的设计中会通过印制电路板端的设计对栅极的输出进行削角，即将33V下降至-7V的变化时间拉长，以减小对基准电压影响，进行削角后的栅极输出波形。
由于电容耦合效应的影响，TFT(Thin Film Transistor，主动开关)打开与关闭时，会影响到数据(Data)信号电压的稳定，进而影响画面品质，因此需 要对TFT的栅极开启电压VGH进行削角处理，以降低TFT关闭时栅极开启电压VGH与栅极关闭电压VGL之间的电压差，减小对数据信号电压的影响。例如采用电阻接地放电的方法来达到削角的目的，但是此削角结构的部分组件设置于非显示区印制电路板上，其散热面积较小，容易使得印制电路板的温度上升，且削角结构还需占用部分印制电路板，不利于显示装置的集成化。
申请内容
本申请的目的在于，提供一种显示面板，包括但不限于解决削角结构的部分组件设置于非显示区印制电路板上，其散热面积较小，容易使得印制电路板的温度上升，且削角结构还需占用部分印制电路板，不利于显示装置的集成化的问题。
本申请实施例采用的技术方案是：一种显示面板，包括：显示区和非显示区；控制电路，包括开启电压；缓冲电路，设置于所述非显示区，并耦接所述控制电路；驱动电路，设置于所述非显示区，并耦接所述缓冲电路；像素模块，设置于所述显示区，并耦接所述驱动电路；其中，所述开启电压通过所述缓冲电路，并利用所述缓冲电路的缓冲作用，使所述开启电压形成削角，并通过所述驱动电路导通至所述像素模块。
在本申请的一实施例中，其中，所述开启电压为方波电压。
在本申请的一实施例中，其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联。
在本申请的一实施例中，其中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合。
在本申请的一实施例中，其中，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路在所述开启电压的上升沿和下降沿形成弧形倾斜部。
在本申请的一实施例中，其中，所述控制电路通过导线连接至所述多个像素单元中远离所述驱动电路的一端。
本申请的另一目的在于提供一种显示面板的驱动方法，包括：
通过控制电路，输出开启电压；
通过缓冲电路，使所述开启电压形成削角；
通过驱动电路，使削角的所述开启电压传输至像素模块。
在本申请的一实施例中，其中，所述开启电压为方波电压。
缓冲电路
在本申请的一实施例中，其中，所述通过缓冲电路，使所述开启电压形成削角的步骤具体包括：
利用所述缓冲电路的缓冲作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联。
在本申请的一实施例中，其中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合。
在本申请的一实施例中，其中，利用所述电容和所述电阻，减缓所述开启 电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路在所述开启电压的上升沿和下降沿形成弧形倾斜部。
在本申请的一实施例中，其中，所述控制电路通过导线连接至所述多个像素单元中远离所述驱动电路的一端。
本申请的再一目的在于提供一种显示装置，包括：显示区和非显示区；
控制电路，包括开启电压；
缓冲电路，设置于所述非显示区，并耦接所述控制电路；
驱动电路，设置于所述非显示区，并耦接所述缓冲电路；
像素模块，设置于所述显示区，并耦接所述驱动电路；
其中，所述开启电压通过所述缓冲电路，并利用所述缓冲电路的缓冲作用，使所述开启电压形成削角，并通过所述驱动电路导通至所述像素模块；
其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角；
其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
本申请通过非显示区的缓冲电路，可以节省显示装置的削角电路成本，减小印制电路板的面积，并消除由削角电路所造成的印制电路板温度过高的问题。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为范例性的显示装置；
图2a为范例性的削角电路示意图；
图2b为范例性的削角波形示意图；
图3为本申请一实施例的显示装置模块图；
图4为本申请一实施例的驱动电路波形图；
图5为本申请一实施例的显示装置结构图；
图6为本申请一实施例的驱动方法流程图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者 隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
图1为范例性的显示装置，请参考图1，一种范例性的显示装置100，包括：显示面板140，具有显示区141和非显示区142；系统主板(图未示)，所述系统主板将R/G/B压缩信号、控制信号及电源通过线材与印制电路板(Printed Circuit Board，PCB)110上的连接器111相连接，数据经过印制电路板110上的时序控制器(Timing Controller，TCON)(图未示)处理后，再通过源极驱动芯片120(Source-Chip on Film，S-COF)和栅极驱动芯片130(Gate-Chip on Film，G-COF)与显示面板140连接，从而使得显示面板140获得所需的电源、信号。在显示装置100的运行中，栅极开启电压输出的下降沿变化过快(可例如由33V下降至-7V)，其会影响面板内部的基准电压，且影响的程度与单位时间内电压的变化量成正相关。
图2a为范例性的削角电路示意图，图2b为范例性的削角波形示意图。请同时参考图2a和图2b，一种范例性的削角结构101，包括：集成控制芯片102(Integrated Circuit，IC)，及削角电阻103。所述削角电阻103一端耦接所述集成控制芯片102，另一端接地GND。通过所述集成控制芯片102产生栅极开启电压VGH，在所述栅极开启电压经过所述削角电阻103之后，形成削角 △V(其如图2b所示)，以此缓解栅极开启电压下降过快，并减小电压变化对基准电压的影响。但是，此削角结构的部分组件设置于显示面板的非显示区，其散热面积较大，容易使得显示面板或显示装置的温度上升。另一方面，削角结构还需占用部分印制电路板，不利于显示装置的集成化。
图3为本申请一实施例的显示装置模块图，请参考图3，在本申请的一实施例中，一种显示装置200，包括：显示面板，具有显示区和非显示区；控制电路210，具有开启电压；缓冲电路220，设置于所述非显示区，并耦接所述控制电路210；栅极驱动电路230，设置于所述非显示区，并耦接所述缓冲电路220；像素模块240，设置于所述显示区，并耦接所述栅极驱动电路230；其中，所述开启电压通过所述缓冲电路220，并利用所述缓冲电路的缓冲作用，使所述开启电压形成削角，并通过所述栅极驱动电路导通至所述像素模块。
在本申请的一实施例中，所述开启电压为方波电压。
在本申请的一实施例中，所述缓冲电路220包括阵列设置的多个像素单元，所述多个像素单元之间的连接方式为串联。
在本申请的一实施例中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，所述缓冲电路220包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间的连接方式为串联或并联或其二者的结合。
在本申请的一实施例中，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，所述控制电路通过导线连接至所述多个像素单元中远离栅极驱动电路的一端。
在本申请的一实施例中，所述控制电路通过导线连接至所述多个像素单元的中端，在设计需求下，可适当调整连接点与栅极驱动电路之间的像素单元的数量。
在本申请的一实施例中，所述多个像素单元为设置于非显示区的非显示用的像素单元。
图4为本申请一实施例的驱动电路波形图。请同时参考图3和图4，栅极初始电压在所述缓冲电路的作用下，调整成削角的开启电压。所述开启电压导通至栅极驱动电路，由于栅极驱动电路的输出电压是基于所述开启电压，因此，由栅极驱动电路输出至显示面板的输出电压的上升沿和下降沿亦被减缓。图4中例示的输出电压为第一输出电压，第二输出电压，第三输出电压，但非以此限制只有三个输出电压，此依据设计人员的需求而定。同理而言，图4的削角后的开启电压波形仅为例示，并非以此限制其波形的形状及削角程度，其波形依据缓冲电路中像素单元或电容或电阻的数量及参数变化而有所调动。
图5为本申请一实施例的显示装置结构图。请同时参考图3至图5，在本申请的一实施例中，一种显示装置300，包括：显示面板140，具有显示区141和非显示区142；印制电路板110，与所述显示面板140相连，所述印制电路板具有一电源芯片112；多个非显示用的像素单元242，设置于所述显示面板的非显示区142，并通过导线，一端与印制电路板110的电源芯片112相连接，另一端与显示面板的栅极驱动芯片130相连接；多个显示用的像素单元241，设置于所述显示面板的显示区141，用于呈现显示画面。其中，印制电路板110和电源芯片112可等效为控制电路，多个像素单元242可等效为缓冲电路。所述开启电压通过多个像素单元242，并利用像素单元242的缓冲作用，使所述开启电压的上升沿和下降沿减缓，形成削角。而后，通过所述栅极驱动芯片 130输出多个输出电压至显示区的像素单元241。
在本申请的一实施例中，所述电源芯片112通过导线连接至所述多个非显示用的像素单元242中远离栅极驱动芯片130的一端。此可以充分发挥非显示用的像素单元242的减缓作用。所述电源芯片112亦可以连接至所述多个非显示用的像素单元242的中端，在设计需求下，适当调整连接点与栅极驱动芯片130之间的像素单元242的数量。
在本申请的一实施例中，所述多个像素单元242为串联设置，开启电压在通过该些像素单元242之后，形成削角后的开启电压，经由栅极驱动芯片130，导通至显示用的像素单元241。
图6为本申请一实施例的驱动方法流程图。请同时参考图3至图6，一种显示面板的驱动方法，其步骤包括：
S101：通过控制电路，输出开启电压；
S102：通过缓冲电路，使所述开启电压形成削角；
S103：通过栅极驱动电路，使削角的所述开启电压传输至像素模块；
缓冲电路在本申请的一实施例中，其中，所述开启电压为方波电压。
在本申请的一实施例中，其中，所述通过缓冲电路，使所述开启电压形成削角的步骤具体包括：
利用所述缓冲电路的缓冲作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联。
在本申请的一实施例中，其中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合。
在本申请的一实施例中，其中，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，其中，所述缓冲电路在所述开启电压的上升沿和下降沿形成弧形倾斜部。在本申请的一实施例中，所述缓冲电路220包括阵列设置的多个像素单元，所述多个像素单元之间的连接方式为串联。
在本申请的一实施例中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
在本申请的一实施例中，所述缓冲电路220包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间的连接方式为串联或并联或其二者的结合。
在本申请的一实施例中，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
在一些实施例中，通过所述缓冲电路，可以充分利用非显示区的像素单元242，不需要耗费大量的设计成本，亦可以节省印制电路板上削角电路的成本，利于显示装置的集成化。
在一些实施例中，本申请的显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请通过利用显示面板非显示区的缓冲电路，可以节省显示装置的削角电路成本，减小印制电路板的面积，并消除由削角电路所造成的印制电路板温度过高的问题，进一步提高显示装置的稳定性。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例，并非对本申请作任何形式上的限制，虽然本申请已以具体的实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (18)

  1. 一种显示面板，包括：
    显示区和非显示区；
    控制电路，包括开启电压；
    缓冲电路，设置于所述非显示区，并耦接所述控制电路；
    驱动电路，设置于所述非显示区，并耦接所述缓冲电路；
    像素模块，设置于所述显示区，并耦接所述驱动电路；
    其中，所述开启电压通过所述缓冲电路，并利用所述缓冲电路的缓冲作用，使所述开启电压形成削角，并通过所述驱动电路导通至所述像素模块。
  2. 如权利要求1所述的显示面板，其中，所述开启电压为方波电压。
  3. 如权利要求1所述的显示面板，其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联。
  4. 如权利要求3所述的显示面板，其中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
  5. 如权利要求1所述的显示面板，其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合。
  6. 如权利要求5所述的显示面板，其中，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
  7. 如权利要求1所述的显示面板，其中，所述缓冲电路在所述开启电压的上升沿和下降沿形成弧形倾斜部。
  8. 如权利要求1所述的显示面板，其中，所述控制电路通过导线连接至所述多个像素单元中远离所述驱动电路的一端。
  9. 一种显示面板的驱动方法，其中，包括：
    通过控制电路，输出开启电压；
    通过缓冲电路，使所述开启电压形成削角；
    通过驱动电路，使削角的所述开启电压传输至像素模块。
  10. 如权利要求9所述的显示面板的驱动方法，其中，所述开启电压为方波电压。
    缓冲电路
  11. 如权利要求9所述的显示面板的驱动方法，其中，所述通过缓冲电路，使所述开启电压形成削角的步骤具体包括：
    利用所述缓冲电路的缓冲作用，减缓所述开启电压的上升沿和下降沿，形成削角。
  12. 如权利要求9所述的显示面板的驱动方法，其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联。
  13. 如权利要求12所述的显示面板的驱动方法，其中，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角。
  14. 如权利要求9所述的显示面板的驱动方法，其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合。
  15. 如权利要求14所述的显示面板的驱动方法，其中，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
  16. 如权利要求9所述的显示面板的驱动方法，其中，所述缓冲电路在所述开启电压的上升沿和下降沿形成弧形倾斜部。
  17. 如权利要求9所述的显示面板的驱动方法，其中，所述控制电路通过 导线连接至所述多个像素单元中远离所述驱动电路的一端。
  18. 一种显示装置，包括：显示区和非显示区；
    控制电路，包括开启电压；
    缓冲电路，设置于所述非显示区，并耦接所述控制电路；
    驱动电路，设置于所述非显示区，并耦接所述缓冲电路；
    像素模块，设置于所述显示区，并耦接所述驱动电路；
    其中，所述开启电压通过所述缓冲电路，并利用所述缓冲电路的缓冲作用，使所述开启电压形成削角，并通过所述驱动电路导通至所述像素模块；
    其中，所述缓冲电路包括阵列设置的多个像素单元，所述多个像素单元之间为串联，利用所述像素单元的阻抗作用，减缓所述开启电压的上升沿和下降沿，形成削角；
    其中，所述缓冲电路包括阵列设置的多个电容和多个电阻，所述多个电容和所述多个电阻之间为串联或并联或其二者的结合，利用所述电容和所述电阻，减缓所述开启电压的上升沿和下降沿，形成削角。
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