WO2020052080A1 - 显示装置和驱动方法 - Google Patents

显示装置和驱动方法 Download PDF

Info

Publication number
WO2020052080A1
WO2020052080A1 PCT/CN2018/117431 CN2018117431W WO2020052080A1 WO 2020052080 A1 WO2020052080 A1 WO 2020052080A1 CN 2018117431 W CN2018117431 W CN 2018117431W WO 2020052080 A1 WO2020052080 A1 WO 2020052080A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
timing controller
display data
data signal
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/117431
Other languages
English (en)
French (fr)
Inventor
赵文勤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US17/042,813 priority Critical patent/US11295692B2/en
Publication of WO2020052080A1 publication Critical patent/WO2020052080A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application relates to the field of liquid crystal display technology, and more particularly, to a display device and a driving method.
  • EMI electromagnetic interference
  • an object of the present application is to propose a display device and a driving method for solving the problem of electromagnetic interference caused by high-frequency data transmission.
  • the present application provides a display device including a timing controller that generates a timing control verification signal based on a display data signal.
  • the timing controller transmits the display data signal to the driver through a high-speed interface, and The low-speed interface transmits the timing control verification signal to the driver;
  • a driving circuit is connected to the timing controller, and generates a source drive verification signal based on the display data signal from the timing controller, the A driving circuit comparing the source driving verification signal with the timing control verification signal from the timing controller, and triggering the timing controller to adjust the display data signal based on a comparison result; and a display panel,
  • the driving circuit is connected, and the display data signal adjusted by the timing controller is output to the display panel through the driving circuit for display.
  • the present application provides a method for driving a display device, including: generating a timing control check signal based on a display data signal by a timing controller; and transmitting the display data signal to the timing controller via a high-speed interface of the timing controller.
  • a driver and transmitting the timing control verification signal to the driver through a low-speed interface of the timing controller; generating a source drive verification signal based on the display data signal by the driver; comparing the driver with the driver The source driving check signal and the timing control check signal; and the driver triggering the timing controller to adjust the display data signal based on a comparison result.
  • the present application provides a method for driving a display device, which includes the following steps: minimizing the amplitude of a display data signal by a timing controller; and generating a timing control check signal based on the display data signal by the timing controller. Transmitting the display data signal to the driver through a high-speed interface of the timing controller, and transmitting the timing control verification signal to the driver through a low-speed interface of the timing controller; The display data signal generates a source drive check signal; and the driver compares whether the source drive check signal is equal to the timing control check signal, and if so, triggers the timing controller through the driver.
  • the present application provides a display device and a driving method.
  • the display device includes a timing controller, a driver, and a display panel.
  • the driver is connected to the timing controller and the display panel, respectively.
  • the timing controller sends a display data signal and a timing control check signal to the driver.
  • the driver generates a source driving check signal based on the display data signal.
  • the driver compares the source driving verification signal with the timing control verification signal from the timing controller, and triggers the timing controller to adjust the display data signal based on a comparison result.
  • the driver triggers the timing controller to record the display data signal, and sends the recorded data signal to the display panel Display it.
  • the display device reduces the electromagnetic interference by increasing the checking mechanism to reduce the amplitude of the data signal as much as possible while ensuring the correctness of data transmission.
  • FIG. 1 is a schematic diagram of a display panel and peripheral circuits of a display device in an embodiment of the present application
  • FIG. 2 is a schematic diagram of a sequence controller and a driving circuit of a display device according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a sequence controller and a driving circuit of a display device according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of an embodiment of a verification method for a driving method of a display device in an embodiment of the present application
  • FIG. 5 is a schematic diagram of another embodiment of a verification method for a driving method of a display device according to an embodiment of the present application.
  • FIG. 6 is a flowchart of steps in an embodiment of a method for driving a display device according to an embodiment of the present application
  • FIG. 7 is a flowchart of steps in another embodiment of a method for driving a display device according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a display panel 30 and peripheral circuits of a display device 100 of the present application
  • FIG. 2 is a schematic diagram of a sequence controller and a driving circuit 20 of the display device 100 of the present application.
  • the display device 100 includes a display panel 30 and a peripheral circuit surrounding the display panel 30, where the display panel 30 may include a display and a non-display area surrounding the display area.
  • the peripheral circuit can include a control circuit board (Control / Board, C / B), which is generally a packaged printed circuit board (Printed Circuit, Board, Assembly, PCBA).
  • the timing controller 10 (Timing, Controller, T-CON) is provided on the display Control signals and display data of panel 30;
  • Source-Chip On-Film (S-COF) package which is a flexible circuit board packaged on Chip-On-Film (COF), and the main chip above It is a source driver 21 (Source Driver, S / D);
  • G-COF gate-on-chip film
  • the gate driver 21 (gate array, GOA) actually does not have a separate gate driver 21 on some gate drive circuits 20 provided on the array substrate;
  • the circuit boards XL and XR are two packaged printed circuit boards, respectively.
  • Flexible flat cable Flexible Flat Cable, FFC
  • FFC Flexible Flat Cable
  • the timing controller 10 on the control circuit board C / B transmits data according to the format of Miniature-Low Voltage Differential Signaling (Mini-LVDS) or Universal Serial Interface (USI-T), Image signal processing (Image Signal Processing, ISP) and other point-to-point (P2P) transmission formats, the data is transmitted through the FFC-X / B-COF-S / D path, this transmission path is generally In order to reduce the number of pins (PINs) transmitted, the transmission frequency is very high. According to the Mini-LVDS protocol, it is generally around 300MHz, so electromagnetic interference problems are prone to occur on this path.
  • the usual method is to reduce the amplitude of the Mini-LVDS signal (Swing), but reducing the signal amplitude easily causes the source driver 21 to fail to receive the correct display data.
  • This application adds a check mechanism to ensure the correct data transmission Under the circumstance of low frequency, try to reduce the amplitude of the data signal to reduce electromagnetic interference.
  • FIG. 2 is a schematic diagram of a sequence controller and a driving circuit 20 of the display device 100 of the present application.
  • the display device 100 includes a timing controller 10 and a source driver 21.
  • the timing controller 10 Before the timing controller 10 outputs the display data signal to the source driver 21, the timing controller 10 can minimize the amplitude of the display data signal.
  • the timing controller 10 has a signal receiving unit that receives the display data signal. 12.
  • the analysis and processing module 11 and the signal output unit 13 that outputs the analyzed signal display the data signal in the analysis and processing module 11 to minimize the amplitude through an arithmetic method including methods such as a least square method and a gradient descent method.
  • the display data signal is analyzed by the analysis processing module 11 and then output through the signal output unit 13.
  • the timing controller 10 generates a timing control check signal based on the display data signal, and then the timing controller 10 transmits the display data signal to the source driver 21 through the high-speed interface 131, and transmits the timing control check signal to the low-speed interface 132 to Source driver 21. Because the display data signal and the timing control check signal have different interface transmission speeds, when the timing controller 10 outputs the display data signal and the timing control check signal at the same time, the display data signal is more important than the timing control check signal. Reaching the source driver 21 early, so that the source driver 21 can process the display data and the timing control check signal respectively. However, since the display data signal may cause electromagnetic interference problems due to the use of high-frequency data transmission, the present application checks and appropriately adjusts the display data signal later.
  • the source driver 21 is connected to the timing controller 10 and generates a source driving check signal based on a display data signal from the timing controller 10.
  • the source driver 21 compares the source drive verification signal with the timing control verification signal from the timing controller 10. If the source drive verification signal generated by the source driver 21 is equal to the timing control verification signal from the timing controller 10, the source driver 21 triggers the timing controller 10 to directly record the current display data signal. However, if the source drive verification signal generated by the source driver 21 is not equal to the timing control verification signal from the timing controller 10, the source driver 21 triggers the timing controller 10 to adjust (e.g., increase) the display data signal. Characteristics (such as amplitude).
  • the source driver 21 no longer triggers the timing controller 10 to adjust the display data signal, but triggers the timing controller 10 to record the currently adjusted display data signal. That is, until the amplitude of the display data signal is reduced as much as possible under the condition of ensuring the correctness of data transmission, thereby reducing the possibility of electromagnetic interference.
  • the driving circuit 20 may further include a logic gate 22, which is connected between the timing controller 10 and the source driver 21, and each source driver 21 After comparing the source drive verification signal and the timing control verification signal, the corresponding source drive verification signal is output to the logic gate 22, and the logic gate 22 triggers timing based on the multiple source drive verification signals of the plurality of source drivers 21.
  • the controller 10 adjusts the display data signal.
  • the driving circuit 20 may include a plurality of source drivers 21. In this embodiment, four source drivers 21 are taken as an example, but it is not limited thereto. In fact, there may be only one or more source drivers 21 and an appropriate number of logic gates 22.
  • the logic gate 22 is an AND gate, and the AND gate is connected between the output terminal of the source driver 21 and the input terminal of the timing controller 10.
  • the outputs of the four source drivers 21 as inputs of the AND gate shown in FIG. 2 are lock value 1, lock value 2, lock value 3, and lock value 4, respectively.
  • the source driver 21 compares the source drive verification signal with the timing control verification signal from the timing controller 10 to be not equal, the source driver 21 outputs a low-level source drive verification signal to the AND gate. .
  • each source driver 21 compares the source drive verification signal with the timing control verification signal
  • the source driver 21 outputs a high-level source drive verification signal to the AND gate.
  • the logic gate 22 is an OR gate.
  • each source driver 21 compares the source drive verification signal with the timing control verification signal from the timing controller 10, they are not equal.
  • the source driver 21 outputs a high-level source drive check signal to the OR gate, on the contrary, when the comparison is equal, it outputs a low-level source drive check signal to the OR gate.
  • the OR gate outputs the high level signal to the timing controller 10 to trigger the timing controller 10 to increase the display data.
  • the amplitude of the signal (the timing controller 10 can be set to a high level to trigger the amplitude of the display data signal in advance); to put it another way, all of the multiple source drive verification signals from multiple source drivers 21 are When the level is low, the OR gate outputs a low level signal to the timing controller 10. In this case, the display data signal is directly recorded without adjusting the amplitude of the display data signal.
  • the driving circuit 20 further includes a converter 23, a judger 24 and a flip-flop 25.
  • the converter 23 is communicatively connected to a high-speed interface and a low-speed interface of the output unit 13 respectively.
  • the converter 23 generates a source driving check signal based on the display data signal from the timing controller 10.
  • the judger 24 is communicatively connected with the logic gate 22 and the converter 23 respectively.
  • the judger 24 compares whether the source drive verification signal is equal to the timing control verification signal from the timing controller 10).
  • the trigger 25 is disposed between the judger 24 and the receiving unit 12.
  • the trigger 25 may send a high-level signal or a low-level signal to the receiving unit 12 according to a determination result.
  • the analysis processing module 11 adjusts the amplitude of the display data signal or records the display data signal according to the signal sent by the trigger and sends the display data signal to the display panel 30 for display via the driver 21.
  • the display data signal adjusted by the control circuit board C / B can pass through the Source-Chip On Film (S-COF) (including the source electrode).
  • S-COF Source-Chip On Film
  • the driver 21 outputs to the display panel 30, so that the display panel 30 performs display according to the adjusted display data signal.
  • FIG. 4 is a schematic diagram of an embodiment of a verification method for a driving method of the display device 100 of the present application.
  • the timing controller 10 and the source driver 21 respectively generate timing control check signals and source drive check signals generated based on the display data signals, and each of them may include a cyclic redundancy check code CRC corresponding to each other.
  • a case is listed in which the timing controller 10 sends display data and cyclic redundancy check code CRC data, that is, the timing controller 10 (see FIG. 2) calculates a cyclic redundancy calibration for each frame
  • the check code CRC is sent to the source driver 21 (see FIG. 2), and the source driver 21 also calculates a cyclic redundancy check code CRC every frame.
  • FIG. 5 is a schematic diagram of another embodiment of a verification method for a driving method of the display device 100 of the present application.
  • the timing controller 10 and the source driver 21 respectively generate timing control check signals and source drive check signals generated based on the display data signals, and each of them may include a cyclic redundancy check code CRC corresponding to each other.
  • the timing controller 10 sends display data and cyclic redundancy check code CRC data is listed, that is, the timing controller 10 (see FIG. 2)
  • the cyclic redundancy check code CRC is calculated once for each m line and sent to the source driver 21 (see FIG. 2), and the source driver 21 also calculates the cyclic redundancy check code CRC once for m lines.
  • FIG. 6 is a flowchart of steps in an embodiment of a driving method of the display device 100 of the present application.
  • the driving method of the display device 100 may include the following steps s1 to s5:
  • Step s1 generating a timing control check signal based on the display data signal by the timing controller 10;
  • Step s2 transmitting the display data signal to the source driver 21 through the high-speed interface 131 of the timing controller 10, and transmitting the timing control verification signal to the source through the low-speed interface 132 of the timing controller 10 Said source driver 21;
  • Step s3 generating a source driving check signal based on the display data signal by the source driver 21;
  • Step s4 comparing the source drive verification signal with the timing control verification signal through the source driver 21;
  • Step s5 The source driver 21 triggers the timing controller 10 to adjust the display data signal based on the comparison result.
  • the driving method of the display device 100 further includes minimizing the amplitude of the display data signal by the timing controller 10 before outputting the display data signal to the source driver 21, wherein
  • the timing controller 10 has a signal receiving unit 12 for receiving a display data signal, an analysis processing module 11 and a signal output unit 13 for outputting an analyzed signal.
  • the display data signal in the analysis processing module 11 includes, for example, a least square method and a gradient. Algorithms such as the descent method minimize the amplitude.
  • the display data signal is output through the signal output unit 13 after being analyzed by the analysis processing module 11; and the source driver 21 is used to compare the source drive verification signal with the timing control from the timing controller 10 When the check signals are not equal, the source driver 21 triggers the timing controller 10 to increase the amplitude of the display data signal.
  • This embodiment is optional, and further includes comparing the source drive verification signal with the timing control verification signal through the source drivers 21 and outputting the corresponding source drive verification signal to a logic gate. 22; and triggering the timing controller 10 to adjust the display data signal by the logic gate 22 based on the plurality of source driving check signals of the plurality of source drivers 21.
  • the driving method of the display device 100 further includes comparing the source driving check signal with the timing control check signal from the timing controller 10 through the source driver 21. When they are equal, the source driver 21 triggers the timing controller 10 to record the display data signal.
  • FIG. 7 is a flowchart of steps in another embodiment of a method for driving the display device 100 of the present application.
  • the driving method of the display device 100 may include the following steps a to g:
  • Step a Minimize the amplitude of the displayed data signal through the timing controller 10;
  • Step b generating a timing control check signal based on the display data signal by the timing controller 10;
  • Step c transmitting the display data signal to the source driver 21 through the high-speed interface 131 of the timing controller 10, and transmitting the timing control check signal to the source through the low-speed interface 132 of the timing controller 10 Said source driver 21;
  • Step d generating a source driving check signal based on the display data signal by the source driver 21;
  • Step e The source driver 21 is used to compare whether the source drive verification signal is equal to the timing control verification signal. If yes, perform the following step f, and if not, execute the following step g:
  • Step f trigger the timing controller 10 to record the display data signal to be output to the display panel 30 through the source driver 21;
  • the source driver 21 is used to trigger the timing controller 10 to increase the amplitude of the display data signal, and then jump back to step b.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示装置和驱动方法，包括时序控制器基于显示数据信号生成时序控制校验信号。时序控制器的高速接口传输显示数据信号至驱动器，并时序控制器的低速接口传输时序控制校验信号至驱动器。驱动器基于显示数据信号生成源极驱动校验信号；驱动器比对源极驱动校验信号与时序控制校验信号；驱动器基于比对结果触发时序控制器调整显示数据信号。

Description

显示装置和驱动方法
相关申请
本申请要求2018年09月10日申请的，申请号为2018110511800，名称为“显示装置和驱动方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶显示技术领域，更具体的说，涉及一种显示装置和驱动方法。
背景技术
随着液晶显示领域的发展，液晶显示器凭借低功耗、超薄等优点得到了市场的广泛认可，但是随着环保意识的提高，各大厂商对电磁干扰(Electromagnetic Interference EMI)的要求越来越高，EMI主要是由于电子产品高频率的信号跳变，向周围环境中发射的电磁干扰信号，对于液晶显示器而言EMI产生部分主要有两个部分，1、是开关电源的高频开关导致，2、高频的数据传输导致。
发明内容
有鉴于上述现有技术的问题，本申请的目的是提出一种显示装置和驱动方法，其用以解决由于高频的数据传输导致的电磁干扰问题。
基于上述目的，本申请提供一种显示装置，其包括时序控制器，基于显示数据信号生成时序控制校验信号，所述时序控制器通过高速接口传输所述显示数据信号至所述驱动器，并通过低速接口传输所述时序控制校验信号至所述驱动器；驱动电路，连接至所述时序控制器，并基于来自所述时序控制器的所述 显示数据信号生成源极驱动校验信号，所述驱动电路比对所述源极驱动校验信号与来自所述时序控制器的所述时序控制校验信号，并基于比对结果触发所述时序控制器调整所述显示数据信号；以及显示面板，连接所述驱动电路，通过所述时序控制器调整后的所述显示数据信号通过所述驱动电路输出至所述显示面板进行显示。
基于上述目的，本申请提供一种显示装置的驱动方法，包括：通过时序控制器基于显示数据信号生成时序控制校验信号；通过所述时序控制器的高速接口传输所述显示数据信号至所述驱动器，并通过所述时序控制器的低速接口传输所述时序控制校验信号至所述驱动器；通过所述驱动器基于所述显示数据信号生成源极驱动校验信号；通过所述驱动器比对所述源极驱动校验信号与所述时序控制校验信号；以及通过所述驱动器基于比对结果触发所述时序控制器调整所述显示数据信号。
基于上述目的，本申请提供一种显示装置的驱动方法，其包括以下步骤：通过时序控制器最小化显示数据信号的振幅；通过所述时序控制器基于所述显示数据信号生成时序控制校验信号；通过所述时序控制器的高速接口传输所述显示数据信号至所述驱动器，并通过所述时序控制器的低速接口传输所述时序控制校验信号至所述驱动器；通过所述驱动器基于所述显示数据信号生成源极驱动校验信号；以及通过所述驱动器比对所述源极驱动校验信号与所述时序控制校验信号是否相等，若是，通过所述驱动器触发所述时序控制器记录待输出至显示面板的所述显示数据信号，若否，则通过所述驱动器触发所述时序控制器调大所述显示数据信号的振幅，并接着跳回执行通过所述时序控制器基于所述显示数据信号生成所述时序控制校验信号的步骤。
本申请提供一种显示装置和驱动方法。所述显示装置包括时序控制器、驱动器和显示面板。所述驱动器分别与所述时序控制器和所述显示面板连接。所 述时序控制器将显示数据信号和时序控制校验信号发送至所述驱动器。所述驱动器基于所述显示数据信号生成源极驱动校验信号。并且，所述驱动器比对所述源极驱动校验信号与来自所述时序控制器的所述时序控制校验信号，并基于比对结果触发所述时序控制器调整所述显示数据信号。当所述源极驱动校验信号与所述时序控制校验信号相等时，所述驱动器触发所述时序控制器记录所述显示数据信号，并将记录所述显示数据信号发送至所述显示面板进行显示。所述显示装置通过增加校验机制，确保数据传输正确性的情况下尽量降低数据信号的振幅来降低电磁干扰。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图:
图1为本申请一个实施例中显示装置的显示面板和周边电路的示意图；
图2为本申请一个实施例中显示装置的序控制器和驱动电路的示意图；
图3本申请一个实施例提供的显示装置的序控制器和驱动电路的示意图；
图4为本申请一个实施例中显示装置的驱动方法的校验手段的一实施例的示意图；
图5为本申请一个实施例中显示装置的驱动方法的校验手段的另一实施例的示意图；
图6为本申请一个实施例中显示装置的驱动方法的一实施例的步骤流程图；
图7为本申请一个实施例中显示装置的驱动方法的另一实施例的步骤流程图。
主要元件附图标号说明
显示装置100
时序控制器10
分析处理模组11
接收单元12
输出单元13
高速接口131
低速接口132
驱动电路20
驱动器21
逻辑闸22
转换器23
判断器24
触发器25
显示面板30
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其为本申请的显示装置100的显示面板30和周边电路的示意图；图2为本申请的显示装置100的序控制器和驱动电路20的示意图。如图所示，显示装置100包括显示面板30和围绕所述显示面板30的周边电路，其中 显示面板30可以包括显示器和围绕所述显示区的非显示区。
周边电路可以包括控制电路板(Control Board，C/B)，其一般为一块封装印刷线路板(Printed Circuit Board Assembly，PCBA)，上面主要有时序控制器10(Timing Controller，T-CON)提供显示面板30的控制信号和显示数据；源极覆晶薄膜(Source-Chip On Film，S-COF)封装，其为一块覆晶薄膜(Chip On Film,COF)封装的柔性电路板，上边的主要芯片为源极驱动器21(Source Driver，S/D)；门极覆晶薄膜(Gate-Chip On Film，G-COF)封装，其为一块覆晶薄膜封装的柔性电路板，上边的主要芯片为栅极驱动器21(gate on array,GOA)，实际上在一些设置在阵列基板上的栅极驱动电路20上没有单独的栅极驱动器21；电路板XL、XR，分别为两个封装印刷线路板，用以连接控制电路板C/B和源极覆晶薄膜S-COF；柔性扁平电缆(Flexible Flat Cable，FFC)，其用以连接控制电路板C/B和电路板XL或XR等。实际上，对于一些产品，控制电路板C/B和电路板XL或XR合并，没有单独的控制电路板C/B，不需要柔性扁平电缆。
控制电路板C/B上的时序控制器10通过把数据按照微型低压差分信号传输(Miniature-Low Voltage Differential Signaling,Mini-LVDS)的格式或者通用串行接口(Universal serial interface，USI-T)、图像信号处理(Image Signal Processing，ISP)等一些点到点(Point to Point,P2P)传输的格式，将数据经FFC-X/B-COF-S/D的路径传输，这条传输路径一般为了达到减少传输的引脚(PIN)数，传输的频率都很高，按Mini-LVDS协议一般在300MHz左右，所以在这条路径上容易产生电磁干扰问题。为了解决EMI问题，通常的做法是降低Mini-LVDS信号的振幅(Swing)，但是降低信号振幅容易导致源极驱动器21接收不到正确的显示数据，本申请通过增加校验机制，确保数据传输正确性的情况下尽量降低数据信号的振幅来降低电磁干扰。
请参阅图2，其为本申请的显示装置100的序控制器和驱动电路20的示意 图。如图所示，显示装置100包括时序控制器10以及源极驱动器21。
本实施例可选的，时序控制器10在输出显示数据信号至源极驱动器21前，时序控制器10可以最小化显示数据信号的振幅,其中时序控制器10具有接收显示数据信号的信号接收单元12，分析处理模组11以及输出分析后信号的信号输出单元13，显示数据信号在分析处理模组11中透过包含如最小二乘法和梯度下降法等方法构成的运算方法最小化振幅。显示数据信号经分析处理模组11分析后透过信号输出单元13输出。
接着或首先，时序控制器10基于显示数据信号生成时序控制校验信号，接着时序控制器10通过高速接口131传输显示数据信号至源极驱动器21，并通过低速接口132传输时序控制校验信号至源极驱动器21。由于显示数据信号和时序控制校验信号两信号采用的接口传输速度不同，当时序控制器10同的时间点输出显示数据信号和时序控制校验信号时，显示数据信号比时序控制校验信号较早到达源极驱动器21，使源极驱动器21可先后分别对显示数据和时序控制校验信号进行处理。然而，由于显示数据信号由于采用高频的数据传输可能会导致电磁干扰问题，因此本申请在后续对显示数据信号进行校验并适当地调整。
接着，源极驱动器21连接时序控制器10，并基于来自时序控制器10的显示数据信号生成源极驱动校验信号。接着，源极驱动器21比对源极驱动校验信号与来自时序控制器10的时序控制校验信号。若源极驱动器21生成的源极驱动校验信号与来自时序控制器10的时序控制校验信号相等时，源极驱动器21触发时序控制器10直接记录当下的显示数据信号。然而，若源极驱动器21生成的源极驱动校验信号与来自时序控制器10的时序控制校验信号不相等时，源极驱动器21触发时序控制器10调整(例如调大)显示数据信号的特征(例如振幅)。直到，源极驱动校验信号与时序控制校验信号为相等时，源极驱动器21不再触发时序控制器10调整显示数据信号，而是触发时序控制器10记录当 下调整后的显示数据信号。也就是说，直到在确保数据传输正确性的条件下尽可能地降低显示数据信号的振幅，从而降低电磁干扰的可能性。
本实施例可选的，在多个源极驱动器21的情况下，驱动电路20还可以包括逻辑闸22，逻辑闸22连接至时序控制器10以及源极驱动器21之间，各个源极驱动器21比对源极驱动校验信号与时序控制校验信号后输出对应的源极驱动校验信号至逻辑闸22，逻辑闸22基于多个源极驱动器21的多个源极驱动校验信号触发时序控制器10调整显示数据信号。另外，驱动电路20可以包括多个源极驱动器21。在本实施例中，源极驱动器21以四个为例，但不以此为限，实际上亦可以仅有单个或更多的源极驱动器21和适当数量的逻辑闸22。
例如，所述逻辑闸22为与门(AND gate)，所述与门连接至源极驱动器21的输出端子以及时序控制器10的输入端子之间。如图2所示的作为与门的输入的四个源极驱动器21的输出分别为锁定值1、锁定值2、锁定值3和锁定值4，与门的输出为锁定值＝(锁定值1)(锁定值2)(锁定值3)(锁定值4)。当各个源极驱动器21比对源极驱动校验信号与来自时序控制器10的时序控制校验信号为不相等时，所述源极驱动器21输出低准位源极驱动校验信号至与门。相反地，当各个源极驱动器21比对源极驱动校验信号与时序控制校验信号为相等时，所述源极驱动器21输出高准位源极驱动校验信号至与门。接着，当来自多个源极驱动器21的多个源极驱动校验信号中至少一个为低准位时，与门输出低准位信号至时序控制器10，即锁定值＝(锁定值1＝0)(锁定值2)(锁定值3)(锁定值4)＝0x1x1x1＝0时，以触发时序控制器10调大显示数据信号的振幅(时序控制器10可以预先设定为低准位触发调大显示数据信号的振幅)；换个角度说，来自多个源极驱动器21的多个源极驱动校验信号中全部皆为高准位时，即(锁定值1)(锁定值2)(锁定值3)(锁定值4)＝1x1x1x1＝1时，与门始输出高准位信号至时序控制器10，以触发时序控制器10纪录显示数据信号。
或例如，所述逻辑闸22为或门(OR gate)，在此情况下，当各个源极驱动器21比对源极驱动校验信号与来自时序控制器10的时序控制校验信号为不相等时，所述源极驱动器21输出高准位源极驱动校验信号至或门；相反地，当比对为相等时，输出低准位源极驱动校验信号至或门。接着，来自多个源极驱动器21的多个源极驱动校验信号中至少一个为高准位时，或门输出高准位信号至时序控制器10，以触发时序控制器10调大显示数据信号的振幅(时序控制器10可以预先设定为高准位触发调大显示数据信号的振幅)；换个角度说，来自多个源极驱动器21的多个源极驱动校验信号中全部皆为低准位时，或门始输出低准位信号至时序控制器10，在此情况下直接记录显示数据信号而不需对显示数据信号的振幅进行调整。
请参照图3，所述驱动电路20还包括转换器23、判断器24和触发器25。
所述转换器23分别与所述输出单元13的高速接口和低速接口通信连接。所述转换器23基于来自所述时序控制器10的所述显示数据信号生成源极驱动校验信号。所述判断器24分别与所述逻辑闸22和所述转化器23通信连接。所述判断器24比对所述源极驱动校验信号与来自所述时序控制器10)所述时序控制校验信号是否相等。所述触发器25设置于所述判断器24与所述接收单元12之间。所述触发器25可以根据判断结果发送高准位信号或低准位信号至所述接收单元12。所述分析处理模组11根据所述触发器发送的信号调整所述显示数据信号的振幅或记录所述显示数据信号并经所述驱动器21发送至所述显示面板30进行显示。
最后，请再次参照图1，通过控制电路板C/B(包括时序控制器10)调整后的显示数据信号可以通过源极覆晶薄膜(Source-Chip On Film,S-COF)(包括源极驱动器21)输出至显示面板30，使得显示面板30根据调整后的显示数据信号进行显示。
请参阅图4，其为本申请的显示装置100的驱动方法的校验手段的一实施例的示意图。上述时序控制器10以及源极驱动器21基于显示数据信号分别生成的时序控制校验信号以及源极驱动校验信号可各自包括彼此对应的循环冗余校验码CRC。如图4所示，列举了时序控制器10发送显示数据和循环冗余校验码CRC数据关系的一种情况，即时序控制器10(见图2)对每一帧计算一次循环冗余校验码CRC发送给源极驱动器21(见图2)，同时源极驱动器21也每帧计算一次循环冗余校验码CRC。
请参阅图5，其为本申请的显示装置100的驱动方法的校验手段的另一实施例的示意图。上述时序控制器10以及源极驱动器21基于显示数据信号分别生成的时序控制校验信号以及源极驱动校验信号可各自包括彼此对应的循环冗余校验码CRC。不同于图4所示，在图5所示的实施例中，列举了时序控制器10发送显示数据和循环冗余校验码CRC数据关系的另一种情况，即时序控制器10(见图2)对每m行计算一次循环冗余校验码CRC发送给源极驱动器21(见图2)，同时源极驱动器21也m行计算一次循环冗余校验码CRC。
请参阅图6，其为本申请的显示装置100的驱动方法的一实施例的步骤流程图。如图6所示，显示装置100的驱动方法可以包括以下步骤s1至s5：
步骤s1：通过时序控制器10基于显示数据信号生成时序控制校验信号；
步骤s2：通过所述时序控制器10的高速接口131传输所述显示数据信号至所述源极驱动器21，并通过所述时序控制器10的低速接口132传输所述时序控制校验信号至所述源极驱动器21；
步骤s3：通过所述源极驱动器21基于所述显示数据信号生成源极驱动校验信号；
步骤s4：通过所述源极驱动器21比对所述源极驱动校验信号与所述时序控制校验信号；以及
步骤s5：通过所述源极驱动器21基于比对结果触发所述时序控制器10调整所述显示数据信号。
本实施例可选的，所述显示装置100的驱动方法还包括通过所述时序控制器10在输出所述显示数据信号至所述源极驱动器21前最小化所述显示数据信号的振幅,其中时序控制器10具有接收显示数据信号的信号接收单元12，分析处理模组11以及输出分析后信号的信号输出单元13，显示数据信号在分析处理模组11中透过包含如最小二乘法和梯度下降法等方法构成的运算方法最小化振幅。显示数据信号经分析处理模组11分析后透过信号输出单元13输出；以及通过所述源极驱动器21比对所述源极驱动校验信号与来自所述时序控制器10的所述时序控制校验信号为不相等时，通过所述源极驱动器21触发所述时序控制器10调大所述显示数据信号的振幅。
本实施例可选的，还包括通过个所述源极驱动器21比对所述源极驱动校验信号与所述时序控制校验信号后输出对应的所述源极驱动校验信号至逻辑闸22；以及通过所述逻辑闸22基于所述多个所述源极驱动器21的所述多个源极驱动校验信号触发所述时序控制器10调整所述显示数据信号。
本实施例可选的，所述显示装置100的驱动方法还包括通过所述源极驱动器21比对所述源极驱动校验信号与来自所述时序控制器10的所述时序控制校验信号为相等时，通过所述源极驱动器21触发所述时序控制器10记录所述显示数据信号。
根据上述步骤，可以防止由于高频的显示数据传输导致电磁干扰问题。
图7为本申请的显示装置100的驱动方法的另一实施例的步骤流程图。如图7所示，显示装置100的驱动方法可以包括以下步骤a至g：
步骤a：通过时序控制器10最小化显示数据信号的振幅；
步骤b：通过所述时序控制器10基于所述显示数据信号生成时序控制校验 信号；
步骤c：通过所述时序控制器10的高速接口131传输所述显示数据信号至所述源极驱动器21，并通过所述时序控制器10的低速接口132传输所述时序控制校验信号至所述源极驱动器21；
步骤d：通过所述源极驱动器21基于所述显示数据信号生成源极驱动校验信号；以及
步骤e：通过所述源极驱动器21比对所述源极驱动校验信号与所述时序控制校验信号是否相等，若是，执行下列步骤f，若否，则执行下列步骤g：
步骤f：通过所述源极驱动器21触发所述时序控制器10记录待输出至显示面板30的所述显示数据信号；或
g：通过所述源极驱动器21触发所述时序控制器10调大所述显示数据信号的振幅，并接着跳回执行步骤b。
根据上述步骤，可以防止由于高频的显示数据传输导致电磁干扰问题。
需要说明的是，在所述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其他实施例的相关描述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的 其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种显示装置(100)，其中，包括：
    时序控制器(10)，基于显示数据信号生成时序控制校验信号；
    驱动电路(20)，连接至所述时序控制器(10)，并基于来自所述时序控制器(10)的所述显示数据信号生成源极驱动校验信号，所述驱动电路(20)比对所述源极驱动校验信号与所述时序控制校验信号，并基于比对结果触发所述时序控制器(10)调整所述显示数据信号；以及
    显示面板(30)，连接所述驱动电路(20)，通过所述时序控制器(10)调整后的所述显示数据信号通过所述驱动电路(20)输出至所述显示面板(30)进行显示。
  2. 如权利要求1所述的显示装置(100)，其中，所述时序控制器(10)包括：
    分析处理模组(11)，在输出所述显示数据信号至所述驱动电路(20)之前，所述分析处理模组(11)最小化所述显示数据信号的振幅；
    当所述驱动电路(20)比对所述源极驱动校验信号与来自所述时序控制器(10)的所述时序控制校验信号的结果为不相等时，所述驱动电路(20)触发所述时序控制器(10)调大所述显示数据信号的振幅。
  3. 如权利要求2所述的显示装置(100)，其中，所述时序控制器(10)还包括：
    接收单元(12)，与所述分析处理模组(11)连接，设置为接收所述显示数据信号，并将所述显示数据信号发送至所述分析处理模组(11)。
  4. 如权利要求2所述的显示装置(100)，其中，所述时序控制器(10)还包括：
    输出单元(13)，分别与所述分析处理模组(11)和所述驱动电路(20)连接，设置为将所述分析处理模组(11)处理后的信号发送至所述驱动电路(20)。
  5. 如权利要求4所述的显示装置(100)，其中，所述输出单元(13)包括：
    高速接口(131)，与所述驱动电路(10)连接，所述时序控制器(10)通过所述高速接口(131)传输所述显示数据信号至所述驱动电路(20)。
  6. 如权利要求5所述的显示装置(100)，其中，所述输出单元(13)还包括：
    低速接口(132)，与所述驱动电路(10)连接，所述时序控制器(10)通过所述低速接口(132)传输所述时序控制校验信号至所述驱动电路(20)。
  7. 如权利要求1所述的显示装置(100)，其中，所述驱动电路(20)还包括：
    多个驱动器(21)；
    逻辑闸(22)，连接于所述时序控制器(10)以及各个驱动器(21)之间，各个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号后输出对应的所述源极驱动校验信号至所述逻辑闸(22)，所述逻辑闸(22)基于所述多个所述驱动器(21)的所述多个源极驱动校验信号触发所述时序控制器(10)调整所述显示数据信号。
  8. 如权利要求7所述的显示装置(100)，其中，所述逻辑闸(22)为与门，各个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号为不相等时输出低准位所述源极驱动校验信号至所述逻辑闸(22)；各个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号为相等时输出高准位所述源极驱动校验信号至所述逻辑闸(22)，所述逻辑闸(22)基于来自所述多个驱动器(21)的所述多个源极驱动校验信号中至少一个为低准 位时触发所述时序控制器(10)调整所述显示数据信号。
  9. 如权利要求7所述的显示装置(100)，其中，所述逻辑闸(22)为或门，各个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号为不相等时输出低准位所述源极驱动校验信号至所述或门；各个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号为相等时输出高准位所述源极驱动校验信号至所述或门，所述或门基于来自所述多个驱动器(21)的所述多个源极驱动校验信号中均为低准位时触发所述时序控制器(10)调整所述显示数据信号。
  10. 如权利要求1所述的显示装置(100)，其中，所述驱动电路(20)还包括：
    转换器(23)，与所述时序控制器(10)连接，所述转换器(23)基于来自所述时序控制器(10)的所述显示数据信号生成源极驱动校验信号。
  11. 如权利要求10所述的显示装置(100)，其中，所述驱动电路(20)还包括：
    判断器(24)，与所述转换器(23)连接，所述判断器(24)比对所述源极驱动校验信号与来自所述时序控制器(10)的所述时序控制校验信号是否相等。
  12. 如权利要求11所述的显示装置(100)，其中，所述驱动电路(20)还包括：
    触发器(25)，与所述判断器(24)连接，所述判断器(24)判断所述源极驱动校验信号与来自所述时序控制器(10)的所述时序控制校验信号相等时，所述触发器(25)触发所述时序控制器(10)记录所述显示数据信号。
  13. 一种显示装置的驱动方法，其中，包括：
    通过时序控制器(10)基于显示数据信号生成时序控制校验信号；
    通过所述高速接口(131)传输所述显示数据信号至所述驱动器(21)，并 通过所述低速接口(132)传输所述时序控制校验信号至所述驱动器(21)；
    通过所述驱动器(21)基于所述显示数据信号生成源极驱动校验信号；
    通过所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号；
    以及
    通过所述驱动器(21)基于比对结果触发所述时序控制器(10)调整所述显示数据信号。
  14. 如权利要求13所述的显示装置的驱动方法，其中，还包括：
    通过所述时序控制器(10)在输出所述显示数据信号至所述驱动器(21)前最小化所述显示数据信号的振幅。
  15. 如权利要求13所述的显示装置的驱动方法，其中，还包括：
    通过所述驱动器(21)比对所述源极驱动校验信号与来自所述时序控制器(10)的所述时序控制校验信号为不相等时，通过所述驱动器(21)触发所述时序控制器(10)调大所述显示数据信号的振幅。
  16. 如权利要求13所述的显示装置的驱动方法，其中，还包括：
    通过所述驱动器(21)比对所述源极驱动校验信号与来自所述时序控制器(10)的所述时序控制校验信号为相等时，通过所述驱动器(21)触发所述时序控制器(10)记录此时的所述显示数据信号。
  17. 如权利要求13所述的显示装置的驱动方法，其中，还包括：
    通过多个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号后输出对应的所述源极驱动校验信号至所述逻辑闸(22)。
  18. 如权利要求17所述的显示装置的驱动方法，其中，还包括：
    通过所述逻辑闸(22)基于所述多个所述驱动器(21)的所述多个源极驱动校验信号触发所述时序控制器(10)调整所述显示数据信号。
  19. 如权利要求17所述的显示装置的驱动方法，其中，还包括：
    通过多个所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校 验信号后输出对应的所述源极驱动校验信号至所述逻辑闸(22)；
    当所述逻辑闸(22)接收都是高准位信号时，所述逻辑闸(22)输出高准位信号至所述时序控制器(10)，以触发所述时序控制器(10)记录所述显示数据信号；以及
    当所述逻辑闸(22)接收至少一个准位信号时，所述逻辑闸(22)输出低准位信号至所述时序控制器(10)，以触发所述时序控制器(10)调大所述显示数据信号的振幅。
  20. 一种显示装置的驱动方法，其中，包括：
    通过时序控制器(10)最小化显示数据信号的振幅；
    通过所述时序控制器(10)基于所述显示数据信号生成时序控制校验信号；
    通过所述高速接口(131)传输所述显示数据信号至所述驱动器(21)，并通过所述低速接口(132)传输所述时序控制校验信号至所述驱动器(21)；
    通过所述驱动器(21)基于所述显示数据信号生成源极驱动校验信号；以及
    通过所述驱动器(21)比对所述源极驱动校验信号与所述时序控制校验信号是否相等，若是，通过所述驱动器(21)触发所述时序控制器记录待输出至显示面板(30)的所述显示数据信号，若否，则通过所述驱动器(20)触发所述时序控制器(10)调大所述显示数据信号的振幅，并接着跳回执行通过所述时序控制器(10)基于所述显示数据信号生成所述时序控制校验信号。
PCT/CN2018/117431 2018-09-10 2018-11-26 显示装置和驱动方法 Ceased WO2020052080A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/042,813 US11295692B2 (en) 2018-09-10 2018-11-26 Display device and driving method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811051180.0 2018-09-10
CN201811051180.0A CN109036317A (zh) 2018-09-10 2018-09-10 显示装置和驱动方法

Publications (1)

Publication Number Publication Date
WO2020052080A1 true WO2020052080A1 (zh) 2020-03-19

Family

ID=64620903

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/117431 Ceased WO2020052080A1 (zh) 2018-09-10 2018-11-26 显示装置和驱动方法

Country Status (3)

Country Link
US (1) US11295692B2 (zh)
CN (1) CN109036317A (zh)
WO (1) WO2020052080A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102545589B1 (ko) * 2018-12-28 2023-06-21 삼성디스플레이 주식회사 표시 시스템 및 이를 위한 감마 전압 생성 방법
CN110930911A (zh) * 2019-12-02 2020-03-27 Tcl华星光电技术有限公司 一种显示面板控制电路的监测方法及监测系统
CN113345359B (zh) * 2020-03-03 2025-01-10 硅工厂股份有限公司 用于驱动显示装置的数据处理装置、数据驱动装置和系统
CN111445875A (zh) * 2020-04-22 2020-07-24 Tcl华星光电技术有限公司 像素数据信号配置系统及显示面板
US11475863B2 (en) * 2020-06-07 2022-10-18 Himax Technologies Limited Display driving device and anti-interference method thereof
CN112951137B (zh) * 2021-01-29 2023-07-25 深圳市华星光电半导体显示技术有限公司 一种识别信号传送完整性的方法及装置
CN115116380B (zh) * 2021-03-18 2024-10-01 合肥京东方显示技术有限公司 时序控制板、主控制板、显示装置及其检测方法
CN115203104B (zh) * 2022-05-30 2023-11-28 北京奕斯伟计算技术股份有限公司 数据传输方法、时序控制器、源极驱动芯片及系统
CN119380646A (zh) * 2023-07-27 2025-01-28 新加坡商群丰骏科技股份有限公司 车用显示系统
US12462728B2 (en) * 2023-11-06 2025-11-04 Himax Technologies Limited Display system and method with electromagnetic susceptibility
CN119068799B (zh) * 2024-10-29 2025-11-04 昆山龙腾光电股份有限公司 显示装置、时序控制器及其信号处理方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050090644A (ko) * 2004-03-09 2005-09-14 엘지.필립스 엘시디 주식회사 액정표시장치의 구동회로 및 이의 구동방법
JP2007212433A (ja) * 2006-02-08 2007-08-23 Samsung Electronics Co Ltd 信号処理装置、液晶表示装置及び液晶表示装置のテストシステム
CN101635127A (zh) * 2008-07-25 2010-01-27 乐金显示有限公司 显示器件及其驱动方法
CN103489392A (zh) * 2013-10-22 2014-01-01 合肥京东方光电科技有限公司 一种时序控制方法、时序控制器及显示装置
CN107680554A (zh) * 2017-11-22 2018-02-09 深圳市华星光电技术有限公司 显示装置驱动系统及方法
CN108156396A (zh) * 2016-12-06 2018-06-12 矽创电子股份有限公司 显示系统及其视讯数据显示方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582246B (zh) * 2008-05-12 2011-05-04 北京京东方光电科技有限公司 减小电磁干扰的数据驱动系统和数据驱动方法
CN201374641Y (zh) * 2008-12-08 2009-12-30 康佳集团股份有限公司 一种大屏幕液晶电视抗电磁干扰的电路结构
US20100176749A1 (en) * 2009-01-13 2010-07-15 Himax Technologies Limited Liquid crystal display device with clock signal embedded signaling
CN101833924A (zh) * 2009-03-11 2010-09-15 奇景光电股份有限公司 具有时钟信号内嵌传送的液晶显示器
KR102154186B1 (ko) * 2013-12-03 2020-09-10 삼성전자 주식회사 테스트 효율성을 향상한 타이밍 콘트롤러, 소스 드라이버, 디스플레이 구동회로 및 디스플레이 구동회로의 동작방법
WO2016143550A1 (ja) * 2015-03-06 2016-09-15 シャープ株式会社 表示装置およびその駆動方法
KR102288319B1 (ko) * 2015-06-10 2021-08-11 삼성디스플레이 주식회사 표시 장치 및 그 제어 방법
CN106098017B (zh) * 2016-08-25 2019-02-22 深圳市华星光电技术有限公司 一种降低电磁干扰的驱动方法及驱动装置
KR102549463B1 (ko) * 2016-08-30 2023-06-30 삼성전자주식회사 이미지 처리 방법 및 이를 지원하는 전자 장치
CN106205535B (zh) * 2016-08-30 2019-02-22 深圳市华星光电技术有限公司 一种降低液晶显示装置数据信号电磁干扰的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050090644A (ko) * 2004-03-09 2005-09-14 엘지.필립스 엘시디 주식회사 액정표시장치의 구동회로 및 이의 구동방법
JP2007212433A (ja) * 2006-02-08 2007-08-23 Samsung Electronics Co Ltd 信号処理装置、液晶表示装置及び液晶表示装置のテストシステム
CN101635127A (zh) * 2008-07-25 2010-01-27 乐金显示有限公司 显示器件及其驱动方法
CN103489392A (zh) * 2013-10-22 2014-01-01 合肥京东方光电科技有限公司 一种时序控制方法、时序控制器及显示装置
CN108156396A (zh) * 2016-12-06 2018-06-12 矽创电子股份有限公司 显示系统及其视讯数据显示方法
CN107680554A (zh) * 2017-11-22 2018-02-09 深圳市华星光电技术有限公司 显示装置驱动系统及方法

Also Published As

Publication number Publication date
CN109036317A (zh) 2018-12-18
US11295692B2 (en) 2022-04-05
US20210020136A1 (en) 2021-01-21

Similar Documents

Publication Publication Date Title
WO2020052080A1 (zh) 显示装置和驱动方法
US8418046B2 (en) Data signal handling circuitry and methods with error analysis capabilities
WO2018036097A1 (zh) 一种降低电磁干扰的驱动方法及驱动装置
TW201616471A (zh) 顯示器驅動裝置及顯示裝置的驅動方法
CN106297721A (zh) 液晶面板驱动电路及液晶显示装置
CN101217651B (zh) 处理串行化的视频数据以用于显示的方法和设备
TWI292569B (en) Chip-on-glass liquid crystal display and transmission method thereof
KR100701086B1 (ko) 액정표시장치의 구동회로
KR20060097552A (ko) 액정 표시 장치 구동 시스템
US7617347B2 (en) Data transfer control device and electronic instrument
CN101197114A (zh) 液晶显示器中时序控制器至源极驱动装置的数据传输方法
US10672316B2 (en) COF circuit board, display device, signal processing method and bridging chip
US20190197929A1 (en) Driving apparatus of display panel and operation method thereof
US10013380B2 (en) Method and system for address decoding in a data communications system using a serial data transfer bus
US8471804B2 (en) Control signal generation method of integrated gate driver circuit, integrated gate driver circuit and liquid crystal display device
CN100416349C (zh) 采用玻璃覆晶封装的液晶显示器及其数据传输方法
CN101819744A (zh) 栅极驱动器及其所应用的液晶显示器
CN101354876B (zh) 栅极驱动集成电路及其控制信号产生方法及液晶显示器
CN102855850A (zh) 电子装置和液晶显示模组
TWI725863B (zh) 顯示裝置、操作方法、驅動電路以及時序控制電路
CN110956913B (zh) 时序控制器验证系统及时序控制器验证方法
US7774516B2 (en) Communicating system and method thereof
US20220270231A1 (en) Circuit Device, Electronic Apparatus, And Image Processing Method
CN100594539C (zh) 源极驱动器
CN101533612A (zh) 液晶显示装置及其驱动模块

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18933623

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 29.06.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18933623

Country of ref document: EP

Kind code of ref document: A1