WO2020051992A1 - 一种驱动电路、驱动方法和显示面板 - Google Patents

一种驱动电路、驱动方法和显示面板 Download PDF

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Publication number
WO2020051992A1
WO2020051992A1 PCT/CN2018/111332 CN2018111332W WO2020051992A1 WO 2020051992 A1 WO2020051992 A1 WO 2020051992A1 CN 2018111332 W CN2018111332 W CN 2018111332W WO 2020051992 A1 WO2020051992 A1 WO 2020051992A1
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WO
WIPO (PCT)
Prior art keywords
transistor
sub
pixel
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/111332
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English (en)
French (fr)
Inventor
黄笑宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US16/340,384 priority Critical patent/US11475856B2/en
Publication of WO2020051992A1 publication Critical patent/WO2020051992A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • the present application relates to the field of display technology, and more particularly, to a driving circuit, a driving method, and a display panel.
  • liquid crystal displays have become mainstream products due to their thin body, power saving and low radiation, which have been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of a liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage to the two glass substrates to control the rotation direction of the liquid crystal molecules so as to refract the light of the backlight module to generate a picture.
  • OLED Organic Light-Emitting Diode
  • the system motherboard connects the R / G / B compression signal, control signal and power supply to the connector on the PCB through the wire, and the data passes through the TCON (Timing Controller) on the PCB.
  • TCON Transmission Controller
  • the IC is processed, it is connected to the display area through the PCB through S-COF (Source-Chip on Film) and G-COF (Gate-Chip on Film).
  • S-COF Source-Chip on Film
  • G-COF Gate-Chip on Film
  • the present application provides a driving circuit, a driving method, and a display panel that are advantageous for saving scan lines and / or data lines.
  • a driving circuit including:
  • pixels including a first sub-pixel and a second sub-pixel
  • a scanning line connected to the gate ends of the first subpixel and the second subpixel
  • a data line connected to source extremes of the first subpixel and the second subpixel
  • a switching circuit for switching the connection relationship between the scan line, the data line, the first sub-pixel and the second sub-pixel, so that one or both of the first sub-pixel and the second sub-pixel are related to the scan line and data Line connection
  • the first subpixel and the second subpixel are connected to the same scan line and the same data line.
  • the driving circuit of the present application since the first subpixel and the second subpixel are respectively connected by the same scanning line and the same data line, and a switching circuit is provided, the first subpixel and the second subpixel are switched with the scanning line and The conduction relationship of the data lines. In this way, the driving circuit can control one of the sub-pixels to be connected to the scanning line and the data line while the other sub-pixel is not connected.
  • the data lines are connected; thus, by using one scan line and one data line, and controlling the first sub-pixel and the second sub-pixel to work separately, the use of the scan line and the data line is saved; and, if necessary, the One of the first subpixel and the second subpixel is connected to the scanning line data line, reducing the first subpixel and the second subpixel, and displaying the same screen for a long time, and the problem of "burning screen" appears, which is beneficial to delaying the display panel Life.
  • FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present application
  • FIG. 2 is a circuit diagram of a driving circuit according to an embodiment of the present application.
  • FIG. 3 is a circuit diagram of a driving circuit according to another embodiment of the present application.
  • FIG. 4 is a circuit diagram of another driving circuit according to an embodiment of the present application.
  • FIG. 5 is a flowchart of a driving method applicable to a driving circuit according to an embodiment of the present application.
  • FIG. 6 is a flowchart of a driving method applicable to a driving circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a driving circuit according to the present application
  • FIG. 2 is a circuit diagram of a driving circuit according to an embodiment of the present application
  • FIG. 3 is a circuit diagram of a driving circuit according to another embodiment of the present application
  • FIG. 4 is another embodiment of the present application.
  • a circuit diagram of a driving circuit is shown in FIG. 1 to FIG. 4.
  • An embodiment of the present application discloses a driving circuit 1 including:
  • a plurality of pixels including a first sub-pixel 40 and a second sub-pixel 50;
  • the scanning line 10 is connected to the gate ends of the first sub-pixel 40 and the second sub-pixel 50;
  • the data line 20 is connected to the source terminals of the first sub-pixel 40 and the second sub-pixel 50;
  • the switching circuit 30 switches the connection relationship between the scan line 10, the data line 20, the first sub-pixel 40 and the second sub-pixel 50, so that one or both of the first sub-pixel 40 and the second sub-pixel 50 are connected. It is in communication with the scanning line 10 and the data line 20.
  • the driving circuit of the present application since the first subpixel and the second subpixel are respectively connected by the same scanning line and the same data line, and a switching circuit is provided, the first subpixel and the second subpixel are switched with the scanning line and The conduction relationship of the data lines. In this way, the driving circuit can control one of the sub-pixels to be connected to the scanning line and the data line while the other sub-pixel is not connected.
  • the data lines are connected; thus, by using one scan line and one data line, and controlling the first sub-pixel and the second sub-pixel to work separately, the use of the scan line and the data line is saved; and, if necessary, the One of the first subpixel and the second subpixel is connected to the scanning line data line, reducing the first subpixel and the second subpixel, and displaying the same screen for a long time, and the problem of "burning screen" appears, which is beneficial to delaying the display panel Life.
  • the pixel further includes a third subpixel, a fourth subpixel, a fifth subpixel, and a sixth subpixel;
  • the first and second sub-pixels 40 and 50 are red sub-pixels; the third and fourth sub-pixels are green sub-pixels; and the fifth and sixth sub-pixels are blue sub-pixels .
  • two sub-pixels are used as one pixel.
  • two red sub-pixels are used as a pixel.
  • the two red sub-pixels can be controlled by the switching circuit under the control of the switching circuit. , Controlling one or two of them to be connected to the scanning line and the data line at the same time, while saving the scanning line and the data line, so that the two red sub-pixels can turn off the connection to the scanning line and the data line when needed, Avoid the problem of “burning screen” caused by the red sub-pixel displaying the same screen for a long time; of course, the sub-pixel can also be a green sub-pixel, a blue sub-pixel, or even a white sub-pixel and a yellow sub-pixel.
  • the first subpixel 40 and the second subpixel 50 include a red subpixel, a green subpixel, and a blue subpixel, respectively.
  • two sub-pixels are used as one pixel.
  • two red sub-pixels, two green sub-pixels, and two blue sub-pixels are structured as one pixel, and divided into two groups respectively connected to the switch circuit.
  • Scan line and data line, two sub-pixels can be controlled under the control of the switching circuit, one or two of them can be connected to the scan line and data line at the same time, while saving the scan line and data line, the two sub-pixels can be When the connection with the scan line and the data line is turned off, the problem of “burn-in” caused by the sub-pixel displaying the same screen for a long time is avoided; of course, the sub-pixels contained in the sub-pixel are not necessarily in the same row, for example ,
  • the first row of pixels includes a first red subpixel, a first green subpixel, and a first blue subpixel, and the second row of pixels includes a second red subpixel, a second green subpixel, and a second blue subpixel, and
  • the first sub-pixel may include
  • the switching circuit 30 includes a gate line switching circuit 32 and a gate line switching signal A that controls the gate line switching circuit 32;
  • the gate line switching circuit 32 includes a first transistor M1, a second transistor M2, a first storage capacitor C1, and a second storage capacitor C2;
  • the first transistor M1 is a transistor whose control terminal is turned on in a negative polarity, and the second
  • the transistor M2 is a transistor in which the control terminal is turned on in a positive polarity;
  • the source of the first transistor M1 is connected to the scan line 10, and the drain is connected to the first storage capacitor C1 and the gate terminal of the first sub-pixel;
  • the source of the second transistor M2 is connected to the scan line 10, and the drain is connected to the second storage capacitor C2 and the gate terminal of the second sub-pixel;
  • the gates of the first transistor M1 and the second transistor M2 are connected to each other, and are connected to a gate line switching signal A.
  • the scanning line 10 receives the gate line signal GateOutput, and the data line 20 transmits the data signal SourceOutput.
  • the transistor generally refers to a metal-oxide-semiconductor field-effect transistor, that is, a MOS tube (metal oxide semiconductor); of course, it can also be a component with other similar functions.
  • the transistor with a negative polarity at the control terminal is a P-channel MOS transistor, which is P-MOS; and the transistor with a positive polarity at the control terminal is an N-channel MOS transistor, which is N-MOS.
  • the switching circuit includes a gate line switching circuit, wherein the first sub-pixel and the second sub-pixel are connected to a scanning line through the gate line switching circuit, respectively, because the gates of the first transistor and the second transistor are connected to each other.
  • the gates of the first transistor and the second transistor are a transistor with a negative polarity on the control terminal and a transistor with a negative polarity on the control terminal. Therefore, at the same time, the first subpixel and the second subpixel are at the same time. There is only one connected and working, and the first sub pixel and the winning sub pixel can be switched by the gate line switching signal. Therefore, the first sub pixel and the second sub pixel can avoid the problem of displaying the same picture for a long time, reducing or even avoiding A "burning screen" situation occurred.
  • the gate line switching signal A is a logic signal output by a timing control chip (TCON).
  • the first transistor M1 is an N-type crystal with a negative polarity, which is turned on when the gate signal is L, and is turned off when its gate signal is H;
  • the second transistor M2 is an N-type crystal, which is turned on with a positive polarity. It turns on when the gate signal is H, and turns off when its gate signal is L.
  • the first transistor M1 and the second transistor M2 are located in the non-display area of the liquid crystal panel and are generated by a shared array process.
  • the scan line 20 receives a gate-on signal GateOutput, and the gate-on signal GateOutput is output by a gate driving chip (G-COF).
  • G-COF gate driving chip
  • the display pixels (red sub-pixel, green sub-pixel, blue sub-pixel, red sub-pixel) in the panel are divided into two parts, a and b.
  • the first red sub-pixel R1a, the first green sub-pixel G1a, the first blue sub-pixel B1a, and the fourth red sub-pixel R2b are connected to the first storage capacitor C1 corresponding to the first transistor M1, and the second red sub-pixel R1b, the first The two green sub-pixels G1b, the second blue sub-pixel B1b, and the third red sub-pixel R2a are connected to the second storage capacitor C2 corresponding to the second transistor M2.
  • the refresh rate of the panel display is 120Hz or 60Hz. Take 120Hz as an example, that is, 120 frames per second can be displayed.
  • the gate line switching signal A in the first half of the turn-on time of each line is output to a low level L, and TCON normally outputs the picture.
  • the first transistor M1 is turned on and the second transistor M2 is turned off.
  • the pixels connected to the first storage capacitor C1 can be displayed normally.
  • the gate line switching signal A is output to a high level H, and TCON outputs a black screen.
  • the pixel connected to the second storage capacitor C2 is overwritten with a black screen.
  • the gate line switching signal A in the first half of the turn-on time of each line is output to a high level H, and TCON normally outputs the picture.
  • the second transistor M2 is turned on and the first transistor M1 is turned off.
  • the pixels connected to the second storage capacitor C2 can be displayed normally.
  • the gate line switching signal A is output as a low level L, and TCON outputs a black screen.
  • the pixels connected to the first storage capacitor C1 are overwritten as a black screen.
  • every pixel will experience two states of light and dark every other frame, avoiding the damage to the pixels caused by displaying the same screen for a long time, and finally avoiding the screen burn-in phenomenon.
  • the driving circuit 1 further includes a ground control signal B that controls the data line 20 or the ground GND;
  • the switching circuit 30 further includes a ground switching circuit 31.
  • the ground switching circuit 31 includes a third transistor M3 and a fourth transistor M4.
  • the third transistor M3 is a transistor whose control terminal is turned on in a negative polarity.
  • the fourth transistor M4 is a transistor with a positive polarity at the control end;
  • the gates of the third transistor M3 and the fourth transistor M4 are connected to each other, and are connected to the ground control signal B;
  • the source of the third transistor M3 is grounded, and the drain is connected to the source terminals of the first and second sub-pixels;
  • the source of the fourth transistor M4 is connected to the data line 20, and the drain is connected to the source terminals of the first and second sub-pixels.
  • the scan line 10 receives a gate line signal GateOutput, and the data line 20 receives a data signal SourceOutput.
  • the switching circuit further includes a third transistor and a fourth transistor that are controlled to communicate with the data line or ground.
  • the third transistor and the fourth transistor may be coordinated with the ground control signal under the control of the ground control signal.
  • the gate line switching signal so that the first sub-pixel or the second sub-pixel connected to the scanning line can be connected to the data line at the same time to display the picture normally; and the second sub-pixel or the second sub-pixel whose communication with the scanning line is turned off is turned off.
  • the first sub-pixel can display a black screen by grounding when the scan line is not connected; for example, the first sub-pixel can be controlled to display a normal screen in the first half of a frame and a black screen in the second half.
  • the second sub-pixel can display a black picture in the first half of a frame and a normal picture in the second half.
  • the first sub-pixel and the second sub-pixel can go through two frames in each frame.
  • the light and dark states prevent damage to the pixels caused by displaying the same screen for a long time, and finally avoid screen burn-in.
  • a gate line switching signal A is output as a low-level L and a ground control signal B in the first half of each row on time.
  • the output is high-level H.
  • the first transistor M1, the fourth transistor M4 are turned on, and the second transistor M2, the third transistor M3 are turned off.
  • the pixels connected to the first storage capacitor C1 can be displayed normally.
  • the gate line switching signal A is output as a high level H
  • the ground control signal B is output as a low level L.
  • the first transistor M1, the fourth transistor M4 are turned off, and the second transistor M2, the first The three transistors M3 are turned on, and the pixels connected to the second storage capacitor C2 are connected to the ground GND.
  • the first half of the turn-on time of each line is output as low-level L and the ground control signal B is output as low-level L.
  • the first transistor M1 and the third transistor M3 is turned on, and the second transistor M2 and the fourth transistor M4 are turned off.
  • the pixel connected to the first storage capacitor C1 is displayed as a black screen because it is connected to the ground GND; the gate line switching signal A is output as a high level H and the ground control signal B is output as a high level in the second half of each line on time H.
  • the first transistor M1, the third transistor M3 are turned off, the second transistor M2, the fourth transistor M4 is turned on, and the pixels connected to the second storage capacitor C2 can be displayed normally.
  • every pixel will experience two states of light and dark every other frame, avoiding the damage to the pixels caused by displaying the same screen for a long time, and finally avoiding the screen burn-in phenomenon.
  • the driving circuit 1 further includes a switching signal C that controls the switching circuit 30;
  • the switching circuit 30 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.
  • the first transistor M1 and the fourth transistor M4 are transistors with a positive polarity of the control terminal, and the second transistor M2 and the third transistor M3 are transistors with a negative polarity of the control terminal;
  • the source of the first transistor M1 is connected to the data line 20, and the drain is connected to the source terminal of the first sub-pixel;
  • the source of the second transistor M2 is connected to the data line 20, the drain is connected to the source terminal of the first sub-pixel, and the gate is connected to the switching signal C;
  • a source of the third transistor M3 is grounded, and a drain is connected to a source terminal of the second sub-pixel;
  • a source of the fourth transistor M4 is grounded, a drain is connected to a source terminal of the second sub-pixel, and a gate is connected to the switching signal;
  • the gates of the first transistor M1 and the fourth transistor M4 are connected to each other, and are connected to the switching signal C.
  • the scan line 10 receives a gate line signal GateOutput, and the data line 20 receives a data signal SourceOutput.
  • the switching circuit includes a first transistor and a second transistor that control the first subpixel and the second subpixel to be connected to the data line, and also includes a third transistor and a fourth transistor that control the data line or ground. ;
  • the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor are all connected to a switching signal, in view that the first transistor and the fourth transistor are transistors whose control terminals are positively turned on, the first transistor
  • the second transistor and the third transistor are transistors with negative polarity at the control end. Therefore, under the control of the switching signal, one of the first subpixel and the second subpixel can be controlled to connect to the data line while the other is grounded.
  • the first sub-pixel can be controlled to display a normal picture on the first frame of the two-frame picture and a black picture on the second frame, and the second sub-pixel to display the normal picture on the second frame of the two-frame picture and the first The frame displays a black screen.
  • the first subpixel and the second subpixel can experience two bright and dark states in every two frames, avoiding long-term display. Damage to a screen pixel, and ultimately avoid burn-in phenomenon.
  • the switching signal C is a logic signal output by a timing control chip (TCON).
  • the second transistor M2 and the third transistor M3 are N-type crystals that are turned on in a negative polarity, and are turned on when the gate signal is at a low level L, and turned off when the gate signal is at a high level H;
  • the fourth transistor M4 is an N-type crystal that is turned on in a positive polarity, and is turned on when the gate signal is high level H, and turned off when the gate signal is low level L;
  • the third transistor M3 and the fourth transistor M4 are located in a non-display area of the liquid crystal panel and are generated through a shared array process.
  • the scan line 20 receives a gate-on signal GateOutput, and the gate-on signal GateOutput is output by a gate driving chip (G-COF).
  • the data line 10 receives a data signal Source Output, which is a signal output from a data driving chip (S-COF) to a pixel electrode.
  • the display pixels (red sub-pixel R1, green sub-pixel G1, blue sub-pixel B1, and red sub-pixel R2) in the panel are divided into two parts, a and b.
  • It may include the first red sub-pixel R1a and the second red sub-pixel R1b, or may include the first red sub-pixel R1a, the first green sub-pixel G1a, and the first blue sub-pixel B1a, respectively; the second red sub-pixel R1b , A second green sub-pixel G1b, and a second blue sub-pixel B1b.
  • the display pixels (red sub-pixel, green sub-pixel, blue sub-pixel, and red sub-pixel) in the panel are divided into two parts, a and b.
  • the first red sub-pixel R1a, the first green sub-pixel G1a, the first blue sub-pixel B1a, and the fourth red sub-pixel R2b are connected to the first storage capacitor C1 corresponding to the first transistor M1, and the second red sub-pixel R1b, the first The two green sub-pixels G1b, the second blue sub-pixel B1b, and the third red sub-pixel R2a are connected to the second storage capacitor C2 corresponding to the second transistor M2.
  • TCON output switching signal C is H.
  • M1, M4 are turned on, and M2 and M3 are turned off.
  • Source Output is connected to B1, and GND is connected to B2.
  • R1b can normally display the corresponding screen output by TCON, and R1a is displayed as a black screen because it is connected to GND.
  • TCON output C is at a low level L.
  • the second transistor M2, the third transistor M3 is turned on, and the first transistor M1, the fourth transistor M4 is turned off.
  • the data line or Source Output is connected to the first sub-pixel, and the ground GND is connected to the second sub-pixel.
  • the first red sub-pixel R1a can normally display the corresponding screen output by TCON, and the second red sub-pixel R1b is displayed as a black screen because it is connected to GND.
  • every pixel of every two frames will experience two states of light and dark, avoiding the damage to the pixels caused by displaying the same screen for a long time, and finally avoiding the screen burn-in phenomenon.
  • the scan line 10 is connected to the gate ends of the first sub-pixel and the second sub-pixel at the same time.
  • the scanning line when a scanning line is used, the scanning line can control the work of the first subpixel and the second subpixel respectively; the first subpixel and the second subpixel can be the same Two sub-pixels in a pixel can also be two adjacent pixels.
  • FIG. 5 is a flowchart of a driving method applicable to a driving circuit according to an embodiment of the present application. Referring to FIG. 5 and FIG. 1 to FIG. 4, it is known that the present application also provides a disclosure suitable for any disclosure of the present application.
  • the driving method of a driving circuit includes steps:
  • S52 Control the second sub-pixel to display the second half of a frame on a normal screen, and control the first sub-pixel to display a black frame on the second half of a frame.
  • each frame of the first sub-pixel and the second sub-pixel will experience light and dark states, so as to avoid displaying the same screen for a long time and causing damage to the pixels, thereby avoiding the “burn-in” phenomenon.
  • the sub-pixel and the second sub-pixel are controlled to be turned off by the switching circuit. Therefore, the switching display of the first sub-pixel and the second sub-pixel of the present application does not affect the resolution of the display panel and does not cause the resolution. The reduction.
  • FIG. 6 is a flowchart of a driving method applicable to another driving circuit of the embodiment of the present application. Referring to FIG. 6 and FIG. 1 to FIG. 5, it can be seen that:
  • the driving method of the disclosed driving circuit includes steps:
  • the first and second sub-pixels will experience light and dark states every two frames, to avoid displaying the same screen for a long time, causing damage to the pixels, and thus avoiding the "burn-in" phenomenon.
  • a sub-pixel and a second sub-pixel are respectively controlled to be turned off by the switching circuit. Therefore, the switching display of the first sub-pixel and the second sub-pixel of the present application does not affect the resolution of the display panel and does not cause discrimination. Rate reduction.
  • FIG. 7 is a schematic diagram of a display panel of the present application. Referring to FIG. 7 and FIG. 1 to FIG. 6, it can be seen that:
  • the present application further provides a display panel including the driving circuit 1 as disclosed in the present application;
  • the display panel 100 further includes an array substrate 2 including a display area 3 and a non-display area 4;
  • the display panel 100 further includes an array substrate 2 including a display area 3 and a non-display area 4;
  • the switching circuit 30 is disposed in the non-display area 4;
  • the switching circuit 30 and the array substrate 2 are formed by a common array process
  • the switching circuit 30 may include at least one of a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are formed with the array substrate through a common array process.
  • the display panel of the present application includes a new type of driving circuit in which the first sub-pixel and the second sub-pixel are connected by the same scanning line and the same data line, respectively, and a switching circuit is provided to switch the The conducting relationship between the first subpixel and the second subpixel and the scanning line and the data line.
  • the driving circuit can control one of the subpixels to be connected to the scanning line and the data line while the other subpixel is not. You can also control the connection of both sub-pixels with the scanning line and the data line. In this way, through one scanning line and one data line, and controlling the first sub-pixel and the second sub-pixel to work separately, the scanning line and the data line are saved.
  • one of the first subpixel and the second subpixel may be disconnected from the scan line data line, the first subpixel and the second subpixel may be reduced, and the same screen may be displayed for a long time.
  • the problem of "burning screen" is beneficial to delaying the service life of the display panel.
  • the panel of this application is an OLED panel, of course, it can also be a TN panel (full name is Twisted Nematic, that is, a twisted nematic panel), an IPS panel (N-type PlaneSwitcing (plane conversion) with positive conduction), and a VA panel (Multi- domain vertical alignment (multi-quadrant vertical alignment technology), of course, other types of panels, such as organic light-emitting display panels (organic light-emitting diodes, OLED display panels for short), can be applied.
  • TN panel full name is Twisted Nematic, that is, a twisted nematic panel
  • IPS panel N-type PlaneSwitcing (plane conversion) with positive conduction
  • VA panel Multi- domain vertical alignment (multi-quadrant vertical alignment technology)
  • organic light-emitting display panels organic light-emitting diodes, OLED display panels for short

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Abstract

一种驱动电路(1)、驱动方法和显示面板(100)，包括：多个像素，所述像素包括第一子像素(40)和第二子像素(50)；切换电路(30)，使得第一子像素(40)和第二子像素(50)中的一个或两个与扫描线(10)和数据线(20)连通。

Description

一种驱动电路、驱动方法和显示面板
本申请要求于2018年09月11日提交中国专利局、申请号为CN 201811054995.4、发明名称为“一种驱动电路、驱动方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，更具体的说，涉及一种驱动电路、驱动方法和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlightmodule)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
OLED(Organic Light-Emitting Diode，有机电致发光技术)是当前平板显示的前沿技术，已经成为了现代IT、视讯产品中重要研究方向。OLED主要驱动原理，系统主板将R/G/B压缩信号、控制信号及电源通过线材与PCB板上的连接器(connector)相连接，数据经过PCB板上的TCON(Timing Controller，时序控制器)IC处理后，经PCB板，通过S-COF(Source-Chip on Film，源极薄膜驱动芯片)和G-COF(Gate-Chip on Film，栅极薄膜驱动芯片)与显示区连接，从而使得屏幕显示获得所需的电源、信号。
因而，OLED的相应改进，例如关于OLED的显示驱动架构等技术成为本领域技术人员热衷的研究方法。
技术解决方案
有鉴于上述示例性技术的缺陷，本申请提供一种有利于节约扫描线和/或数据线的一种驱动电路、驱动方法和显示面板。
为实现上述目的，本申请提供了一种驱动电路，包括：
多个像素，所述像素包括第一子像素和第二子像素；
扫描线，连接于所述第一子像素和第二子像素的栅极端；
数据线，连接于所述第一子像素和第二子像素的源极端；
切换电路，切换所述扫描线、数据线、第一子像素和第二子像素的连接关系，使得所述第一子像素和第二子像素中的一个或两个与所述扫描线和数据线连通；
所述第一子像素和第二子像素与同一条扫描线和同一条数据线连接。
本申请的驱动电路，由于第一子像素和第二子像素分别受到同一条扫描线和同一条数据线连接，并且设置有切换电路，切换该第一子像素和第二子像素与扫描线和数据线的导通关系，如此，该驱动电路在工作时，可以控制其中一个子像素与扫描线和数据线连接，而另一个子像素则不连接；也可以控制两个子像素都与扫描线和数据线连接；如此，通过一条扫描线和一条数据线，并控制该第一子像素和第二子像素分别工作，节约了扫描线和数据线的使用；并且，在必要时，可以关断该第一子像素和第二子像素的其中一个与扫描线数据线的连接，减少该第一子像素和第二子像素，长期显示同一画面而出现“烧屏”的问题，有利于延迟显示面板的使用寿命。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种驱动电路的示意图；
图2是本申请实施例一种驱动电路的电路图；
图3是本申请另一实施例一种驱动电路的电路图；
图4是本申请实施例又一种驱动电路的电路图；
图5是本申请一种适用于本申请实施例一种驱动电路的驱动方法的流程图；
图6是本申请一种适用于本申请另一实施例一种驱动电路的驱动方法的流程图；
图7是本申请实施例一种显示面板的示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是以描述本申请的示例性实施例为目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请作说明。
图1是本申请一种驱动电路的示意图，图2是本申请实施例一种驱动电路的电路图，图3是本申请另一实施例一种驱动电路的电路图，图4是本申请实施例又一种驱动电路的电路图，如图1至图4所示，本申请实施例公布了一种一种驱动电路1，包括：
多个像素，所述像素包括第一子像素40和第二子像素50；
扫描线10，连接于所述第一子像素40和第二子像素50的栅极端；
数据线20，连接于所述第一子像素40和第二子像素50的源极端；
切换电路30，切换所述扫描线10、数据线20、第一子像素40和第二子像素50的连接关系，使得所述第一子像素40和第二子像素50中的一个或两个与所述扫描线10和数据线20连通。
本申请的驱动电路，由于第一子像素和第二子像素分别受到同一条扫描线和同一条数据线连接，并且设置有切换电路，切换该第一子像素和第二子像素与扫描线和数据线的导通关系，如此，该驱动电路在工作时，可以控制其中一个子像素与扫描线和数据线连接，而另一个子像素则不连接；也可以控制两个子像素都与扫描线和数据线连接；如此，通过一条扫描线和一条数据线，并控制该第一子像素和第二子像素分别工作，节约了扫描线和数据线的使用；并且，在必要时，可以关断该第一子像素和第二子像素的其中一个与扫描线数据线的连接，减少该第一子像素和第二子像素，长期显示同一画面而出现“烧屏”的问题，有利于延迟显示面板的使用寿命。
本实施例可选的，所述像素还包括第三子像素、第四子像素、第五子像素和第六子像素；
所述第一子像素40和第二子像素50为红色子像素；所述第三子像素和第四子像素为绿色子像素；所述第五子像素和第六子像素为蓝色子像素。
本方案中，将两个子像素作为一个像素，例如将两个红色子像素作为一个像素进行架构，并通过切换电路分别连接到扫描线和数据线，两个红色子像素可以在切换电路的控制下，控制其中一个或者两个同时连接到扫描线和数据线，在节约扫描线和数据线的同时，使得该两个红色子像素可以在需要的时候关断与该扫描线和数据线的连接，避免红色子像素长时间显示同一画面而造成“烧屏”的问题；当然，该子像素也 可以是绿色子像素、蓝色子像素甚至是白色子像素和黄色子像素，适用即可。
本实施例可选的，所述第一子像素40和第二子像素50分别包括一个红色子像素、一个绿色子像素和一个蓝色子像素。
本方案中，将两个子像素作为一个像素，例如将两个红色子像素、两个绿色子像素和两个蓝色子像素，作为一个像素进行架构，并划分为两组通过切换电路分别连接到扫描线和数据线，两个子像素可以在切换电路的控制下，控制其中一个或者两个同时连接到扫描线和数据线，在节约扫描线和数据线的同时，使得该两个子像素可以在需要的时候关断与该扫描线和数据线的连接，避免子像素长时间显示同一画面而造成“烧屏”的问题；当然，该子像素所包含的子像素不一定是在同一行的，例如，第一行像素包括第一红色子像素、第一绿色子像素和第一蓝色子像素，第二行像素包括第二红色子像素、第二绿色子像素和第二蓝色子像素，而该第一子像素可以包括第一红色子像素、第二子像素和第一子像素，而该第二子像素可以包括第二红色子像素、第一子像素和第二子像素；当然，其他的像素架构也是可以的，根据实际情况灵活设置，适用即可。
其中，因为OLED的自发光特性，长时间显示同一画面，会导致对应画素的材料特性衰减速度与其余画素不同，使得输入相同的电流，两类画素的显示亮度不同，显示出无法消除的印记，即所谓“烧屏”。为了更好的解决“烧屏”的技术问题，申请人改进得到如下的方案：
本实施例可选的，所述切换电路30包括栅线切换电路32，以及控制所述栅线切换电路32的栅线切换信号A；
所述栅线切换电路32包括第一晶体管M1、第二晶体管M2、第一存储电容C1和第二存储电容C2；所述第一晶体管M1为控制端负极性导通的晶体管，所述第二晶体管M2为控制端正极性导通的晶体管；
所述第一晶体管M1的源极连接于扫描线10，漏极连接于所述第一存储电容C1以及所述第一子像素的栅极端；
所述第二晶体管M2的源极连接于扫描线10，漏极连接于所述第二存储电容C2以及所述第二子像素的栅极端；
所述第一晶体管M1和第二晶体管M2的栅极相互连接，且连接于栅线切换信号A。
其中该扫描线10接收栅线信号Gate Output，该数据线20传输数据信号Source Output。
其中，该晶体管一般指的是金属—氧化物—半导体场效应晶体管，即MOS管(metal oxide semiconductor)；当然，也可以是其他相似功能的部件。其中，控制端负极性导通的晶体管即P沟道的MOS管，即P-MOS；其中，控制端正极性导通的晶体管即N沟道的MOS管，即N-MOS。
本方案中，该切换电路包括栅线切换电路，其中，该第一子像素和第二子像素分别通过该栅线切换电路连接于扫描线，由于该第一晶体管和第二晶体管栅极相互连接，且该第一晶体管和第二晶体管栅极一个为控制端负极性导通的晶体管一个为控制端负极性导通的晶体管，因而，该第一子像素和第二子像素，在同一时间，仅有一个连通并工作，并且可以通过该栅线切换信号切换第一子像素和得人子像素，因而，该第一子像素和第二子像素可以避免长期显示同一画面的问题，减少甚至避免了“烧屏”的情况发生。
具体的，参考图2，其中，栅线切换信号A为时序控制芯片(TCON)输出的逻辑讯号。第一晶体管M1为负极性导通的N型晶体，当其栅极讯号为L时开启，当其栅极讯号为H时关闭；第二晶体管M2为正极性导通的N型晶体，当其栅极讯号为H时开启，当其栅极讯号为L时关闭；第一晶体管M1、第二晶体管M2位于液晶面板的非显示区域，通过共用阵列制程产生。
该扫描线20接收栅极开启信号Gate Output，该栅极开启信号Gate Output由栅极驱动芯片(G-COF)输出。面板内的显示画素(图中红色子像素、绿色子像素、蓝色子像素、红色子像素)被分为a、b两个部分。第一红色子像素R1a、第一绿色子像素G1a、第一蓝色子像素B1a、第四红色子像素R2b与第一晶体管M1对应的第一存储电容C1相连，第二红色子像素R1b、第二绿色子像素G1b、第二蓝色子像素B1b、第三红色子像素R2a与第二晶体管M2对应的第二存储电容C2相连。
实际应用中，面板显示的刷新频率为120Hz或60Hz。以120Hz为例，即每秒可以显示120帧画面。
当TCON输出第一帧画面时，每一行开启时间的前一半中栅线切换信号A输出为低电平L，TCON正常输出画面，此时第一晶体管M1开启，第二晶体管M2关闭。连接至第一存储电容C1的画素可以正常显示。 每一行开启时间的后一半中栅线切换信号A输出为高电平H，TCON输出黑画面，此时连接至第二存储电容C2的画素被覆写为黑画面。
当TCON输出下一帧画面时，每一行开启时间的前一半中栅线切换信号A输出为高电平H，TCON正常输出画面，此时第二晶体管M2开启，第一晶体管M1关闭。连接至第二存储电容C2的画素可以正常显示。每一行开启时间的后一半中栅线切换信号A输出为低电平L，TCON输出黑画面，此时连接至第一存储电容C1的画素被覆写为黑画面。
综上，每隔一帧则每个画素都会经历亮和暗两种状态，避免了长时间显示同一画面造成对画素的损伤，最终避免了烧屏现象。
本实施例可选的，所述驱动电路1还包括控制连通所述数据线20或接地GND的接地控制信号B；
所述切换电路30还包括接地切换电路31，所述接地切换电路31包括第三晶体管M3和第四晶体管M4；所述第三晶体管M3为控制端负极性导通的晶体管，所述第四晶体管M4为控制端正极性导通的晶体管；
所述第三晶体管M3和第四晶体管M4的栅极相互连接，并连接于接地控制信号B；
所述第三晶体管M3的源极接地，漏极连接于所述第一子像素和第二子像素的源极端；
所述第四晶体管M4的源极连接于所述数据线20，漏极连接于所述第一子像素和第二子像素的源极端。
其中该扫描线10接收栅线信号Gate Output，该数据线20接收数据信号Source Output。
本方案中，该切换电路还包括控制连通所述数据线或接地的第三晶体管和第四晶体管，该第三晶体管和第四晶体管在该接地控制信号的控制下，可以通过协调该接地控制信号和栅线切换信号，使得被连通于该扫描线的第一子像素或第二子像素可以同时连通于该数据线而正常显示画面；而被关断与扫描线的连通的第二子像素或第一子像素，则可以在不连通扫描线的情况下，通过接地来显示黑画面；例如，可以控制该第一子像素在一帧画面的前半帧显示正常画面而在后半帧显示黑画面，而该第二子像素则可以在一帧画面的前半帧显示黑画面而在后半帧显示正常画面，如此，该第一子像素和第二子像素可以在每帧画面中分别经历了两亮和暗两种状态，避免了长时间显示同一画面造成对画素的 损伤，最终避免了烧屏现象。
具体的，参考该图3，在实际应用中，当时序控制芯片(TCON)输出当前帧画面时，每一行开启时间的前一半中栅线切换信号A输出为低电平L，接地控制信号B输出为高电平H，此时第一晶体管M1、第四晶体管M4开启，第二晶体管M2、第三晶体管M3关闭。连接至第一存储电容C1的画素可以正常显示。每一行开启时间的后一半中栅线切换信号A输出为高电平H，接地控制信号B输出为低电平L，此时第一晶体管M1、第四晶体管M4关闭，第二晶体管M2、第三晶体管M3开启，连接至第二存储电容C2的画素因为连接至接地GND。
当TCON输出下一帧画面时，每一行开启时间的前一半中栅线切换信号A输出为低电平L，接地控制信号B输出为低电平L，此时第一晶体管M1、第三晶体管M3开启，第二晶体管M2、第四晶体管M4关闭。连接至第一存储电容C1的画素因为连接至接地GND，所以显示为黑画面；每一行开启时间的后一半中栅线切换信号A输出为高电平H，接地控制信号B输出为高电平H，此时第一晶体管M1、第三晶体管M3关闭，第二晶体管M2、第四晶体管M4开启，连接至第二存储电容C2的画素可以正常显示。
综上，每隔一帧则每个画素都会经历亮和暗两种状态，避免了长时间显示同一画面造成对画素的损伤，最终避免了烧屏现象。
本实施例可选的，所述驱动电路1还包括控制所述切换电路30的切换信号C；
所述切换电路30包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4；
所述第一晶体管M1和第四晶体管M4是控制端正极性导通的晶体管，所述第二晶体管M2和第三晶体管M3是控制端负极性导通的晶体管；
所述第一晶体管M1的源极连接于数据线20，漏极连接于所述第一子像素的源极端；
所述第二晶体管M2的源极连接于数据线20，漏极连接于所述第一子像素的源极端，栅极连接于所述切换信号C；
所述第三晶体管M3源极接地，漏极连接于所述第二子像素的源极端；
所述第四晶体管M4源极接地，漏极连接于所述第二子像素的源 极端，栅极连接于所述切换信号；
所述第一晶体管M1和第四晶体管M4的栅极相互连接，并连接于所述切换信号C。
其中该扫描线10接收栅线信号Gate Output，该数据线20接收数据信号Source Output。
本方案中，该切换电路包括控制第一子像素和第二子像素连接于数据线的第一晶体管和第二晶体管，同时还包括控制连通所述数据线或接地的第三晶体管和第四晶体管；该第一晶体管、第二晶体管、第三晶体管和第四晶体管的栅极均连接于切换信号，鉴于该所述第一晶体管和第四晶体管是控制端正极性导通的晶体管，所述第二晶体管和第三晶体管是控制端负极性导通的晶体管，因而，在切换信号的控制下，可以控制该第一子像素和第二子像素中的一个连通数据线的同时，另一个接地，例如，可以控制该第一子像素在两帧画面的第一帧显示正常画面而在第二帧显示黑画面，而该第二子像素在两帧画面的第二帧显示正常画面而在第一帧显示黑画面，如此，该第一子像素和第二子像素可以在每两帧画面中分别经历了两亮和暗两种状态，避免了长时间显示同一画面造成对画素的损伤，最终避免了烧屏现象。
具体的，参考图4，在实际应用中，切换信号C为时序控制芯片(TCON)输出的逻辑讯号。第二晶体管M2、第三晶体管M3为负极性导通的N型晶体，当其栅极讯号为低电平L时开启，当其栅极讯号为高电平H时关闭；第一晶体管M1、第四晶体管M4为正极性导通的N型晶体，当其栅极讯号为高电平H时开启，当其栅极讯号为低电平L时关闭；第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4位于液晶面板的非显示区域，通过共用阵列制程产生。该扫描线20接收栅极开启信号Gate Output，该栅极开启信号Gate Output由栅极驱动芯片(G-COF)输出。数据线10接收数据信号Source Output，该数据信号Source Output为数据驱动芯片(S-COF)输出至画素电极的信号。面板内的显示画素(图中红色子像素R1、绿色子像素G1、蓝色子像素B1、红色子像素R2)被分为a、b两个部分。可以是分别包括第一红色子像素R1a和第二红色子像素R1b，也可以分别包括第一红色子像素R1a、第一绿色子像素G1a、第一蓝色子像素B1a；第二红色子像素R1b、第二绿色子像素G1b、第二蓝色子像素B1b。
其中，面板内的显示画素(图中红色子像素、绿色子像素、蓝色子像素、红色子像素)被分为a、b两个部分。第一红色子像素R1a、第一绿色子像素G1a、第一蓝色子像素B1a、第四红色子像素R2b与第一晶体管M1对应的第一存储电容C1相连，第二红色子像素R1b、第二绿色子像素G1b、第二蓝色子像素B1b、第三红色子像素R2a与第二晶体管M2对应的第二存储电容C2相连。
当TCON输出第一帧画面时，TCON输出切换信号C为H，此时M1、M4开启，M2、M3关闭。此时Source Output与B1相连，GND与B2相连。此时R1b可以正常显示TCON输出的对应画面，R1a因为连接至GND，显示为黑画面。
当TCON输出下一帧画面时，TCON输出C为低电平L，此时第二晶体管M2、第三晶体管M3开启，第一晶体管M1、第四晶体管M4关闭。此时数据线，或者Source Output与第一子像素相连，接地GND与第二子像素相连。此时第一红色子像素R1a可以正常显示TCON输出的对应画面，第二红色子像素R1b因为连接至GND，显示为黑画面。
综上，每两帧每个画素都会经历亮和暗两种状态，避免了长时间显示同一画面造成对画素的损伤，最终避免了烧屏现象。
本实施例可选的，所述扫描线10同时连接于所述第一子像素和第二子像素的栅极端。
本方案中，借助该切换电路，在使用一条扫描线的情况下，该扫描线可以分别控制该第一子像素和第二子像素的工作；该第一子像素和第二子像素可以是同一个像素中的两个子像素，也可以是相邻的两个像素。
图5是本申请一种适用于本申请实施例一种驱动电路的驱动方法的流程图，参考图5，结合图1-图4可知：本申请还提供了一种适用于本申请任一公开的驱动电路的驱动方法，包括步骤：
S51:在输出一帧画面时，控制第一子像素在一帧画面的前半帧显示正常画面，控制第二子像素在一帧画面的前半帧显示黑画面；
S52:控制第二子像素在一帧画面的后半帧显示在正常画面，控制第一子像素在一帧画面的后半帧显示黑画面。
本方案中，该第一子像素和第二子像素每帧画面都会经历亮和暗 状态，避免长时间显示同一画面，造成像素的损伤，从而避免“烧屏”现象；同时，由于该第一子像素和第二子像素分别通过该切换电路控制关断连接，因而，本申请的第一子像素和第二子像素的切换显示，并不影响显示面板的分辨率，并不会造成分辨率的降低。
图6是本申请一种适用于本申请实施例另一种驱动电路的驱动方法的流程图，参考图6，结合图1-图5可知：本申请还提供了一种适用于本申请任一公开的驱动电路的驱动方法，包括步骤：
S61:在输出第一帧画面时，控制所述第一子像素在第一帧画面时间内显示正常画面，控制第二子像素在第一帧画面时间内显示黑画面；
S62:在输出第二帧画面时，控制所述第二子像素在第二帧画面时间内显示正常画面，控制第一子像素在第二帧画面时间内显示黑画面。
本方案中，该第一子像素和第二子像素每两帧画面都会经历亮和暗状态，避免长时间显示同一画面，造成像素的损伤，从而避免“烧屏”现象；同时，由于该第一子像素和第二子像素分别通过该切换电路控制关断连接，因而，本申请的第一子像素和第二子像素的切换显示，并不影响显示面板的分辨率，并不会造成分辨率的降低。
图7是本申请一种显示面板的示意图，参考图7，结合图1-图6可知：
本申请还提供了一种显示面板，包括如本申请公开的所述的驱动电路1；
所述显示面板100还包括阵列基板2，所述阵列基板2包括显示区3和非显示区4；
所述显示面板100还包括阵列基板2，所述阵列基板2包括显示区3和非显示区4；
所述切换电路30设置在所述非显示区4；
所述切换电路30与所述阵列基板2通过公用阵列制程形成；
具体的，所述切换电路30可以包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4中的至少一个。
所述第一晶体管、第二晶体管、第三晶体管和第四晶体管与所述阵列基板通过公用阵列制程形成。
本申请的显示面板，包括一种新型的驱动电路，在该驱动电路中由于第一子像素和第二子像素分别受到同一条扫描线和同一条数据线连接，并且设置有切换电路，切换该第一子像素和第二子像素与扫描线和数据线的导通关系，如此，该驱动电路在工作时，可以控制其中一个子像素与扫描线和数据线连接，而另一个子像素则不连接；也可以控制两个子像素都与扫描线和数据线连接；如此，通过一条扫描线和一条数据线，并控制该第一子像素和第二子像素分别工作，节约了扫描线和数据线的使用；并且，在必要时，可以关断该第一子像素和第二子像素的其中一个与扫描线数据线的连接，减少该第一子像素和第二子像素，长期显示同一画面而出现“烧屏”的问题，有利于延迟显示面板的使用寿命。
本申请的面板是OLED面板，当然也可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(I正极性导通的N型PlaneSwitcing，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，，如有机发光显示面板(organic light-emitting diode，简称OLED显示面板)，适用即可。
以上内容是结合具体的优选实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种驱动电路，包括：
    多个像素，所述像素包括第一子像素和第二子像素；
    扫描线，连接于所述第一子像素和第二子像素的栅极端；
    数据线，连接于所述第一子像素和第二子像素的源极端；
    以及切换电路，切换所述扫描线、数据线、第一子像素和第二子像素的连接关系，使得所述第一子像素和第二子像素中的一个或两个与所述扫描线和数据线连通。
  2. 如权利要求1所述的一种驱动电路，其中，所述像素还包括第三子像素、第四子像素、第五子像素和第六子像素；
    所述第一子像素和第二子像素为红色子像素；所述第三子像素和第四子像素为绿色子像素；所述第五子像素和第六子像素为蓝色子像素。
  3. 如权利要求1所述的一种驱动电路，其中，所述第一子像素和第二子像素分别包括一个红色子像素、一个绿色子像素和一个蓝色子像素。
  4. 如权利要求1所述的一种驱动电路，其中，所述切换电路包括栅线切换电路，以及控制所述栅线切换电路的栅线切换信号；
    所述栅线切换电路包括第一晶体管、第二晶体管、第一存储电容和第二存储电容；所述第一晶体管为控制端负极性导通的晶体管，所述第二晶体管为控制端正极性导通的晶体管；
    所述第一晶体管的源极连接于扫描线，漏极连接于所述第一存储电容以及所述第一子像素的栅极端；
    所述第二晶体管的源极连接于扫描线，漏极连接于所述第二存储电容以及所述第二子像素的栅极端；
    所述第一晶体管和第二晶体管的栅极相互连接，且连接于栅线切换信号。
  5. 如权利要求2所述的一种驱动电路，其中，所述切换电路包括栅线切换电路，以及控制所述栅线切换电路的栅线切换信号；
    所述栅线切换电路包括第一晶体管、第二晶体管、第一存储电容和第二存储电容；所述第一晶体管为控制端负极性导通的晶体管，所述第二晶 体管为控制端正极性导通的晶体管；
    所述第一晶体管的源极连接于扫描线，漏极连接于所述第一存储电容以及所述第一子像素的栅极端；
    所述第二晶体管的源极连接于扫描线，漏极连接于所述第二存储电容以及所述第二子像素的栅极端；
    所述第一晶体管和第二晶体管的栅极相互连接，且连接于栅线切换信号。
  6. 如权利要求3所述的一种驱动电路，其中，所述切换电路包括栅线切换电路，以及控制所述栅线切换电路的栅线切换信号；
    所述栅线切换电路包括第一晶体管、第二晶体管、第一存储电容和第二存储电容；所述第一晶体管为控制端负极性导通的晶体管，所述第二晶体管为控制端正极性导通的晶体管；
    所述第一晶体管的源极连接于扫描线，漏极连接于所述第一存储电容以及所述第一子像素的栅极端；
    所述第二晶体管的源极连接于扫描线，漏极连接于所述第二存储电容以及所述第二子像素的栅极端；
    所述第一晶体管和第二晶体管的栅极相互连接，且连接于栅线切换信号。
  7. 如权利要求4所述的一种驱动电路，其中，所述驱动电路还包括控制连通所述数据线或接地的接地控制信号；
    所述切换电路还包括接地切换电路，所述接地切换电路包括第三晶体管和第四晶体管；所述第三晶体管为控制端负极性导通的晶体管，所述第四晶体管为控制端正极性导通的晶体管；
    所述第三晶体管和第四晶体管的栅极相互连接，并连接于接地控制信号；
    所述第三晶体管的源极接地，漏极连接于所述第一子像素和第二子像素的源极端；
    所述第四晶体管的源极连接于所述数据线，漏极连接于所述第一子像素和第二子像素的源极端。
  8. 如权利要求5所述的一种驱动电路，其中，所述驱动电路还包括控 制连通所述数据线或接地的接地控制信号；
    所述切换电路还包括接地切换电路，所述接地切换电路包括第三晶体管和第四晶体管；所述第三晶体管为控制端负极性导通的晶体管，所述第四晶体管为控制端正极性导通的晶体管；
    所述第三晶体管和第四晶体管的栅极相互连接，并连接于接地控制信号；
    所述第三晶体管的源极接地，漏极连接于所述第一子像素和第二子像素的源极端；
    所述第四晶体管的源极连接于所述数据线，漏极连接于所述第一子像素和第二子像素的源极端。
  9. 如权利要求6所述的一种驱动电路，其中，所述驱动电路还包括控制连通所述数据线或接地的接地控制信号；
    所述切换电路还包括接地切换电路，所述接地切换电路包括第三晶体管和第四晶体管；所述第三晶体管为控制端负极性导通的晶体管，所述第四晶体管为控制端正极性导通的晶体管；
    所述第三晶体管和第四晶体管的栅极相互连接，并连接于接地控制信号；
    所述第三晶体管的源极接地，漏极连接于所述第一子像素和第二子像素的源极端；
    所述第四晶体管的源极连接于所述数据线，漏极连接于所述第一子像素和第二子像素的源极端。
  10. 如权利要求1所述的一种驱动电路，其中，所述驱动电路还包括控制所述切换电路的切换信号；
    所述切换电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管和第四晶体管是控制端正极性导通的晶体管，所述第二晶体管和第三晶体管是控制端负极性导通的晶体管；
    所述第一晶体管的源极连接于数据线，漏极连接于所述第一子像素的源极端；
    所述第二晶体管的源极连接于数据线，漏极连接于所述第一子像素的 源极端，栅极连接于所述切换信号；
    所述第三晶体管源极接地，漏极连接于所述第二子像素的源极端；
    所述第四晶体管源极接地，漏极连接于所述第二子像素的源极端，栅极连接于所述切换信号；
    所述第一晶体管和第四晶体管的栅极相互连接，并连接于所述切换信号。
  11. 如权利要求2所述的一种驱动电路，其中，所述驱动电路还包括控制所述切换电路的切换信号；
    所述切换电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管和第四晶体管是控制端正极性导通的晶体管，所述第二晶体管和第三晶体管是控制端负极性导通的晶体管；
    所述第一晶体管的源极连接于数据线，漏极连接于所述第一子像素的源极端；
    所述第二晶体管的源极连接于数据线，漏极连接于所述第一子像素的源极端，栅极连接于所述切换信号；
    所述第三晶体管源极接地，漏极连接于所述第二子像素的源极端；
    所述第四晶体管源极接地，漏极连接于所述第二子像素的源极端，栅极连接于所述切换信号；
    所述第一晶体管和第四晶体管的栅极相互连接，并连接于所述切换信号。
  12. 如权利要求3所述的一种驱动电路，其中，所述驱动电路还包括控制所述切换电路的切换信号；
    所述切换电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管和第四晶体管是控制端正极性导通的晶体管，所述第二晶体管和第三晶体管是控制端负极性导通的晶体管；
    所述第一晶体管的源极连接于数据线，漏极连接于所述第一子像素的源极端；
    所述第二晶体管的源极连接于数据线，漏极连接于所述第一子像素的 源极端，栅极连接于所述切换信号；
    所述第三晶体管源极接地，漏极连接于所述第二子像素的源极端；
    所述第四晶体管源极接地，漏极连接于所述第二子像素的源极端，栅极连接于所述切换信号；
    所述第一晶体管和第四晶体管的栅极相互连接，并连接于所述切换信号。
  13. 如权利要求10所述的一种驱动电路，其中，所述扫描线同时连接于所述第一子像素和第二子像素的栅极端。
  14. 如权利要求11所述的一种驱动电路，其中，所述扫描线同时连接于所述第一子像素和第二子像素的栅极端。
  15. 如权利要求12所述的一种驱动电路，其中，所述扫描线同时连接于所述第一子像素和第二子像素的栅极端。
  16. 一种使用驱动电路的驱动方法，所述驱动电路包括：
    多个像素，所述像素包括第一子像素和第二子像素；
    扫描线，连接于所述第一子像素和第二子像素的栅极端；
    数据线，连接于所述第一子像素和第二子像素的源极端；
    以及切换电路，切换所述扫描线、数据线、第一子像素和第二子像素的连接关系，使得所述第一子像素和第二子像素中的一个或两个与所述扫描线和数据线连通；
    所述驱动方法包括步骤：
    在输出一帧画面时，控制第一子像素在一帧画面的前半帧显示正常画面，控制第二子像素在一帧画面的前半帧显示黑画面；
    控制第二子像素在一帧画面的后半帧显示在正常画面，控制第一子像素在一帧画面的后半帧显示黑画面。
  17. 一种驱动电路的驱动方法，所述驱动电路包括：
    多个像素，所述像素包括第一子像素和第二子像素；
    扫描线，连接于所述第一子像素和第二子像素的栅极端；
    数据线，连接于所述第一子像素和第二子像素的源极端；
    以及切换电路，切换所述扫描线、数据线、第一子像素和第二子像素的连接关系，使得所述第一子像素和第二子像素中的一个或两个与所述扫 描线和数据线连通；
    所述驱动方法包括步骤：
    在输出第一帧画面时，控制所述第一子像素在第一帧画面时间内显示正常画面，控制第二子像素在第一帧画面时间内显示黑画面；
    在输出第二帧画面时，控制所述第二子像素在第二帧画面时间内显示正常画面，控制第一子像素在第二帧画面时间内显示黑画面。
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EP3171357A1 (en) * 2015-08-26 2017-05-24 BOE Technology Group Co., Ltd. Pixel unit driving circuit and method, and display device

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