WO2020050330A1 - Method of applying solder paste and mask - Google Patents
Method of applying solder paste and mask Download PDFInfo
- Publication number
- WO2020050330A1 WO2020050330A1 PCT/JP2019/034832 JP2019034832W WO2020050330A1 WO 2020050330 A1 WO2020050330 A1 WO 2020050330A1 JP 2019034832 W JP2019034832 W JP 2019034832W WO 2020050330 A1 WO2020050330 A1 WO 2020050330A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- solder paste
- peripheral
- application
- area
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D7/00—Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D7/00—Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials
- B05D7/24—Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials for applying particular liquids or other fluent materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0557—Non-printed masks
Definitions
- the present invention relates to a method for applying a solder paste and a mask.
- Priority is claimed on Japanese Patent Application No. 2018-166395 filed on September 5, 2018, the content of which is incorporated herein by reference.
- solder paste is widely used in surface mount technology (SMT) in which electronic components such as LGA (Land Grid Array) and BGA (Ball Grid Array) are mounted on the surface of a printed circuit board or the like.
- SMT surface mount technology
- the solder paste is produced by mixing a solder powder with a flux.
- a solder paste is applied to a surface of a printed circuit board on which pads (electrodes) are provided.
- the solder paste is applied to the pad, and the application range is equal to the area of the pad.
- the electronic component is placed on the surface of the printed board so that the pads of the printed board and the lands (electrodes) of the electronic component face each other.
- the solder paste is located between both electrodes of the printed circuit board and the electronic component.
- the printed circuit board on which the electronic components are mounted is heated (reflowed) in a reflow oven, and the solder powder of the solder paste is melted and bonded to each other, and then solidified again to electrically connect the two electrodes.
- Surface mounting is completed.
- the resistance value of the solder connecting between the electrodes must be equal to or less than a predetermined value. Further, even if a shock or the like is applied to the printed circuit board after surface mounting, the solder is required to have a predetermined strength in order to maintain appropriate electrical connection without being damaged.
- the void is a void formed in the solder, and the void is filled with a gas obtained by vaporizing a resin component of the flux or a solvent of the flux.
- the voids cause a reduction in the strength of the solder, and when an impact or the like is applied, the electrical connection between the two electrodes may not be maintained.
- a relatively small void may not cause such a defect, and since the void causing the above-described defect is a relatively large void, the size of the generated void is suppressed in the field of surface mounting. Is required.
- the present invention has been made in view of such circumstances, and even when a void is formed in solder in surface mounting, a solder paste coating method and a mask that can suppress the size of the void.
- the purpose is to provide.
- a first aspect of the present invention is a method of applying a solder paste to an object to be applied, wherein at least a part of the solder paste is positioned in the joint area so as to form a non-application area in the joint area of the object to be applied. Applying a solder paste to an application region to be formed, wherein the application region has a plurality of peripheral regions arranged at intervals in a circumferential direction around a center of the joining region.
- the plurality of peripheral regions may be arranged to face each other with the center of the joining region interposed therebetween.
- the plurality of peripheral regions may be arranged so as to extend in a direction intersecting the direction in which the plurality of peripheral regions oppose each other.
- a gap between the plurality of peripheral regions may be 30% or more and 70% or less of a maximum diameter of the joining region.
- the gap between the plurality of peripheral regions may be not less than 85.7% and not more than 200% of the width of each peripheral region in the direction facing the plurality of peripheral regions.
- the number of the plurality of peripheral regions may be two to six.
- the plurality of peripheral regions may be arranged at equal intervals in the circumferential direction.
- the plurality of peripheral regions include a first region and a second region having different circumferential lengths, and the first region and the second region are arranged in the circumferential direction. May be arranged alternately.
- opposing sides of the plurality of peripheral regions adjacent in the circumferential direction may be parallel to each other.
- the application region may further include a central region located radially inside the plurality of peripheral regions.
- opposing sides of the central region and each peripheral region may be parallel to each other.
- the area of the central region may be not less than 44.4% and not more than 278% of the area of each peripheral region.
- the plurality of peripheral regions may be arranged so as to partially contact each other.
- each peripheral region may be gradually increased from the center of the joint region toward the outside in the radial direction.
- a ratio of a gap between the plurality of peripheral regions, which opens radially outward from a center of the bonding region, to a whole circumference of the bonding region is 11.5%. It may be the above.
- the plurality of peripheral regions may be arranged so as to overlap an outer edge of the joining region.
- the plurality of peripheral regions may be arranged in the joining region.
- a method of applying a solder paste to an object to be applied wherein at least a part of the solder paste is positioned in the joint region so as to form a non-application region in the joint region of the object.
- the extension region may be arranged so as to overlap an outer edge of the joining region.
- the extension region may be arranged in the joining region.
- the application region may further include a plurality of side regions arranged so as to sandwich the extension region in a direction intersecting the longitudinal direction of the extension region.
- opposing sides of the extension region and each side region may be parallel to each other.
- the plurality of side regions may be arranged so as to overlap an outer edge of the joining region.
- the plurality of side regions may be arranged in the joining region.
- a third aspect of the present invention is a mask used in the method for applying a solder paste according to the first or second aspect, wherein an opening is formed at a position corresponding to the application region.
- the size of the void can be suppressed. Therefore, it is possible to secure an appropriate electrical connection between the object to be coated such as a substrate and the two electrodes of the electronic component, and to prevent a decrease in the strength of the solder connecting between the two electrodes. Etc. can be provided.
- FIG. 1 is a schematic diagram illustrating a solder printing apparatus according to an embodiment of the present invention. It is a top view of a substrate which is an application object concerning one embodiment of the present invention. It is a top view of the mask used for screen printing concerning one embodiment of the present invention. It is a schematic diagram showing each process of the application method of the solder paste concerning one embodiment of the present invention.
- FIG. 7 is a schematic view showing a step after a solder paste application step in surface mounting.
- FIG. 3 is a plan view showing a solder paste application region in the first embodiment.
- FIG. 10 is a plan view showing a solder paste application region in a second embodiment.
- FIG. 13 is a plan view illustrating a solder paste application region in a third embodiment.
- FIG. 14 is a plan view showing a solder paste application region in a fourth embodiment.
- FIG. 14 is a plan view showing a solder paste application region in a fifth embodiment.
- FIG. 15 is a plan view showing a solder paste application region in a sixth embodiment.
- FIG. 15 is a plan view showing a solder paste application region in a seventh embodiment.
- FIG. 19 is a plan view showing a solder paste application region in Example 8.
- FIG. 21 is a plan view showing a solder paste application region in a ninth embodiment.
- FIG. 21 is a plan view showing a solder paste application region in Example 10.
- FIG. 21 is a plan view showing a solder paste application region in an eleventh embodiment.
- FIG. 39 is a plan view showing a solder paste application region in Example 12.
- FIG. 39 is a plan view showing a solder paste application region in a thirteenth embodiment.
- FIG. 39 is a plan view showing a solder paste application region in Example 14.
- FIG. 39 is a plan view showing a solder paste application region in Example 15.
- FIG. 39 is a plan view showing a solder paste application region in Example 16.
- FIG. 39 is a plan view showing a solder paste application region in Example 17.
- FIG. 39 is a plan view showing a solder paste application region in Example 18.
- FIG. 39 is a plan view showing a solder paste application region in Example 19.
- FIG. 39 is a plan view showing a solder paste application region in Example 20.
- FIG. 39 is a plan view showing a solder paste application region in Example 21.
- FIG. 39 is a plan view showing a solder paste application region in Example 14.
- FIG. 39 is a plan view showing a solder paste application region in Example 22.
- FIG. 39 is a plan view showing a solder paste application region in Example 23.
- FIG. 39 is a plan view showing a solder paste application region in Example 24.
- FIG. 35 is a plan view showing a solder paste application region in Example 25.
- FIG. 39 is a plan view showing a solder paste application region in Example 26.
- the solder printing apparatus 1 of the present embodiment is a screen printing apparatus using a mask M.
- the solder printing apparatus 1 includes a substrate supporting unit 2 that supports a substrate B on which a solder paste S is to be applied, a printing unit 3 that is disposed vertically above the substrate supporting unit 2, And a housing 4 for accommodating the support unit 2 and the printing unit 3.
- the mask M is held at a predetermined position in the housing 4 by a mask support (not shown) fixed to the housing 4 and the like.
- the substrate supporting unit 2 includes a stage 21 that supports the substrate B from below vertically so that the mounting surface of the substrate B faces vertically upward, and a stage that can move the stage 21 in the horizontal and vertical directions and can rotate around an axis that extends in the vertical direction. And a moving unit 22.
- the stage 21 is provided with a clamp member 23 for holding the substrate B.
- the solder printing apparatus 1 is provided with a board transport section (not shown) for loading and unloading the board B between the board support section 2 and the outside of the housing 4.
- the printing unit 3 includes a squeegee 31 for moving the solder paste S on the surface (upper surface) of the mask M, a vertical moving device 32 that can move the squeegee 31 up and down, and a horizontal moving device 33 that can move the vertical moving device 32 horizontally.
- the squeegee 31 is a member that spreads the solder paste S supplied on the mask M by moving in the horizontal + X direction while being in contact with the surface of the mask M.
- the squeegee 31 is connected to a vertical moving device 32.
- the squeegee 31 may be a plate member made of a single material such as metal, resin, or rubber, or a plate member in which a portion of the metal plate or the like that contacts the mask M is covered with resin or rubber. You may.
- the squeegee 31 is arranged so as to be inclined vertically downward in the ⁇ X direction opposite to the + X direction.
- the inclination angle of the squeegee 31 may be adjustable manually or automatically.
- the vertical moving device 32 is supported by the horizontal moving device 33 and includes, for example, a ball screw.
- the vertical moving device 32 can press the lower end of the squeegee 31 against the surface of the mask M with a predetermined force.
- the horizontal moving device 33 is fixed to the housing 4, and has a linear guide 34 that guides the vertical moving device 32 in a horizontal direction, and a motor that rotates a ball screw (not shown) provided in parallel with the linear guide 34. 35.
- the horizontal moving device 33 can move the vertical moving device 32 connected to the ball screw via a nut member in the horizontal direction by driving of the motor 35.
- the horizontal moving device 33 moves the vertical moving device 32 in the horizontal direction while the squeegee 31 presses the mask M downward by the vertical moving device 32, so that the squeegee 31 presses the mask M. While moving in the horizontal direction. Further, the solder printing apparatus 1 is provided with a dispenser (not shown) for supplying the solder paste S on the mask M.
- the housing 4 has sufficient rigidity to support the mask support section and the printing section 3.
- the housing 4 may have a structure capable of hermetically sealing the inside.
- the housing 4 may be provided with an exhaust device such as a vacuum pump and an atmosphere release valve.
- FIG. 2A is a plan view of the substrate B
- FIG. 2B is a plan view of the mask M.
- the “plan view” refers to a view as seen from a direction perpendicular to the mounting surface of the substrate B and the upper surface of the mask M.
- the substrate B to which the solder paste S is applied in the present embodiment is a printed circuit board made of a hard plate-shaped base material, and has a plurality of pads P (electrodes, bondings) on at least one plate surface. Area).
- This one plate surface is a mounting surface on which an electronic component E described later is mounted. Examples of the material of the pad P include copper, gold, and silver.
- a solder resist having a property of repelling molten solder is applied to a region other than the plurality of pads P on the mounting surface of the substrate B.
- the mask M used in the present embodiment is made of a metal plate such as stainless steel and has a plurality of openings H penetrating in the thickness direction.
- the thickness of the mask M is, for example, from 30 ⁇ m to 200 ⁇ m, but may be changed as appropriate according to the thickness of the solder paste S to be applied on the substrate B.
- an opening is formed in a region corresponding to a pad of a substrate at a position facing the pad, but the opening H of the present embodiment is formed on a plane different from the pad P of the substrate B. It has a visual shape.
- an opening H for applying the solder paste S to an application region at least partially located in the pad P is formed so as to form a non-application region in the pad P of the substrate B. Is formed. In other words, the opening H is formed in the same shape at a position corresponding to the application region.
- the shape of the opening H in the mask M of the present embodiment that is, the shape of the application region of the solder paste S applied to the substrate B will be described in detail in Examples 1 to 26 described later.
- two rectangular openings H are formed for one pad P, and these openings H are arranged to face each other with the center of the pad P interposed therebetween.
- the solder paste S used in the present embodiment is not particularly limited, and may be appropriately selected according to the use mode such as the coating atmosphere, the temperature, the opening size and the shape of the mask M.
- the solder paste is produced by mixing the solder powder with the flux. Copper, tin, silver, alloys thereof, and the like are used for the solder powder, and the shape of the solder powder may be spherical or irregular.
- the flux includes, for example, a resin such as rosin, a solvent for adjusting the viscosity and the like, an activator for cleaning the surface of the electrode, and a thixotropic agent for adjusting the viscosity, tackiness and thixotropy. May be appropriately adjusted according to the mode of use.
- the substrate B is placed on the stage 21 by the substrate transport unit, and the substrate B is held on the stage 21 by the clamp members 23. Subsequently, the horizontal position of the substrate B with respect to the fixed mask M and the rotational position about an axis extending in the vertical direction with respect to the fixed mask M are adjusted by the operation of the stage moving unit 22, and then the stage moving unit 22 is moved from the state shown in FIG. The stage 21 is raised, and the upper surface (mounting surface) of the substrate B is brought into close contact with the lower surface of the mask M as shown in FIG.
- the opening H of the mask M is arranged at an appropriate position with respect to the pad P of the substrate B. That is, when the surface of the substrate B on which the pads P are provided and the mask M come into contact with each other, a position of the mask M corresponding to (opposed to) the region (application region) where the solder paste S is applied to the substrate B. , An opening H is formed.
- the dispenser supplies the solder paste S onto the mask M where the squeegee 31 advances, that is, on the + X side of the squeegee 31.
- the squeegee 31 is lowered by the driving of the vertical moving device 32, and presses the mask M downward with a predetermined force.
- the horizontal moving device 33 moves the vertical moving device 32 in the + X direction, so that the squeegee 31 moves in the + X direction while pressing the mask M. Since the solder paste S is supplied to the position where the squeegee 31 advances, the solder paste S moves in the + X direction as the squeegee 31 moves.
- the squeegee 31 is inclined as described above, a force directed vertically downward is applied to the solder paste S as the squeegee 31 moves. For this reason, as shown in FIG. 3D, the solder paste S is pressed into the opening H of the mask M and filled, and comes into contact with the upper surface (mounting surface) of the substrate B. Further, since the squeegee 31 moves in the + X direction while pressing the mask M downward, the squeegee 31 can be moved while scraping the solder paste S from the upper surface of the mask M other than the opening H, so that the solder paste S is supplied only to the opening H. Can be. When the horizontal movement of the squeegee 31 by the horizontal movement device 33 is completed, the filling of the solder paste S into the plurality of openings H of the mask M is completed as shown in FIG.
- the stage B is moved down by the stage moving unit 22 so that the substrate B is separated downward from the lower surface of the mask M.
- the solder paste S filled in the opening H adheres to the upper surface of the substrate B
- the solder paste S is also separated from the mask M, and thus has a pattern corresponding to the opening H of the mask M. Is printed on the mounting surface of the substrate B. Since the opening H of the mask M has a shape as shown in FIG. 2B, the method of applying the solder paste according to the present embodiment employs a method in which the non-applied region is formed in the pad P on the substrate B.
- a step of applying a solder paste S to an application region where at least a part is located When the substrate B is separated from the lower surface of the mask M and the solder paste S is printed on the substrate B, the solder paste application process of the present embodiment is completed.
- the board B to which the solder paste S has been applied is carried out of the solder printing apparatus 1 by the board transport unit.
- the electronic component E is mounted on the mounting surface of the substrate B on which the solder paste S has been applied.
- the electronic component E may be an LGA or a BGA.
- a plurality of lands L are provided on the bottom surface of the electronic component E (the surface facing the substrate B) so as to correspond to the plurality of pads P of the substrate B.
- the electronic component E is mounted on the substrate B such that the pads P of the substrate B and the lands L of the electronic component E face each other. At this time, the solder paste S is located between the pad P of the substrate B and the land L of the electronic component E.
- the substrate B on which the electronic component E is mounted is heated in a reflow furnace (not shown), and the solder powder in the solder paste S is melted and bonded to each other.
- the molten solder contacts both electrodes of the substrate B and the electronic component E.
- the wettability of the molten solder to the pads P is improved, and the surface of the substrate B other than the pads P is coated with a solder resist that repels the molten solder.
- the molten solder flows radially inward of the pad P.
- solder paste S is applied to the two regions as in the present embodiment, the solder included in the two regions is integrated in the reflow process. Thereafter, by cooling and solidifying the molten solder, both electrodes of the board B and the electronic component E are electrically connected by the solder S1. Thus, the surface mounting of the electronic component E on the substrate B is completed.
- FIGS. 5 to 30 are plan views of the mounting surface of the substrate B. This is an enlarged view of one pad P.
- the shape of the pad P in plan view was a circle having a diameter of 1.0 mm.
- a direction passing through the center of the pad P and crossing an axis orthogonal to the mounting surface of the substrate B is referred to as a radial direction, and a direction around the axis is referred to as a circumferential direction.
- the vertical direction of the drawing of each drawing may be simply referred to as “vertical direction”, and the horizontal direction of the drawing may be simply referred to as “lateral direction”.
- a gap ratio GR, a coating area ratio AR, and a maximum void area ratio VR described below were confirmed.
- the gap ratio GR refers to a ratio of a gap between a plurality of peripheral regions A1 described later that opens radially outward from the center of the pad P with respect to the entire circumference of the pad P.
- the gap ratio GR is set. In the case where a plurality of pairs of two straight lines that do not include the peripheral area A1 can be drawn between them, the ratio of the total angle between the two straight lines of each pair to 360 ° is defined as the gap ratio GR. Note that the calculation of the gap ratio GR does not consider the presence of a central region A2 described later.
- the application area ratio AR refers to the ratio of the entire application area of the solder paste applied to one pad P to the area of the pad P.
- the circular constant ⁇ was set to 3.14.
- the comparative example has a conventional configuration in which a solder paste is applied to a pad P having a diameter of 1.0 mm in the same region as the pad P.
- This comparative example is indicated by “Ref” in Table 1 below.
- the gap ratio GR cannot be calculated, and the application area ratio AR is 100%.
- the maximum void area ratio VR was 43.5%.
- the application region of the solder paste in the first embodiment will be described with reference to FIG.
- the solder paste is applied to the application region T at least partially located in the pad P so as to form the non-application region N in the pad P of the substrate B.
- the region where the solder paste is applied is shaded (the same applies to other FIGS. 6 to 30).
- the application region T has a plurality (two) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P.
- Each peripheral area A1 has a rectangular shape extending in one direction, has a length in the longitudinal direction of 0.7 mm, and a width in the transverse direction orthogonal to the longitudinal direction is 0.35 mm.
- the plurality of peripheral areas A1 are arranged to face each other with the center O of the pad P interposed therebetween.
- the plurality of peripheral areas A1 are arranged so as to extend in a direction orthogonal to the direction in which the plurality of peripheral areas A1 are opposed to each other (vertical direction in FIG. 5). That is, each peripheral area A1 extends in the left-right direction on the paper.
- a plurality of peripheral regions A1 may be arranged so as to extend in a direction intersecting the opposing direction.
- the size of the gap between the plurality of peripheral regions A1 (the gap in the facing direction) is 0.7 mm.
- the gap between the plurality of peripheral regions A1 is 70% of the maximum diameter (1.0 mm) of the pad P, and is 200% of the width of each peripheral region A1 in the facing direction.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction. Opposite sides a and b of the plurality of peripheral regions A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
- the plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
- the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the angle ⁇ G to 90 ° between the straight lines L1 and L2 is defined as the gap ratio GR of the present embodiment.
- the angle ⁇ G is an angle between the straight line L1 and a straight line L3 extending radially outward from the center O and in contact with the lower right vertex of the peripheral area A1 on the upper side of the drawing.
- the maximum void area ratio of the present example was 2.3%.
- Example 2 The application area of the solder paste in the second embodiment will be described with reference to FIG. In the second embodiment, only the configuration different from the first embodiment will be described below, and the description of the other configurations will be omitted.
- the size of the gap between the plurality of peripheral areas A1 (the gap in the facing direction) is 0.3 mm. Therefore, the gap between the plurality of peripheral regions A1 is 30% of the maximum diameter (1.0 mm) of the pad P, and is 85.7% of the width of each peripheral region A1 in the facing direction.
- the maximum void area ratio of the present example was 13.8%.
- Example 3 The region where the solder paste is applied in the third embodiment will be described with reference to FIG. In the third embodiment, only the configuration different from the first embodiment will be described below, and the description of the other configurations will be omitted.
- the size of the gap (gap in the facing direction) between the plurality of peripheral areas A1 is 0.4 mm. Therefore, the gap between the plurality of peripheral regions A1 is 40% of the maximum diameter (1.0 mm) of the pad P, and is 114% of the width of each peripheral region A1 in the facing direction.
- the maximum void area ratio of the present example was 11.7%.
- Example 4 The solder paste application area in the fourth embodiment will be described with reference to FIG. In the fourth embodiment, only configurations different from those of the first embodiment will be described below, and descriptions of other configurations will be omitted.
- the size of the gap between the plurality of peripheral areas A1 (the gap in the facing direction) is 0.5 mm. Therefore, the gap between the plurality of peripheral regions A1 is 50% of the maximum diameter (1.0 mm) of the pad P, and is 143% of the width of each peripheral region A1 in the facing direction.
- the maximum void area ratio of the present example was 7.0%.
- Example 5 The application region of the solder paste in the fifth embodiment will be described with reference to FIG. In the fifth embodiment, only the configuration different from the first embodiment will be described below, and the description of the other configurations will be omitted.
- the size of the gap between the plurality of peripheral areas A1 (the gap in the facing direction) is 0.6 mm. Therefore, the gap between the plurality of peripheral regions A1 is 60% of the maximum diameter (1.0 mm) of the pad P, and is 171% of the width of each peripheral region A1 in the facing direction.
- the maximum void area ratio in the present example was 4.2%.
- each peripheral area A1 is 0.35 mm, which is significantly smaller than the maximum diameter (1.0 mm) of the pad P. For this reason, when the resin component or the like of the flux moves in the short direction of the peripheral area A1, the flux is discharged from the molten solder relatively early, and the size of the void is suppressed in each peripheral area A1 as compared with the comparative example. It is thought that. Further, as shown in FIG. 4, the solder powder in the solder paste applied to the two regions is also integrated in the reflow process. That is, the solder powder melted in the two peripheral regions A1 flows toward the center O of the pad P and comes into contact with each other near the center of the pad P.
- connection portion of the molten solder flowing from the two regions expands outward in the radial direction. It is considered that since the connecting portion expands outward in the radial direction, a force for causing the resin component of the flux to move outward in the radial direction is generated, and it is considered that the resin component can be discharged toward the outside of the solder by this force.
- the gap between the plurality of peripheral regions A1 was 30% or more and 70% or less of the maximum diameter (1.0 mm) of the pad P.
- the gap between the plurality of peripheral regions A1 was 85.7% or more and 200% or less of the width of each peripheral region A1 in the facing direction of the plurality of peripheral regions A1.
- Each peripheral area A1 has a rectangular shape in plan view, but may have an elliptical or elliptical shape in plan view.
- the opposing sides a and b of the plurality of peripheral areas A1 are formed in a straight line, the opposing sides may have a shape that bulges inward in the radial direction, or may bulge outward in the radial direction. It may have a concave shape.
- the radially outer side of the peripheral region A1 may be depressed inward in the radial direction or may bulge outward in the radial direction.
- the solder paste application area in the sixth embodiment will be described with reference to FIG.
- the solder paste is applied to the application region T at least partially located in the pad P so as to form the non-application region N in the pad P of the substrate B.
- the application region T includes a plurality (six) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the plurality of peripheral regions A1.
- Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral areas A1 are arranged at substantially equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- Opposite sides a and b of a plurality of peripheral regions A1 circumferentially adjacent to each other are parallel to each other.
- the opposite sides a and b may be non-parallel to each other.
- Opposite sides c and d of the central area A2 and the peripheral areas A1 are parallel to each other.
- the opposite sides c and d may be non-parallel to each other.
- the area of the central area A2 is the same (100%) as the area of each peripheral area A1.
- the plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
- the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the sum of the angle ⁇ G1 and the angle ⁇ G2 to 90 ° formed between the straight lines L1 and L2 is determined by the gap in the present embodiment.
- the ratio GR was set.
- the angle ⁇ G1 is an angle between the straight line L1 and a straight line L3 extending radially outward from the center O and in contact with the lower right vertex of the peripheral area A1 on the upper right of the paper, and arctan (0.1 / 0) .65).
- the angle ⁇ G2 is a straight line L4 extending radially outward from the center O and in contact with the upper left vertex of the peripheral area A1 on the upper right of the drawing, and a straight line L4 extending radially outward from the center O and a lower right apex of the upper peripheral area A1 on the drawing.
- the maximum void area ratio of the present example was 4.8%.
- the application area of the solder paste in the seventh embodiment will be described with reference to FIG. In the seventh embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the central area A2 has a square shape with a side length of 0.4 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the gap ratio GR of the present embodiment is 29.7%, similarly to the sixth embodiment.
- the maximum void area ratio of the present example was 3.9%.
- the solder paste application area in the eighth embodiment will be described with reference to FIG. In the eighth embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the central region A2 has a square shape with a side length of 0.5 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the gap ratio GR of the present embodiment is 29.7%, similarly to the sixth embodiment.
- the maximum void area ratio of the present example was 13.9%.
- the central area A2 has a square shape with a side length of 0.2 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the gap ratio GR of the present embodiment is 29.7%, similarly to the sixth embodiment.
- the maximum void area ratio of the present example was 12.3%.
- the application area of the solder paste in the tenth embodiment will be described with reference to FIG. In the tenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the application area T includes a plurality (two) of peripheral areas A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central area A2 located radially inside the plurality of peripheral areas A1. And
- Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
- the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the angle ⁇ G to 90 ° between the straight lines L1 and L2 is defined as the gap ratio GR of the present embodiment.
- the angle ⁇ G is an angle between the straight line L1 and a straight line L3 extending radially outward from the center O and in contact with the lower right vertex of the peripheral region A1 on the upper side of the drawing.
- the maximum void area ratio of the present example was 3.1%.
- the application region of the solder paste in the eleventh embodiment will be described with reference to FIG. In the eleventh embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the application region T includes a plurality (three) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral areas A1 are arranged at substantially equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction. Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
- the right-hand section of the straight line is a mirror image of the left-hand section, and therefore, the straight line L1 extending upward from the center O.
- the ratio of the sum of the angles ⁇ G1 , ⁇ G2, and ⁇ G3 to 180 ° formed between the straight line L2 extending downward from the center O is defined as the gap ratio GR of the present embodiment.
- the angle ⁇ G1 is an angle between a straight line L3 extending from the center O to the right side of the drawing and a straight line L4 extending radially outward from the center O and in contact with the lower right vertex of the peripheral region A1 on the upper side of the drawing. , Arctan (0.35 / 0.15).
- the angle ⁇ G2 is an angle between the straight line L2 and a straight line L5 extending radially outward from the center O and in contact with the lower left vertex of the peripheral area A1 on the lower right side of the drawing, and is (90 ° ⁇ arctan (0 .45 / 0.35)).
- the maximum void area ratio of the present example was 4.0%.
- the application area of the solder paste in the twelfth embodiment will be described with reference to FIG. In the twelfth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the application region T includes a plurality (four) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And
- Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
- the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the angle ⁇ G to 90 ° between the straight lines L1 and L2 is defined as the gap ratio GR of the present embodiment.
- the angle ⁇ G is a straight line L3 extending radially outward from the center O and in contact with the upper left vertex of the peripheral region A1 on the right side of the drawing, and a straight line L3 extending radially outward from the center O and a lower right vertex of the peripheral region A1 on the upper side of the drawing.
- the maximum void area ratio in the present example was 2.6%.
- the solder paste application area in the thirteenth embodiment will be described with reference to FIG. In the thirteenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the application region T includes a plurality (four) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1.
- the plurality of peripheral regions A1 have a first region A11 and a second region A12 having different circumferential lengths, and the first region A11 and the second region A12 are alternately arranged in the circumferential direction.
- the first area A11 and the second area A12 are provided two by two.
- the first region A11 has a rectangular shape extending in one direction, has a length in the longitudinal direction of 0.6 mm, and has a width in the short direction orthogonal to the longitudinal direction of 0.3 mm.
- Each of the second area A12 and the central area A2 is a square having a side length of 0.3 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of first regions A11, the plurality of second regions A12, and the central region A2 is shown in FIG. Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
- the maximum void area ratio in this example was 1.8%.
- the application region T includes a plurality (six) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the plurality of peripheral regions A1.
- Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm. However, in the peripheral area A1, a portion radially outside the outer edge of the pad P is excluded.
- FIG. 1 The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- Opposite sides a and b of a plurality of peripheral regions A1 circumferentially adjacent to each other are parallel to each other.
- the opposite sides a and b may be non-parallel to each other.
- Opposite sides c and d of the central area A2 and the peripheral areas A1 are parallel to each other.
- the opposite sides c and d may be non-parallel to each other.
- the application area ratio AR of this embodiment is about 43%.
- the maximum void area ratio of the present example was 13.8%.
- the ratio of the gap between the plurality of peripheral regions A1 opening radially outward from the center O of the pad P to the entire circumference of the pad P is calculated as the gap ratio GR. It was also found that in the embodiment of the present invention, the opening was provided from the center O toward the outside in the radial direction with an interval G therebetween. For this reason, it is considered that the molten solder from the central region A2 can appropriately flow radially outward through the gap G, and thereby the resin component of the flux can be discharged radially outward. In Examples 6 to 14, the area of the central region A2 was 44.4% or more and 278% or less of the area of each peripheral region A1.
- Example 15 The application region of the solder paste in the embodiment 15 will be described with reference to FIG. In the fifteenth embodiment, only the configuration different from that of the twelfth embodiment will be described below, and the description of the other configurations will be omitted.
- the fifteenth embodiment has a configuration in which the central region A2 is excluded from the twelfth embodiment.
- the gap ratio GR of the present embodiment is the same as that of the twelfth embodiment, and is 48.4%.
- the maximum void area ratio of the present example was 13.4%.
- Example 16 The application region of the solder paste in the sixteenth embodiment will be described with reference to FIG. In the sixteenth embodiment, only the configuration different from that of the thirteenth embodiment will be described below, and the description of the other configurations will be omitted.
- the sixteenth embodiment has a configuration in which the central region A2 is excluded from the thirteenth embodiment.
- the gap ratio GR of the present embodiment is the same as that of the thirteenth embodiment, and is 29.1%.
- the maximum void area ratio of the present example was 13.8%.
- the application area of the solder paste in the seventeenth embodiment will be described with reference to FIG. In the seventeenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the application region T includes a plurality (six) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the plurality of peripheral regions A1. And
- Each of the peripheral area A1 and the central area A2 has a circular shape with a diameter of 0.3 mm.
- the center of each peripheral area A1 is located on the outer peripheral edge of the pad P.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- the area of the central area A2 is the same (100%) as the area of each peripheral area A1.
- the plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
- the gap ratio GR according to the present embodiment is calculated.
- the angle ⁇ C is defined by a straight line L1 extending radially outward from the center O and passing through the center of the peripheral area A1 on the upper right of the drawing, and a straight line L2 extending radially outward from the center O and contacting the peripheral area A1 on the upper right of the drawing.
- the angle between expressed as arcsin (0.15 / 0.5).
- the maximum void area ratio of the present example was 10.9%.
- Example 18 The area to which the solder paste is applied in Example 18 will be described with reference to FIG. In the eighteenth embodiment, only the configuration different from that of the seventeenth embodiment will be described below, and the description of the other configurations will be omitted.
- the central area A2 has a circular shape with a diameter of 0.4 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the area of the central area A2 is 178% of the area of each peripheral area A1.
- the gap ratio GR of the present embodiment is 41.8% as in the seventeenth embodiment.
- the maximum void area ratio of the present example was 4.6%.
- the application area of the solder paste in the nineteenth embodiment will be described with reference to FIG. In the nineteenth embodiment, only the configuration different from that of the seventeenth embodiment will be described below, and description of the other configurations will be omitted.
- the central area A2 has a circular shape with a diameter of 0.5 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the area of the central area A2 is 278% of the area of each peripheral area A1.
- the gap ratio GR of the present embodiment is 41.8% as in the seventeenth embodiment.
- the maximum void area ratio in the present example was 12.4%.
- the solder paste application area in the twentieth embodiment will be described with reference to FIG. In the twentieth embodiment, only the configuration different from that of the seventeenth embodiment will be described below, and the description of the other configurations will be omitted.
- the central region A2 has a circular shape with a diameter of 0.2 mm.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- FIG. 24 shows the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2.
- the area of the central area A2 is 44.4% of the area of each peripheral area A1.
- the gap ratio GR of the present embodiment is 41.8% as in the seventeenth embodiment.
- the maximum void area ratio of the present example was 17.8%.
- the application region of the solder paste in the twenty-first embodiment will be described with reference to FIG. In the twenty-first embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
- the application area T includes a plurality (two) of peripheral areas A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central area A2 located radially inside the plurality of peripheral areas A1. And
- Each of the peripheral area A1 and the central area A2 has a circular shape with a diameter of 0.3 mm.
- the center of each peripheral area A1 is located on the outer peripheral edge of the pad P.
- the central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view.
- the positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- the maximum void area ratio of the present example was 3.8%.
- the application region T includes a plurality (four) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And Each of the peripheral area A1 and the central area A2 has a circular shape with a diameter of 0.3 mm. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- the maximum void area ratio in this example was 4.9%.
- the ratio of the gap between the plurality of peripheral regions A1 opening radially outward from the center O of the pad P with respect to the entire circumference of the pad P is calculated as the gap ratio GR. It was also found that in the embodiment of the present invention, the opening was provided from the center O toward the outside in the radial direction with an interval G therebetween. For this reason, it is considered that the molten solder from the central region A2 can appropriately flow radially outward through the gap G, and thereby the resin component of the flux can be discharged radially outward. In Examples 17 to 22, the area of the central area A2 was 44.4% or more and 278% or less of the area of each peripheral area A1.
- Example 23 The area to which the solder paste is applied in Example 23 will be described with reference to FIG.
- the solder paste is applied to the application region T where at least a part is located in the pad P so that the non-application region N is formed in the pad P of the substrate B.
- the application region T has a plurality (two) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P.
- the two peripheral regions A1 are arranged so as to be in contact with each other at a part on the radially inner side.
- the contact points of the two peripheral areas A1 are arranged at the same position as the center O in plan view.
- each peripheral area A1 is a right-angled isosceles triangle having a vertex located at the center O and an apex angle of 90 °.
- the length of the bottom side (side facing the apex) of each peripheral area A1 is 1.0 mm.
- the distance between the bottom sides of the two peripheral areas A1 is also 1.0 mm.
- the circumferential width of each peripheral area A1 gradually increases from the center O of the pad P toward the outside in the radial direction.
- the plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
- the plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P.
- each peripheral area A1 is located radially outside the pad P.
- the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
- the gap ratio GR of the present embodiment is 50%.
- the maximum void area ratio of the present example was 12.5%.
- Example 24 The application area of the solder paste in Example 24 will be described with reference to FIG. In the twenty-fourth embodiment, only the configuration different from that of the twenty-third embodiment will be described below, and the description of the other configurations will be omitted.
- the length of the base of each peripheral area A1 is 1.3 mm.
- the distance between the bases of the two peripheral regions A1 is also 1.3 mm.
- the maximum void area ratio in this example was 14.6%.
- the solder powder in the solder paste applied to the radially inner portion of the peripheral region A1 may flow in the lateral direction on the paper toward the radially outer side after melting.
- the gap ratio GR it was found that in each of the embodiments 23 and 24, the opening was provided from the center O toward the outside in the radial direction with a gap G therebetween. For this reason, the molten solder from the radially inner portion of the peripheral region A1 can appropriately flow radially outward through the gap G, whereby the resin component and the like of the flux can be discharged radially outward. it is conceivable that.
- the solder paste is applied to the application region T at least partially located in the pad P so as to form the non-application region N in the pad P of the substrate B.
- the application region T includes an extension region A3 that includes the center O of the pad P and extends in one direction (in the present embodiment, the left-right direction in the drawing).
- the planar shape of the extension region A3 is rectangular, the length in the longitudinal direction is 1.3 mm, and the width in the lateral direction is 0.3 mm.
- the extension region A3 is arranged so as to overlap the outer edge of the pad P.
- a part of the extension region A3 is located radially outside the pad P.
- both longitudinal ends of the extension region A3 are located radially outside the pad P.
- the configuration may be such that the entire extension region A3 is arranged in the pad P, or only one end in the longitudinal direction of the extension region A3 may be located radially outside the pad P.
- the gap ratio GR cannot be calculated because the extension region A3 reaches the outside of the pad P in the radial direction.
- the maximum void area ratio of the present example was 17.5%.
- the solder paste application region in the twenty-sixth embodiment will be described with reference to FIG. In the twenty-sixth embodiment, only the configuration different from that of the twenty-fifth embodiment is described below, and the description of the other configurations is omitted.
- the application region T further includes a plurality (two) of side regions A4 arranged so as to sandwich the extension region A3 in a direction intersecting the longitudinal direction of the extension region A3.
- the planar shape of each side area A4 is a square having a side of 0.3 mm in length, and one side of the side area A4 extends in the vertical direction on the paper.
- the mutual positional relationship between the plurality of side regions A4 and the extended region A3 is shown in FIG.
- Opposite sides a and b of the extension region A3 and the side regions A4 are parallel to each other.
- the opposite sides a and b may be non-parallel to each other.
- the plurality of side areas A4 are arranged so as to overlap the outer edge of the pad P. That is, a part of each side area A4 is located radially outside the pad P. Note that the configuration may be such that the plurality of side regions A4 are all arranged in the pad P.
- the maximum void area ratio in the present example was 15.0%.
- the number of the plurality of side regions A4 may be three or more.
- Table 1 shows the gap ratio GR, the coating area ratio AR, and the maximum void area ratio VR of Examples 1 to 26 described above.
- the shape of the pad P on the substrate B, which is the object to be coated is circular in plan view, but is not limited thereto, and may be, for example, rectangular or polygonal.
- a printed board made of a hard plate-shaped base material is used as an object to be applied, but a flexible substrate may be used as an object to be applied with a solder paste.
- a solder paste may be applied to the electrode surface of the one electronic component as an application target.
- the object to be applied may be any member as long as the solder paste can be applied.
- a fourth aspect of the present invention is a mask for applying a solder paste to an application object, at least a part of which is formed in the bonding region so as to form a non-application region in the bonding region of the application object.
- An opening is formed at a position corresponding to the located application region, and the opening has a plurality of peripheral openings arranged at intervals in a circumferential direction around a center of the joining region.
- a mask for applying a solder paste to an object to be applied wherein at least a part of the mask is formed in the joining region so as to form a non-application region in the joining region of the object.
- An opening is formed at a position corresponding to the located application region, and the opening has an extension opening including the center of the joining region and extending in one direction.
- the present invention is applicable to a method of applying a solder paste to an object to be applied such as a printed circuit board, and a mask used for the application. Even when voids are formed in solder in surface mounting, the voids may be formed. Can be suppressed.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Life Sciences & Earth Sciences (AREA)
- Wood Science & Technology (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
Abstract
Description
本願は、2018年9月5日に日本に出願された特願2018-166395号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a method for applying a solder paste and a mask.
Priority is claimed on Japanese Patent Application No. 2018-166395 filed on September 5, 2018, the content of which is incorporated herein by reference.
本発明の第1の態様は、塗布対象物へのソルダペーストの塗布方法であって、塗布対象物における接合領域内に非塗布領域を形成するように、前記接合領域内に少なくとも一部が位置する塗布領域にソルダペーストを塗布する工程を備え、前記塗布領域は、前記接合領域の中心回りの周方向に間隔をあけて配置された複数の周辺領域を有する。 The present invention employs the following means in order to solve the above problems.
A first aspect of the present invention is a method of applying a solder paste to an object to be applied, wherein at least a part of the solder paste is positioned in the joint area so as to form a non-application area in the joint area of the object to be applied. Applying a solder paste to an application region to be formed, wherein the application region has a plurality of peripheral regions arranged at intervals in a circumferential direction around a center of the joining region.
まず、図4(a)に示すように、ソルダペーストSが塗布された基板Bの実装面に電子部品Eを載置する。電子部品Eは、LGAやBGAであってもよい。この電子部品Eの底面(基板Bに対向する面)には、基板Bの複数のパッドPに対応するように、複数のランドL(電極)が設けられている。図4(a)に示す工程では、基板BのパッドPと電子部品EのランドLとが互いに対向するように電子部品Eを基板B上に載置する。この際、基板BのパッドPと電子部品EのランドLとの間にソルダペーストSが位置している。 Next, steps after the solder paste application step of the present embodiment in surface mounting will be described with reference to FIG.
First, as shown in FIG. 4A, the electronic component E is mounted on the mounting surface of the substrate B on which the solder paste S has been applied. The electronic component E may be an LGA or a BGA. A plurality of lands L (electrodes) are provided on the bottom surface of the electronic component E (the surface facing the substrate B) so as to correspond to the plurality of pads P of the substrate B. In the step shown in FIG. 4A, the electronic component E is mounted on the substrate B such that the pads P of the substrate B and the lands L of the electronic component E face each other. At this time, the solder paste S is located between the pad P of the substrate B and the land L of the electronic component E.
以下の実施例1~26では、基板Bの実装面の平面図を示す図5~30を用いてソルダペーストの塗布領域を説明しており、各平面図は、接合領域である基板Bの1つのパッドPを拡大した図となっている。各実施例において、パッドPの平面視形状は、直径1.0mmの円形とした。以下の説明では、パッドPの中心を通り基板Bの実装面に直交する軸に交差する方向を径方向といい、当該軸回り方向を周方向という。また、便宜上、各図面の紙面上下方向を単に「上下方向」、紙面左右方向を単に「左右方向」と称する場合がある。
これら実施例と比較例において、以下に説明する隙間割合GR、塗布面積率AR、及び最大ボイド面積率VRを確認した。 Next, a plurality of specific examples of the method of applying a solder paste according to the present embodiment will be described with reference to the drawings. Further, for comparison with these examples, comparative examples corresponding to the conventional coating method were also examined.
In the following Examples 1 to 26, the application region of the solder paste is described with reference to FIGS. 5 to 30 which are plan views of the mounting surface of the substrate B. This is an enlarged view of one pad P. In each embodiment, the shape of the pad P in plan view was a circle having a diameter of 1.0 mm. In the following description, a direction passing through the center of the pad P and crossing an axis orthogonal to the mounting surface of the substrate B is referred to as a radial direction, and a direction around the axis is referred to as a circumferential direction. Further, for convenience, the vertical direction of the drawing of each drawing may be simply referred to as “vertical direction”, and the horizontal direction of the drawing may be simply referred to as “lateral direction”.
In these examples and comparative examples, a gap ratio GR, a coating area ratio AR, and a maximum void area ratio VR described below were confirmed.
比較例は、直径1.0mmのパッドPに対して、当該パッドPと同一の領域でソルダペーストを塗布する従来の構成とした。この比較例は、後に示す表1において「Ref」で示されている。この比較例において、複数の周辺領域は存在しないので隙間割合GRは算出できず、塗布面積率ARは100%である。また、最大ボイド面積率VRは、43.5%であった。 (Comparative example)
The comparative example has a conventional configuration in which a solder paste is applied to a pad P having a diameter of 1.0 mm in the same region as the pad P. This comparative example is indicated by “Ref” in Table 1 below. In this comparative example, since there is no plurality of peripheral regions, the gap ratio GR cannot be calculated, and the application area ratio AR is 100%. Further, the maximum void area ratio VR was 43.5%.
実施例1におけるソルダペーストの塗布領域を図5を参照して説明する。
実施例1では、基板BにおけるパッドP内に非塗布領域Nを形成するように、パッドP内に少なくとも一部が位置する塗布領域Tにソルダペーストが塗布されている。図5において、ソルダペーストが塗布されている領域に網掛けを付している(他の図6~30でも同様)。塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(2つ)の周辺領域A1を有する。各周辺領域A1は一方向に延びた矩形状であり、長手方向の長さは0.7mm、当該長手方向と直交する短手方向の幅は0.35mmである。
複数の周辺領域A1は、パッドPの中心Oを挟んで互いに対向して配置されている。
複数の周辺領域A1は、当該複数の周辺領域A1の対向方向(図5の紙面上下方向)と直交する方向に延びて配置されている。すなわち、各周辺領域A1は、紙面左右方向に延びている。なお、複数の周辺領域A1が、前記対向方向と交差する方向に延びて配置されてもよい。
複数の周辺領域A1間の隙間(前記対向方向の隙間)の大きさは、0.7mmである。このため、複数の周辺領域A1間の隙間は、パッドPの最大径(1.0mm)の70%であり、前記対向方向における各周辺領域A1の幅の200%である。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
複数の周辺領域A1の対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。
複数の周辺領域A1は、パッドPの外縁に重なって配置されている。すなわち、各周辺領域A1の一部は、パッドPの径方向外側に位置している。なお、複数の周辺領域A1が、全てパッドP内に配置される構成であってもよい。 (Example 1)
The application region of the solder paste in the first embodiment will be described with reference to FIG.
In the first embodiment, the solder paste is applied to the application region T at least partially located in the pad P so as to form the non-application region N in the pad P of the substrate B. In FIG. 5, the region where the solder paste is applied is shaded (the same applies to other FIGS. 6 to 30). The application region T has a plurality (two) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P. Each peripheral area A1 has a rectangular shape extending in one direction, has a length in the longitudinal direction of 0.7 mm, and a width in the transverse direction orthogonal to the longitudinal direction is 0.35 mm.
The plurality of peripheral areas A1 are arranged to face each other with the center O of the pad P interposed therebetween.
The plurality of peripheral areas A1 are arranged so as to extend in a direction orthogonal to the direction in which the plurality of peripheral areas A1 are opposed to each other (vertical direction in FIG. 5). That is, each peripheral area A1 extends in the left-right direction on the paper. Note that a plurality of peripheral regions A1 may be arranged so as to extend in a direction intersecting the opposing direction.
The size of the gap between the plurality of peripheral regions A1 (the gap in the facing direction) is 0.7 mm. Therefore, the gap between the plurality of peripheral regions A1 is 70% of the maximum diameter (1.0 mm) of the pad P, and is 200% of the width of each peripheral region A1 in the facing direction.
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
Opposite sides a and b of the plurality of peripheral regions A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
The plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
本実施例の塗布面積率ARは、(0.7×0.35×2)/(0.52×π)=62.4%である。
本実施例の最大ボイド面積率は、2.3%であった。 When the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the angle θ G to 90 ° between the straight lines L1 and L2 is defined as the gap ratio GR of the present embodiment. The angle θ G is an angle between the straight line L1 and a straight line L3 extending radially outward from the center O and in contact with the lower right vertex of the peripheral area A1 on the upper side of the drawing. No peripheral area A1 is arranged between the straight lines L1 and L3. Therefore, the gap ratio GR of the present embodiment is (arctan (0.35 / 0.35) / 90 °) = 50%.
The application area ratio AR in this embodiment is (0.7 × 0.35 × 2) / (0.5 2 × π) = 62.4%.
The maximum void area ratio of the present example was 2.3%.
実施例2におけるソルダペーストの塗布領域を図6を参照して説明する。なお、実施例2において、前記実施例1と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
複数の周辺領域A1間の隙間(前記対向方向の隙間)の大きさは、0.3mmである。このため、複数の周辺領域A1間の隙間は、パッドPの最大径(1.0mm)の30%であり、前記対向方向における各周辺領域A1の幅の85.7%である。 (Example 2)
The application area of the solder paste in the second embodiment will be described with reference to FIG. In the second embodiment, only the configuration different from the first embodiment will be described below, and the description of the other configurations will be omitted.
The size of the gap between the plurality of peripheral areas A1 (the gap in the facing direction) is 0.3 mm. Therefore, the gap between the plurality of peripheral regions A1 is 30% of the maximum diameter (1.0 mm) of the pad P, and is 85.7% of the width of each peripheral region A1 in the facing direction.
本実施例の最大ボイド面積率は、13.8%であった。 The gap ratio GR of the present embodiment is (arctan (0.15 / 0.35) / 90 °) = 25.8%.
The maximum void area ratio of the present example was 13.8%.
実施例3におけるソルダペーストの塗布領域を図7を参照して説明する。なお、実施例3において、前記実施例1と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
複数の周辺領域A1間の隙間(前記対向方向の隙間)の大きさは、0.4mmである。このため、複数の周辺領域A1間の隙間は、パッドPの最大径(1.0mm)の40%であり、前記対向方向における各周辺領域A1の幅の114%である。 (Example 3)
The region where the solder paste is applied in the third embodiment will be described with reference to FIG. In the third embodiment, only the configuration different from the first embodiment will be described below, and the description of the other configurations will be omitted.
The size of the gap (gap in the facing direction) between the plurality of peripheral areas A1 is 0.4 mm. Therefore, the gap between the plurality of peripheral regions A1 is 40% of the maximum diameter (1.0 mm) of the pad P, and is 114% of the width of each peripheral region A1 in the facing direction.
本実施例の最大ボイド面積率は、11.7%であった。 The gap ratio GR of the present embodiment is (arctan (0.2 / 0.35) / 90 °) = 33%.
The maximum void area ratio of the present example was 11.7%.
実施例4におけるソルダペーストの塗布領域を図8を参照して説明する。なお、実施例4において、前記実施例1と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
複数の周辺領域A1間の隙間(前記対向方向の隙間)の大きさは、0.5mmである。このため、複数の周辺領域A1間の隙間は、パッドPの最大径(1.0mm)の50%であり、前記対向方向における各周辺領域A1の幅の143%である。 (Example 4)
The solder paste application area in the fourth embodiment will be described with reference to FIG. In the fourth embodiment, only configurations different from those of the first embodiment will be described below, and descriptions of other configurations will be omitted.
The size of the gap between the plurality of peripheral areas A1 (the gap in the facing direction) is 0.5 mm. Therefore, the gap between the plurality of peripheral regions A1 is 50% of the maximum diameter (1.0 mm) of the pad P, and is 143% of the width of each peripheral region A1 in the facing direction.
本実施例の最大ボイド面積率は、7.0%であった。 The gap ratio GR of the present embodiment is (arctan (0.25 / 0.35) / 90 °) = 39.5%.
The maximum void area ratio of the present example was 7.0%.
実施例5におけるソルダペーストの塗布領域を図9を参照して説明する。なお、実施例5において、前記実施例1と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
複数の周辺領域A1間の隙間(前記対向方向の隙間)の大きさは、0.6mmである。このため、複数の周辺領域A1間の隙間は、パッドPの最大径(1.0mm)の60%であり、前記対向方向における各周辺領域A1の幅の171%である。 (Example 5)
The application region of the solder paste in the fifth embodiment will be described with reference to FIG. In the fifth embodiment, only the configuration different from the first embodiment will be described below, and the description of the other configurations will be omitted.
The size of the gap between the plurality of peripheral areas A1 (the gap in the facing direction) is 0.6 mm. Therefore, the gap between the plurality of peripheral regions A1 is 60% of the maximum diameter (1.0 mm) of the pad P, and is 171% of the width of each peripheral region A1 in the facing direction.
本実施例の最大ボイド面積率は、4.2%であった。 The gap ratio GR in this embodiment is (arctan (0.3 / 0.35) / 90 °) = 45.1%.
The maximum void area ratio in the present example was 4.2%.
実施例1~5の最大ボイド面積率VRは、全て比較例より低くなった。このため、実施例1~5のいずれにおいても、生じたボイドの大きさを抑制できたことが判る。
ボイドの大きさが抑制できた原因を以下に検討する。リフロー工程で溶融したはんだ粉末が互いに結合する際、溶融前のはんだ粉末間に位置していたフラックスの樹脂成分等は溶融はんだの結合によって外部に向けて押し出される。しかし、ソルダペーストの塗布領域が大きいと、前記樹脂成分がはんだから排出される前にはんだが冷えて固化してしまい、このため樹脂成分がはんだ内に残されていたこと(すなわちボイド)が考えられる。一方、実施例1~5では、各周辺領域A1の幅は0.35mmであり、パッドPの最大径(1.0mm)よりも大幅に小さい。このため、フラックスの樹脂成分等が周辺領域A1の短手方向に移動した場合は比較的早期に溶融はんだから排出されるため、各周辺領域A1において、比較例よりもボイドの大きさが抑制されると考えられる。
また、図4に示したように、2つの領域に塗布されたソルダペースト内のはんだ粉末もリフロー工程において一体化する。すなわち、2つの周辺領域A1で溶融したはんだ粉末は、パッドPの中心Oに向けて流動し、パッドPの中央付近で互いに接する。径方向内側へ向かう溶融はんだの流動は維持されるので、2つの領域から流動した溶融はんだの接続箇所は、径方向外側に向けて拡大する。この接続箇所が径方向外側に向けて拡大するために、フラックスの樹脂成分等を径方向外側に向かわせる力が生じ、この力によっても樹脂成分をはんだの外側に向けて排出できると考えられる。 (Study of Examples 1 to 5)
The maximum void area ratios VR of Examples 1 to 5 were all lower than those of Comparative Examples. Therefore, it can be seen that the size of the generated voids could be suppressed in any of Examples 1 to 5.
The reason why the size of the void could be suppressed will be discussed below. When the solder powders melted in the reflow step are bonded to each other, the resin component of the flux located between the solder powders before the melting is extruded outward by the bonding of the molten solder. However, if the solder paste application area is large, the solder cools and solidifies before the resin component is discharged from the solder, so that the resin component was left in the solder (ie, voids). Can be On the other hand, in Examples 1 to 5, the width of each peripheral area A1 is 0.35 mm, which is significantly smaller than the maximum diameter (1.0 mm) of the pad P. For this reason, when the resin component or the like of the flux moves in the short direction of the peripheral area A1, the flux is discharged from the molten solder relatively early, and the size of the void is suppressed in each peripheral area A1 as compared with the comparative example. It is thought that.
Further, as shown in FIG. 4, the solder powder in the solder paste applied to the two regions is also integrated in the reflow process. That is, the solder powder melted in the two peripheral regions A1 flows toward the center O of the pad P and comes into contact with each other near the center of the pad P. Since the flow of the molten solder flowing inward in the radial direction is maintained, the connection portion of the molten solder flowing from the two regions expands outward in the radial direction. It is considered that since the connecting portion expands outward in the radial direction, a force for causing the resin component of the flux to move outward in the radial direction is generated, and it is considered that the resin component can be discharged toward the outside of the solder by this force.
また、複数の周辺領域A1間の隙間は、複数の周辺領域A1の対向方向における各周辺領域A1の幅の85.7%以上200%以下であった。 In Examples 1 to 5, the gap between the plurality of peripheral regions A1 was 30% or more and 70% or less of the maximum diameter (1.0 mm) of the pad P.
The gap between the plurality of peripheral regions A1 was 85.7% or more and 200% or less of the width of each peripheral region A1 in the facing direction of the plurality of peripheral regions A1.
実施例1~5には以下の変形例が考えられる。
各周辺領域A1は平面視矩形状であるが、平面視で楕円状または長円状であってもよい。複数の周辺領域A1の対向辺a,bは直線状に形成されているが、これらの対向辺が径方向内側に向けて膨出する形状であってもよく、また、径方向外側に向けて窪んだ形状であってもよい。同様に、周辺領域A1の径方向外側の辺が径方向内側に窪んでいたり、径方向外側に膨出したりしていてもよい。 (Modifications of
The following modifications are conceivable in the first to fifth embodiments.
Each peripheral area A1 has a rectangular shape in plan view, but may have an elliptical or elliptical shape in plan view. Although the opposing sides a and b of the plurality of peripheral areas A1 are formed in a straight line, the opposing sides may have a shape that bulges inward in the radial direction, or may bulge outward in the radial direction. It may have a concave shape. Similarly, the radially outer side of the peripheral region A1 may be depressed inward in the radial direction or may bulge outward in the radial direction.
実施例6におけるソルダペーストの塗布領域を図10を参照して説明する。
実施例6では、基板BにおけるパッドP内に非塗布領域Nを形成するように、パッドP内に少なくとも一部が位置する塗布領域Tにソルダペーストが塗布されている。塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(6つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも一辺の長さが0.3mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図10に示されている。
複数の周辺領域A1は、周方向に略等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
周方向に隣り合う複数の周辺領域A1の対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。
中央領域A2と各周辺領域A1との対向辺c,dは、互いに平行している。なお、対向辺c,dが、互いに非平行であってもよい。
中央領域A2の面積は、各周辺領域A1の面積と同一(100%)である。
複数の周辺領域A1は、パッドPの外縁に重なって配置されている。すなわち、各周辺領域A1の一部は、パッドPの径方向外側に位置している。なお、複数の周辺領域A1が、全てパッドP内に配置される構成であってもよい。 (Example 6)
The solder paste application area in the sixth embodiment will be described with reference to FIG.
In the sixth embodiment, the solder paste is applied to the application region T at least partially located in the pad P so as to form the non-application region N in the pad P of the substrate B. The application region T includes a plurality (six) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the plurality of peripheral regions A1. And Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral areas A1 are arranged at substantially equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
Opposite sides a and b of a plurality of peripheral regions A1 circumferentially adjacent to each other are parallel to each other. The opposite sides a and b may be non-parallel to each other.
Opposite sides c and d of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides c and d may be non-parallel to each other.
The area of the central area A2 is the same (100%) as the area of each peripheral area A1.
The plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
本実施例の塗布面積率ARは、(0.32×7)/(0.52×π)=80.3%である。
本実施例の最大ボイド面積率は、4.8%であった。 When the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the sum of the angle θ G1 and the angle θ G2 to 90 ° formed between the straight lines L1 and L2 is determined by the gap in the present embodiment. The ratio GR was set. The angle θ G1 is an angle between the straight line L1 and a straight line L3 extending radially outward from the center O and in contact with the lower right vertex of the peripheral area A1 on the upper right of the paper, and arctan (0.1 / 0) .65). The angle θ G2 is a straight line L4 extending radially outward from the center O and in contact with the upper left vertex of the peripheral area A1 on the upper right of the drawing, and a straight line L4 extending radially outward from the center O and a lower right apex of the upper peripheral area A1 on the drawing. And an angle between the straight line L5 and the arc L, which is expressed by (arctan (0.35 / 0.15) -arctan (0.4 / 0.35)). Therefore, the gap ratio GR of the present embodiment is (θ G1 + θ G2 ) /90°=29.7%.
The application area ratio AR in this embodiment is (0.3 2 × 7) / (0.5 2 × π) = 80.3%.
The maximum void area ratio of the present example was 4.8%.
実施例7におけるソルダペーストの塗布領域を図11を参照して説明する。なお、実施例7において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
中央領域A2は一辺の長さが0.4mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図11に示されている。
中央領域A2の面積は、各周辺領域A1の面積の178%(=0.42/0.32)である。 (Example 7)
The application area of the solder paste in the seventh embodiment will be described with reference to FIG. In the seventh embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The central area A2 has a square shape with a side length of 0.4 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
Area of the central region A2 is 178% of the area of each peripheral regions A1 (= 0.4 2 /0.3 2) .
本実施例の塗布面積率ARは、(0.32×6+0.42)/(0.52×π)=89.2%である。
本実施例の最大ボイド面積率は、3.9%であった。 The gap ratio GR of the present embodiment is 29.7%, similarly to the sixth embodiment.
The application area ratio AR in this embodiment is (0.3 2 × 6 + 0.4 2 ) / (0.5 2 × π) = 89.2%.
The maximum void area ratio of the present example was 3.9%.
実施例8におけるソルダペーストの塗布領域を図12を参照して説明する。なお、実施例8において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
中央領域A2は一辺の長さが0.5mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図12に示されている。
中央領域A2の面積は、各周辺領域A1の面積の278%(=0.52/0.32)である。 (Example 8)
The solder paste application area in the eighth embodiment will be described with reference to FIG. In the eighth embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The central region A2 has a square shape with a side length of 0.5 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The area of the central area A2 is 278% (= 0.5 2 /0.3 2 ) of the area of each peripheral area A1.
本実施例の塗布面積率ARは、(0.32×6+0.52)/(0.52×π)=100.6%である。
本実施例の最大ボイド面積率は、13.9%であった。 The gap ratio GR of the present embodiment is 29.7%, similarly to the sixth embodiment.
The application area ratio AR in this embodiment is (0.3 2 × 6 + 0.5 2 ) / (0.5 2 × π) = 100.6%.
The maximum void area ratio of the present example was 13.9%.
実施例9におけるソルダペーストの塗布領域を図13を参照して説明する。なお、実施例9において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
中央領域A2は一辺の長さが0.2mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図13に示されている。
中央領域A2の面積は、各周辺領域A1の面積の44.4%(=0.22/0.32)である。 (Example 9)
The application area of the solder paste in the ninth embodiment will be described with reference to FIG. In the ninth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The central area A2 has a square shape with a side length of 0.2 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The area of the central area A2 is 44.4% (= 0.2 2 /0.3 2 ) of the area of each peripheral area A1.
本実施例の塗布面積率ARは、(0.32×6+0.22)/(0.52×π)=73.9%である。
本実施例の最大ボイド面積率は、12.3%であった。 The gap ratio GR of the present embodiment is 29.7%, similarly to the sixth embodiment.
The application area ratio AR in this embodiment is (0.3 2 × 6 + 0.2 2 ) / (0.5 2 × π) = 73.9%.
The maximum void area ratio of the present example was 12.3%.
実施例10におけるソルダペーストの塗布領域を図14を参照して説明する。なお、実施例10において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(2つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも一辺の長さが0.3mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図14に示されている。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
中央領域A2と各周辺領域A1との対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。 (Example 10)
The application area of the solder paste in the tenth embodiment will be described with reference to FIG. In the tenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application area T includes a plurality (two) of peripheral areas A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central area A2 located radially inside the plurality of peripheral areas A1. And Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
本実施例の塗布面積率ARは、(0.32×3)/(0.52×π)=34.4%である。
本実施例の最大ボイド面積率は、3.1%であった。 When the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the angle θ G to 90 ° between the straight lines L1 and L2 is defined as the gap ratio GR of the present embodiment. The angle θ G is an angle between the straight line L1 and a straight line L3 extending radially outward from the center O and in contact with the lower right vertex of the peripheral region A1 on the upper side of the drawing. No peripheral area A1 is arranged between the straight lines L1 and L3. Therefore, the gap ratio GR of the present embodiment is (arctan (0.35 / 0.15) / 90 °) = 74.2%.
The application area ratio AR in this example is (0.3 2 × 3) / (0.5 2 × π) = 34.4%.
The maximum void area ratio of the present example was 3.1%.
実施例11におけるソルダペーストの塗布領域を図15を参照して説明する。なお、実施例11において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(3つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図15に示されている。
複数の周辺領域A1は、周方向に略等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
中央領域A2と各周辺領域A1との対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。 (Example 11)
The application region of the solder paste in the eleventh embodiment will be described with reference to FIG. In the eleventh embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application region T includes a plurality (three) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral areas A1 are arranged at substantially equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
本実施例の塗布面積率ARは、(0.32×4)/(0.52×π)=45.9%である。
本実施例の最大ボイド面積率は、4.0%であった。 When the application region T of the present embodiment is divided into two by a straight line extending through the center O and extending in the up-down direction, the right-hand section of the straight line is a mirror image of the left-hand section, and therefore, the straight line L1 extending upward from the center O. The ratio of the sum of the angles θ G1 , θ G2, and θ G3 to 180 ° formed between the straight line L2 extending downward from the center O is defined as the gap ratio GR of the present embodiment. The angle θ G1 is an angle between a straight line L3 extending from the center O to the right side of the drawing and a straight line L4 extending radially outward from the center O and in contact with the lower right vertex of the peripheral region A1 on the upper side of the drawing. , Arctan (0.35 / 0.15). The angle θ G2 is an angle between the straight line L2 and a straight line L5 extending radially outward from the center O and in contact with the lower left vertex of the peripheral area A1 on the lower right side of the drawing, and is (90 ° −arctan (0 .45 / 0.35)). The angle θ G3 is an angle between the straight line L3 and a straight line L6 extending radially outward from the center O and in contact with the upper right vertex of the peripheral area A1 on the lower right of the paper, and arctan (0.15 / 0) .65)). Therefore, the gap ratio GR of the present embodiment is (θ G1 + θ G2 + θ G3 ) /90°=65.4%.
The application area ratio AR in this example is (0.3 2 × 4) / (0.5 2 × π) = 45.9%.
The maximum void area ratio of the present example was 4.0%.
実施例12におけるソルダペーストの塗布領域を図16を参照して説明する。なお、実施例12において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(4つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも一辺の長さが0.3mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図16に示されている。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
中央領域A2と各周辺領域A1との対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。 (Example 12)
The application area of the solder paste in the twelfth embodiment will be described with reference to FIG. In the twelfth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application region T includes a plurality (four) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
本実施例の塗布面積率ARは、(0.32×5)/(0.52×π)=57.1%である。
本実施例の最大ボイド面積率は、2.6%であった。 When the application region T of this embodiment is divided into four by two straight lines passing through the center O and extending in the vertical and horizontal directions, for example, a straight line L1 extending from the center O to the right side of the paper and extending from the center O to an upper side of the paper Since the section between the straight line L2 and the other three sections is the same or a mirror image, the ratio of the angle θ G to 90 ° between the straight lines L1 and L2 is defined as the gap ratio GR of the present embodiment. The angle θ G is a straight line L3 extending radially outward from the center O and in contact with the upper left vertex of the peripheral region A1 on the right side of the drawing, and a straight line L3 extending radially outward from the center O and a lower right vertex of the peripheral region A1 on the upper side of the drawing. And the straight line L4 that is in contact with No peripheral area A1 is arranged between the straight lines L3 and L4. Therefore, the gap ratio GR in the present embodiment is (arctan (0.35 / 0.15) -arctan (0.15 / 0.35)) = 48.4%.
The application area ratio AR in this embodiment is (0.3 2 × 5) / (0.5 2 × π) = 57.1%.
The maximum void area ratio in the present example was 2.6%.
実施例13におけるソルダペーストの塗布領域を図17を参照して説明する。なお、実施例13において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(4つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。また、複数の周辺領域A1は、周方向の長さが異なる第1領域A11及び第2領域A12を有し、第1領域A11及び第2領域A12は、周方向で交互に配置されている。第1領域A11及び第2領域A12は、2つづつ設けられている。第1領域A11は、一方向に延びる矩形状であり、長手方向の長さが0.6mm、当該長手方向に直交する短手方向の幅が0.3mmである。第2領域A12及び中央領域A2は、いずれも一辺の長さが0.3mmの正方形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の第1領域A11及び複数の第2領域A12並びに中央領域A2の相互の位置関係は、図17に示されている。
中央領域A2と各周辺領域A1との対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。 (Example 13)
The solder paste application area in the thirteenth embodiment will be described with reference to FIG. In the thirteenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application region T includes a plurality (four) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And The plurality of peripheral regions A1 have a first region A11 and a second region A12 having different circumferential lengths, and the first region A11 and the second region A12 are alternately arranged in the circumferential direction. The first area A11 and the second area A12 are provided two by two. The first region A11 has a rectangular shape extending in one direction, has a length in the longitudinal direction of 0.6 mm, and has a width in the short direction orthogonal to the longitudinal direction of 0.3 mm. Each of the second area A12 and the central area A2 is a square having a side length of 0.3 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of first regions A11, the plurality of second regions A12, and the central region A2 is shown in FIG.
Opposite sides a and b of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
本実施例の塗布面積率ARは、(0.6×0.3×2+0.32×3)/(0.52×π)=34.6%である。
本実施例の最大ボイド面積率は、1.8%であった。 The gap ratio GR of the present embodiment is calculated in the same manner as in the twelfth embodiment, and is (arctan (0.35 / 0.15) -arctan (0.3 / 0.35)) = 29.1%.
The application area ratio AR in this embodiment is (0.6 × 0.3 × 2 + 0.3 2 × 3) / (0.5 2 × π) = 34.6%.
The maximum void area ratio in this example was 1.8%.
実施例14におけるソルダペーストの塗布領域を図18を参照して説明する。なお、実施例14において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(6つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも一辺の長さが0.3mmの正方形状である。ただし、周辺領域A1のうち、パッドPの外縁よりも径方向外側の部分は除外されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図18に示されている。
周方向に隣り合う複数の周辺領域A1の対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。
中央領域A2と各周辺領域A1との対向辺c,dは、互いに平行している。なお、対向辺c,dが、互いに非平行であってもよい。 (Example 14)
The area where the solder paste is applied in Example 14 will be described with reference to FIG. In the fourteenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application region T includes a plurality (six) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the plurality of peripheral regions A1. And Each of the peripheral area A1 and the central area A2 has a square shape with a side length of 0.3 mm. However, in the peripheral area A1, a portion radially outside the outer edge of the pad P is excluded. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
Opposite sides a and b of a plurality of peripheral regions A1 circumferentially adjacent to each other are parallel to each other. The opposite sides a and b may be non-parallel to each other.
Opposite sides c and d of the central area A2 and the peripheral areas A1 are parallel to each other. The opposite sides c and d may be non-parallel to each other.
本実施例の塗布面積率ARは、約43%である。
本実施例の最大ボイド面積率は、13.8%であった。 The gap ratio GR of the present embodiment was calculated by the same method as in the sixth embodiment. However, since the angle θ G1 is represented by arcsin (0.05 / 0.5), the gap ratio GR is (θ a G1 + θ G2) /90°=11.5%.
The application area ratio AR of this embodiment is about 43%.
The maximum void area ratio of the present example was 13.8%.
実施例6~14の最大ボイド面積率VRは、全て比較例より低くなった。このため、実施例6~14のいずれにおいても、生じたボイドの大きさを抑制できたことが判る。
ボイドの大きさが抑制できた原因を以下に検討する。まず、周辺領域A1や中央領域A2が比較例の塗布領域よりも小さいため、フラックスの樹脂成分等が早期に溶融はんだ内から排出されやすいことは、実施例1~5と同様であると考えられる。
また、実施例6~14では全て中央領域A2を有しているが、中央領域A2に塗布されたソルダペースト内のはんだ粉末は、溶融後径方向外側に向けて流動する。なお、パッドPの中心Oから径方向外側に向けて開口する、複数の周辺領域A1の間の隙間の、パッドPの全周に対する割合を隙間割合GRとして算出し、実施例6~14のいずれの実施例でも中心Oから径方向外側に向けて間隔Gを介して開口していることが判った。このため、中央領域A2からの溶融はんだは間隔Gを通って適切に径方向外側に流動することができ、これによりフラックスの樹脂成分等を径方向外側に向かわせて排出できると考えられる。
実施例6~14において、中央領域A2の面積は、各周辺領域A1の面積の44.4%以上278%以下であった。 (Study of Examples 6 to 14)
The maximum void area ratios VR of Examples 6 to 14 were all lower than those of Comparative Examples. Therefore, it can be seen that the size of the generated voids could be suppressed in any of Examples 6 to 14.
The reason why the size of the void could be suppressed will be discussed below. First, since the peripheral region A1 and the central region A2 are smaller than the application region of the comparative example, it is considered that the resin component of the flux is easily discharged from the molten solder early as in the first to fifth embodiments. .
Further, although all of Examples 6 to 14 have the central region A2, the solder powder in the solder paste applied to the central region A2 flows radially outward after melting. Note that the ratio of the gap between the plurality of peripheral regions A1 opening radially outward from the center O of the pad P to the entire circumference of the pad P is calculated as the gap ratio GR. It was also found that in the embodiment of the present invention, the opening was provided from the center O toward the outside in the radial direction with an interval G therebetween. For this reason, it is considered that the molten solder from the central region A2 can appropriately flow radially outward through the gap G, and thereby the resin component of the flux can be discharged radially outward.
In Examples 6 to 14, the area of the central region A2 was 44.4% or more and 278% or less of the area of each peripheral region A1.
実施例15におけるソルダペーストの塗布領域を図19を参照して説明する。なお、実施例15において、前記実施例12と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
実施例15は、実施例12から中央領域A2を除外した構成を有している。
本実施例の隙間割合GRは、実施例12と同様であり、48.4%である。
本実施例の塗布面積率ARは、(0.32×4)/(0.52×π)=45.7%である。
本実施例の最大ボイド面積率は、13.4%であった。 (Example 15)
The application region of the solder paste in the embodiment 15 will be described with reference to FIG. In the fifteenth embodiment, only the configuration different from that of the twelfth embodiment will be described below, and the description of the other configurations will be omitted.
The fifteenth embodiment has a configuration in which the central region A2 is excluded from the twelfth embodiment.
The gap ratio GR of the present embodiment is the same as that of the twelfth embodiment, and is 48.4%.
The application area ratio AR of this embodiment is (0.3 2 × 4) / (0.5 2 × π) = 45.7%.
The maximum void area ratio of the present example was 13.4%.
実施例16におけるソルダペーストの塗布領域を図20を参照して説明する。なお、実施例16において、前記実施例13と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
実施例16は、実施例13から中央領域A2を除外した構成を有している。
本実施例の隙間割合GRは、実施例13と同様であり、29.1%である。
本実施例の塗布面積率ARは、(0.6×0.3×2+0.32×2)/(0.52×π)=23.2%である。
本実施例の最大ボイド面積率は、13.8%であった。 (Example 16)
The application region of the solder paste in the sixteenth embodiment will be described with reference to FIG. In the sixteenth embodiment, only the configuration different from that of the thirteenth embodiment will be described below, and the description of the other configurations will be omitted.
The sixteenth embodiment has a configuration in which the central region A2 is excluded from the thirteenth embodiment.
The gap ratio GR of the present embodiment is the same as that of the thirteenth embodiment, and is 29.1%.
The coating area ratio AR in this embodiment is (0.6 × 0.3 × 2 + 0.3 2 × 2) / (0.5 2 × π) = 23.2%.
The maximum void area ratio of the present example was 13.8%.
実施例15,16の最大ボイド面積率VRは、全て比較例より低くなった。このため、実施例15,16のいずれにおいても、生じたボイドの大きさを抑制できたことが判る。
ボイドの大きさが抑制できた原因を以下に検討すると、周辺領域A1や中央領域A2が比較例の塗布領域よりも小さいため、フラックスの樹脂成分等が早期に溶融はんだ内から排出されやすいことは、実施例1~5と同様であると考えられる。 (Study of Examples 15 and 16)
The maximum void area ratios VR of Examples 15 and 16 were all lower than those of Comparative Examples. Therefore, it can be seen that in each of Examples 15 and 16, the size of the generated void could be suppressed.
When the cause of the suppression of the size of the void is examined below, since the peripheral region A1 and the central region A2 are smaller than the application region of the comparative example, the resin component of the flux is easily discharged from the molten solder at an early stage. It is considered to be the same as in Examples 1 to 5.
実施例17におけるソルダペーストの塗布領域を図21を参照して説明する。なお、実施例17において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(6つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも直径が0.3mmの円形状である。各周辺領域A1の中心は、パッドPの外周縁上に位置している。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図21に示されている。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
中央領域A2の面積は、各周辺領域A1の面積と同一(100%)である。
複数の周辺領域A1は、パッドPの外縁に重なって配置されている。すなわち、各周辺領域A1の一部は、パッドPの径方向外側に位置している。なお、複数の周辺領域A1が、全てパッドP内に配置される構成であってもよい。 (Example 17)
The application area of the solder paste in the seventeenth embodiment will be described with reference to FIG. In the seventeenth embodiment, only the configuration different from that of the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application region T includes a plurality (six) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the plurality of peripheral regions A1. And Each of the peripheral area A1 and the central area A2 has a circular shape with a diameter of 0.3 mm. The center of each peripheral area A1 is located on the outer peripheral edge of the pad P. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
The area of the central area A2 is the same (100%) as the area of each peripheral area A1.
The plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
本実施例の塗布面積率ARは、(0.152×π×7)/(0.52×π)=63%である。
本実施例の最大ボイド面積率は、10.9%であった。 The gap ratio GR according to the present embodiment is calculated. The angle θ C is defined by a straight line L1 extending radially outward from the center O and passing through the center of the peripheral area A1 on the upper right of the drawing, and a straight line L2 extending radially outward from the center O and contacting the peripheral area A1 on the upper right of the drawing. The angle between, expressed as arcsin (0.15 / 0.5). The peripheral area A1 is located between the straight lines L1 and L2. Therefore, the gap ratio GR of the present embodiment is (180 ° −6 × θ C ) /180°=41.8%.
The application area ratio AR in this embodiment is (0.15 2 × π × 7) / (0.5 2 × π) = 63%.
The maximum void area ratio of the present example was 10.9%.
実施例18におけるソルダペーストの塗布領域を図22を参照して説明する。なお、実施例18において、前記実施例17と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
中央領域A2は直径が0.4mmの円形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図22に示されている。
中央領域A2の面積は、各周辺領域A1の面積の178%である。
本実施例の隙間割合GRは、実施例17と同じく、41.8%である。
本実施例の塗布面積率ARは、(0.152×π×6+0.22×π)/(0.52×π)=43.1%である。
本実施例の最大ボイド面積率は、4.6%であった。 (Example 18)
The area to which the solder paste is applied in Example 18 will be described with reference to FIG. In the eighteenth embodiment, only the configuration different from that of the seventeenth embodiment will be described below, and the description of the other configurations will be omitted.
The central area A2 has a circular shape with a diameter of 0.4 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The area of the central area A2 is 178% of the area of each peripheral area A1.
The gap ratio GR of the present embodiment is 41.8% as in the seventeenth embodiment.
The application area ratio AR in this embodiment is (0.15 2 × π × 6 + 0.2 2 × π) / (0.5 2 × π) = 43.1%.
The maximum void area ratio of the present example was 4.6%.
実施例19におけるソルダペーストの塗布領域を図23を参照して説明する。なお、実施例19において、前記実施例17と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
中央領域A2は直径が0.5mmの円形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図23に示されている。
中央領域A2の面積は、各周辺領域A1の面積の278%である。
本実施例の隙間割合GRは、実施例17と同じく、41.8%である。
本実施例の塗布面積率ARは、(0.152×π×6+0.252×π)/(0.52×π)=48.7%である。
本実施例の最大ボイド面積率は、12.4%であった。 (Example 19)
The application area of the solder paste in the nineteenth embodiment will be described with reference to FIG. In the nineteenth embodiment, only the configuration different from that of the seventeenth embodiment will be described below, and description of the other configurations will be omitted.
The central area A2 has a circular shape with a diameter of 0.5 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The area of the central area A2 is 278% of the area of each peripheral area A1.
The gap ratio GR of the present embodiment is 41.8% as in the seventeenth embodiment.
The application area ratio AR in this embodiment is (0.15 2 × π × 6 + 0.25 2 × π) / (0.5 2 × π) = 48.7%.
The maximum void area ratio in the present example was 12.4%.
実施例20におけるソルダペーストの塗布領域を図24を参照して説明する。なお、実施例20において、前記実施例17と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
中央領域A2は直径が0.2mmの円形状である。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図24に示されている。
中央領域A2の面積は、各周辺領域A1の面積の44.4%である。
本実施例の隙間割合GRは、実施例17と同じく、41.8%である。
本実施例の塗布面積率ARは、(0.152×π×6+0.12×π)/(0.52×π)=35.7%である。
本実施例の最大ボイド面積率は、17.8%であった。 (Example 20)
The solder paste application area in the twentieth embodiment will be described with reference to FIG. In the twentieth embodiment, only the configuration different from that of the seventeenth embodiment will be described below, and the description of the other configurations will be omitted.
The central region A2 has a circular shape with a diameter of 0.2 mm. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. FIG. 24 shows the mutual positional relationship between the plurality of peripheral areas A1 and the central area A2.
The area of the central area A2 is 44.4% of the area of each peripheral area A1.
The gap ratio GR of the present embodiment is 41.8% as in the seventeenth embodiment.
The coating area ratio AR in this embodiment is (0.15 2 × π × 6 + 0.1 2 × π) / (0.5 2 × π) = 35.7%.
The maximum void area ratio of the present example was 17.8%.
実施例21におけるソルダペーストの塗布領域を図25を参照して説明する。なお、実施例21において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(2つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも直径が0.3mmの円形状である。各周辺領域A1の中心は、パッドPの外周縁上に位置している。中央領域A2は、その中心がパッドPの中心Oと平面視で一致するように配置されている。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図25に示されている。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
本実施例の隙間割合GRは、前記実施例17を参照して、(180°-2×θC)/180°=80.6%である。
本実施例の塗布面積率ARは、(0.152×π×3)/(0.52×π)=27%である。
本実施例の最大ボイド面積率は、3.8%であった。 (Example 21)
The application region of the solder paste in the twenty-first embodiment will be described with reference to FIG. In the twenty-first embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application area T includes a plurality (two) of peripheral areas A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central area A2 located radially inside the plurality of peripheral areas A1. And Each of the peripheral area A1 and the central area A2 has a circular shape with a diameter of 0.3 mm. The center of each peripheral area A1 is located on the outer peripheral edge of the pad P. The central area A2 is arranged such that the center thereof coincides with the center O of the pad P in plan view. The positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
The gap ratio GR of this embodiment is (180 ° −2 × θ C ) /180°=80.6% with reference to the seventeenth embodiment.
The application area ratio AR in this embodiment is (0.15 2 × π × 3) / (0.5 2 × π) = 27%.
The maximum void area ratio of the present example was 3.8%.
実施例22におけるソルダペーストの塗布領域を図26を参照して説明する。なお、実施例22において、前記実施例6と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(4つ)の周辺領域A1と、当該複数の周辺領域A1の径方向内側に位置する中央領域A2とを有する。各周辺領域A1と中央領域A2はいずれも直径が0.3mmの円形状である。複数の周辺領域A1及び中央領域A2の相互の位置関係は、図26に示されている。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
本実施例の隙間割合GRは、前記実施例17を参照して、(180°-4×θC)/180°=61.2%である。
本実施例の塗布面積率ARは、(0.152×π×5)/(0.52×π)=45%である。
本実施例の最大ボイド面積率は、4.9%であった。 (Example 22)
The area to which the solder paste is applied in Example 22 will be described with reference to FIG. In the twenty-second embodiment, only the configuration different from the sixth embodiment will be described below, and the description of the other configurations will be omitted.
The application region T includes a plurality (four) of peripheral regions A1 arranged at intervals G in the circumferential direction around the center O of the pad P, and a central region A2 located radially inward of the peripheral regions A1. And Each of the peripheral area A1 and the central area A2 has a circular shape with a diameter of 0.3 mm. The mutual positional relationship between the plurality of peripheral areas A1 and the central area A2 is shown in FIG.
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
The gap ratio GR of the present embodiment is (180 ° −4 × θ C ) /180°=61.2% with reference to the seventeenth embodiment.
The application area ratio AR of this embodiment is (0.15 2 × π × 5) / (0.5 2 × π) = 45%.
The maximum void area ratio in this example was 4.9%.
実施例17~22の最大ボイド面積率VRは、全て比較例より低くなった。このため、実施例17~22のいずれにおいても、生じたボイドの大きさを抑制できたことが判る。
ボイドの大きさが抑制できた原因を以下に検討する。まず、周辺領域A1や中央領域A2が比較例の塗布領域よりも小さいため、フラックスの樹脂成分等が早期に溶融はんだ内から排出されやすいことは、実施例1~5と同様であると考えられる。
また、実施例17~22では全て中央領域A2を有しているが、中央領域A2に塗布されたソルダペースト内のはんだ粉末は、溶融後径方向外側に向けて流動する。なお、パッドPの中心Oから径方向外側に向けて開口する、複数の周辺領域A1の間の隙間の、パッドPの全周に対する割合を隙間割合GRとして算出し、実施例17~22のいずれの実施例でも中心Oから径方向外側に向けて間隔Gを介して開口していることが判った。このため、中央領域A2からの溶融はんだは間隔Gを通って適切に径方向外側に流動することができ、これによりフラックスの樹脂成分等を径方向外側に向かわせて排出できると考えられる。
実施例17~22において、中央領域A2の面積は、各周辺領域A1の面積の44.4%以上278%以下であった。 (Study of Examples 17 to 22)
The maximum void area ratios VR of Examples 17 to 22 were all lower than those of Comparative Examples. For this reason, it can be seen that in all of Examples 17 to 22, the size of the generated void could be suppressed.
The reason why the size of the void could be suppressed will be discussed below. First, since the peripheral region A1 and the central region A2 are smaller than the application region of the comparative example, it is considered that the resin component of the flux is easily discharged from the molten solder early as in the first to fifth embodiments. .
In addition, although Examples 17 to 22 all have the central region A2, the solder powder in the solder paste applied to the central region A2 flows radially outward after melting. The ratio of the gap between the plurality of peripheral regions A1 opening radially outward from the center O of the pad P with respect to the entire circumference of the pad P is calculated as the gap ratio GR. It was also found that in the embodiment of the present invention, the opening was provided from the center O toward the outside in the radial direction with an interval G therebetween. For this reason, it is considered that the molten solder from the central region A2 can appropriately flow radially outward through the gap G, and thereby the resin component of the flux can be discharged radially outward.
In Examples 17 to 22, the area of the central area A2 was 44.4% or more and 278% or less of the area of each peripheral area A1.
実施例23におけるソルダペーストの塗布領域を図27を参照して説明する。
実施例23では、基板BにおけるパッドP内に非塗布領域Nを形成するように、パッドP内に少なくとも一部が位置する塗布領域Tにソルダペーストが塗布されている。塗布領域Tは、パッドPの中心O回りの周方向に間隔Gをあけて配置された複数(2つ)の周辺領域A1を有する。2つの周辺領域A1は、径方向内側の一部で互いに接して配置されている。本実施例では、2つの周辺領域A1の接触箇所は平面視で中心Oと同一の位置に配置されている。各周辺領域A1の形状は、中心Oに頂点が位置し、頂角が90°である直角二等辺三角形である。各周辺領域A1の底辺(前記頂点に対向する辺)の長さは1.0mmである。また、2つの周辺領域A1の底辺間の距離も1.0mmである。各周辺領域A1の周方向の幅が、パッドPの中心Oから径方向外側に向かうに従い漸次拡大している。
複数の周辺領域A1は、周方向に等間隔で配置されている。なお、複数の周辺領域A1が、周方向に等間隔で配置されずともよい。
複数の周辺領域A1は、パッドPの外縁に重なって配置されている。すなわち、各周辺領域A1の一部は、パッドPの径方向外側に位置している。なお、複数の周辺領域A1が、全てパッドP内に配置される構成であってもよい。
本実施例の隙間割合GRは、50%である。
本実施例の塗布面積率ARは、(1.02/2)/(0.52×π)=63.7%である。
本実施例の最大ボイド面積率は、12.5%であった。 (Example 23)
The area to which the solder paste is applied in Example 23 will be described with reference to FIG.
In the
The plurality of peripheral regions A1 are arranged at equal intervals in the circumferential direction. Note that the plurality of peripheral regions A1 may not be arranged at equal intervals in the circumferential direction.
The plurality of peripheral areas A1 are arranged so as to overlap the outer edge of the pad P. That is, a part of each peripheral area A1 is located radially outside the pad P. Note that the configuration may be such that the plurality of peripheral regions A1 are all arranged in the pad P.
The gap ratio GR of the present embodiment is 50%.
The application area ratio AR in this embodiment is (1.0 2 /2)/(0.5 2 × π) = 63.7%.
The maximum void area ratio of the present example was 12.5%.
実施例24におけるソルダペーストの塗布領域を図28を参照して説明する。なお、実施例24において、前記実施例23と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
各周辺領域A1の底辺の長さは1.3mmである。また、2つの周辺領域A1の底辺間の距離も1.3mmである。
本実施例の塗布面積率ARは、(1.32/2)/(0.52×π)=107.6%である。
本実施例の最大ボイド面積率は、14.6%であった。 (Example 24)
The application area of the solder paste in Example 24 will be described with reference to FIG. In the twenty-fourth embodiment, only the configuration different from that of the twenty-third embodiment will be described below, and the description of the other configurations will be omitted.
The length of the base of each peripheral area A1 is 1.3 mm. The distance between the bases of the two peripheral regions A1 is also 1.3 mm.
The application area ratio AR in this embodiment is (1.3 2 /2)/(0.5 2 × π) = 107.6%.
The maximum void area ratio in this example was 14.6%.
実施例23,24の最大ボイド面積率VRは、全て比較例より低くなった。このため、実施例23,24のいずれにおいても、生じたボイドの大きさを抑制できたことが判る。
ボイドの大きさが抑制できた原因を以下に検討する。まず、周辺領域A1が比較例の塗布領域よりも小さいため、フラックスの樹脂成分等が早期に溶融はんだ内から排出されやすいことは、実施例1~5と同様であると考えられる。
また、実施例23,24は中央領域を有していないが、周辺領域A1の径方向内側部分はパッドPの中央部に達している。このため、周辺領域A1の径方向内側部分に塗布されたソルダペースト内のはんだ粉末は、溶融後径方向外側に向けて紙面左右方向に流動する場合がある。なお、隙間割合GRとして算出したことで、実施例23,24のいずれの実施例でも中心Oから径方向外側に向けて間隔Gを介して開口していることが判った。このため、周辺領域A1の径方向内側部分からの溶融はんだは間隔Gを通って適切に径方向外側に流動することができ、これによりフラックスの樹脂成分等を径方向外側に向かわせて排出できると考えられる。 (Study of Examples 23 and 24)
The maximum void area ratios VR of Examples 23 and 24 were all lower than those of Comparative Examples. Therefore, it can be seen that in each of Examples 23 and 24, the size of the generated void could be suppressed.
The reason why the size of the void could be suppressed will be discussed below. First, since the peripheral region A1 is smaller than the application region of the comparative example, it is considered that the resin component of the flux is easily discharged from the molten solder at an early stage, as in the case of Examples 1 to 5.
Although Examples 23 and 24 do not have a central area, the radially inner part of the peripheral area A1 reaches the central part of the pad P. For this reason, the solder powder in the solder paste applied to the radially inner portion of the peripheral region A1 may flow in the lateral direction on the paper toward the radially outer side after melting. In addition, by calculating the gap ratio GR, it was found that in each of the
実施例23,24には以下の変形例が考えられる。
これらの実施例では2つの周辺領域A1が設けられているが、周辺領域A1の数は3以上でもよい。この場合、各周辺領域A1の周方向の幅が径方向外側に向かうに従い拡大する割合を小さくしてもよい。また、2つの周辺領域A1の接触箇所が平面視でパッドPの中心Oと異なる位置に配置されてもよい。 (Modifications of Embodiments 23 and 24)
The following modifications are conceivable for the
In these embodiments, two peripheral areas A1 are provided, but the number of peripheral areas A1 may be three or more. In this case, the rate of expansion in the circumferential direction of each peripheral region A1 toward the outside in the radial direction may be reduced. Further, the contact point between the two peripheral regions A1 may be arranged at a position different from the center O of the pad P in plan view.
実施例25におけるソルダペーストの塗布領域を図29を参照して説明する。
実施例25では、基板BにおけるパッドP内に非塗布領域Nを形成するように、パッドP内に少なくとも一部が位置する塗布領域Tにソルダペーストが塗布されている。塗布領域Tは、パッドPの中心Oを含み且つ一方向(本実施例では紙面左右方向)に延びて配置された延在領域A3を有する。延在領域A3の平面視形状は矩形であって、長手方向の長さが1.3mm、短手方向の幅が0.3mmである。
延在領域A3は、パッドPの外縁に重なって配置されている。すなわち、延在領域A3の一部は、パッドPの径方向外側に位置している。本実施例では、延在領域A3の長手方向両端部のいずれもが、パッドPの径方向外側に位置している。なお、延在領域A3が全てパッドP内に配置される構成であってもよいし、延在領域A3の長手方向の一端部のみがパッドPの径方向外側に位置してもよい。
本実施例では、延在領域A3がパッドPの径方向外側まで達しているため、隙間割合GRは算出不可能である。
本実施例の塗布面積率ARは、(1.3×0.3)/(0.52×π)=49.7%である。
本実施例の最大ボイド面積率は、17.5%であった。 (Example 25)
The application area of the solder paste in the twenty-fifth embodiment will be described with reference to FIG.
In the twenty-fifth embodiment, the solder paste is applied to the application region T at least partially located in the pad P so as to form the non-application region N in the pad P of the substrate B. The application region T includes an extension region A3 that includes the center O of the pad P and extends in one direction (in the present embodiment, the left-right direction in the drawing). The planar shape of the extension region A3 is rectangular, the length in the longitudinal direction is 1.3 mm, and the width in the lateral direction is 0.3 mm.
The extension region A3 is arranged so as to overlap the outer edge of the pad P. That is, a part of the extension region A3 is located radially outside the pad P. In the present embodiment, both longitudinal ends of the extension region A3 are located radially outside the pad P. Note that the configuration may be such that the entire extension region A3 is arranged in the pad P, or only one end in the longitudinal direction of the extension region A3 may be located radially outside the pad P.
In the present embodiment, the gap ratio GR cannot be calculated because the extension region A3 reaches the outside of the pad P in the radial direction.
The application area ratio AR in this embodiment is (1.3 × 0.3) / (0.5 2 × π) = 49.7%.
The maximum void area ratio of the present example was 17.5%.
実施例26におけるソルダペーストの塗布領域を図30を参照して説明する。なお、実施例26において、前記実施例25と異なる構成のみを以下に説明し、それ以外の構成の説明は省略する。
塗布領域Tは、延在領域A3の長手方向に交差する方向において延在領域A3を挟んで配置された複数(2つ)の側方領域A4をさらに有する。各側方領域A4の平面視形状は、一辺の長さが0.3mmの正方形であって、その一辺は紙面上下方向に延びている。複数の側方領域A4及び延在領域A3の相互の位置関係は、図30に示されている。
延在領域A3と各側方領域A4との対向辺a,bは、互いに平行している。なお、対向辺a,bが、互いに非平行であってもよい。
複数の側方領域A4は、パッドPの外縁に重なって配置されている。すなわち、各側方領域A4の一部は、パッドPの径方向外側に位置している。なお、複数の側方領域A4が、全てパッドP内に配置される構成であってもよい。
本実施例の塗布面積率ARは、(1.3×0.3+0.32×2)/(0.52×π)=72.6%である。
本実施例の最大ボイド面積率は、15.0%であった。 (Example 26)
The solder paste application region in the twenty-sixth embodiment will be described with reference to FIG. In the twenty-sixth embodiment, only the configuration different from that of the twenty-fifth embodiment is described below, and the description of the other configurations is omitted.
The application region T further includes a plurality (two) of side regions A4 arranged so as to sandwich the extension region A3 in a direction intersecting the longitudinal direction of the extension region A3. The planar shape of each side area A4 is a square having a side of 0.3 mm in length, and one side of the side area A4 extends in the vertical direction on the paper. The mutual positional relationship between the plurality of side regions A4 and the extended region A3 is shown in FIG.
Opposite sides a and b of the extension region A3 and the side regions A4 are parallel to each other. The opposite sides a and b may be non-parallel to each other.
The plurality of side areas A4 are arranged so as to overlap the outer edge of the pad P. That is, a part of each side area A4 is located radially outside the pad P. Note that the configuration may be such that the plurality of side regions A4 are all arranged in the pad P.
The application area ratio AR of this embodiment is (1.3 × 0.3 + 0.3 2 × 2) / (0.5 2 × π) = 72.6%.
The maximum void area ratio in the present example was 15.0%.
実施例25,26の最大ボイド面積率VRは、全て比較例より低くなった。このため、実施例25,26のいずれにおいても、生じたボイドの大きさを抑制できたことが判る。
ボイドの大きさが抑制できた原因を以下に検討すると、延在領域A3や側方領域A4が比較例の塗布領域よりも小さいため、フラックスの樹脂成分等が早期に溶融はんだ内から排出されやすいことは、実施例1~5と同様であると考えられる。 (Study of Examples 25 and 26)
The maximum void area ratios VR of Examples 25 and 26 were all lower than those of Comparative Examples. Therefore, it can be seen that in each of Examples 25 and 26, the size of the generated void could be suppressed.
When the cause of the suppression of the size of the voids is examined below, since the extending region A3 and the side region A4 are smaller than the application region of the comparative example, the resin component of the flux is easily discharged from the molten solder at an early stage. This is considered to be the same as in Examples 1 to 5.
実施例25,26には以下の変形例が考えられる。
例えば、複数の側方領域A4の数を3以上にしてもよい。 (Modifications of Embodiments 25 and 26)
The following modifications can be considered for the embodiments 25 and 26.
For example, the number of the plurality of side regions A4 may be three or more.
本発明の第4の態様は、塗布対象物へソルダペーストを塗布するためのマスクであって、塗布対象物における接合領域内に非塗布領域を形成するように前記接合領域内に少なくとも一部が位置する塗布領域と相当する位置に開口が形成され、前記開口は、前記接合領域の中心回りの周方向に間隔をあけて配置された複数の周辺開口を有する。
本発明の第5の態様は、塗布対象物へソルダペーストを塗布するためのマスクであって、塗布対象物における接合領域内に非塗布領域を形成するように前記接合領域内に少なくとも一部が位置する塗布領域と相当する位置に開口が形成され、前記開口は、前記接合領域の中心を含み且つ一方向に延びて配置された延在開口を有する。 Further, the present invention may include the following aspects.
A fourth aspect of the present invention is a mask for applying a solder paste to an application object, at least a part of which is formed in the bonding region so as to form a non-application region in the bonding region of the application object. An opening is formed at a position corresponding to the located application region, and the opening has a plurality of peripheral openings arranged at intervals in a circumferential direction around a center of the joining region.
According to a fifth aspect of the present invention, there is provided a mask for applying a solder paste to an object to be applied, wherein at least a part of the mask is formed in the joining region so as to form a non-application region in the joining region of the object. An opening is formed at a position corresponding to the located application region, and the opening has an extension opening including the center of the joining region and extending in one direction.
A11 第1領域
A12 第2領域
A2 中央領域
A3 延在領域
A4 側方領域
B 基板(塗布対象物)
N 非塗布領域
O 中心
P パッド(接合領域)
S ソルダペースト
T 塗布領域 A1 Peripheral area A11 First area A12 Second area A2 Central area A3 Extended area A4 Side area B Substrate (object to be coated)
N Non-coating area O Center P Pad (joining area)
S Solder paste T Application area
Claims (25)
- 塗布対象物へのソルダペーストの塗布方法であって、
塗布対象物における接合領域内に非塗布領域を形成するように、前記接合領域内に少なくとも一部が位置する塗布領域にソルダペーストを塗布する工程を備え、
前記塗布領域は、前記接合領域の中心回りの周方向に間隔をあけて配置された複数の周辺領域を有する、ソルダペーストの塗布方法。 A method of applying a solder paste to an object to be applied,
A step of applying a solder paste to an application region at least partially located in the bonding region so as to form a non-application region in a bonding region of the application target,
The method of applying a solder paste, wherein the application region has a plurality of peripheral regions arranged at intervals in a circumferential direction around a center of the bonding region. - 前記複数の周辺領域は、前記接合領域の中心を挟んで互いに対向して配置されている、請求項1に記載のソルダペーストの塗布方法。 The solder paste application method according to claim 1, wherein the plurality of peripheral regions are arranged to face each other with the center of the bonding region interposed therebetween.
- 前記複数の周辺領域は、当該複数の周辺領域の対向方向と交差する方向に延びて配置されている、請求項2に記載のソルダペーストの塗布方法。 The method according to claim 2, wherein the plurality of peripheral regions are arranged so as to extend in a direction intersecting a direction in which the plurality of peripheral regions oppose each other.
- 前記複数の周辺領域間の隙間は、前記接合領域の最大径の30%以上70%以下である、請求項2または3に記載のソルダペーストの塗布方法。 4. The solder paste application method according to claim 2, wherein a gap between the plurality of peripheral regions is 30% or more and 70% or less of a maximum diameter of the joining region. 5.
- 前記複数の周辺領域間の隙間は、前記複数の周辺領域の対向方向における各周辺領域の幅の85.7%以上200%以下である、請求項2から4のいずれか一項に記載のソルダペーストの塗布方法。 5. The solder according to claim 2, wherein a gap between the plurality of peripheral regions is equal to or greater than 85.7% and equal to or less than 200% of a width of each peripheral region in a direction facing the plurality of peripheral regions. Paste application method.
- 前記複数の周辺領域の数が、2から6である、請求項1に記載のソルダペーストの塗布方法。 The method according to claim 1, wherein the number of the plurality of peripheral regions is two to six.
- 前記複数の周辺領域は、前記周方向に等間隔で配置されている、請求項1または6に記載のソルダペーストの塗布方法。 7. The method according to claim 1, wherein the plurality of peripheral regions are arranged at equal intervals in the circumferential direction. 8.
- 前記複数の周辺領域は、前記周方向の長さが異なる第1領域及び第2領域を有し、
前記第1領域及び及び前記第2領域は、前記周方向で交互に配置されている、請求項1,6または7に記載のソルダペーストの塗布方法。 The plurality of peripheral regions include a first region and a second region having different circumferential lengths,
The method of claim 1, wherein the first region and the second region are alternately arranged in the circumferential direction. - 前記周方向に隣り合う前記複数の周辺領域の対向辺は、互いに平行している、請求項1から8のいずれか一項に記載のソルダペーストの塗布方法。 The solder paste application method according to any one of claims 1 to 8, wherein opposing sides of the plurality of peripheral regions adjacent in the circumferential direction are parallel to each other.
- 前記塗布領域は、前記複数の周辺領域の径方向内側に位置する中央領域をさらに有する、請求項1から9のいずれか一項に記載のソルダペーストの塗布方法。 10. The method of applying a solder paste according to claim 1, wherein the application region further has a central region located radially inward of the plurality of peripheral regions. 11.
- 前記中央領域と各周辺領域との対向辺は、互いに平行している、請求項10に記載のソルダペーストの塗布方法。 The solder paste application method according to claim 10, wherein opposing sides of the central region and each peripheral region are parallel to each other.
- 前記中央領域の面積は、各周辺領域の面積の44.4%以上278%以下である、請求項10または11に記載のソルダペーストの塗布方法。 The solder paste application method according to claim 10 or 11, wherein the area of the central region is not less than 44.4% and not more than 278% of the area of each peripheral region.
- 前記複数の周辺領域は、一部で互いに接して配置されている、請求項1に記載のソルダペーストの塗布方法。 The method according to claim 1, wherein the plurality of peripheral regions are partially arranged in contact with each other.
- 各周辺領域の前記周方向の幅が、前記接合領域の中心から径方向外側に向かうに従い漸次拡大している、請求項13に記載のソルダペーストの塗布方法。 14. The method of applying a solder paste according to claim 13, wherein the circumferential width of each peripheral region gradually increases from the center of the joining region toward the outside in the radial direction.
- 前記接合領域の中心から径方向外側に向けて開口する、前記複数の周辺領域の間の隙間の、前記接合領域の全周に対する割合が、11.5%以上である、請求項1から14のいずれか一項に記載のソルダペーストの塗布方法。 The ratio of a gap between the plurality of peripheral regions, which opens radially outward from the center of the bonding region, to the entire periphery of the bonding region is 11.5% or more. A method for applying the solder paste according to any one of the preceding claims.
- 前記複数の周辺領域は、前記接合領域の外縁に重なって配置されている、請求項1から15のいずれか一項に記載のソルダペーストの塗布方法。 The method according to any one of claims 1 to 15, wherein the plurality of peripheral regions are arranged so as to overlap an outer edge of the bonding region.
- 前記複数の周辺領域は、前記接合領域内に配置されている、請求項1から15のいずれか一項に記載のソルダペーストの塗布方法。 The method according to any one of claims 1 to 15, wherein the plurality of peripheral regions are arranged in the bonding region.
- 塗布対象物へのソルダペーストの塗布方法であって、
塗布対象物における接合領域内に非塗布領域を形成するように、前記接合領域内に少なくとも一部が位置する塗布領域にソルダペーストを塗布する工程を備え、
前記塗布領域は、前記接合領域の中心を含み且つ一方向に延びて配置された延在領域を有する、ソルダペーストの塗布方法。 A method of applying a solder paste to an object to be applied,
A step of applying a solder paste to an application region at least partially located in the bonding region so as to form a non-application region in a bonding region of the application target,
The solder paste application method, wherein the application area includes an extension area including the center of the bonding area and extending in one direction. - 前記延在領域は、前記接合領域の外縁に重なって配置されている、請求項18に記載のソルダペーストの塗布方法。 19. The method for applying a solder paste according to claim 18, wherein the extension region is disposed so as to overlap an outer edge of the joining region.
- 前記延在領域は、前記接合領域内に配置されている、請求項18に記載のソルダペーストの塗布方法。 19. The method for applying a solder paste according to claim 18, wherein the extension region is disposed in the bonding region.
- 前記塗布領域は、前記延在領域の長手方向に交差する方向において前記延在領域を挟んで配置された複数の側方領域をさらに有する、請求項18から20のいずれか一項に記載のソルダペーストの塗布方法。 The solder according to any one of claims 18 to 20, wherein the application region further has a plurality of side regions arranged so as to sandwich the extension region in a direction intersecting the longitudinal direction of the extension region. How to apply the paste.
- 前記延在領域と各側方領域との対向辺は、互いに平行している、請求項21に記載のソルダペーストの塗布方法。 22. The method for applying a solder paste according to claim 21, wherein opposing sides of the extension region and the side regions are parallel to each other.
- 前記複数の側方領域は、前記接合領域の外縁に重なって配置されている、請求項21または22に記載のソルダペーストの塗布方法。 23. The method for applying a solder paste according to claim 21, wherein the plurality of side regions are arranged so as to overlap an outer edge of the bonding region.
- 前記複数の側方領域は、前記接合領域内に配置されている、請求項21または22に記載のソルダペーストの塗布方法。 23. The method of applying a solder paste according to claim 21, wherein the plurality of side regions are arranged in the bonding region.
- 請求項1から24のいずれか一項に記載のソルダペーストの塗布方法に用いられるマスクであって、
前記塗布領域に相当する位置に開口が形成されたマスク。 A mask used in the method for applying a solder paste according to any one of claims 1 to 24,
A mask having an opening formed at a position corresponding to the application region.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020541277A JP7438116B2 (en) | 2018-09-05 | 2019-09-04 | Solder paste application method and mask |
KR1020217009697A KR20210052527A (en) | 2018-09-05 | 2019-09-04 | Solder paste application method and mask |
CN201980069254.XA CN112913339A (en) | 2018-09-05 | 2019-09-04 | Method for coating solder paste and mask |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018-166395 | 2018-09-05 | ||
JP2018166395 | 2018-09-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2020050330A1 true WO2020050330A1 (en) | 2020-03-12 |
Family
ID=69722428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2019/034832 WO2020050330A1 (en) | 2018-09-05 | 2019-09-04 | Method of applying solder paste and mask |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP7438116B2 (en) |
KR (1) | KR20210052527A (en) |
CN (1) | CN112913339A (en) |
WO (1) | WO2020050330A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0712237U (en) * | 1993-08-03 | 1995-02-28 | 住友ベークライト株式会社 | Metal mask for solder paste printing |
JP2000252617A (en) * | 1999-03-01 | 2000-09-14 | Ngk Spark Plug Co Ltd | Manufacture of wiring board |
JP2004314601A (en) * | 2003-03-31 | 2004-11-11 | Sanyo Electric Co Ltd | Metal mask and lead-free solder paste printing method using it |
US20050061854A1 (en) * | 2003-09-19 | 2005-03-24 | Advanced Semiconductor Engineering, Inc. | Method for mounting a semiconductor package onto PCB |
JP2017139337A (en) * | 2016-02-04 | 2017-08-10 | Necプラットフォームズ株式会社 | Metal mask |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100329490B1 (en) * | 1996-05-29 | 2002-08-13 | 로무 가부시키가이샤 | Method of mounting terminal to circuit board and circuit board |
JP2001077521A (en) | 1999-08-31 | 2001-03-23 | Senju Metal Ind Co Ltd | Method and device forsolder paste printing |
JP4735332B2 (en) * | 2006-03-01 | 2011-07-27 | トヨタ自動車株式会社 | Vehicle side structure |
-
2019
- 2019-09-04 KR KR1020217009697A patent/KR20210052527A/en not_active Application Discontinuation
- 2019-09-04 WO PCT/JP2019/034832 patent/WO2020050330A1/en active Application Filing
- 2019-09-04 JP JP2020541277A patent/JP7438116B2/en active Active
- 2019-09-04 CN CN201980069254.XA patent/CN112913339A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0712237U (en) * | 1993-08-03 | 1995-02-28 | 住友ベークライト株式会社 | Metal mask for solder paste printing |
JP2000252617A (en) * | 1999-03-01 | 2000-09-14 | Ngk Spark Plug Co Ltd | Manufacture of wiring board |
JP2004314601A (en) * | 2003-03-31 | 2004-11-11 | Sanyo Electric Co Ltd | Metal mask and lead-free solder paste printing method using it |
US20050061854A1 (en) * | 2003-09-19 | 2005-03-24 | Advanced Semiconductor Engineering, Inc. | Method for mounting a semiconductor package onto PCB |
JP2017139337A (en) * | 2016-02-04 | 2017-08-10 | Necプラットフォームズ株式会社 | Metal mask |
Also Published As
Publication number | Publication date |
---|---|
JPWO2020050330A1 (en) | 2021-09-24 |
JP7438116B2 (en) | 2024-02-26 |
KR20210052527A (en) | 2021-05-10 |
CN112913339A (en) | 2021-06-04 |
TW202034752A (en) | 2020-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101156819B1 (en) | Methods of fluxless micro-piercing of solder balls, and resulting devices | |
WO2010101236A1 (en) | Bump, method for forming bump, and method for mounting substrate having the bump formed thereon | |
WO2006067827A1 (en) | Solder precoating method and work for electronic device | |
JP2007116145A (en) | Method for manufacturing circuit substrate equipped with plural solder connection parts on upper surface thereof | |
JP4696110B2 (en) | Electronic component mounting method and electronic component mounting apparatus | |
US9674952B1 (en) | Method of making copper pillar with solder cap | |
WO2020050330A1 (en) | Method of applying solder paste and mask | |
JP2023153935A (en) | solder paste | |
JP2014045190A (en) | Method for manufacturing printed-circuit board | |
JP2009010302A (en) | Method for forming solder paste layer | |
TWI833798B (en) | Application method of solder paste and mask | |
JP5560713B2 (en) | Electronic component mounting method, etc. | |
WO2022168209A1 (en) | Solder paste, method for forming solder bumps, and method for producing member with solder bumps | |
JP6124032B2 (en) | Mounting structure and manufacturing method of mounting structure | |
JPH0846349A (en) | Soldering | |
JP2018006465A (en) | Method of manufacturing printed wiring board, and mask for screen printing | |
KR101145076B1 (en) | Method for producing electronic part unit | |
JP4590783B2 (en) | Method for forming solder balls | |
JP7069404B2 (en) | Printed wiring board and electronic equipment | |
WO2022168207A1 (en) | Solder paste, method for forming solder bumps, and method for manufacturing member provided with solder bumps | |
JP4381795B2 (en) | Electronic component mounting method | |
JP4102538B2 (en) | Electronic circuit board repair method | |
TW202147472A (en) | Method for forming bump electrode substrate | |
US20090111299A1 (en) | Surface Mount Array Connector Leads Planarization Using Solder Reflow Method | |
JP2009111263A (en) | Rework method of electronic component |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 19857423 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2020541277 Country of ref document: JP Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20217009697 Country of ref document: KR Kind code of ref document: A |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 19857423 Country of ref document: EP Kind code of ref document: A1 |