WO2020049811A1 - 表示装置、及び表示装置の製造方法 - Google Patents

表示装置、及び表示装置の製造方法 Download PDF

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Publication number
WO2020049811A1
WO2020049811A1 PCT/JP2019/021314 JP2019021314W WO2020049811A1 WO 2020049811 A1 WO2020049811 A1 WO 2020049811A1 JP 2019021314 W JP2019021314 W JP 2019021314W WO 2020049811 A1 WO2020049811 A1 WO 2020049811A1
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Prior art keywords
bank
display device
layer
region
inorganic sealing
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PCT/JP2019/021314
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English (en)
French (fr)
Japanese (ja)
Inventor
圭輔 原田
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株式会社ジャパンディスプレイ
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Publication of WO2020049811A1 publication Critical patent/WO2020049811A1/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/22—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers

Definitions

  • the present disclosure relates to a display device and a method for manufacturing the display device.
  • the display region may be covered with a sealing layer in order to prevent moisture and dust from penetrating into the plurality of self-luminous elements formed in the display region.
  • the sealing layer has a three-layer structure including two inorganic sealing layers formed of an inorganic material, and an organic sealing layer formed of an organic material disposed therebetween. ing.
  • the organic sealing layer is disposed in the display area, and is formed of a material having low viscosity in order to improve the flatness of the display area.
  • a first outside bank which rises upward from the substrate and surrounds the outside of the display area, and further outside the first outside bank.
  • the second and third outer banks are formed.
  • the uppermost inorganic sealing layer and the inorganic sealing layer immediately thereunder cover the display region including the organic sealing layer and the display region including the first to third outer banks, and are separated from each other outside the display region. In contact.
  • These inorganic sealing layers are formed by CVD (Chemical Vapor Deposition).
  • the inorganic sealing layer In the display device, there is a region where it is not preferable to form the inorganic sealing layer by CVD. For example, in a region where a control circuit board (flexible printed circuit board: FPC) is attached to wiring provided below the plurality of light emitting elements outside the display region, an inorganic sealing layer which is an upper insulating layer is sputtered. It is necessary to remove by such as. Further, for example, in a manufacturing method of cutting out a plurality of display devices by cutting a single laminated structure including a plurality of product regions with a laser, a cutter, or the like, an inorganic sealing layer remains at a cutting line when cutting.
  • a control circuit board flexible printed circuit board: FPC
  • the inventors are studying a manufacturing method (mask CVD) in which a region where an inorganic sealing layer is unnecessary is previously covered with a mask when the inorganic sealing layer is formed by CVD.
  • a manufacturing method mask CVD
  • the inorganic material enters through the gap, and the inorganic sealing layer may be formed in a region covered with the mask. . That is, the inorganic sealing layer may be formed in a region where the inorganic sealing layer is unnecessary in the display device.
  • One object of the present invention is to prevent an inorganic sealing layer from being formed in a region where an inorganic sealing layer is unnecessary in a display device.
  • a display device includes an element substrate having a display region in which a plurality of self-luminous elements are formed, an outer bank formed outside the display region and having a convex cross section, and An inorganic sealing layer that covers the self-light-emitting element, wherein the inorganic sealing layer is formed on the side surface of the outer bank on the display region side, and is not formed on at least a part of the top of the outer bank. It is characterized by the following.
  • the method for manufacturing a display device includes a step of preparing an element substrate having a plurality of self-luminous elements formed in a display region, and forming an outer bank formed outside the display region and having a convex cross section.
  • An outer bank forming step a mask step of disposing a mask having an opening on the outer bank, and, after the masking step, an inorganic sealing layer covering the plurality of self-luminous elements, And forming an inorganic sealing layer on the side surface on the display region side except for at least a part of the top of the outer bank.
  • FIG. 1 is a schematic plan view of a display device according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a pixel of the display device according to the embodiment of the present invention.
  • FIG. 3 is a schematic sectional view of the display device taken along the line III-III in FIG. 1. It is a typical sectional view of the display concerning an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. 1.
  • FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. 1. It is a schematic plan view in a manufacturing process of a display concerning an embodiment of the present invention.
  • FIG. 1 is a schematic plan view of the display device according to the present embodiment.
  • the display device 1 is formed by stacking a touch sensor 50, a polarizing plate 60, and a counter substrate 3, which will be described later, on an element substrate 2 forming a plurality of self-luminous elements.
  • the display device 1 includes a display region 5 in which a plurality of pixels 100 are provided in a matrix, which is a region for displaying an image, a frame region 6 which is a region outside the display region 5, and a frame region 6.
  • the curved area 7 and the attachment area 8 are areas that are apart from the display area 5.
  • An IC driver chip is mounted on a circuit board attached to the attachment area 8. The IC driver chip may not be mounted on the circuit board, and may be mounted on the mounting area 8 together with the circuit board.
  • FIG. 2 is a circuit diagram of the pixel 100 of the display device 1.
  • the display device 1 displays an image by controlling each pixel provided in a matrix in the display area 5 of the element substrate 2 with an IC driver chip.
  • the IC driver chip transmits a video signal and a scanning signal to each pixel 100 via a scanning signal line 101 and a video signal line 102, respectively.
  • the scanning signal line 101 is a common wiring for the transistors of the pixels 100 arranged in one row
  • the video signal line 102 and the power supply line 103 are common wirings for the pixels 100 arranged in one column.
  • a power supply voltage is applied to the power supply line 103.
  • the scanning signal line 101 is electrically connected to the gate (electrode 202: FIG.
  • the pixel transistor SST and the driving transistor DRT are, for example, p-channel or n-channel field effect transistors.
  • the anode (lower electrode 31: FIG. 3) of the self-luminous element OLED that emits light of each pixel 100 is electrically connected to the drain or source (electrode 304: FIG. 4) of the driving transistor DRT. Further, a ground potential or a negative potential is input to the cathode (upper electrode 33: FIG. 3) of the self-luminous element OLED.
  • FIGS. 3 to 6 are schematic cross-sectional views of the display device 1.
  • 3 and 5 show cross sections in the display area 5 and the frame area 6, and
  • FIG. 4 shows a cross section in the display area 5.
  • FIG. 6 shows a cross section of the frame region 6, the curved region 7, and the attachment region 8.
  • FIG. 3 shows a cross section taken along line III-III extending in the lateral direction in FIG.
  • FIG. 5 shows a cross section taken along a line VV extending in the vertical direction in FIG. 1, and shows a cross section on the side in contact with the curved region 7 and the mounting region 8.
  • FIG. 6 shows a cross section taken along the line VI-VI extending in the vertical direction in FIG.
  • the display device 1 has a structure in which an element substrate 2 and a counter substrate 3 are bonded together with a plurality of layers for realizing display of an image in the display area 5 interposed therebetween.
  • the element substrate 2 is made of a flexible insulating material such as polyimide, and is formed over the entire display area 5, frame area 6, curved area 7, and mounting area 8.
  • the opposing substrate 3 is made of a transparent material and is formed over the display area 5 and the frame area 6.
  • the counter substrate 3 may be formed of, for example, a hard material such as resin or glass, or may be formed of a flexible insulating material like the element substrate 2.
  • a circuit layer 10, a passivation layer 11, a planarization layer 21, a bank 23, a lower electrode 31, a light emitting layer 34, and an upper electrode 35 are stacked. Further, a barrier structure 40 provided so as to be continuously mounted on the upper side of the upper electrode 35 is formed on the element substrate 2.
  • a touch sensor 50 and a protective layer 51 covering the touch sensor 50 are formed on the barrier structure 40, and a polarizing plate 60 is adhered on the touch sensor 50 by an adhesive layer 61.
  • the counter substrate 3 covers the upper side of the polarizing plate 60.
  • a plurality of pixel transistors SST and a plurality of drive transistors DRT are arranged in the circuit layer 10.
  • Each pixel transistor SST and each drive transistor DRT are arranged at positions respectively corresponding to a plurality of pixels 100 forming an image in the display area 5.
  • the pixel transistor SST includes a semiconductor 201, an electrode 202 serving as a gate of the pixel transistor SST, an electrode 203 serving as a source or a drain of the pixel transistor SST, and a capacitor electrode 204.
  • the driving transistor DRT includes a semiconductor 301, an electrode 302 that contributes as a gate of the driving transistor DRT, and electrodes 303 and 304 that contribute as a source or a drain of the driving transistor DRT.
  • the lower electrode 31 described later is connected to the electrode 304 of the driving transistor DRT.
  • the capacitor electrode 204 forms a storage capacitor Cs with the semiconductor 301 of the drive transistor DRT that overlaps in the vertical direction.
  • the circuit layer 10 has a plurality of insulating layers laminated on the element substrate 2.
  • the circuit layer 10 includes an undercoat layer 400 and first to fourth interlayer insulating films 401 to 404.
  • the undercoat layer 400 and the first to fourth interlayer insulating films 401 to 404 are formed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNy).
  • the undercoat layer 400 is disposed between the semiconductor 201 of the pixel transistor SST and the element substrate 2 and covers the element substrate 2.
  • the first interlayer insulating film 401 covers between the semiconductor 201 of the pixel transistor SST, the electrode 202, and the capacitor electrode 204.
  • the second and third interlayer insulating films 402 and 403 cover between the electrode 202 and the capacitor electrode 204 of the pixel transistor SST and the semiconductor 301 of the driving transistor DRT.
  • the fourth interlayer insulating film 404 covers between the semiconductor 301 of the driving transistor DRT and the electrode 302.
  • the passivation layer 11 is formed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNy), and is above the circuit layer 10 (more specifically, above the drive transistor DRT electrode 302). Is covered. Further, between a first intermediate bank 22a, which will be described later, and the planarization layer 21, the wiring 12a (see FIG. 3) and the wiring 12b (see FIG. 5) formed in the circuit layer 10 are exposed from the passivation layer 11. ing.
  • silicon oxide SiOx
  • SiNy silicon nitride
  • the circuit layer 10 is formed in the display area 5, the frame area 6, and the attachment area 8, but not in the curved area 7.
  • an insulating film 28 made of an organic insulating material such as resin is formed in the same layer as the circuit layer 10.
  • the insulating film 28 may be formed of a flexible material.
  • a wiring 80 exposed from the passivation layer 11 is formed.
  • the wiring 80 is in contact with the circuit layer 10 and is electrically connected to a circuit board (for example, FPC) mounted on the mounting area 8 or an IC driver chip.
  • a flattening layer 21 made of an organic insulating material such as a resin is laminated on the passivation layer 11.
  • a dam structure 22 is formed so as to surround the outside of the flattening layer 21. This is to prevent the later-described organic sealing layer 42 and protective layer 51 from overflowing to the end of the display device 1.
  • the dam structure 22 has a first intermediate bank 22a surrounding the outside of the planarizing layer 21 and a second intermediate bank 22b surrounding the outside. Both the cross section of the first intermediate bank 22a and the cross section of the second intermediate bank 22b are formed in a convex shape. By forming a double dam in the frame region 6 in this way, it is possible to more reliably prevent the organic sealing layer 42 from overflowing as compared with a case where a single dam is formed.
  • the first intermediate bank 22a and the second intermediate bank 22b are formed in the same layer as the flattening layer 21.
  • the first intermediate bank 22a and the second intermediate bank 22b may be formed of the same organic insulating material (for example, resin) as the flattening layer 21. Further, the first intermediate bank 22a and the second intermediate bank 22b are formed between the display area 5 and an outer bank 90 described later.
  • insulating films 26 and 27 made of an organic insulating material such as resin are formed in the same layer as the flattening layer 21 outside the dam structure 22.
  • the insulating film 26 is formed in the frame region 6, and the insulating film 27 covers the wiring 70 in the curved region 7.
  • an adjusting insulating film 29 made of an organic insulating material such as a resin is placed on the insulating film 27, on the insulating film 27, an adjusting insulating film 29 made of an organic insulating material such as a resin is placed.
  • the insulating films 27 and 29 may be formed of a flexible material.
  • the adjusting insulating film 29 is for adjusting the position of the wiring 70 in the entire insulating film.
  • a plurality of lower electrodes 31 made of a given conductive material are stacked on the planarization layer 21.
  • a contact hole CH is formed in the flattening layer 21, and a lower electrode 31 described later is connected to an electrode 304 constituting the drain or source of the driving transistor DRT through this hole.
  • the plurality of lower electrodes 31 are arranged at positions respectively corresponding to the plurality of pixels 100 when viewed in plan.
  • the plurality of lower electrodes 31 may be formed by forming a single conductive material on the upper side of the planarization layer 21 and separating the pixels 100 from each other by etching or the like.
  • the lower electrode 31 is configured as an anode.
  • a positive potential is input to the lower electrode 31 by the driving transistor DRT included in the circuit layer 10.
  • An upper electrode 35 described later is configured as a cathode (cathode), and receives a ground potential or a negative potential.
  • a conductive portion 32a (see FIG. 3) and a conductive portion 32b (see FIG. 5) made of a given conductive material are laminated.
  • the conductive portions 32a and 32b are formed in the same layer as the lower electrode 31.
  • the conductive portions 32a and 32b may be formed of the same conductive material as the lower electrode 31.
  • the conductive portions 32a and 32b are in contact with the wirings 12a and 12b on the same layer as the electrode 304 (see FIG. 4) on the passivation layer 11, respectively.
  • the conductive portions 32a and 32b are in contact with an upper electrode 35 described later.
  • a bank 23 made of an organic insulating material such as a resin is formed between the plurality of lower electrodes 31.
  • the bank 23 is arranged so as to surround the outer periphery of each pixel 100. More specifically, the bank 23 is provided so as to cover the periphery of each lower electrode 31 arranged at a position corresponding to each pixel 100 and to be mounted on an end of each lower electrode 31.
  • a supplementary layer 24 made of an organic insulating material such as resin is laminated on the first intermediate bank 22a in the frame region 6, a supplementary layer 24 made of an organic insulating material such as resin is laminated.
  • the supplementary layer 24 may be formed on the same layer as the bank 23. By stacking the supplementary layer 24 on the first intermediate bank 22a, the height of the first intermediate bank 22a is increased. By doing so, it is possible to more reliably prevent the later-described organic sealing layer 42 from overflowing as compared with the case where the supplementary layer 24 is not formed.
  • a light emitting layer 34 is stacked on the lower electrode 31 and the bank 23.
  • the light emitting layer 34 is formed over the entire display area 5 and is provided so as to be continuously mounted on the lower electrode 31 and the bank 23.
  • the light emitting layer 34 emits light from the plurality of pixels 100, and may include a hole injection layer, a hole transport layer, a hole block layer, an electron transport layer, and the like.
  • a plurality of self-luminous elements OLED each of which is formed on the element substrate 2 and emits light of the pixel 100, includes a plurality of lower electrodes 31, a light-emitting layer 34 covering these, and an upper electrode 35.
  • each layer disposed above the light emitting layer 34 is formed to be transparent or translucent.
  • the lower electrode 31 may include a material that reflects light, such as a metal (for example, silver (Ag)).
  • Light emitted from each of the plurality of regions may be colored by partially applying the light emitting layer 34 separately.
  • the light-emitting layer 34 is colored with a predetermined color (for example, three colors of red, green, and blue, and four colors obtained by adding white to each of the plurality of pixels 100).
  • a color filter that transmits light in a predetermined color for each of the plurality of pixels 100 may be provided above the light emitting layer 34.
  • An upper electrode 35 is laminated on the light emitting layer 34.
  • the upper electrode 35 is configured as an electrode common to all the pixels 100, is arranged over a part of the display area 5 and the frame area 6, and is provided so as to cover the entire area of the light emitting layer 34.
  • the upper electrode 35 may be formed of a transparent conductive material such as magnesium-silver (MgAg), which is a thin film material containing silver, or indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the lower electrode 31 is configured as an anode
  • the upper electrode 35 is configured as a cathode.
  • the upper electrode 35 is electrically connected to the conductive portions 32a and 32b and the wirings 12a and 12b.
  • a ground potential or a negative potential is input to the upper electrode 35 via the conductive portions 32a and 32b and the wirings 12a and 12b. Is done.
  • a barrier structure 40 for preventing moisture from entering the light emitting layer 34 and various electrodes is laminated on the upper electrode 35.
  • the barrier structure 40 covers a plurality of self-luminous elements OLED constituted by the plurality of lower electrodes 31, the light emitting layer 34, and the upper electrode 35 in the display area 5. Details of the barrier structure 40 will be described later.
  • a touch sensor 50 is stacked on the barrier structure 40 (more specifically, a second inorganic sealing layer 43 described later), and a protective layer 51 is further formed thereon.
  • the touch sensor 50 is, for example, a projection-type capacitive touch sensor, and detects whether or not a user's finger or the like approaches or touches the display area 5 and the position thereof.
  • the touch sensor 50 is formed over the entire display area 5 and is electrically connected to the wiring 13 exposed from the passivation layer 11 in the frame area 6.
  • the protection layer 51 is for protecting the touch sensor 50, and covers the entire area of the touch sensor 50 in the display area 5.
  • the protection layer 51 may be formed of an organic insulating material such as a resin.
  • An end portion of the protective layer 51 is formed between the first intermediate bank 22a and the second intermediate bank 22b having a convex cross section that forms the barrier structure 22, but is formed outside the barrier structure 22. Not.
  • An adhesive layer 61 (glue) is laid on the touch sensor 50 and the protective layer 51, and a polarizing plate 60 is attached thereon.
  • the polarizing plate 60 is for suppressing external light reflection in the display area 5, and is formed, for example, as a circular polarizing plate having a laminated structure of a ⁇ plate 60a and a linear polarizing plate 60b disposed thereon. You may.
  • the counter substrate 3 is attached on the polarizing plate 60.
  • An outer bank 90 having a convex cross section is formed in the frame region 6 outside the display region 5.
  • the outer bank 90 is formed at an end of the element substrate 2. More specifically, the outer bank 90 is formed continuously along the edge of the element substrate 2.
  • the outer bank 90 is formed in the regions 9a and 9c shown in FIG.
  • the element substrate 2 has a rectangular or substantially rectangular shape, and the area 9a is an area extending along an end (vertical side) of the element substrate 2 extending in the vertical direction.
  • the region 9b is a region extending along an end (horizontal side) of the element substrate 2 extending in the lateral direction.
  • the outer bank 90 is also formed at a position between the display area 5 and the mounting area 8. More specifically, the outer bank 90 is formed at a position between the display area 5 and the curved area 7.
  • the outer bank 90 is formed in the region 9c shown in FIG.
  • the region 9c is a region extending linearly in the horizontal direction at a position between the display region 5 and the curved region 7.
  • the region 9c may be in contact with the region 9a as shown in FIG. 1 or may be apart from the region 9a.
  • the outer bank 90 may have a tapered shape in which the width in the left-right direction decreases toward the upper direction.
  • the top 91 which is the tip of the outer bank 90 whose cross section is formed in a convex shape, is positioned higher than the top of the first intermediate bank 22a (the supplemental layer 24) and the top of the second intermediate bank 22b. Good.
  • an outer bank 90 formed at an end of the element substrate 2 is directly mounted on the element substrate 2.
  • the top 91 of the outer bank 90 formed at the end of the element substrate 2 has a notch (or crushed) end face 91a with respect to a convex shape (for example, a gentle mountain shape). May be formed.
  • the top 91 and the end face 91 a of the outer bank 90 are also in contact with the end of the element substrate 2.
  • the outer bank 90 formed between the display area 5 and the curved area 7 is mounted on the insulating film 26 formed on the same layer as the flattening layer 21.
  • the top portion 91 of the outer bank 90 formed between the display region 5 and the curved region 7 has a gentle mountain shape, and has a cut-out (or crushed) end surface 91a ( 3 (see FIG. 3) are not formed.
  • the second intermediate bank 22b is not formed between the display area 5 and the curved area 7.
  • the second intermediate bank 22b may be formed between the display area 5 and the curved area 7.
  • the second intermediate bank 22b is located between the first intermediate bank 22a and the outer bank 90 in the left-right direction, and the insulating film 26 and the barrier structure 40 (first inorganic sealing layer 41) in the vertical direction. May be formed between them.
  • the end of the protective layer 51 is formed between the first intermediate bank 22a and the second intermediate bank 22b having a convex cross section constituting the barrier structure 22, and the second intermediate bank 22b and the outer bank are formed. 90 (that is, outside the second intermediate bank 22b).
  • the barrier structure 40 includes a first inorganic sealing layer 41, a second inorganic sealing layer 43, and an organic sealing layer disposed between the first inorganic sealing layer 41 and the second inorganic sealing layer 43. 42.
  • the first and second inorganic sealing layers 41 and 43 cover a plurality of self-light-emitting elements OLED formed by the plurality of lower electrodes 31, the light-emitting layer 34, and the upper electrode 35 formed in the display region 5.
  • the first and second inorganic sealing layers 41 and 43 include a plurality of self-luminous elements OLED formed in the display area 5, a first intermediate bank 22 a and a second intermediate bank 22 b formed in the frame area 6. Is continuously covered.
  • the second inorganic sealing layer 43 covers the entire area of the first inorganic sealing layer 41.
  • the first and second inorganic sealing layers 41 and 43 are formed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNy).
  • the organic sealing layer 42 is formed of an organic insulating material such as a resin.
  • the first and second inorganic sealing layers 41 and 43 are formed of a material harder than the organic sealing layer 42. Stated another way, the organic sealing layer 42 is formed of a material that is softer than the first and second inorganic sealing layers 41 and 43.
  • the dam structure 22 which is a double dam is formed in the frame area 6 to prevent the organic sealing layer 42 from overflowing from the display area 5.
  • the organic sealing layer 42 is formed in the display region 5 surrounded by the dam structure 22, and is not formed outside the display structure 5 with respect to the display region 5. .
  • the organic sealing layer 42 is not formed at least on the top of the second intermediate bank 22b having a convex cross section.
  • the first and second inorganic sealing layers 41 and 43 cover the entire area of the organic sealing layer 42 and are in contact with each other outside the display area 5, so that moisture is absorbed in the organic sealing layer 42 and the light emitting layer 34. Prevents intrusion. As shown in FIGS. 3 and 5, the first and second inorganic sealing layers 41 and 43 are also formed on the top of the first intermediate bank 22a (the supplementary layer 24) and the top of the second intermediate bank 22b. Have been.
  • the first and second inorganic sealing layers 41 and 43 are formed on the side surface 92 on the display region 5 side of the outer bank 90 having a convex cross section, and are not formed on at least a part of the top 91. In this embodiment, the first and second inorganic sealing layers 41 and 43 are not formed on the top 91 of the outer bank 90. In addition, the thickness of the first and second inorganic sealing layers 41 and 43 formed on the side surface 92 of the outer bank 90 may be gradually reduced toward the top 91.
  • the first and second inorganic sealing layers 41 and 43 are not formed on the top 91 (end surface 91 a) of the outer bank 90 located at the end of the element substrate 2. That is, the first and second inorganic sealing layers 41 and 43 are not formed at the end of the element substrate 2. Note that the first and second inorganic sealing layers 41 and 43 need not be formed on all of the tops 91 of the outer bank 90, and may be, for example, mounted on only a part of the tops 91.
  • the first and second inorganic sealing layers 41 and 43 are not formed in the curved region 7 and the attachment region 8. This is because the outer bank 90 prevents the inorganic material from moving to the curved region 7 and the attachment region 8 when the first and second inorganic sealing layers 41 and 43 are formed. Therefore, the first and second inorganic sealing layers 41 and 43 are not formed on the side surface 93 of the outer bank 90 on the curved region 7 side opposite to the display region 5 side.
  • first and second inorganic sealing layers 41 and 43 are formed at the boundaries of regions (hereinafter, also referred to as product regions) that define the vertical and horizontal sizes of the entire display device 1, the boundary between the product regions is formed.
  • regions hereinafter, also referred to as product regions
  • the first and second inorganic sealing layers 41 and 43 are cracked. There is a risk that the crack will spread at 43. Therefore, by forming the outer banks 90 also at the boundaries between the product regions (regions 9a and 9b), it is possible to prevent the first and second inorganic sealing layers 41 and 43 from being formed at the boundaries between the product regions. I have.
  • a method for manufacturing the display device 1 will be described in detail.
  • FIGS. 7, 8A to 8D, and 9 are views for explaining a method of manufacturing the display device 1.
  • FIG. FIG. 7 is a schematic plan view of the element substrate 2 in the manufacturing process of the display device 1.
  • FIGS. 8A to 8D and FIG. 7 are schematic cross-sectional views of the element substrate 2 in the manufacturing process of the display device 1.
  • is there. 8A to 8D show cross sections taken along line VIII-VIII, which extends in the horizontal direction across the product region of FIG.
  • FIG. 9 shows a cross section taken along line IX-IX extending in the vertical direction in the frame region 6 between the display region 5 and the curved region 7 in FIG.
  • an element substrate 2 as a single laminated structure including a plurality of product regions is prepared.
  • a plurality of display areas 5 are formed on the element substrate 2 shown in FIG. 8A, and a plurality of self-luminous elements OLED (see FIG. 2) are formed in each display area 5.
  • the element substrate 2 shown in FIG. 8A includes a circuit layer 10, a passivation layer 11, a planarization layer 21, a bank 23, a lower electrode 31, a light emitting layer 34, and an upper electrode 35.
  • a dam structure 22 (a first intermediate bank 22a, a second intermediate bank 22b, and a supplementary layer 24) are formed.
  • the barrier structure 40 (the first inorganic sealing layer 43, the organic sealing layer 42, and the second inorganic sealing layer 43), the outer bank 90, the touch sensor 50 and the protective layer 51, the adhesive layer 61, and the polarization
  • the plate 60 and the counter substrate 3 have not been formed at this time.
  • an outer bank 90 having a convex cross section is formed outside the display region 5.
  • the outer bank 90 is formed in the regions 9a to 9c shown in FIG. That is, the outer bank 90 is continuously formed in regions (regions 9 a and 9 b) located at the boundaries of the product regions that define the sizes of the plurality of display devices 1, and between the display region 5 and the curved region 7. At a position (region 9c) along the lateral direction.
  • the outer bank 90 may be formed by an inkjet method, an intaglio printing method, or the like.
  • a mask M having a plurality of openings OP is arranged on the outer bank 90.
  • the mask M covers the entire area of the element substrate 2 as a laminated structure including a plurality of product regions, and a plurality of openings OP are formed at positions respectively corresponding to the plurality of display regions 5.
  • Each opening OP is formed so as to expose the entire display region 5.
  • the opening OP is formed to expose the dam structure 22.
  • a barrier structure 40 including the first inorganic sealing layer 41, the organic sealing layer 42, and the second inorganic sealing layer 43 is formed. More specifically, by laminating the first inorganic sealing layer 41, the organic sealing layer 42, and the second inorganic sealing layer 43 in the display region 5 in this order, a plurality of self-light emitting elements OLED (multiple A first inorganic encapsulating layer 41 and a second inorganic encapsulating layer 43 covering a plurality of self-emitting elements (OLEDs) composed of the lower electrode 31, the light emitting layer 34, and the upper electrode 35).
  • OLED multiple A first inorganic encapsulating layer 41 and a second inorganic encapsulating layer 43 covering a plurality of self-emitting elements (OLEDs) composed of the lower electrode 31, the light emitting layer 34, and the upper electrode 35.
  • the first and second inorganic sealing layers 41 and 43 are formed by CVD. More specifically, the first and second inorganic sealing layers 41 and 43 are formed by the inorganic material entering into the plurality of openings OP formed in the mask M. Here, the first and second inorganic sealing layers 41 and 43 are formed on the display region 5 and the side surface 92 on the display region 5 side except for at least a part of the top 91 of the outer bank 90. The first and second inorganic sealing layers 41 and 43 may be formed using the same mask M.
  • the mask M is in close contact with the top 91 of the outer bank 90.
  • the layer of the inorganic material is not formed in the portion where the mask M is in close contact. Therefore, the first and second inorganic sealing layers 41 and 43 are not formed in a portion where the mask M is in close contact. That is, the first and second inorganic sealing layers 41 and 43 are not formed on the top 91 of the outer bank 90.
  • the outer bank 90 is formed in the region (regions 9a and 9b) located at the boundary of the product region, the first and second inorganic sealing layers 41 and 43 are formed at least in the product region. Is not formed at the boundary of.
  • the mask M may be in close contact with a part of the top 91 of the outer bank 90.
  • the first and second inorganic sealing layers 41 and 43 are not formed at a part of the top 91 of the outer bank 90.
  • the probability of the inorganic material adhering to the side closer to the element substrate 2 is higher than the probability of adhering to the side closer to the top 91. Therefore, the first and second inorganic sealing layers 41 and 43 are formed so as to gradually become thinner from the element substrate 2 toward the top 91.
  • the first and second inorganic sealing layers 41 and 43 are not formed on the side surface 93 of the outer bank 90 on the curved region 7 side opposite to the display region 5 side. That is, the first and second inorganic sealing layers 41 and 43 are not formed in the curved region 7 and the attachment region 8 located on the opposite side of the display region 5 with respect to the outer bank 90.
  • FIG. 9 shows in the frame region 6 between the display region 5 and the curved region 7, the inorganic material entering from the opening OP formed in the mask M is blocked by the outer bank 90. Therefore, the first and second inorganic sealing layers 41 and 43 are not formed on the side surface 93 of the outer bank 90 on the curved region 7 side opposite to the display region 5 side. That is, the first and second inorganic sealing layers 41 and 43 are not formed in the curved region 7 and the attachment region 8 located on the opposite side of the display region 5 with respect to the outer bank 90.
  • FIG. 9 shows in the frame region 6 between the display region 5 and the curved region 7, the inorganic material entering from the
  • the organic sealing layer 42 is formed.
  • the organic sealing layer 42 is formed by injecting a liquid organic material so as to be surrounded by the dam structure 22 (particularly, the first intermediate bank 22 a) and fill the inside of the frame including the entire display region 5.
  • the organic sealing layer 42 is cured.
  • the curing method may be appropriately selected depending on the material of the organic sealing layer 42, and may be, for example, a method based on a lapse of time, volatilization of a solvent, light such as UV, reaction by heat, or a combination thereof.
  • the element substrate 2 is cut in each product region using a laser or a cutter.
  • the outer bank 90 is formed along the boundary of the product region of the element substrate 2, the outer bank 90 is also cut as the element substrate 2 is cut. That is, the element substrate 2 is cut such that a laser or a cutter passes through the outer bank 90.
  • an end face 91a cut out (or crushed) from a gentle mountain shape may be formed on the top portion 91 of the outer bank 90 due to heat of a laser, stress of a cutter, or the like.
  • the outer bank 90 is formed in a region (regions 9a and 9b: see FIG. 7) located at the boundary of the product region, the first and second inorganic sealing layers 41 and 43 It is not formed at the boundary of the product area. Therefore, when the element substrate 2 is cut, the first and second inorganic sealing layers 41 and 43 are prevented from being exposed to a laser or a cutter, and the first and second inorganic sealing layers 41 and 43 are prevented from being exposed to the heat of the laser or the stress of the cutter. Of the inorganic sealing layers 41 and 43 can be prevented.
  • the formation of the touch sensor 50, the polarizing plate 60, and the counter substrate 3 is performed after the formation of the barrier structure 40 (more specifically, after the formation of the second inorganic sealing layer 43). Further, the formation of the touch sensor 50, the polarizing plate 60, and the counter substrate 3 may be performed before or after the element substrate 2 is cut in each product region.
  • the outer bank 90 having a convex cross section is formed outside the display region 5.
  • the first and second inorganic sealing layers 41 and 43 are unnecessary (the area where the top 91 of the outer bank 90 is located, and the outer bank 90 is opposite to the display area 5). (Region on the side) can be prevented from forming the first and second inorganic sealing layers 41 and 43. Further, by doing so, the step of removing the first and second inorganic sealing layers 41 and 43 by etching or the like can be omitted, so that the display device 1 can be manufactured more easily than in the past. Will be able to do it.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
PCT/JP2019/021314 2018-09-03 2019-05-29 表示装置、及び表示装置の製造方法 WO2020049811A1 (ja)

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