WO2020047980A1 - 电源控制系统及显示器 - Google Patents

电源控制系统及显示器 Download PDF

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Publication number
WO2020047980A1
WO2020047980A1 PCT/CN2018/113285 CN2018113285W WO2020047980A1 WO 2020047980 A1 WO2020047980 A1 WO 2020047980A1 CN 2018113285 W CN2018113285 W CN 2018113285W WO 2020047980 A1 WO2020047980 A1 WO 2020047980A1
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Prior art keywords
power management
logic board
bus
management unit
unit
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PCT/CN2018/113285
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English (en)
French (fr)
Inventor
谢剑军
黎云涛
高剑
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深圳市华星光电技术有限公司
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Publication of WO2020047980A1 publication Critical patent/WO2020047980A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present application relates to the field of liquid crystal display, and in particular, to a power supply control system and a display.
  • power management chips for non-GOA architecture and two-in-one architecture power management chips for programmable gamma buffer cells as well as power management chips for GOA architecture, programmable gamma buffers, and level conversion Unified architecture power management chip, and in order to achieve the effective use of non-volatile storage devices, the power management chip no longer integrates non-volatile storage devices, but stores its configuration information in code memory outside the logic board. Download the configuration information of the power management chip through the logic board and upload it to the power management chip through the I2C bus, so that the power management chip enters the normal working state.
  • the power management chip will calculate and update the redundant verification data of the internal configuration information in real time, and the logic board reads the redundant verification data in real time through the I2C bus. Compare to confirm whether the working status of the power management chip is normal.
  • the I2C bus will only be used to control the power management chip. If the external chip needs to read and write to the logic board or power management chip, the external chip needs an additional GPI pin (such as low-> high ) Notify the logic board to release the I2C bus control.
  • the purpose of this application is to provide a power control system and display, which can facilitate other control chips to debug the power management module or send instructions to the logic board through the I2C bus to achieve specific functions.
  • An embodiment of the present application provides a power control system, which includes a power management module, a code memory, a logic board, and an I2C bus.
  • the code memory is connected to the logic board, and the power management module communicates with all of the devices through the I2C bus. Said logic board connection;
  • the power management module includes a power management unit and a monitoring unit provided therein, the monitoring unit is configured to obtain cyclic redundancy check data in the power management unit to detect whether an abnormal state occurs in the power management unit,
  • the logic board downloads the configuration information of the power management unit from the code memory and uploads the configuration information to the power management unit through the I2C bus; when the status of the power management unit is abnormal, The I2C bus acquires configuration information after debugging from the logic board;
  • the power management module further includes a programmable gamma buffer unit, and the programmable gamma buffer unit is connected to the power management unit;
  • the power management module further includes a level conversion unit, and the level conversion unit is connected to the power management unit.
  • the I2C bus in the power-on phase, the I2C bus is in a state of being occupied by a logic board, and the power management unit obtains the configuration information from the logic board through the I2C bus; in the working stage , The I2C bus is in a logic board idle state.
  • the I2C bus switches from a logic board idle state to a logic board occupation state and continues A first preset duration T1, and the second preset duration T2 effectively occupied by the logic board and a safety redundancy duration T3 not effectively occupied by the logic board.
  • the power management unit has a status pin GPO.
  • the status pin GPO When the monitoring unit detects that the power management unit is abnormal, the status pin GPO is high. When the monitoring unit detects that there is no abnormality in the power management unit, the status pin GPO is at a low level.
  • the status pin GPO is connected to the logic board unit; when the logic board unit detects that the status pin GPO is at a high level, the I2C bus The state is switched from the logic board idle state to the logic board occupied state, and the configuration information is re-uploaded through the I2C bus.
  • the code memory is a read-only memory.
  • the code memory is a non-volatile memory.
  • An embodiment of the present application further provides a power control system, including: a power management module, a code memory, a logic board, and an I2C bus.
  • the code memory is connected to the logic board, and the power management module communicates with the logic board through the I2C bus.
  • the logic board is connected;
  • the power management module includes a power management unit and a monitoring unit provided therein, the monitoring unit is configured to obtain cyclic redundancy check data in the power management unit to detect whether an abnormal state occurs in the power management unit,
  • the logic board downloads the configuration information of the power management unit from the code memory and uploads the configuration information to the power management unit through the I2C bus; when the status of the power management unit is abnormal,
  • the I2C bus obtains the configuration information after debugging from the logic board.
  • the power management module further includes a programmable gamma buffer unit, and the programmable gamma buffer unit is connected to the power management unit.
  • the power management module further includes a level conversion unit, and the level conversion unit is connected to the power management unit.
  • the I2C bus in the power-on phase, the I2C bus is in a state of being occupied by a logic board, and the power management unit obtains the configuration information from the logic board through the I2C bus; in the working stage , The I2C bus is in a logic board idle state.
  • the I2C bus switches from a logic board idle state to a logic board occupation state and continues A first preset duration T1, and the second preset duration T2 effectively occupied by the logic board and a safety redundancy duration T3 not effectively occupied by the logic board.
  • the power management unit has a status pin GPO.
  • the status pin GPO When the monitoring unit detects that the power management unit is abnormal, the status pin GPO is high. When the monitoring unit detects that there is no abnormality in the power management unit, the status pin GPO is at a low level.
  • the status pin GPO is connected to the logic board unit; when the logic board unit detects that the status pin GPO is at a high level, the I2C bus The state is switched from the logic board idle state to the logic board occupied state, and the configuration information is re-uploaded through the I2C bus.
  • the code memory is a read-only memory.
  • the code memory is a non-volatile memory.
  • An embodiment of the present application further provides a display, which includes a power control system.
  • the power control system includes a power management module, a code memory, a logic board, and an I2C bus.
  • the code memory is connected to the logic board.
  • a management module is connected to the logic board through the I2C bus;
  • the power management module includes a power management unit and a monitoring unit provided therein, the monitoring unit is configured to obtain cyclic redundancy check data in the power management unit to detect whether an abnormal state occurs in the power management unit,
  • the logic board downloads the configuration information of the power management unit from the code memory and uploads the configuration information to the power management unit through the I2C bus; when the status of the power management unit is abnormal,
  • the I2C bus obtains the configuration information after debugging from the logic board.
  • the power management module further includes a programmable gamma buffer unit, and the programmable gamma buffer unit is connected to the power management unit.
  • the power management module further includes a level conversion unit, and the level conversion unit is connected to the power management unit.
  • the I2C bus is in a logic board occupancy state, and the power management unit obtains the configuration information from the logic board through the I2C bus; during the working phase, all The I2C bus is in the idle state of the logic board.
  • the application By setting the monitoring unit inside the power management module, the application makes the I2C bus almost in the idle state of the logic board during the working phase of the entire system, so that the logic board can effectively release the control right of the I2C bus; further facilitating other control chips to pass I2C bus to debug the power management module or send instructions to the logic board to achieve specific functions.
  • FIG. 1 is a schematic structural diagram of a power supply control system in an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality" is two or more, unless specifically defined otherwise.
  • the "first" or “under” of the second feature may include the first and second features in direct contact, and may also include the first and second features. Not directly, but through another characteristic contact between them.
  • the first feature is “above”, “above”, and “above” the second feature, including that the first feature is directly above and obliquely above the second feature, or merely indicates that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” of the second feature, including the fact that the first feature is directly below and obliquely below the second feature, or merely indicates that the first feature is less horizontal than the second feature.
  • FIG. 1 is a schematic structural diagram of a power control system according to an embodiment of the present application.
  • the power control system includes: a power management module 10, a code memory 30, a logic board 20, and an I 2 C bus 40.
  • the code memory 30 is connected to the logic board 20.
  • the power management module 10 communicates with the I 2 C bus 40 through the I 2 C bus 40.
  • the logic board 20 is connected.
  • the power management module 10 includes a power management unit 11 and a monitoring unit 12 disposed therein.
  • the monitoring unit 12 is configured to obtain cyclic redundancy check data in the power management unit 11 to detect whether the power management unit 12 is When an abnormal state occurs, the logic board 20 downloads the configuration information of the power management unit 11 from the code memory 30 and uploads the configuration information to the power management unit 11 through the I2C bus 40; when the power management unit 11 appears in a state When abnormal, the debug configuration information is obtained from the logic board 20 through the I2C bus 40.
  • the power management module 10 is an integrated circuit. It adopts a power management chip with a two-in-one architecture of power management and programmable gamma buffer in the prior art, and a monitoring unit is also provided to monitor the power supply. Manage the status of the chip.
  • the power management module 10 includes a programmable gamma buffer unit 14, a power management unit 11, and a monitoring unit 12.
  • the three-in-one architecture power management module 10 of the Power + P-Gamma + Level Shifter applied to the GOA architecture is an integrated circuit, which uses and applies power management, programmable gamma buffering, and Three-in-one architecture PMIC for level shifting.
  • the power management module 10 specifically includes a programmable gamma buffer unit 14, a level conversion unit 13, a power management unit 11, and a monitoring unit 12.
  • the programmable gamma buffer unit 14 is connected to the power management unit 11.
  • the level conversion unit 13 is connected to the power management unit 11.
  • the I2C bus 40 is in the occupied state of the logic board 20, and the power management unit obtains the configuration information from the logic board 20 through the I2C bus 40; during the work stage, the The I2C bus 40 is in an idle state of the logic board 20.
  • the I2C bus 40 switches from the idle state of the logic board 20 to the occupied state of the logic board 20, and continues for the first preset duration T1, and
  • the first preset time period is a second time period T2 which is effectively occupied by the logic board 20 and a safety redundancy time period T3 which is not effectively occupied by the logic board 20.
  • the power management unit 11 has a status pin GPO.
  • the status pin GPO When the monitoring unit 12 detects that the power management unit 11 is abnormal, the status pin GPO is high. When the monitoring unit 12 monitors the power management When there is no abnormality in the unit 11, the status pin GPO is at a low level.
  • the status pin GPO is connected to the logic board 20 unit; when the logic board 20 unit detects that the status pin GPO is high, the state of the I2C bus 40 is switched from the logic board 20 idle state to the logic board 20 The status is occupied, and the configuration information is uploaded again through the I2C bus 40.
  • the code memory 30 is a read-only memory ROM or a non-volatile memory.
  • the I2C bus 40 is almost in the idle state of the logic board, so that the logic board can effectively release the control power of the I2C bus; further it is convenient for other control chips to debug or manage the power management module through the I2C bus
  • the board sends instructions to implement specific functions.
  • the present application also provides a display, which includes the power supply control system in any one of the above embodiments.

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Abstract

本申请提供一种电源控制系统，包括：电源管理模块、代码存储器、逻辑板以及I2C总线；电源管理模块包括设置于其内的电源管理单元和监控单元，监控单元用于获取电源管理单元内的循环冗余校验数据以检测电源管理单元是否出现异常状态，逻辑板从代码存储器下载电源管理单元的配置信息并将配置信息通过I2C总线上传至电源管理单元。

Description

电源控制系统及显示器 技术领域
本申请涉及液晶显示领域，具体涉及一种电源控制系统及显示器。
 背景技术
随着液晶电视面板的技术发展和进步，以及越来越激烈的市场竞争，其驱动电路的集成度也越来越高，以达到进一步的成本优化。当前已经出现了应用于非GOA架构的电源管理芯片以及可编程伽马缓冲元的二合一架构电源管理芯片，以及应用于GOA架构的电源管理芯片、可编程伽马缓冲及电平转换的三合一架构电源管理芯片，并且为了达到非易失性存储器件的有效利用，电源管理芯片不再集成非易失性存储器件，而将其配置信息存储于逻辑板外部的代码存储器，上电后通过逻辑板下载电源管理芯片的配置信息，并通过I2C总线上传至电源管理芯片，使电源管理芯片进入正常的工作状态。然而，基于电源管理芯片的配置信息安全性及稳定性的考量，电源管理芯片会实时计算并更新内部配置信息的冗余校验数据，逻辑板通过I2C总线实时将冗余校验数据读回来做比对，以确认电源管理芯片的工作状态是否正常。该 I2C总线将只用于控制电源管理芯片，若外部的芯片需要对逻辑板或电源管理芯片进行读写等调试操作，则外部的芯片需要借助一根额外的GPI引脚(如low->high)通知逻辑板释放该I2C总线控制权。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请的目的是提供一种电源控制系统及显示器，能够方便其他控制芯片通过I2C总线来对电源管理模块进行调试或向逻辑板发送指令，以实现特定功能。
 技术解决方案
本申请实施例提供了一种电源控制系统其包括：电源管理模块、代码存储器、逻辑板以及I2C总线，所述代码存储器与所述逻辑板连接，所述电源管理模块通过所述I2C总线与所述逻辑板连接；
所述电源管理模块包括设置于其内的电源管理单元以及监控单元，所述监控单元用于获取所述电源管理单元内的循环冗余校验数据以检测所述电源管理单元是否出现异常状态，所述逻辑板从所述代码存储器下载所述电源管理单元的配置信息并将所述配置信息通过所述I2C总线上传至所述电源管理单元；当所述电源管理单元出现状态异常时，通过所述I2C总线从所述逻辑板获取调试后的配置信息；
所述电源管理模块还包括可编程伽马缓冲单元，所述可编程伽马缓冲单元与所述电源管理单元连接；
所述电源管理模块还包括电平转换单元，所述电平转换单元与所述电源管理单元连接。
在本申请所述的电源控制系统中，在上电阶段，所述I2C总线处于逻辑板占用状态，所述电源管理单元通过所述I2C总线从所述逻辑板获取所述配置信息；在工作阶段，所述I2C总线处于逻辑板空闲状态。
在本申请所述的电源控制系统中，在工作阶段，当所述监控单元监测到所述电源管理单元配置信息异常时，所述I2C总线从逻辑板空闲状态切换为逻辑板占用状态，并持续第一预设时长T1，且所述第一预设时长由逻辑板有效占用的第二时长T2以及逻辑板未有效占用的安全冗余时长T3。
在本申请所述的电源控制系统中，所述电源管理单元具有一状态引脚GPO，当所述监控单元监测到所述电源管理单元异常时，所述状态引脚GPO为高电平，当所述监控单元监测到所述电源管理单无元异常时，所述状态引脚GPO为低电平。
在本申请所述的电源控制系统中，所述状态引脚GPO与所述逻辑板单元连接；当所述逻辑板单元检测到所述状态引脚GPO为高电平时，将所述I2C总线的状态由逻辑板空闲状态切换为逻辑板占用状态，并通过所述I2C总线重新上传所述配置信息。
在本申请所述的电源控制系统中，所述代码存储器为只读存储器。
在本申请所述的电源控制系统中，所述代码存储器为非易失性存储器。
本申请实施例还提供了一种电源控制系统，包括：电源管理模块、代码存储器、逻辑板以及I2C总线，所述代码存储器与所述逻辑板连接，所述电源管理模块通过所述I2C总线与所述逻辑板连接；
所述电源管理模块包括设置于其内的电源管理单元以及监控单元，所述监控单元用于获取所述电源管理单元内的循环冗余校验数据以检测所述电源管理单元是否出现异常状态，所述逻辑板从所述代码存储器下载所述电源管理单元的配置信息并将所述配置信息通过所述I2C总线上传至所述电源管理单元；当所述电源管理单元出现状态异常时，通过所述I2C总线从所述逻辑板获取调试后的配置信息。
在本申请所述的电源控制系统中，所述电源管理模块还包括可编程伽马缓冲单元，所述可编程伽马缓冲单元与所述电源管理单元连接。
在本申请所述的电源控制系统中，所述电源管理模块还包括电平转换单元，所述电平转换单元与所述电源管理单元连接。
在本申请所述的电源控制系统中，在上电阶段，所述I2C总线处于逻辑板占用状态，所述电源管理单元通过所述I2C总线从所述逻辑板获取所述配置信息；在工作阶段，所述I2C总线处于逻辑板空闲状态。
在本申请所述的电源控制系统中，在工作阶段，当所述监控单元监测到所述电源管理单元配置信息异常时，所述I2C总线从逻辑板空闲状态切换为逻辑板占用状态，并持续第一预设时长T1，且所述第一预设时长由逻辑板有效占用的第二时长T2以及逻辑板未有效占用的安全冗余时长T3。
在本申请所述的电源控制系统中，所述电源管理单元具有一状态引脚GPO，当所述监控单元监测到所述电源管理单元异常时，所述状态引脚GPO为高电平，当所述监控单元监测到所述电源管理单无元异常时，所述状态引脚GPO为低电平。
在本申请所述的电源控制系统中，所述状态引脚GPO与所述逻辑板单元连接；当所述逻辑板单元检测到所述状态引脚GPO为高电平时，将所述I2C总线的状态由逻辑板空闲状态切换为逻辑板占用状态，并通过所述I2C总线重新上传所述配置信息。
在本申请所述的电源控制系统中，所述代码存储器为只读存储器。
在本申请所述的电源控制系统中，所述代码存储器为非易失性存储器。
本申请实施例还提供一种显示器，其包括电源控制系统，所述电源控制系统包括：电源管理模块、代码存储器、逻辑板以及I2C总线，所述代码存储器与所述逻辑板连接，所述电源管理模块通过所述I2C总线与所述逻辑板连接；
所述电源管理模块包括设置于其内的电源管理单元以及监控单元，所述监控单元用于获取所述电源管理单元内的循环冗余校验数据以检测所述电源管理单元是否出现异常状态，所述逻辑板从所述代码存储器下载所述电源管理单元的配置信息并将所述配置信息通过所述I2C总线上传至所述电源管理单元；当所述电源管理单元出现状态异常时，通过所述I2C总线从所述逻辑板获取调试后的配置信息。
在本申请所述的显示器中，所述电源管理模块还包括可编程伽马缓冲单元，所述可编程伽马缓冲单元与所述电源管理单元连接。
在本申请所述的显示器中，所述电源管理模块还包括电平转换单元，所述电平转换单元与所述电源管理单元连接。
在本申请所述的显示器中，在上电阶段，所述I2C总线处于逻辑板占用状态，所述电源管理单元通过所述I2C总线从所述逻辑板获取所述配置信息；在工作阶段，所述I2C总线处于逻辑板空闲状态。
 有益效果
本申请通过将监控单元设置在电源管理模块内部，使得在整个系统的工作阶段中使I2C总线几乎都处于逻辑板空闲状态，使逻辑板可以有效释放I2C总线控制权；进一步方便了其他控制芯片通过I2C总线来对电源管理模块进行调试或向逻辑板发送指令，以实现特定功能。
 附图说明
图1是本申请实施例中的电源控制系统的一种结构示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参照图1，图1是本申请一实施例中的电源控制系统的结构示意图。该电源控制系统，包括：电源管理模块10、代码存储器30、逻辑板20以及I2C总线40，所述代码存储器30与所述逻辑板20连接，所述电源管理模块10通过所述I2C总线40与所述逻辑板20连接。
其中，该电源管理模块10包括设置于其内的电源管理单元11以及监控单元12，该监控单元12用于获取该电源管理单元11内的循环冗余校验数据以检测该电源管理单元12是否出现异常状态，所述逻辑板20从所述代码存储器30下载电源管理单元11的配置信息并将该配置信息通过该I2C总线40上传至该电源管理单元11；当所述电源管理单元11出现状态异常时，通过该I2C总线40从该逻辑板20获取调试后的配置信息。
具体地，该电源管理模块10为集成电路，其采用现有技术中的电源管理加可编程伽马缓冲的二合一架构的电源管理芯片，在此基础上还设置了监控单元来监测该电源管理芯片的状态。该电源管理模块10具体包括：可编程伽马缓冲单元14、电源管理单元11以及监控单元12。在一些实施例中，该应用于GOA架构的Power+P-Gamma+Level Shifter的三合一架构电源管理模块10为集成电路，其采用以及应用于GOA架构的电源管理、可编程伽马缓冲以及电平转换的三合一架构PMIC。该电源管理模块10具体包括：可编程伽马缓冲单元14、电平转换单元13、电源管理单元11以及监控单元12。该可编程伽马缓冲单元14与该电源管理单元11连接。电平转换单元13与该电源管理单元11连接。
实际工作中，该电源控制系统在上电阶段时，该I2C总线40处于逻辑板20占用状态，该电源管理单元通过该I2C总线40从该逻辑板20获取所述配置信息；在工作阶段，该I2C总线40处于逻辑板20空闲状态。
当然，在工作阶段，当该监控单元监测到该电源管理单元配置信息异常时，该I2C总线40从逻辑板20空闲状态切换为逻辑板20占用状态，并持续第一预设时长T1，且该第一预设时长由逻辑板20有效占用的第二时长T2以及逻辑板20未有效占用的安全冗余时长T3。
具体地，该电源管理单元11具有一状态引脚GPO，当该监控单元12监测到该电源管理单元11异常时，该状态引脚GPO为高电平，当该监控单元12监测到该电源管理单元11没有异常时，该状态引脚GPO为低电平。
该状态引脚GPO与该逻辑板20单元连接；当所述逻辑板20单元检测到该状态引脚GPO为高电平时，将该I2C总线40的状态由逻辑板20空闲状态切换为逻辑板20占用状态，并通过该I2C总线40重新上传所述配置信息。
其中，该代码存储器30为只读存储器ROM或者为非易失性存储器。
在整个系统的工作阶段中使I2C总线40几乎都处于逻辑板空闲状态，使逻辑板可以有效释放I2C总线控制权；进一步方便了其他控制芯片通过该I2C总线来对电源管理模块进行调试或向逻辑板发送指令，以实现特定功能。
本申请还提供了一种显示器，其包括上述任一实施例中的电源控制系统。
在本说明书的描述中，参考术语“一个实施方式”、“某些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种电源控制系统，其包括：电源管理模块、代码存储器、逻辑板以及I2C总线，所述代码存储器与所述逻辑板连接，所述电源管理模块通过所述I2C总线与所述逻辑板连接；
    所述电源管理模块包括设置于其内的电源管理单元以及监控单元，所述监控单元用于获取所述电源管理单元内的循环冗余校验数据以检测所述电源管理单元是否出现异常状态，所述逻辑板从所述代码存储器下载所述电源管理单元的配置信息并将所述配置信息通过所述I2C总线上传至所述电源管理单元；当所述电源管理单元出现状态异常时，通过所述I2C总线从所述逻辑板获取调试后的配置信息；
    所述电源管理模块还包括可编程伽马缓冲单元，所述可编程伽马缓冲单元与所述电源管理单元连接；
    所述电源管理模块还包括电平转换单元，所述电平转换单元与所述电源管理单元连接。
  2. 根据权利要求1所述的电源控制系统，其中，在上电阶段，所述I2C总线处于逻辑板占用状态，所述电源管理单元通过所述I2C总线从所述逻辑板获取所述配置信息；在工作阶段，所述I2C总线处于逻辑板空闲状态。
  3. 根据权利要求2所述的电源控制系统，其中，在工作阶段，当所述监控单元监测到所述电源管理单元配置信息异常时，所述I2C总线从逻辑板空闲状态切换为逻辑板占用状态，并持续第一预设时长T1，且所述第一预设时长由逻辑板有效占用的第二时长T2以及逻辑板未有效占用的安全冗余时长T3。
  4. 根据权利要求3所述的电源控制系统，其中，所述电源管理单元具有一状态引脚GPO，当所述监控单元监测到所述电源管理单元异常时，所述状态引脚GPO为高电平，当所述监控单元监测到所述电源管理单无元异常时，所述状态引脚GPO为低电平。
  5. 根据权利要求4所述的电源控制系统，其中，所述状态引脚GPO与所述逻辑板单元连接；当所述逻辑板单元检测到所述状态引脚GPO为高电平时，将所述I2C总线的状态由逻辑板空闲状态切换为逻辑板占用状态，并通过所述I2C总线重新上传所述配置信息。
  6. 根据权利要求1所述的电源控制系统，其中，所述代码存储器为只读存储器。
  7. 根据权利要求1所述的电源控制系统，其中，所述代码存储器为非易失性存储器。
  8. 一种电源控制系统，其包括：电源管理模块、代码存储器、逻辑板以及I2C总线，所述代码存储器与所述逻辑板连接，所述电源管理模块通过所述I2C总线与所述逻辑板连接；
    所述电源管理模块包括设置于其内的电源管理单元以及监控单元，所述监控单元用于获取所述电源管理单元内的循环冗余校验数据以检测所述电源管理单元是否出现异常状态，所述逻辑板从所述代码存储器下载所述电源管理单元的配置信息并将所述配置信息通过所述I2C总线上传至所述电源管理单元；当所述电源管理单元出现状态异常时，通过所述I2C总线从所述逻辑板获取调试后的配置信息。
  9. 根据权利要求8所述的电源控制系统，其中，所述电源管理模块还包括可编程伽马缓冲单元，所述可编程伽马缓冲单元与所述电源管理单元连接。
  10. 根据权利要求8所述的电源控制系统，其中，所述电源管理模块还包括电平转换单元，所述电平转换单元与所述电源管理单元连接。
  11. 根据权利要求8所述的电源控制系统，其中，在上电阶段，所述I2C总线处于逻辑板占用状态，所述电源管理单元通过所述I2C总线从所述逻辑板获取所述配置信息；在工作阶段，所述I2C总线处于逻辑板空闲状态。
  12. 根据权利要求11所述的电源控制系统，其中，在工作阶段，当所述监控单元监测到所述电源管理单元配置信息异常时，所述I2C总线从逻辑板空闲状态切换为逻辑板占用状态，并持续第一预设时长T1，且所述第一预设时长由逻辑板有效占用的第二时长T2以及逻辑板未有效占用的安全冗余时长T3。
  13. 根据权利要求12所述的电源控制系统，其中，所述电源管理单元具有一状态引脚GPO，当所述监控单元监测到所述电源管理单元异常时，所述状态引脚GPO为高电平，当所述监控单元监测到所述电源管理单无元异常时，所述状态引脚GPO为低电平。
  14. 根据权利要求13所述的电源控制系统，其中，所述状态引脚GPO与所述逻辑板单元连接；当所述逻辑板单元检测到所述状态引脚GPO为高电平时，将所述I2C总线的状态由逻辑板空闲状态切换为逻辑板占用状态，并通过所述I2C总线重新上传所述配置信息。
  15. 根据权利要求8所述的电源控制系统，其中，所述代码存储器为只读存储器。
  16. 根据权利要求8所述的电源控制系统，其中，所述代码存储器为非易失性存储器。
  17. 一种显示器，其包括电源控制系统，所述电源控制系统包括：电源管理模块、代码存储器、逻辑板以及I2C总线，所述代码存储器与所述逻辑板连接，所述电源管理模块通过所述I2C总线与所述逻辑板连接；
    所述电源管理模块包括设置于其内的电源管理单元以及监控单元，所述监控单元用于获取所述电源管理单元内的循环冗余校验数据以检测所述电源管理单元是否出现异常状态，所述逻辑板从所述代码存储器下载所述电源管理单元的配置信息并将所述配置信息通过所述I2C总线上传至所述电源管理单元；当所述电源管理单元出现状态异常时，通过所述I2C总线从所述逻辑板获取调试后的配置信息。
  18. 根据权利要求17所述的显示器，其中，所述电源管理模块还包括可编程伽马缓冲单元，所述可编程伽马缓冲单元与所述电源管理单元连接。
  19. 根据权利要求17所述的显示器，其中，所述电源管理模块还包括电平转换单元，所述电平转换单元与所述电源管理单元连接。
  20. 根据权利要求17所述的显示器，其中，在上电阶段，所述I2C总线处于逻辑板占用状态，所述电源管理单元通过所述I2C总线从所述逻辑板获取所述配置信息；在工作阶段，所述I2C总线处于逻辑板空闲状态。
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