WO2020042222A1 - 栅极驱动单元的下拉电路及显示装置 - Google Patents

栅极驱动单元的下拉电路及显示装置 Download PDF

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Publication number
WO2020042222A1
WO2020042222A1 PCT/CN2018/105189 CN2018105189W WO2020042222A1 WO 2020042222 A1 WO2020042222 A1 WO 2020042222A1 CN 2018105189 W CN2018105189 W CN 2018105189W WO 2020042222 A1 WO2020042222 A1 WO 2020042222A1
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Prior art keywords
gate
source
drain
pull
film transistor
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PCT/CN2018/105189
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/336,738 priority Critical patent/US10714511B2/en
Publication of WO2020042222A1 publication Critical patent/WO2020042222A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to a display device, and more particularly to a pull-down circuit of a gate driving unit and a display device.
  • Gate Driver On Array refers to a technology in which a gate-level driving circuit is fabricated on an array substrate by using an array process of an existing thin-film transistor liquid crystal display device to realize progressive driving of scanning lines.
  • Low Power Wake-up Gesture is a unique feature of current smart phones, that is, it supports screen sliding operation when the smart phone is in a black screen, and users can wake up the smart directly through preset gestures. Some features of the phone or corresponding software. In the LPWG mode of the smartphone, the backlight is turned off, and all pixels store a common potential (VCOM).
  • VCOM common potential
  • the gate line is driven in two stages.
  • the first stage no scanning signal is provided to the gate lines, and the screen of the smartphone can be used to sense touch signals.
  • the panel of the smartphone In the second stage, when the scanning signals are sequentially provided to the gate lines, the panel of the smartphone can be used to display images.
  • the first and second phases operate alternately.
  • the components inside the pull-down circuit of the GOA module will have a micro-short phenomenon due to the above-mentioned touch signals, which makes the power consumption of the panel in the LPWG mode higher.
  • the components inside the pull-down circuit of the GOA module may cause a micro-short circuit due to the above-mentioned touch signals, which makes the power consumption of the panel in the LPWG mode higher.
  • a pull-down circuit of a gate driving unit includes: a first thin film transistor having a first gate, a first source, and a first drain, and a scanning direction signal is input to the first A gate, the clock signal is input to the first drain; a second thin film transistor having a second gate, a second source, and a second drain; the second gate is connected to the first source; The second source is connected to the pull-down control node, and the first DC voltage is input to the second drain.
  • the third thin film transistor has a third gate, a third source, and a third drain.
  • the first control signal is input to The third gate, the third source is connected to the pull-down control node, and the third drain is connected to a second DC voltage; and a fourth thin film transistor having a fourth gate and a fourth source And a fourth drain, the fourth gate is connected to the pull-down control node, the fourth source is connected to an output node, and the fourth drain is connected to the second DC voltage, wherein the first A thin film transistor and the second thin film transistor
  • the third thin film transistor and the fourth thin film transistor is an N-channel metal oxide semiconductor field effect transistor.
  • the pull-down circuit of the gate driving unit further includes a fifth thin film transistor having a fifth gate, a fifth source, and a fifth drain, and the first control signal is input to the first Five gates and fifth drain, the fifth source is connected to the output node.
  • the pull-down circuit of the gate driving unit further includes a sixth thin film transistor having a sixth gate, a sixth source, and a sixth drain, and a second control signal is input to the sixth gate.
  • the sixth source is connected to the second DC voltage
  • the sixth drain is connected to the output node.
  • the display device in the first stage, is used to sense a touch signal; and in the second stage, the display device is used to display an image.
  • the scan direction signal is converted from a first level to a second level for a predetermined time after the first phase ends and before the second phase starts, and then is converted to all Mentioned first level.
  • a pull-down circuit of a gate driving unit includes: a first thin film transistor having a first gate, a first source, and a first drain, and a scanning direction signal is input to the first A gate, the clock signal is input to the first drain; a second thin film transistor having a second gate, a second source, and a second drain; the second gate is connected to the first source; The second source is connected to the pull-down control node, and the first DC voltage is input to the second drain.
  • the third thin film transistor has a third gate, a third source, and a third drain.
  • the first control signal is input to The third gate, the third source is connected to the pull-down control node, and the third drain is connected to a second DC voltage; and a fourth thin film transistor having a fourth gate and a fourth source And a fourth drain, the fourth gate is connected to the pull-down control node, the fourth source is connected to an output node, and the fourth drain is connected to the second DC voltage.
  • the pull-down circuit of the gate driving unit further includes a fifth thin film transistor having a fifth gate, a fifth source, and a fifth drain, and the first control signal is input to the first Five gates and fifth drain, the fifth source is connected to the output node.
  • the pull-down circuit of the gate driving unit further includes a sixth thin film transistor having a sixth gate, a sixth source, and a sixth drain, and a second control signal is input to the sixth gate.
  • the sixth source is connected to the second DC voltage
  • the sixth drain is connected to the output node.
  • the display device in the first stage, is used to sense a touch signal; and in the second stage, the display device is used to display an image.
  • the scan direction signal is converted from a first level to a second level for a predetermined time after the first phase ends and before the second phase starts, and then is converted to all Mentioned first level.
  • a display device provided by the present disclosure has a display area and a non-display area.
  • the display device includes: a plurality of source lines and a plurality of gate lines disposed on the display area; and at least one source driving unit disposed on the display area.
  • the non-display area is configured to provide data signals to the plurality of source lines; and at least one gate driving unit is disposed on the non-display area and configured to provide scan signals to the plurality of gate lines.
  • the gate driving unit includes at least a pull-down circuit.
  • the pull-down circuit includes a first thin film transistor having a first gate, a first source, and a first drain. A scanning direction signal is input to the first gate.
  • a clock signal is input to the first drain; a second thin film transistor has a second gate, a second source, and a second drain, and the second gate is connected to the first source and the second source Electrode is connected to the pull-down control node, a first DC voltage is input to the second drain; a third thin film transistor has a third gate, a third source, and a third drain, and a first control signal is input to the first Three gates, the third source is connected to the pull-down control node, the third drain is connected to a second DC voltage; and a fourth thin film transistor having a fourth gate, a fourth source, and a fourth A drain, the fourth gate is connected to the pull-down control node, the fourth source is connected to an output node, and the fourth drain is connected to the second DC voltage.
  • the display device further includes a fifth thin film transistor having a fifth gate, a fifth source, and a fifth drain, and the first control signal is input to the fifth gate and the fifth gate. Five drains, the fifth source is connected to the output node.
  • the display device further includes a sixth thin film transistor having a sixth gate, a sixth source, and a sixth drain.
  • a second control signal is input to the sixth gate.
  • Six sources are connected to the second DC voltage, and the sixth drain is connected to the output node.
  • the display device in the first stage, is used to sense a touch signal; and in the second stage, the display device is used to display an image.
  • the scan direction signal is converted from a first level to a second level for a predetermined time after the first phase ends and before the second phase starts, and then is converted to all Mentioned first level.
  • the pull-down circuit and the display device of the present disclosure can reduce the scanning direction signal from the first level to the second level for a predetermined time and then to the first level, thereby reducing the Power consumption in black screen gesture wake mode.
  • FIG. 1 shows a display device according to an embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram of a pull-down circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a driving waveform diagram of a pull-down circuit in a black screen gesture wake-up mode according to an embodiment of the present disclosure.
  • FIG. 1 illustrates a display device according to an embodiment of the present disclosure.
  • the display device has a display area 10 and a non-display area 20.
  • the display device includes a plurality of source lines S1-SN, a plurality of gate lines G1-GM, at least one source driving unit 12 (one source driving unit 12 is shown in the figure), and at least one gate driving unit 14 ( (The figure shows a gate drive unit).
  • the plurality of source lines S1-SN and the plurality of gate lines G1-GM are disposed on the display area 10. More specifically, the plurality of source lines S1-SN are disposed on the display area 10 and extend to the source driving unit 12. The plurality of gate lines G1-GM are disposed on the display area 10 and extend to the gate driving unit 14. The plurality of source lines S1-SN are formed along a first direction. The plurality of gate lines G1-GM are formed along a second direction. The first direction is perpendicular to the second direction.
  • the source lines S1-SN and the gate lines G1-GM define a plurality of pixels 16. Each of the pixels 16 is electrically connected to a thin film transistor 18.
  • the source driving unit 12 is disposed on the non-display area 20.
  • the source driving unit 12 is electrically connected to the plurality of source lines S1-SN and is used to provide data signals to the plurality of source lines S1-SN, and the data signals are used to write to the pixels 16. .
  • the gate driving unit 14 is disposed on the non-display area 20. That is, the gate driving unit 14 is a GOA circuit.
  • the gate driving unit 14 is electrically connected to the plurality of gate lines G1-GM and is used to provide a scanning signal to the plurality of gate lines G1-GM to turn on the thin film transistor 18.
  • the gate driving unit 14 includes at least a pull-down circuit 140.
  • FIG. 2 shows a circuit diagram of a pull-down circuit 140 according to an embodiment of the present disclosure.
  • the pull-down circuit 140 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the first thin film transistor T1 has a first gate, a first source, and a first drain.
  • a scanning direction signal U2D / D2U is input to the first gate.
  • a clock signal CK is input to the first drain.
  • the second thin film transistor T2 has a second gate, a second source, and a second drain.
  • the second gate is connected to the first source.
  • the second source is connected to the pull-down control node P.
  • a first DC voltage VGH is input to the second drain.
  • the third thin film transistor T3 has a third gate, a third source, and a third drain.
  • a first control signal GAS1 is input to the third gate.
  • the third source is connected to the pull-down control node P.
  • the third drain is connected to a second DC voltage VGL.
  • the fourth thin film transistor T4 has a fourth gate, a fourth source, and a fourth drain.
  • the fourth gate is connected to the pull-down control node P.
  • the fourth source is connected to an output node GATE_OUT.
  • the fourth drain is connected to the second DC voltage VGL.
  • the fifth thin film transistor T5 has a fifth gate, a fifth source, and a fifth drain.
  • the first control signal GAS1 is input to the fifth gate and the fifth drain.
  • the fifth source is connected to the output node GATE_OUT.
  • the sixth thin film transistor T6 has a sixth gate, a sixth source, and a sixth drain.
  • a second control signal GAS2 is input to the sixth grid.
  • the sixth source is connected to the second DC voltage VGL.
  • the sixth drain is connected to the output node GATE_OUT.
  • the thin film transistor T6 may be an N-channel metal oxide semiconductor field effect transistor (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET).
  • N-MOSFET N-channel Metal-Oxide-Semiconductor Field-Effect Transistor
  • FIG. 3 shows driving waveforms of the pull-down circuit 140 in a Low Power Wake-up Gesture (LPWG) mode according to an embodiment of the present disclosure.
  • LPWG Low Power Wake-up Gesture
  • the gate line In LPWG mode, the gate line is driven in two stages. In the first stage S1, no scanning signal (All Gate Off) is provided to the gate lines G1-GM, and the display device can be used to sense a touch signal. At the second stage S2, a scanning signal (All Gate On) is sequentially provided to the gate lines G1-GM, and the display device can be used to display an image. The first stage and the second stage operate alternately.
  • the touch pulse signal of the first stage S1 is at a high level, so that a competition is formed between the second thin film transistor T2 and the third thin film transistor T3. Relationship, that is, a short-circuit path from Vsp to Vsn occurs.
  • the pull-down control node P will turn on the fourth thin-film transistor T4. That is, a competitive relationship is formed between the fourth thin film transistor T4 and the fifth thin film transistor T5, that is, a short circuit between the first control signal GAS1 (Vsp) and the second DC voltage VGL (Vsn) occurs. path.
  • the scanning direction signal U2D / D2U is pulled up from a low level Vsn to a high level Vsp is reduced to a low level Vsn after a predetermined time.
  • the predetermined time may be obtained according to a characteristic of the display device (for example, a frame rate).
  • the high-level Vsp of the scan direction signal U2D / D2U will clear the second gate of the second thin film transistor T2 (ie, pull down to Vsn), so that the second thin film transistor T2 is not turned on. Therefore, a competitive path between the second thin film transistor T2 and the third thin film transistor T3 does not occur.
  • the first control signal GAS1 turns on the third thin film transistor T3, and the pull-down control node P is pulled down to a low level Vsn, so that the fourth thin film transistor T4 is not turned on, so that the In a competing path between the fourth thin film transistor T4 and the fifth thin film transistor T5, the output node GATE_OUT may output a high level Vsp.
  • the scanning direction signal U2D / D2U may be reduced from a high level Vsp to a low level Vsn for a predetermined time and then pulled up to a high level Vsp. That is, the present disclosure may convert the scanning direction signal U2D / D2U from a first level to a second level for a predetermined time before converting to the first level.
  • the first level is a low level Vsn
  • the second level is a high level Vsp.
  • the second level is a low level Vsn.
  • the pull-down circuit and the display device of the present disclosure convert the scanning direction signal from the first level to the second level for a predetermined time and then to the first level, thereby reducing the time when the black screen gesture wakes up. Power consumption.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种栅极驱动单元的下拉电路，包括：第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压。

Description

栅极驱动单元的下拉电路及显示装置 技术领域
本揭示涉及显示装置，特别是涉及一种栅极驱动单元的下拉电路及显示装置。
 背景技术
Gate Driver On Array（GOA）是指利用现有薄膜晶体管液晶显示装置的阵列制程将栅级驱动电路制作在阵列基板上以实现对扫描线逐行扫描的驱动方式的技术。
黑屏手势唤醒（Low Power Wake-up Gesture，LPWG）是目前智能手机的一种具特色的功能，即在智能手机待机黑屏的情况下支持屏幕滑动操作，用户可通过预设的手势来直接唤醒智能手机的某些功能或相应的软件。智能手机在LPWG模式下，背光处于关闭状态，全部的像素存储共通电位（VCOM）。
在LPWG模式下，栅极线分成两个阶段驱动。于第一阶段，未向栅极线提供扫描信号，智能手机的屏幕可用于感测触控信号。于第二阶段，依序向栅极线提供扫描信号时，智能手机的面板可用于显示影像。第一阶段及第二阶段交替操作。
然而，从第一阶段切换到第二阶段时，GOA模组的下拉电路内部的组件会因为上述触控信号的影响而产生微短路的现象，使得面板在LPWG模式下的功耗变高。
因此需要对现有技术中的问题提出解决方法。
 技术问题
GOA模组的下拉电路内部的组件会因为上述触控信号的影响而产生微短路的现象，使得面板在LPWG模式下的功耗变高。
 技术解决方案
为解决上述问题，本揭示提供的一种栅极驱动单元的下拉电路包括：第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压，其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管以及所述第四薄膜晶体管为N通道金属氧化物半导体场效晶体管。
于一实施例中，所述栅极驱动单元的下拉电路进一步包括：第五薄膜晶体管，具有第五栅极、第五源极以及第五漏极，所述第一控制信号输入至所述第五栅极及第五漏极，所述第五源极连接至所述输出节点。
于一实施例中，所述栅极驱动单元的下拉电路进一步包括：第六薄膜晶体管，具有第六栅极、第六源极以及第六漏极，第二控制信号输入至所述第六栅极，所述第六源极连接至所述第二直流电压，所述第六漏极连接至所述输出节点。
于一实施例中，于第一阶段，所述显示装置用于感测触控信号；以及于第二阶段，所述显示装置用于显示影像。
于一实施例中，于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。
为解决上述问题，本揭示提供的一种栅极驱动单元的下拉电路包括：第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压。
于一实施例中，所述栅极驱动单元的下拉电路进一步包括：第五薄膜晶体管，具有第五栅极、第五源极以及第五漏极，所述第一控制信号输入至所述第五栅极及第五漏极，所述第五源极连接至所述输出节点。
于一实施例中，所述栅极驱动单元的下拉电路进一步包括：第六薄膜晶体管，具有第六栅极、第六源极以及第六漏极，第二控制信号输入至所述第六栅极，所述第六源极连接至所述第二直流电压，所述第六漏极连接至所述输出节点。
于一实施例中，于第一阶段，所述显示装置用于感测触控信号；以及于第二阶段，所述显示装置用于显示影像。
于一实施例中，于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。
本揭示提供的一种显示装置具有显示区以及非显示区，所述显示装置包括：多条源极线及多条栅极线设置于所述显示区上；至少一源极驱动单元，设置于所述非显示区上并用于向所述多条源极线提供数据信号；以及至少一栅极驱动单元，设置于所述非显示区上并用于向所述多条栅极线提供扫描信号。所述栅极驱动单元至少包括下拉电路，所述下拉电路包括：第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压。
于一实施例中，所述显示装置进一步包括：第五薄膜晶体管，具有第五栅极、第五源极以及第五漏极，所述第一控制信号输入至所述第五栅极及第五漏极，所述第五源极连接至所述输出节点。
于一实施例中，所述显示装置进一步包括：第六薄膜晶体管，具有第六栅极、第六源极以及第六漏极，第二控制信号输入至所述第六栅极，所述第六源极连接至所述第二直流电压，所述第六漏极连接至所述输出节点。
于一实施例中，于第一阶段，所述显示装置用于感测触控信号；以及于第二阶段，所述显示装置用于显示影像。
于一实施例中，于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。
 有益效果
相较于现有技术，本揭示之下拉电路及显示装置通过将所述扫描方向信号从第一电平转换为第二电平一预定时间后再转换为所述第一电平，藉此可降低在黑屏手势唤醒模式时的功耗。
 附图说明
图1显示根据本揭示一实施例之显示装置。
图2显示根据本揭示一实施例之下拉电路的电路图。
图3显示根据本揭示一实施例之下拉电路在黑屏手势唤醒模式的驱动波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
请参阅图1，图1显示根据本揭示一实施例之显示装置。
所述显示装置具有一显示区10以及一非显示区20。所述显示装置包括多条源极线S1-SN、多条栅极线G1-GM、至少一源极驱动单元12（图中显示一个源极驱动单元12）以及至少一栅极驱动单元14（图中显示一个栅极驱动单元）。
所述多条源极线S1-SN及所述多条栅极线G1-GM设置于所述显示区10上。更明确地说，所述多条源极线S1-SN设置于所述显示区10上并延伸至所述源极驱动单元12。所述多条栅极线G1-GM设置于所述显示区10上并延伸至所述栅极驱动单元14。所述多条源极线S1-SN沿一第一方向形成。所述多条栅极线G1-GM沿一第二方向形成。所述第一方向垂直于所述第二方向。所述源极线S1-SN及所述栅极线G1-GM定义出多个像素16。每一所述像素16电性连接至一薄膜晶体管18。
所述源极驱动单元12设置于所述非显示区20上。所述源极驱动单元12电性连接至所述多条源极线S1-SN并用于向所述多条源极线S1-SN提供数据信号，所述数据信号用于写入所述像素16。
所述栅极驱动单元14设置于所述非显示区20上。也就是说，所述栅极驱动单元14为GOA电路。所述栅极驱动单元14电性连接至所述多条栅极线G1-GM并用于向所述多条栅极线G1-GM提供扫描信号以导通所述薄膜晶体管18。所述栅极驱动单元14至少包括一下拉电路140。
请参阅图1及图2，图2显示根据本揭示一实施例之下拉电路140的电路图。
所述下拉电路140包括一第一薄膜晶体管T1、一第二薄膜晶体管T2、一第三薄膜晶体管T3、一第四薄膜晶体管T4、一第五薄膜晶体管T5以及一第六薄膜晶体管T6。
所述第一薄膜晶体管T1具有一第一栅极、一第一源极以及一第一漏极。一扫描方向信号U2D/D2U输入至所述第一栅极。一时钟信号CK输入至所述第一漏极。
所述第二薄膜晶体管T2具有一第二栅极、一第二源极以及一第二漏极。所述第二栅极连接至所述第一源极。所述第二源极连接至一下拉控制节点P。一第一直流电压VGH输入至所述第二漏极。
所述第三薄膜晶体管T3具有一第三栅极、一第三源极以及一第三漏极。一第一控制信号GAS1输入至所述第三栅极。所述第三源极连接至所述下拉控制节点P。所述第三漏极连接至一第二直流电压VGL。
所述第四薄膜晶体管T4具有一第四栅极、一第四源极以及一第四漏极。所述第四栅极连接至所述下拉控制节点P。所述第四源极连接至一输出节点GATE_OUT。所述第四漏极连接至所述第二直流电压VGL。
所述第五薄膜晶体管T5具有一第五栅极、一第五源极以及一第五漏极。所述第一控制信号GAS1输入至所述第五栅极及第五漏极。所述第五源极连接至所述输出节点GATE_OUT。
所述第六薄膜晶体管T6具有一第六栅极、一第六源极以及一第六漏极。一第二控制信号GAS2输入至所述第六栅极。所述第六源极连接至所述第二直流电压VGL。所述第六漏极连接至所述输出节点GATE_OUT。
于本实施例中，所述第一薄膜晶体管T1、所述第二薄膜晶体管T2、所述第三薄膜晶体管T3、所述第四薄膜晶体管T4、所述第五薄膜晶体管T5以及所述第六薄膜晶体管T6可以为N通道金属氧化物半导体场效晶体管（N-channel Metal-Oxide-Semiconductor Field-Effect Transistor，N-MOSFET）。
请参阅图1至图3，图3显示根据本揭示一实施例之下拉电路140在黑屏手势唤醒（Low Power Wake-up Gesture，LPWG）模式的驱动波形图。
在LPWG模式下，栅极线分成两个阶段驱动。于第一阶段S1，未向栅极线G1-GM提供扫描信号（All Gate Off），所述显示装置可用于感测触控信号。于第二阶段S2，依序向栅极线G1-GM提供扫描信号（All Gate On），所述显示装置可用于显示影像。所述第一阶段及所述第二阶段交替操作。
当第一阶段S1结束后进入所述第二阶段S2，由于第一阶段S1的触控脉冲信号位于高电平，使得所述第二薄膜晶体管T2与所述第三薄膜晶体管T3之间形成竞争关系，即出现Vsp到Vsn之间的微短路路径。此时，所述第一控制信号GAS1通过所述第三薄膜晶体管T3对于所述下拉控制节点P的电位的下拉能力不足，则所述下拉控制节点P会导通所述第四薄膜晶体管T4。也就是说，所述第四薄膜晶体管T4与所述第五薄膜晶体管T5之间形成竞争关系，即出现所述第一控制信号GAS1（Vsp）到所述第二直流电压VGL（Vsn）的短路路径。
因此，上述竞争关系造成功耗变高。
本揭示之显示装置中，如图3所示，于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号U2D/D2U从低电平Vsn拉升至高电平Vsp一预定时间后再降低为低电平Vsn。所述预定时间可根据所述显示装置的特性（例如图框率）而得。所述扫描方向信号U2D/D2U的高电平Vsp会将所述第二薄膜晶体管T2的第二栅极清零（亦即下拉至Vsn），从而使得所述第二薄膜晶体管T2不导通，因此不会出现所述第二薄膜晶体管T2与所述第三薄膜晶体管T3之间的竞争通路。所述第一控制信号GAS1导通所述第三薄膜晶体管T3，所述下拉控制节点P会被下拉至低电平Vsn，从而不导通所述第四薄膜晶体管T4，因此不会出现所述第四薄膜晶体管T4与所述第五薄膜晶体管T5之间的竞争通路，输出节点GATE_OUT可以输出高电平Vsp。
于另一实施例中，可以将所述扫描方向信号U2D/D2U从高电平Vsp降低为低高电平Vsn一预定时间后再拉升至高电平Vsp。也就是说，本揭示可以将所述扫描方向信号U2D/D2U从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。当第一电平为低电平Vsn时，第二电平为高电平Vsp。当第一电平为高电平Vsp时，第二电平为低电平Vsn。
本揭示之下拉电路及显示装置通过将所述扫描方向信号从第一电平转换为第二电平一预定时间后再转换为所述第一电平，藉此可降低在黑屏手势唤醒模式时的功耗。
综上所述，虽然本揭示已以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种栅极驱动单元的下拉电路，用于显示装置，所述栅极驱动单元的下拉电路包括：
    第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；
    第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；
    第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及
    第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压，
    其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管以及所述第四薄膜晶体管为N通道金属氧化物半导体场效晶体管。
  2. 根据权利要求1所述的栅极驱动单元的下拉电路，进一步包括：
    第五薄膜晶体管，具有第五栅极、第五源极以及第五漏极，所述第一控制信号输入至所述第五栅极及第五漏极，所述第五源极连接至所述输出节点。
  3. 根据权利要求2所述的栅极驱动单元的下拉电路，进一步包括：
    第六薄膜晶体管，具有第六栅极、第六源极以及第六漏极，第二控制信号输入至所述第六栅极，所述第六源极连接至所述第二直流电压，所述第六漏极连接至所述输出节点。
  4. 根据权利要求1所述的栅极驱动单元的下拉电路，其中于第一阶段，所述显示装置用于感测触控信号；以及
    于第二阶段，所述显示装置用于显示影像。
  5. 根据权利要求4所述的栅极驱动单元的下拉电路，其中于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。
  6. 一种栅极驱动单元的下拉电路，用于显示装置，所述栅极驱动单元的下拉电路包括：
    第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；
    第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；
    第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及
    第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压。
  7. 根据权利要求6所述的栅极驱动单元的下拉电路，进一步包括：
    第五薄膜晶体管，具有第五栅极、第五源极以及第五漏极，所述第一控制信号输入至所述第五栅极及第五漏极，所述第五源极连接至所述输出节点。
  8. 根据权利要求7所述的栅极驱动单元的下拉电路，进一步包括：
    第六薄膜晶体管，具有第六栅极、第六源极以及第六漏极，第二控制信号输入至所述第六栅极，所述第六源极连接至所述第二直流电压，所述第六漏极连接至所述输出节点。
  9. 根据权利要求6所述的栅极驱动单元的下拉电路，其中于第一阶段，所述显示装置用于感测触控信号；以及
    于第二阶段，所述显示装置用于显示影像。
  10. 根据权利要求9所述的栅极驱动单元的下拉电路，其中于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。
  11. 一种显示装置，具有显示区以及非显示区，所述显示装置包括：
    多条源极线及多条栅极线设置于所述显示区上；
    至少一源极驱动单元，设置于所述非显示区上并用于向所述多条源极线提供数据信号；以及
    至少一栅极驱动单元，设置于所述非显示区上并用于向所述多条栅极线提供扫描信号，
    其中所述栅极驱动单元至少包括下拉电路，所述下拉电路包括：
    第一薄膜晶体管，具有第一栅极、第一源极以及第一漏极，扫描方向信号输入至所述第一栅极，时钟信号输入至第一漏极；
    第二薄膜晶体管，具有第二栅极、第二源极以及第二漏极，所述第二栅极连接至所述第一源极，所述第二源极连接至下拉控制节点，第一直流电压输入至所述第二漏极；
    第三薄膜晶体管，具有第三栅极、第三源极以及第三漏极，第一控制信号输入至所述第三栅极，所述第三源极连接至所述下拉控制节点，所述第三漏极连接至第二直流电压；以及
    第四薄膜晶体管，具有第四栅极、第四源极以及第四漏极，所述第四栅极连接至所述下拉控制节点，所述第四源极连接至输出节点，所述第四漏极连接至所述第二直流电压。
  12. 根据权利要求11所述的显示装置，进一步包括：
    第五薄膜晶体管，具有第五栅极、第五源极以及第五漏极，所述第一控制信号输入至所述第五栅极及第五漏极，所述第五源极连接至所述输出节点。
  13. 根据权利要求12所述的显示装置，进一步包括：
    第六薄膜晶体管，具有第六栅极、第六源极以及第六漏极，第二控制信号输入至所述第六栅极，所述第六源极连接至所述第二直流电压，所述第六漏极连接至所述输出节点。
  14. 根据权利要求11所述的显示装置，其中于第一阶段，所述显示装置用于感测触控信号；以及
    于第二阶段，所述显示装置用于显示影像。
  15. 根据权利要求14所述的显示装置，其中于所述第一阶段结束之后且在所述第二阶段开始之前，将所述扫描方向信号从一第一电平转换为一第二电平一预定时间后再转换为所述第一电平。
PCT/CN2018/105189 2018-08-28 2018-09-12 栅极驱动单元的下拉电路及显示装置 Ceased WO2020042222A1 (zh)

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