WO2020042187A1 - 逆流开关 - Google Patents

逆流开关 Download PDF

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Publication number
WO2020042187A1
WO2020042187A1 PCT/CN2018/103680 CN2018103680W WO2020042187A1 WO 2020042187 A1 WO2020042187 A1 WO 2020042187A1 CN 2018103680 W CN2018103680 W CN 2018103680W WO 2020042187 A1 WO2020042187 A1 WO 2020042187A1
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WO
WIPO (PCT)
Prior art keywords
voltage
input terminal
mos tube
unit
controlled
Prior art date
Application number
PCT/CN2018/103680
Other languages
English (en)
French (fr)
Inventor
张孟文
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201880001287.6A priority Critical patent/CN109314512B/zh
Priority to EP18918407.0A priority patent/EP3644508B1/en
Priority to PCT/CN2018/103680 priority patent/WO2020042187A1/zh
Priority to US16/686,097 priority patent/US11342913B2/en
Publication of WO2020042187A1 publication Critical patent/WO2020042187A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
    • H04R1/1041—Mechanical or electronic switches, or control elements
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/02—Detecting, measuring or recording pulse, heart rate, blood pressure or blood flow; Combined pulse/heart-rate/blood pressure determination; Evaluating a cardiovascular condition not otherwise provided for, e.g. using combinations of techniques provided for in this group with electrocardiography or electroauscultation; Heart catheters for measuring blood pressure
    • A61B5/024—Detecting, measuring or recording pulse rate or heart rate
    • A61B5/02444—Details of sensor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/18—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to reversal of direct current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
    • H04R1/1091—Details not provided for in groups H04R1/1008 - H04R1/1083
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/007—Protection circuits for transducers
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B2560/00—Constructional details of operational features of apparatus; Accessories for medical measuring apparatus
    • A61B2560/02—Operational features
    • A61B2560/0204—Operational features of power management
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K2017/307—Modifications for providing a predetermined threshold before switching circuits simulating a diode, e.g. threshold zero
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a reverse current switch.
  • the wire-controlled headset in order to prevent the power supply system from working abnormally and affecting the power supply circuit, it is usually necessary to add a reverse current switch between the two.
  • a reverse current switch between the two.
  • the wire-controlled headset includes a microphone and a button. Since the mobile phone supplies power to the wire-controlled headset through a resistor R0, the resistance of the resistor is generally relatively large, so the current that the extension circuit can obtain from the mobile phone is limited.
  • the expansion circuit For the normal operation of the expansion circuit, the expansion circuit generally includes a large capacitor for energy storage, which is C1 in FIG. 1.
  • C1 in FIG. 1.
  • a reverse current switch needs to be added between Vdda and Vddb.
  • the structure of the existing reverse current switch is relatively complicated.
  • inventions of the present application provide a reverse current switch.
  • the reverse current switch has a simple structure and can work under low voltage conditions.
  • a reverse current switch includes: a comparator unit including a first input terminal, a second input terminal, and a first output terminal; a switch resistance unit, a first end of the switch resistance unit and the The first input terminal is connected, the second terminal of the switching resistance unit is connected to the second input terminal, the third terminal of the switching resistance unit is connected to the output terminal of the comparator unit, and the switching resistance unit is controlled by the first The voltage of an output terminal; when the voltage of the first input terminal is greater than the voltage of the second input terminal, the voltage of the first output terminal controls the switch resistance unit to be in an on state; the voltage at the first input terminal is smaller than that of the second input terminal When the voltage is applied, the voltage of the first output terminal controls the switch resistance unit to be in an off state.
  • the comparator unit controls the on or off of the switch resistance unit, the structure is simple, the power consumption is low, and it can work under low voltage conditions.
  • the reverse current switch further includes: a voltage control unit including a voltage controlled resistance unit and a voltage controlled voltage generating unit, the voltage controlled resistance unit and the switching resistance unit are connected in series at the first input terminal and the Between the second input terminals, the voltage-controlled voltage generating unit is connected in parallel with the comparator unit.
  • the voltage-controlled voltage generating unit includes a second output terminal. The difference between the voltage at the first input terminal and the voltage at the second input terminal increases.
  • the voltage output by the voltage-controlled voltage generating unit controls the resistance of the voltage-controlled resistance unit to become smaller; when the difference between the voltage of the first input terminal and the voltage of the second input terminal decreases, the voltage output by the voltage-controlled voltage generating unit decreases.
  • the voltage-controlled resistance of the voltage-controlled resistance unit increases.
  • the comparator unit includes: a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube, a gate of the first MOS tube and a second MOS tube.
  • the gate is connected, the gate of the third MOS tube is connected to the gate of the fourth MOS tube, the source of the third MOS tube is connected to the source of the fourth MOS tube, and the drain of the first MOS tube is connected.
  • Is connected to the drain of the third MOS tube, the drain of the second MOS tube and the drain of the fourth MOS tube are respectively connected to the first output terminal, and the source of the first MOS tube is connected to the first input And the source is connected to the second input terminal.
  • the first MOS tube and the second MOS tube are PMOS tubes
  • the third MOS tube and the fourth MOS tube are NMOS tubes
  • the gate of the third MOS tube and the first MOS tube are The gates of the four MOS transistors are respectively connected to the bias units
  • the source of the first MOS transistor is connected to the drain of the first MOS transistor.
  • the first MOS tube and the second MOS tube are PMOS tubes
  • the third MOS tube and the fourth MOS tube are NMOS tubes
  • the gate of the first MOS tube and the first MOS tube are The gates of the two MOS transistors are respectively connected to the bias unit
  • the source of the third MOS transistor is connected to the drain of the third MOS transistor.
  • the reverse current switch further includes: a voltage control unit including a voltage controlled resistance unit and a voltage controlled voltage generating unit, the voltage controlled resistance unit and the switching resistance unit are connected in series at the first input terminal and the Between the sources of the second MOS tube, the voltage-controlled voltage generating unit includes a second output terminal, the voltage-controlled voltage generating unit includes a fifth MOS tube and a first resistor, the fifth MOS tube is a PMOS tube, and the fifth The drain of the MOS tube and one end of the first resistor are connected to the second output terminal, the source of the fifth MOS tube is connected to the second input terminal, and the gate of the fifth MOS tube is connected to the first MOS. The gate of the tube is connected, the other end of the first resistor is connected to the source of the third MOS tube, and the voltage-controlled resistance unit is controlled by the voltage of the second output terminal.
  • a voltage control unit including a voltage controlled resistance unit and a voltage controlled voltage generating unit, the voltage controlled resistance unit and the switching resistance unit are connected in series at the
  • the reverse current switch further includes: a voltage control unit including a voltage controlled resistance unit and a voltage controlled voltage generating unit, the voltage controlled resistance unit and the switching resistance unit are connected in series at the first input terminal and the Between the sources of the second MOS tube, the voltage-controlled voltage generating unit includes a second output terminal, the voltage-controlled voltage generating unit includes a fifth MOS tube and a first resistor, the fifth MOS tube is an NMOS tube, and the fifth The drain of the MOS transistor is connected to one end of the first resistor to the second output terminal, the other end of the first resistor is connected to the second input terminal, and the gate of the fifth MOS transistor is connected to the third MOS transistor. The gate of the fifth MOS transistor is connected to the source of the third MOS transistor, and the voltage-controlled resistor unit is controlled by the voltage of the second output terminal.
  • a voltage control unit including a voltage controlled resistance unit and a voltage controlled voltage generating unit, the voltage controlled resistance unit and the switching resistance unit are connected in series at the first input terminal and the Between
  • the reverse current switch further includes: a hysteresis generating unit; when the voltage of the first input terminal is greater than the voltage of the second input terminal, the hysteresis generating unit increases the current of the fourth MOS transistor and / or Reducing the current of the second MOS tube; when the voltage of the first input terminal is less than the voltage of the second input terminal, the hysteresis generating unit reduces the current of the fourth MOS tube and / or increases the current of the second MOS tube .
  • the reverse current switch further includes: an offset correction unit; when the voltage of the first input terminal is equal to the voltage of the second input terminal, the offset correction unit performs offset correction on the reverse current switch.
  • the offset correction unit may be a reset switch connected in parallel to the switch resistance unit, or in parallel with the switch resistance unit and the voltage-controlled resistance unit.
  • the reset switch When the reset switch is closed, the voltage at the first input terminal and the second The voltages at the inputs are equal.
  • the width-to-length ratio of the third MOS tube and the fourth MOS tube can be adjusted to make the current ratio of the fourth MOS tube and the third MOS tube equal to the current ratio of the second MOS tube and the first MOS tube as much as possible.
  • the current detection blind zone of the reverse current switch can be greatly reduced.
  • the switch resistor unit is formed by a sixth MOS transistor and a second resistor in series, and a gate of the sixth MOS transistor is controlled by a voltage of an output terminal of the comparator unit.
  • the voltage-controlled resistor unit is composed of a seventh MOS transistor and a third resistor in parallel, and a gate of the seventh MOS transistor is controlled by a voltage of an output terminal of the voltage-controlled voltage generating unit.
  • the first input terminal is connected to a power supply circuit
  • the second input terminal is connected to a load circuit
  • the power supply circuit when the voltage of the first input terminal is greater than the voltage of the second input terminal, the power supply circuit is the The energy storage capacitor between the load circuit and the power supply circuit is charged; when the voltage at the first input terminal is less than the voltage at the second input terminal, the energy storage capacitor is discharged to the load circuit.
  • the power supply circuit is a wire-controlled headset
  • the load circuit is a heart rate sensor
  • FIG. 1 is a schematic diagram of a power supply system according to an embodiment of the present application.
  • FIG. 2 is a schematic block diagram of a reverse current switch provided by the present application.
  • FIG. 3 is a schematic circuit diagram of a reverse current switch according to an embodiment of the present application.
  • FIG. 4 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • FIG. 5 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • FIG. 6 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • FIG. 7 is a schematic circuit diagram of a switching resistor unit in a reverse current switch provided by the present application.
  • FIG. 8 is a schematic circuit diagram of the reverse current switch combining FIG. 3 and FIG. 7 provided in the present application.
  • FIG. 9 is a schematic circuit diagram of a voltage-controlled resistor unit in a reverse current switch provided by the present application.
  • FIG. 10 is a schematic circuit diagram of the reverse current switch in combination with FIG. 7, FIG. 9, and FIG. 5 provided in the present application.
  • FIG. 11 is a functional block diagram of a reverse current switch provided by the present application.
  • FIG. 12 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • FIG. 1 is a schematic diagram of a power supply system according to an embodiment of the present application.
  • the power supply system includes a power supply circuit, a load circuit, a reverse current switch, and an energy storage capacitor.
  • the power supply circuit may be a wire-controlled headset in FIG. 1, and the load circuit may be an expansion circuit in FIG. 1.
  • the reverse current switch can be closed, so that the power supply circuit charges the energy storage capacitor; when the voltage provided by the power supply circuit is less than the voltage input by the load circuit, the reverse current switch is opened, and the energy storage capacitor is discharged to the load circuit.
  • the reverse current switch provided in the embodiment of the present application is not limited to the above application scenario of FIG. 1, as long as a switch for preventing reverse current is required in the power supply system, the reverse current switch provided in the embodiment of the present application can be used, such as a weak power supply system.
  • the reverse current switch of the embodiment of the present application may be mainly composed of two parts: a switching resistance unit and a comparator unit.
  • the reverse current switch includes a switching resistor unit 110 and a comparator unit 120.
  • the comparator unit includes a first input terminal 125, a second input terminal 126, and a first output terminal 127.
  • a first terminal of the switching resistor unit 110 is connected to a first input terminal 125
  • a second terminal of the switching resistor unit 110 is connected to the second input terminal 126
  • a third terminal of the switching resistor unit 110 is connected to the first input terminal 125.
  • An output terminal 127 is connected, and the switching resistor unit 110 is controlled by the voltage of the first output terminal 127.
  • the first input terminal 125 and the second input terminal 126 of the comparator unit may be Vdda in FIG. 1, respectively.
  • Vddb that is, the voltage provided by the power supply circuit and the input voltage of the load circuit.
  • Vdda When Vdda is greater than Vddb, the voltage at the output terminal of the comparator unit can control the switch resistance unit to be in the on state, then the power supply circuit can charge C1 in Figure 1; when Vdda is less than Vddb, the comparator unit's The output terminal voltage can control the switch resistance to be in the off state, so C1 can discharge the load circuit.
  • FIG. 3 is a schematic circuit diagram of a reverse current switch according to an embodiment of the present application.
  • the reverse current switch may include a switching resistor unit 110 and a first MOS transistor 121, a second MOS transistor 122, a third MOS transistor 123, a fourth MOS transistor 124, a first input terminal 125, and a second input.
  • the comparator unit comprises a terminal 126 and a first output terminal 127.
  • the first terminal of the switching resistor unit 110 is connected to the first input terminal 125
  • the second terminal of the switching resistor unit 110 is connected to the second input terminal 126
  • the gate of the first MOS transistor 121 and the gate of the second MOS transistor 122 The gates of the first MOS tube 121 are connected to the drain of the first MOS tube 121, and the gates of the third MOS tube 123 and the fourth MOS tube 124 are connected to a bias unit other than the reverse current switch.
  • the bias voltage provided by the bias unit is Vbn shown in FIG. 2.
  • the drain of the first MOS tube 121 is connected to the drain of the third MOS tube 123, the drain of the second MOS tube 122 is connected to the drain of the fourth MOS tube 124, and the source of the third MOS tube 123 Is connected to the source of the fourth MOS transistor 124, the source of the first MOS transistor 121 is connected to the first input terminal 125, the source of the second MOS transistor 122 is connected to the second input terminal 126, and the first input
  • the voltage at the terminal 125 is Vdda in FIG. 2, and the voltage at the second input terminal 126 is Vddb in FIG. 2, that is, the first input terminal 125 is connected to the power supply circuit, and the second input terminal 126 is connected to the load circuit.
  • the drain of the two MOS transistors 122 and the drain of the fourth MOS transistor 124 are respectively connected to the first output terminal 127, or the drain of the second MOS transistor 122 and the drain of the fourth MOS transistor 124 are connected to each other and serve as A first output terminal 127, the output voltage of the first output terminal is Vo, a third terminal of the switch resistor unit 110 is connected to the first output terminal 127, and the switch resistor unit 110 receives the output voltage Vo of the first output terminal 127 control.
  • the direction of the arrow in the circuit diagram is the current direction and is not used to limit the type of MOS tube.
  • the first MOS tube 121 and the second MOS tube 122 are PMOS tubes
  • the third MOS tube 123 and the fourth MOS transistor 124 are NMOS transistors, respectively.
  • FIG. 4 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • the reverse current switch may include a switching resistor unit 210 and a comparator unit, where the comparator unit includes a first MOS tube 221, a second MOS tube 222, a third MOS tube 223, a fourth MOS tube 224, The first input terminal 225, the second input terminal 226, and the first output terminal 227.
  • the first terminal of the switching resistor unit 210 is connected to the first input terminal 225, the second terminal of the switching resistor unit 210 is connected to the second input terminal 226, the gate of the first MOS transistor 221 and the gate of the second MOS transistor 222
  • the poles are respectively connected to a bias unit other than the reverse current switch, and the bias voltage provided by the bias unit is Vbp shown in FIG. 3.
  • the gate of the third MOS tube 223 is connected to the gate of the fourth MOS tube 224, the gate of the third MOS tube 223 is connected to the drain of the third MOS tube 223, and the drain of the first MOS tube 221 is connected to the third
  • the drain of the MOS tube 223 is connected
  • the drain of the second MOS tube 222 is connected to the drain of the fourth MOS tube 224
  • the source of the third MOS tube 223 is connected to the source of the fourth MOS tube 224
  • the source of the first MOS transistor 221 is connected to the first input terminal 225
  • the source of the second MOS transistor 222 is connected to the second input terminal 226.
  • the voltage of the first input terminal 225 is Vdda in FIG.
  • the voltage of the second input terminal 226 is Vddb in FIG. 3, that is, the first input terminal 225 is connected to the power supply circuit, the second input terminal 226 is connected to the load circuit, the drain of the second MOS tube 222 and the fourth MOS
  • the drain of the tube 224 is connected to the first output terminal 227, or the drain of the second MOS tube 222 and the drain of the fourth MOS tube 224 are connected to each other and serve as the first output terminal 227.
  • the output voltage of the first output terminal It is Vo.
  • the third terminal of the switching resistor unit 110 is connected to the first output terminal 227, and the switching resistor unit 210 is controlled by the output voltage Vo of the first output terminal 227.
  • the direction of the arrow in the circuit diagram is the current direction and is not used to limit the type of MOS tube.
  • the first MOS tube 121 and the second MOS tube 122 are PMOS tubes
  • the third MOS tube 123 and the fourth MOS transistor 124 are NMOS transistors, respectively.
  • the MOS tube should be selected according to the following rules as far as possible:
  • Vdda Vddb
  • the first The current ratio of the two MOS transistors 122/222 and the first MOS transistors 121/221 may be equal to the current ratio of the fourth MOS transistors 124/224 and the third MOS transistors 123/223.
  • Vdda When Vdda is increased and Vddb is unchanged, I1 is increased, and the current of the fourth MOS transistor 124/224 is also increased.
  • the increase of Vdda causes the first MOS transistor 121/221 and the second MOS transistor 122 /
  • the gate voltage of 222 is increased, so that the current I2 of the second MOS transistor 122/222 is reduced (Vddb is unchanged), so that I1 is greater than I2, the voltage Vo at the first output terminal is low, and controls the switching resistor unit 110. / 210 is on.
  • Vdda when Vdda is reduced and Vddb is unchanged, I1 is reduced, and the current of the fourth MOS transistor 124/224 is also reduced.
  • Vdda causes the first MOS transistor 121/221 and the second MOS transistor.
  • the gate voltage of the tube 122/222 decreases, so that the current I2 of the second MOS tube 122/222 increases (Vddb is unchanged), so that I1 is smaller than I2, the voltage Vo at the first output terminal is high, and controls the switch The resistance units 110/210 are in an off state.
  • the current ratio of the second MOS tube 122/222 to the first MOS tube 121/221 and the current ratio of the fourth MOS tube 124/224 to the third MOS tube 123/223 are 2 Assume that the currents of the first MOS transistors 121/221 and the third MOS transistors 123/223 are 1 mA. Since the current ratio is 2, the currents of the second MOS transistors 122/222 and the fourth MOS transistors 124/224 are 2 mA.
  • Vdda When Vdda is increased, the gate voltages of the first MOS transistors 121/221 and the second MOS transistors 122/222 increase, so that the current of the second MOS transistors 122/222 decreases (Vddb is unchanged), that is, less than 2mA So that the current of the fourth MOS transistor 124/224 is greater than the current of the second MOS transistor, the voltage Vo at the first output terminal is at a low level, and the switching resistor units 110/210 are controlled to be in an on state.
  • Vdda when Vdda is reduced and Vddb is not changed, the currents of the first MOS transistors 121/221 and the third MOS transistors 123/223 are reduced, and the current of the fourth MOS transistors 124/224 is also reduced, that is, less than 2mA, at this time, the reduction of Vdda causes the gate voltages of the first MOS transistors 121/221 and the second MOS transistors 122/222 to decrease, thereby increasing the current of the second MOS transistors 122/222 (Vddb is unchanged), That is, it is greater than 2 mA, so that the current of the fourth MOS tube 124/224 is smaller than the current of the second MOS tube 122/222, the voltage Vo at the first output terminal is high, and the switch resistor unit 110/210 is controlled to be in an off state.
  • the reverse current switch in the embodiment of the present application in the on-state, the smaller the resistance value of the switch resistance unit, the smaller the voltage drop across the switch resistance unit, and the higher the voltage provided to the load circuit. That is, the smaller the resistance value of the switch resistance unit, the better. In terms of sensitivity requirements, the larger the resistance value of the switch resistance unit is, the better, so that the current detection accuracy of the reverse current switch can be improved. Therefore, the reverse current switch in the embodiment of the present application further includes:
  • the voltage-controlled unit includes a voltage-controlled resistor unit and a voltage-controlled voltage generating unit.
  • the voltage-controlled resistor unit and the switching resistor unit are connected in series between the first input terminal and the second input terminal.
  • the voltage-controlled voltage generating unit and the The comparator unit is connected in parallel, and the voltage-controlled voltage generating unit includes a second output terminal;
  • the voltage of the second output terminal controls the resistance of the voltage-controlled resistance unit to become smaller
  • the voltage of the second output terminal controls the resistance of the voltage-controlled resistance unit to increase.
  • FIG. 5 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • FIG. 5 is a voltage control unit added to FIG. 3.
  • the voltage-controlled unit includes a voltage-controlled resistor unit 131, a voltage-controlled voltage generating unit composed of a fifth MOS transistor 132 and a first resistor 133.
  • the voltage-controlled resistor unit 131 and the switching resistor unit 110 are connected in series between the first input terminal 125 and the source of the second MOS transistor 122.
  • the drain of the fifth MOS transistor 132 and the first resistor 133 are connected in series.
  • One terminal is connected to the second output terminal 134 respectively, and the voltage of the second output terminal is Vt in FIG. 5.
  • the source of the fifth MOS transistor 132 is connected to the second input terminal 126, the gate of the fifth MOS transistor 132 is connected to the gate of the first MOS transistor 121, and the other end of the first resistor 133 is connected to the first
  • the sources of the three MOS transistors 123 are connected, the fifth MOS transistor 132 is a PMOS transistor, and the voltage-controlled resistor unit 131 is controlled by the voltage Vt of the second output terminal 134.
  • FIG. 6 is a schematic circuit diagram of a reverse current switch according to another embodiment of the present application.
  • FIG. 6 is a voltage control unit added to FIG. 4.
  • the voltage-controlled unit includes a voltage-controlled resistor unit 231, a voltage-controlled voltage generating unit composed of a fifth MOS transistor 232 and a first resistor 233.
  • the voltage-controlled resistance unit 231 and the switching resistance unit 210 are connected in series between the first input terminal 225 and the source of the second MOS transistor 222, and the drain of the fifth MOS transistor 232 and the first resistor 233
  • One terminal of each is connected to the second output terminal 234, and the voltage of the second output terminal is Vt in FIG.
  • the source of the fifth MOS tube 232 is connected to the source of the third MOS tube 223, the gate of the fifth MOS tube 232 is connected to the gate of the third MOS tube 223, and the other end of the first resistor 233 Connected to the second input terminal 226, the fifth MOS transistor 232 is an NMOS transistor, and the voltage-controlled resistor unit 231 is controlled by the voltage Vt of the second output terminal 234.
  • the switch resistance unit is selected to have a relatively small resistance value, it can meet the requirement that the voltage of the second input terminal is high when the switch resistance unit is turned on.
  • Vdda decreases and Vddb does not change.
  • the gate of the fifth MOS transistor is connected to the gate of the first MOS transistor, the gate voltage of the fifth MOS transistor decreases.
  • the current on the first resistor increases, and the voltage of Vt increases, so that the resistance of the voltage-controlled resistance unit gradually increases.
  • Vdda is less than Vddb
  • the resistance of the voltage-controlled resistance unit gradually increases so that The detection accuracy of the reverse current switch has been improved. Therefore, the voltage difference of the reverse current switch with the voltage control unit changed with the current of the reverse current switch is no longer a linear change.
  • the switching resistor unit 110/210 may be composed of a sixth MOS transistor 111/211 and a second resistor 112/212 in series in FIG. 7, where a gate voltage of the sixth MOS transistor It may be provided by the output voltage Vo of the first output terminal.
  • a gate voltage of the sixth MOS transistor It may be provided by the output voltage Vo of the first output terminal.
  • the drain of the sixth MOS transistor is connected to the first input terminal, and the source is connected to the second input terminal (the embodiments of Figures 3 and 4) or the voltage-controlled resistor unit. (Examples of Figs. 5 and 6).
  • FIG. 8 shows a schematic circuit diagram in which the switched resistor unit in FIG. 7 is applied to FIG. 3.
  • the drain of the sixth MOS transistor 111 is connected to the first input terminal 125
  • the source of the sixth MOS transistor 111 is connected to one end of the second resistor 112
  • the other end of the second resistor 112 is connected to
  • the second input terminal 126 is connected
  • the gate of the sixth MOS transistor 111 is controlled by the output voltage Vo of the first output terminal 127.
  • the voltage-controlled resistor unit 131/231 may be composed of the seventh MOS transistor 135/235 and the third resistor 136/236 in FIG. 9 connected in parallel.
  • the gate voltage of the seventh MOS transistor can be provided by the voltage Vt of the second output terminal.
  • FIG. 10 shows a schematic circuit diagram in which the switched resistor unit in FIG. 7 and the voltage-controlled resistor unit in FIG. 9 are applied to FIG. 5.
  • the drain of the sixth MOS transistor 111 is connected to the first input terminal 125
  • the source of the sixth MOS transistor 111 is connected to one end of the second resistor 112
  • the other end of the second resistor 112 is connected to
  • the seventh MOS transistor 135 is connected to one end in parallel with the third resistor 136.
  • the other end of the seventh MOS transistor 135 is connected to the third resistor 136 in parallel to the second input terminal 126.
  • the gate of the sixth MOS transistor 111 is affected by the first
  • the output voltage Vo of the output terminal 127 is controlled
  • the gate of the seventh MOS transistor 135 is controlled by the output voltage Vt of the second output terminal 134.
  • FIG. 5 For the remaining connection relationship, please refer to FIG. 5.
  • Vdda When Vdda is greater than Vddb, the Vo output is at a low level, the sixth MOS transistor is in an on state, and the resistance of the voltage-controlled resistance unit controlled by Vt is the resistance of the seventh MOS transistor in parallel with the third resistor.
  • Vt When Vdda continues to increase, the Vt decreases, so that the resistance value of the seventh MOS transistor and the third resistor in parallel decreases.
  • the resistance value of the seventh MOS transistor and the third resistor in parallel decreases to It is much smaller than the resistance value of the switch resistance unit, then the sum of the resistance values of the switch resistance unit and the voltage-controlled resistance unit is the resistance value of the second resistance (the resistance value when the switch resistance unit is turned on is the resistance value of the second resistance).
  • the reverse current switch in the embodiment of the present application may not need to add a voltage-controlled resistance unit, and an adjustable resistance may be selected as the switching resistance unit.
  • the voltage of the first output terminal can control the switch resistance unit to be in an on state, or control the switch resistance unit to be off. status.
  • the voltage at the first output terminal may be a low level or a high level.
  • FIG. 11 shows a functional block diagram of a reverse current switch according to an embodiment of the present application.
  • the reverse current switch 300 includes a switching resistor unit 310 and a comparator unit 320.
  • the reverse current switch further includes: a voltage control unit 330 and a hysteresis generating unit 340; when the voltage of the first input terminal is greater than the voltage of the second input terminal, the hysteresis generating unit increases or decreases the current of the fourth MOS transistor. Reduce the current of the second MOS tube; when the voltage of the first input terminal is less than the voltage of the second input terminal, the hysteresis generating unit reduces the current of the fourth MOS tube or increases the current of the second MOS tube.
  • the fourth MOS tube may be composed of multiple sub-MOS tubes, and the sources of the multiple sub-MOS tubes are connected to the source of the third MOS tube, and the drains of the multiple sub-MOS tubes are all connected to the second MOS tube.
  • the drains of the plurality of sub-MOS transistors are connected to the bias unit or the ground by the hysteresis generating unit.
  • the fourth MOS tube 124 in FIG. 3 is composed of ten sub-MOS tubes 1240 to 1249.
  • the current of each sub-MOS tube may be 1/10 of the current of the fourth MOS tube 124.
  • the sources of the ten sub-MOS transistors 1240-1249 are connected to the source of the third MOS transistor 123, and the drains of the ten sub-MOS transistors 1240-1249 are connected to the drain of the second MOS transistor 122.
  • the gates of the tubes 1240 to 1249 are controlled by the hysteresis generating unit and connected to the bias unit Vbn or the ground GND.
  • Vbn the bias unit
  • Vdda is greater than Vddb
  • the hysteresis generating unit controls the sub-MOS transistor in the fourth MOS transistor 124.
  • the gates of 1240 to 1244 are connected to Vbn, and the gates of sub-MOS tubes 1245 to 1249 are connected to GND, and Vo is close to 2V.
  • the hysteresis generating unit can control three sub-MOS tubes 1245 to 1247 in sub-MOS tubes 1245 to 1249
  • the gate of is connected to Vbn, which reduces the Vo to 1.8V, that is, a disturbance of 0.1V is not enough to make Vo flip at a critical point of 2V.
  • Vdda is smaller than Vdda
  • the gates of the sub-MOS transistors 1240-1224 in the fourth MOS transistor 124 are connected to Vbn
  • the gates of the sub-MOS transistors 1245-1249 are connected to GND
  • Vo is close to 2V.
  • the hysteresis generation unit can be connected to GND by controlling the gates of the three sub-MOS transistors 1240-1242 in the sub-MOS transistors 1240-1242, and increase the Vo to 2.2V.
  • the disturbance of 0.1V is not enough to make Vo 2V flips at the critical point.
  • the hysteresis range generated by the hysteresis generating unit is 1.8 to 2.2V. It should be understood that the generation of the hysteresis range may be designed based on the magnitude of the disturbance to which the reverse current switch is subjected.
  • the current of other MOS transistors in the comparator unit may be adjusted to generate a certain hysteresis range.
  • the second MOS tube in FIG. 4 or FIG. 6 may be replaced by 10 sub-MOS tubes, and the current of each sub-MOS tube may be 1/10 of the current of the second MOS tube in FIG. 4 or FIG. 6.
  • Ground assuming that the critical point voltage Vo of the reverse current switch is 2V, and the perturbation of the reverse current switch is 0.1V.
  • Vdda is greater than Vddb, the gates of 5 sub-MOS transistors are connected to Vbp, and 5 sub-MOS transistors are connected.
  • the gate of is connected to GND, and Vo is close to 2V.
  • the hysteresis generating unit can be connected to GND by controlling the gates of three of the five sub-MOS transistors connected to the bias unit to reduce the Vo to 1.8V. That is to say, the disturbance of 0.1V is not enough to make Vo flip at the critical point of 2V.
  • Vdda is less than Vdda
  • the gates of 5 sub-MOS tubes are connected to Vbp
  • the gates of the other 5 sub-MOS tubes are connected to GND, and Vo is close to 2V.
  • the hysteresis generating unit can be connected to GND by control.
  • the gates of three of the five sub-MOS transistors are connected to Vbp to increase the Vo to 2.2V.
  • the disturbance of 0.1V is not enough to make Vo flip at the critical point of 2V.
  • the hysteresis range generated by the hysteresis generating unit is 1.8 to 2.2V.
  • the hysteresis generating unit can also generate a certain hysteresis range by adjusting the current of other MOS transistors in the comparator unit.
  • the embodiments of the present application are not limited to the above technical solutions.
  • the hysteresis generating unit may be implemented by a selector.
  • the gate of the sub-MOS tube in FIG. 11 may be connected to a selector of two alternatives, and the selector is controlled by the voltage Vo at the first output terminal.
  • the reverse current switch 300 further includes an offset correction unit 350.
  • the comparator unit composed of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor may have an out-of-balance.
  • the reverse current switch will be turned off only when Vdda-Vos ⁇ Vddb. open. Vos can be regarded as the offset voltage of the comparator unit.
  • the ratio of the resistance between Vos and Vdda and Vddb is the blind current that cannot be detected. Vos can usually reach 100mV. If the resistance between Vdda and Vddb is 1k ⁇ , there will be a blind current of 100uA, which is not tolerated by this reverse current switch. Therefore, the reverse current switch of the embodiment of the present application may further include: an offset correction unit; when the voltage of the first input terminal is equal to the voltage of the second input terminal, the offset correction unit performs offset correction on the reverse current switch.
  • a reset switch may be connected in parallel with the switch resistance unit, or a reset switch may be connected in parallel with the switch resistance unit and the voltage-controlled resistance unit.
  • the voltages of Vdda and Vddb may be made equal.
  • the current ratio between the fourth MOS tube and the third MOS tube is as much as possible with the current between the second MOS tube and the first MOS tube. Than equal.
  • the physical size of the second MOS tube and the first MOS tube can also be adjusted to make the ratio of the current between the second MOS tube and the first MOS tube equal to the ratio of the current between the fourth MOS tube and the third MOS tube as much as possible.
  • the physical size of any MOS tube in the comparator unit can also be adjusted at the same time to meet the above requirements. By adjusting the offset of the reverse current switch, the blind zone of the reverse current detection can be greatly reduced.
  • the first input terminal is connected to a power supply circuit
  • the second input terminal is connected to a load circuit
  • the reverse current switch Off when the voltage of the first input terminal is greater than the voltage of the second input terminal, the reverse current switch Off, the power supply circuit charges the energy storage capacitor between the load circuit and the power supply circuit; when the voltage at the first input terminal is less than the voltage at the second input terminal, the reverse current switch is turned off, and the energy storage capacitor is turned toward the load.
  • the circuit is discharged.
  • the power supply circuit is a wire-controlled headset
  • the load circuit is a heart rate sensor
  • this back-flow switch is not limited to the scenario where the headset is powered online, and can be applied to any power supply system, such as a weak power supply system.
  • an embodiment or “an embodiment” mentioned throughout the specification means that a particular feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application.
  • the appearances of "in one embodiment” or “in an embodiment” appearing throughout the specification are not necessarily referring to the same embodiment.
  • the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • branches, and units can be implemented in other ways.
  • the branches described above are schematic.
  • the division of the unit is only a logical function division. In actual implementation, there can be another division.
  • multiple units or components can be combined or integrated into A branch, or some features can be ignored or not implemented.
  • the integrated unit When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the technical solution of this application is essentially a part that contributes to the existing technology or a part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.
  • the aforementioned storage media include: U disks, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks or compact discs, and other media that can store program codes .

Abstract

一种逆流开关，该逆流开关包括：比较器单元（120），包括第一输入端（125）、第二输入端（126）和第一输出端（127）；开关电阻单元（110），该开关电阻单元的第一端与该第一输入端相连，该开关电阻单元的第二端与该第二输入端相连，该开关电阻单元的第三端与该比较器单元的输出端相连，且该开关电阻单元受控于该第一输出端的电压，本逆流开关，结构简单，能够实现在低压条件下的工作。

Description

逆流开关 技术领域
本申请涉及电子技术领域，尤其涉及一种逆流开关。
背景技术
在一些供电系统中，为了防止在供电系统非正常工作而对被供电电路造成影响，通常需要在二者之间增加逆流开关。以线控耳机供电的应用为例，如图1所示，为了扩展线控耳机的应用，例如增加心率传感器等扩展电路，需要从耳机口偏置Vdd额外取电。该线控耳机包括麦克风和按键，由于手机通过电阻R0为该线控耳机供电，该电阻的阻值一般比较大，所以扩展电路能从手机端获取的电流是有限的。为了扩展电路的正常运行，扩展电路一般包括一个储能用的大电容，也就是图1中的C1。为了防止在手机耳机口休眠、按键按下等Vdda被拉低的情况下，C1上的电荷被泄放，需要在Vdda和Vddb之间加一个逆流开关。现有的逆流开关的结构比较复杂。
发明内容
有鉴于此，本申请实施例提供了一种逆流开关，该逆流开关结构简单，能够实现在低压条件下的工作。
第一方面，提供了一种逆流开关，该逆流开关包括：比较器单元，包括第一输入端、第二输入端和第一输出端；开关电阻单元，该开关电阻单元的第一端与该第一输入端相连，该开关电阻单元的第二端与该第二输入端相连，该开关电阻单元的第三端与该比较器单元的输出端相连，且该开关电阻单元受控于该第一输出端的电压；在该第一输入端的电压大于该第二输入端的电压时，该第一输出端的电压控制该开关电阻单元处于导通状态；在该第一输入端的电压小于该第二输入端的电压时，该第一输出端的电压控制该开关电阻单元处于断开状态。
由比较器单元控制开关电阻单元的导通或断开，结构简单，功耗低，能够实现在低压条件下的工作。
在一种可能的实现方式中，该逆流开关还包括：压控单元，包括压控电阻单元和压控电压产生单元，该压控电阻单元与该开关电阻单元串联在该第 一输入端和该第二输入端之间，该压控电压产生单元与该比较器单元并联，该压控电压产生单元包括第二输出端；在该第一输入端的电压与该第二输入端的电压之差增大时，该压控电压产生单元输出的电压控制该压控电阻单元的阻值变小；在该第一输入端的电压与该第二输入端的电压之差减小时，该压控电压产生单元输出的电压控制该压控电阻单元的阻值增大。
通过增加压控单元可以提高逆流开关的电流检测精度。
在一种可能的实现方式中，该比较器单元包括：第一MOS管、第二MOS管、第三MOS管和第四MOS管，该第一MOS管的栅极和该第二MOS管的栅极相连，该第三MOS管的栅极和该第四MOS管的栅极相连且该第三MOS管的源极和该第四MOS管的源极相连，该第一MOS管的漏极与该第三MOS管的漏极相连，该第二MOS管的漏极与该第四MOS管的漏极分别与该第一输出端相连，该第一MOS管的源极与该第一输入端相连，该第二MOS管的源极与该第二输入端相连。
在一种可能的实现方式中，该第一MOS管和该第二MOS管为PMOS管，该第三MOS管和该第四MOS管为NMOS管，该第三MOS管的栅极和该第四MOS管的栅极分别与偏置单元相连，该第一MOS管的源极与该第一MOS管的漏极相连。
在一种可能的实现方式中，该第一MOS管和该第二MOS管为PMOS管，该第三MOS管和该第四MOS管为NMOS管，该第一MOS管的栅极和该第二MOS管的栅极分别与偏置单元相连，该第三MOS管的源极与该第三MOS管的漏极相连。
在一种可能的实现方式中，该逆流开关还包括：压控单元，包括压控电阻单元和压控电压产生单元，该压控电阻单元与该开关电阻单元串联在该第一输入端和该第二MOS管的源极之间，该压控电压产生单元包括第二输出端，该压控电压产生单元包括第五MOS管和第一电阻，该第五MOS管为PMOS管，该第五MOS管的漏极与该第一电阻的一端分别与该第二输出端相连，该第五MOS管的源极与该第二输入端相连，该第五MOS管的栅极与该第一MOS管的栅极相连，该第一电阻的另一端与该第三MOS管的源极相连，该压控电阻单元受该第二输出端的电压控制。
在一种可能的实现方式中，该逆流开关还包括：压控单元，包括压控电阻单元和压控电压产生单元，该压控电阻单元与该开关电阻单元串联在该第 一输入端和该第二MOS管的源极之间，该压控电压产生单元包括第二输出端，该压控电压产生单元包括第五MOS管和第一电阻，该第五MOS管为NMOS管，该第五MOS管的漏极与该第一电阻的一端分别与该第二输出端相连，该第一电阻的另一端与该第二输入端相连，该第五MOS管的栅极与该第三MOS管的栅极相连，该第五MOS管的源极与该第三MOS管的源极相连，该压控电阻单元受该第二输出端的电压控制。
在一种可能的实现方式中，该逆流开关还包括：迟滞产生单元；在该第一输入端的电压大于该第二输入端的电压时，该迟滞产生单元增加该第四MOS管的电流和/或减小该第二MOS管的电流；在该第一输入端的电压小于该第二输入端的电压时，该迟滞产生单元减小该第四MOS管的电流和/或增加该第二MOS管的电流。
通过调节比较器单元中的MOS管的电流，有利于提供一定的迟滞范围，使得逆流开关不会受临界点的扰动而频繁翻转。
在一种可能的实现方式中，该逆流开关还包括：失调校正单元；在该第一输入端的电压与该第二输入端的电压相等时，该失调校正单元对该逆流开关进行失调校正。
可选地，该失调校正单元可以是一个复位开关，并联在开关电阻单元上，或并联在开关电阻单元和压控电阻单元之上，在复位开关闭合时，该第一输入端的电压与第二输入端的电压相等。可以通过微调第三MOS管和第四MOS管的宽长比，使得第四MOS管与第三MOS管的电流比尽量等于第二MOS管与第一MOS管的电流比。
通过对逆流开关进行失调校正，可以极大地减小逆流开关的电流检测盲区。
在一种可能的实现方式中，该开关电阻单元由第六MOS管与第二电阻串联构成，该第六MOS管的栅极受该比较器单元的输出端的电压控制。
在一种可能的实现方式中，该压控电阻单元由第七MOS管与第三电阻并联构成，该第七MOS管的栅极受该压控电压产生单元的输出端的电压控制。
在一种可能的实现方式中，该第一输入端与供电电路相连，该第二输入端与负载电路相连；在该第一输入端的电压大于该第二输入端的电压时，该供电电路为该负载电路与该供电电路之间的储能电容充电；在该第一输入端 的电压小于该第二输入端的电压时，该储能电容向该负载电路放电。
在一种可能的实现方式中，该供电电路为线控耳机，该负载电路为心率传感器。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
图1是本申请实施例提供的一种供电系统的示意图。
图2是本申请提供的逆流开关的示意性框图。
图3是本申请的一个实施例的逆流开关的电路示意图。
图4是本申请的另一个实施例的逆流开关的电路示意图。
图5是本申请的再一实施例的逆流开关的电路示意图。
图6是本申请的再一实施例的逆流开关的电路示意图。
图7是本申请提供的逆流开关中的开关电阻单元的电路示意图。
图8是本申请提供的结合图3和图7的逆流开关的电路示意图。
图9是本申请提供的逆流开关中的压控电阻单元的电路示意图。
图10是本申请提供的结合图7、图9以及图5的逆流开关的电路示意图。
图11是本申请提供的逆流开关的功能性框图。
图12是本申请的再一实施例的逆流开关的电路示意图。
具体实施方式
为了使本领域的人员更好地理解本申请实施例中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请实施例的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请实施例保护的范围。
图1示出了本申请实施例提供的一种供电系统的示意图。该供电系统包括供电电路、负载电路、逆流开关以及储能电容，该供电电路可以是图1中的线控耳机，该负载电路可以是图1中的扩展电路，当供电电路提供的电压大于负载电路输入的电压时，逆流开关可以闭合，使得供电电路对储能电容进行充电；而当供电电路提供的电压小于负载电路输入的电压时，逆流开关断开，储能电容向负载电路放电。需要说明的是，本申请实施例提供的逆流 开关不限于上述图1的应用场景，只要在供电系统中需要防止逆流的开关，都可以使用本申请实施例提供的逆流开关，例如弱供电系统。
本申请实施例的逆流开关主要可以由两部分构成：开关电阻单元和比较器单元。具体地，如图2所示，该逆流开关包括开关电阻单元110和比较器单元120，该比较器单元包括第一输入端125、第二输入端126和第一输出端127。该开关电阻单元110的第一端与第一输入端125相连，该开关电阻单元110的第二端与所述第二输入端126相连，所述开关电阻单元110的第三端与所述第一输出端127相连，且所述开关电阻单元110受控于所述第一输出端127的电压；该比较器单元的第一输入端125和第二输入端126可以分别为图1中的Vdda和Vddb，也即，供电电路提供的电压以及负载电路的输入电压。
当Vdda大于Vddb时，该比较器单元的输出端的电压可以控制该开关电阻单元为导通状态，那么该供电电路可以为图1中的C1进行充电；当Vdda小于Vddb时，该比较器单元的输出端电压可以控制该开关电阻为断开状态，那么C1可以为负载电路放电。
下面将结合具体实施例详细说明本申请的逆流开关。
图3是本申请的一个实施例的逆流开关的电路示意图。如图3所示，该逆流开关可以包括开关电阻单元110和由第一MOS管121，第二MOS管122，第三MOS管123，第四MOS管124，第一输入端125，第二输入端126，以及第一输出端127构成的比较器单元。其中，开关电阻单元110的第一端与第一输入端125相连，开关电阻单元110的第二端与第二输入端126相连，第一MOS管121的栅极和第二MOS管122的栅极相连，第一MOS管121的栅极与第一MOS管121的漏极相连，第三MOS管123的栅极和第四MOS管124的栅极分别与逆流开关以外的偏置单元相连，该偏置单元提供的偏置电压为图2所示的Vbn。该第一MOS管121的漏极和第三MOS管123的漏极相连，该第二MOS管122的漏极和该第四MOS管124的漏极相连，该第三MOS管123的源极和该第四MOS管124的源极相连，该第一MOS管121的源极与第一输入端125相连，该第二MOS管122的源极与第二输入端126相连，该第一输入端125的电压为图2中的Vdda，该第二输入端126的电压为图2中的Vddb，即，第一输入端125连接到供电电路，第二输入端126连接到负载电路，该第二MOS管122的漏极与该第四MOS管124 的漏极分别与第一输出端127相连，或者说第二MOS管122的漏极与该第四MOS管124的漏极相互连接并作为第一输出端127，该第一输出端的输出电压为Vo，该开关电阻单元110的第三端与该第一输出端127相连，且该开关电阻单元110受第一输出端127的输出电压Vo控制。
需要说明的是，电路图中的箭头方向为电流方向，并不用来限制MOS管的类型，在图3中，该第一MOS管121和第二MOS管122分别为PMOS管，该第三MOS管123和第四MOS管124分别为NMOS管。
图4是本申请的另一个实施例的逆流开关的电路示意图。如图4所示，该逆流开关可以包括开关电阻单元210和比较器单元，其中，比较器单元包括第一MOS管221、第二MOS管222、第三MOS管223、第四MOS管224、第一输入端225、第二输入端226、以及第一输出端227。其中，开关电阻单元210的第一端与第一输入端225相连，开关电阻单元210的第二端与第二输入端226相连，第一MOS管221的栅极和第二MOS管222的栅极分别与逆流开关以外的偏置单元相连，该偏置单元提供的偏置电压为图3所示的Vbp。第三MOS管223的栅极和第四MOS管224的栅极相连，第三MOS管223的栅极与第三MOS管223的漏极相连，该第一MOS管221的漏极和第三MOS管223的漏极相连，该第二MOS管222的漏极和该第四MOS管224的漏极相连，该第三MOS管223的源极和该第四MOS管224的源极相连，该第一MOS管221的源极与第一输入端225相连，该第二MOS管222的源极与第二输入端226相连，该第一输入端225的电压为图3中的Vdda，该第二输入端226的电压为图3中的Vddb，即，第一输入端225连接到供电电路，第二输入端226连接到负载电路，该第二MOS管222的漏极与该第四MOS管224的漏极与第一输出端227相连，或者说第二MOS管222的漏极与该第四MOS管224的漏极相互连接并作为第一输出端227，该第一输出端的输出电压为Vo，该开关电阻单元110的第三端与该第一输出端227相连，且该开关电阻单元210受第一输出端227的输出电压Vo控制。
需要说明的是，电路图中的箭头方向为电流方向，并不用来限制MOS管的类型，在图4中，该第一MOS管121和第二MOS管122分别为PMOS管，该第三MOS管123和第四MOS管124分别为NMOS管。
下面将结合图3或图4说明本申请实施例的逆流开关的工作原理。
可选地，在设计本申请实施例的逆流开关时，应尽可能地按照以下规则选择MOS管：当第一输入端125的电压等于第二输入端126的电压时，即Vdda＝Vddb，第二MOS管122/222与第一MOS管121/221的电流比可以与第四MOS管124/224与第三MOS管123/223的电流比相等。
为了方便描述，在以下实施例中，可以假设第四MOS管的电流大于第二MOS管的电流时的第一输出端的电压Vo为低电平，第四MOS管的电流小于第二MOS管的电流时的第一输出端的电压Vo为高电平。
例如，当Vdda＝Vddb时，该第二MOS管122/222与第一MOS管121/221的电流比以及第四MOS管124/224与第三MOS管123/223的电流比均为1，由于第一MOS管121/221和第三MOS管123/223串联，第一MOS管121/221和第三MOS管123/223的电流相等且将其设为I1，将第二MOS管122/222的电流设为I2，由于Vdda＝Vddb，故I1＝I2。由于电流比为1，那么第四MOS管124/224的电流也为I1。在Vdda增大，Vddb不变的情况下，I1增大，第四MOS管124/224的电流也增大，此时Vdda的增大导致第一MOS管121/221和第二MOS管122/222的栅极电压增大，从而使得第二MOS管122/222的电流I2减小(Vddb不变)，使得I1大于I2，第一输出端的电压Vo为低电平，并控制开关电阻单元110/210处于导通状态。同样地，在Vdda减小，Vddb不变的情况下，I1减小，第四MOS管124/224的电流也减小，此时Vdda的减小导致第一MOS管121/221和第二MOS管122/222的栅极电压减小，从而使得第二MOS管122/222的电流I2增大(Vddb不变)，使得I1小于I2，第一输出端的电压Vo为高电平，并控制开关电阻单元110/210处于断开状态。
再例如，当Vdda＝Vddb时，该第二MOS管122/222与第一MOS管121/221的电流比以及第四MOS管124/224与第三MOS管123/223的电流比均为2，假设第一MOS管121/221和第三MOS管123/223的电流为1mA，由于电流比为2，那么第二MOS管122/222和第四MOS管124/224的电流均为2mA。在Vdda增大，Vddb不变的情况下，第一MOS管121/221和第三MOS管123/223的电流增大，第四MOS管124/224的电流也增大，即大于2mA，此时Vdda的增大导致第一MOS管121/221和第二MOS管122/222的栅极电压增大，从而使得第二MOS管122/222的电流减小(Vddb不变)，即小于2mA，使得第四MOS管124/224的电流大于第二MOS管的电流， 第一输出端的电压Vo为低电平，并控制开关电阻单元110/210处于导通状态。同样地，在Vdda减小，Vddb不变的情况下，第一MOS管121/221和第三MOS管123/223的电流减小，第四MOS管124/224的电流也减小，即小于2mA，此时Vdda的减小导致第一MOS管121/221和第二MOS管122/222的栅极电压减小，从而使得第二MOS管122/222的电流增大(Vddb不变)，即大于2mA，使得第四MOS管124/224的电流小于第二MOS管122/222的电流，第一输出端的电压Vo为高电平，并控制开关电阻单元110/210处于断开状态。
应理解，上述是以Vddb不变，Vdda增大或减小为例分析逆流开关的工作原理。类似地，Vdda不变，Vddb增大或减小的情况同样适用本申请实施例提供的逆流开关的工作原理，为了简洁，在此不再赘述。
对于本申请实施例中的逆流开关来讲，在导通情况下，开关电阻单元的阻值越小，该开关电阻单元上的压降就越小，为负载电路提供的电压就越高。也就是说，该开关电阻单元的阻值越小越好。而从灵敏度的需求来讲，又需要该开关电阻单元的阻值越大越好，这样就可以提高逆流开关的电流检测精度。因此，本申请实施例的逆流开关还包括：
压控单元，包括压控电阻单元和压控电压产生单元，该压控电阻单元与该开关电阻单元串联在该第一输入端和该第二输入端之间，该压控电压产生单元与该比较器单元并联，该压控电压产生单元包括第二输出端；
在该第一输入端的电压与该第二输入端的电压之差增大时，该第二输出端的电压控制该压控电阻单元的阻值变小；
在该第一输入端的电压与该第二输入端的电压之差减小时，该第二输出端的电压控制该压控电阻单元的阻值增大。
图5是本申请再一实施例的逆流开关的电路示意图。图5是在图3的基础上增加了压控单元。具体地，该压控单元包括压控电阻单元131，由第五MOS管132和第一电阻133组成的压控电压产生单元。其中，该压控电阻单元131与该开关电阻单元110串联在该第一输入端125和该第二MOS管122的源极之间，该第五MOS管132的漏极与该第一电阻133的一端分别与第二输出端134相连，该第二输出端的电压为图5中的Vt。该第五MOS管132的源极与该第二输入端126相连，该第五MOS管132的栅极与该第一MOS管121的栅极相连，该第一电阻133的另一端与该第三MOS管123 的源极相连，该第五MOS管132为PMOS管，该压控电阻单元131受该第二输出端134的电压Vt控制。
图6是本申请再一实施例的逆流开关的电路示意图。图6是在图4的基础上增加了压控单元。具体地，该压控单元包括压控电阻单元231，由第五MOS管232和第一电阻233组成的压控电压产生单元。其中，该压控电阻单元231与该开关电阻单元210串联在该第一输入端225和该第二MOS管222的源极之间，该第五MOS管232的漏极与该第一电阻233的一端分别与第二输出端234相连，该第二输出端的电压为图6中的Vt。该第五MOS管232的源极与该第三MOS管223的源极相连，该第五MOS管232的栅极与该第三MOS管223的栅极相连，该第一电阻233的另一端与第二输入端226相连，该第五MOS管232为NMOS管，该压控电阻单元231受该第二输出端234的电压Vt控制。
下面将以图5或图6分析压控单元的工作原理。在Vdda大于Vddb的情况下，Vo为低电平，开关电阻单元处于导通状态。在Vdda增大，Vddb不变时，由于第五MOS管的栅极与第一MOS管的栅极相连，使得第五MOS管的栅极电压增大，进而第一电阻上的电流就减小了，Vt的电压减小，从而使得压控电阻单元的电阻变小，该开关电阻单元与压控电阻单元串联，在Vdda增大到一定值时，压控电阻单元的阻值远远小于开关电阻单元的导通电阻。若开关电阻单元选用比较小的阻值，就可以满足开关电阻单元导通时，使得第二输入端的电压高的需求。而在开关电阻单元处于导通状态的情况下，Vdda减小，Vddb不变，由于第五MOS管的栅极与第一MOS管的栅极相连，使得第五MOS管的栅极电压减小，进而第一电阻上的电流就增大了，Vt的电压增大，从而使得压控电阻单元的阻值逐渐变大，那么在Vdda小于Vddb之前该压控电阻单元的阻值逐渐增大使得逆流开关的检测精度得到了提高。因此，增加了压控单元的逆流开关的压差随逆流开关的电流的变化不再是一种线性变化。
可选地，在本申请实施例中，该开关电阻单元110/210可以由图7中的第六MOS管111/211和第二电阻112/212串联组成，其中第六MOS管的栅极电压可以由第一输出端的输出电压Vo提供。在接入到图3-6任意实施例中时，第六MOS管的漏极连接到第一输入端，源极连接到第二输入端(图3、4的实施例)或者压控电阻单元(图5、6的实施例)。
举例说明，图8示出了将图7中的开关电阻单元应用到图3中的电路示意图。如图7所示，该第六MOS管111的漏极与第一输入端125相连，该第六MOS管111的源极与第二电阻112的一端相连，该第二电阻112的另一端与第二输入端126相连，该第六MOS管111的栅极受第一输出端127的输出电压Vo控制，其余连接关系请参照图3。
可选地，在本申请实施例中，该压控电阻单元131/231可以由图9中的第七MOS管135/235和第三电阻136/236并联组成。其中第七MOS管的栅极电压可以由第二输出端的电压Vt提供。
举例说明，图10示出了将图7中的开关电阻单元以及将图9中的压控电阻单元应用到图5中的电路示意图。如图10所示，该第六MOS管111的漏极与第一输入端125相连，该第六MOS管111的源极与第二电阻112的一端相连，该第二电阻112的另一端与第七MOS管135与第三电阻136并联的一端相连，该第七MOS管135与第三电阻136并联的另一端与第二输入端126相连，该第六MOS管111的栅极受第一输出端127的输出电压Vo控制，该第七MOS管135的栅极受第二输出端134的输出电压Vt的控制，其余连接关系请参照图5。
下面将结合图10进一步地分析本申请实施例提供的逆流开关的工作原理。
当Vdda大于Vddb时，Vo输出为低电平，第六MOS管处于导通状态，由Vt控制的压控电阻单元的阻值为第七MOS管与第三电阻并联的阻值。当Vdda继续增大时，该Vt减小，从而使得第七MOS管和第三电阻并联的阻值减小，在某一时刻，该第七MOS管和第三电阻并联的阻值减小到远小于开关电阻单元的阻值，那么开关电阻单元与压控电阻单元的阻值之和为该第二电阻的阻值(开关电阻单元导通时的阻值为第二电阻的阻值)。当Vdda减小时，该Vt增大，使得第七MOS管和第三电阻并联的阻值增大，在从Vdda大于Vddb翻转为Vdda小于Vddb之前，该第七MOS管和第三电阻并联的阻值远大于开关电阻单元的阻值，那么开关电阻单元与压控电阻单元的阻值之和为该压控电阻单元的阻值。
需要说明的是，在Vdda增大，而Vddb减小的情况下，Vt同样是减小的，那么此时压控电阻单元的阻值是逐渐减小的；在Vdda减小，而Vddb增大的情况下，Vt同样是增大的，那么此时压控电阻单元的阻值是逐渐增大 的。换句话说，在第一输入端和第二输入端的压差增大时，压控电阻单元的阻值是逐渐减小的，在第一输入端和第二输入端的压差减小时，压控电阻单元的阻值是逐渐增大的。
可选地，本申请实施例的逆流开关也可以不用增加压控电阻单元，可以选择可调电阻作为开关电阻单元。
需要说明的是，在本申请实施例中，当第一输入端与第二输入端的电压相等时，第一输出端的电压可以控制开关电阻单元处于导通状态，也可以控制开关电阻单元处于断开状态。换句话说，在第一输入端输入端与第二输入端的电压相等时，第一输出端的电压可以为低电平也可以为高电平。
图11示出了本申请实施例的逆流开关的功能框图。具体地，如图11所示，该逆流开关300包括：开关电阻单元310以及比较器单元320。可选地，该逆流开关还包括：压控单元330和迟滞产生单元340；在该第一输入端的电压大于该第二输入端的电压时，该迟滞产生单元增加该第四MOS管的电流或减小该第二MOS管的电流；在该第一输入端的电压小于该第二输入端的电压时，该迟滞产生单元减小该第四MOS管的电流或增加该第二MOS管的电流。
这样做的好处是可以提供一定的迟滞范围，该逆流开关不会受临界点的扰动而频繁翻转。
具体地，该第四MOS管可以由多个子MOS管组成，并且该多个子MOS管的源极都与第三MOS管的源极相连，该多个子MOS管的漏极都与第二MOS管的漏极相连，该多个子MOS管的栅极由迟滞产生单元控制与偏置单元或者地相连。举例来说，如图12所示，图3中的第四MOS管124由10个子MOS管1240～1249组成，该每个子MOS管的电流可以为第四MOS管124的电流的1/10，该10个子MOS管1240～1249的源极都与第三MOS管123的源极相连，该10个子MOS管1240～1249的漏极都与第二MOS管122的漏极相连，该10个子MOS管1240～1249的栅极由迟滞产生单元控制与偏置单元Vbn或者地GND相连，其余连接关系可参考图3。假设逆流开关翻转的临界点电压Vo为2V，而该逆流开关受到的扰动为0.1V，在某一时刻，Vdda大于Vddb，迟滞产生单元控制第四MOS管124中的子MOS管
1240～1244的栅极与Vbn相连，而子MOS管1245～1249的栅极与GND相连，并且Vo接近2V，迟滞产生单元可以通过控制子MOS管1245～1249中 的3份子MOS管1245～1247的栅极与Vbn相连，将该Vo降低为1.8V，也就是说，0.1V的扰动已经不足以使Vo在临界点2V翻转。同样地，在某一时刻，Vdda小于Vdda，第四MOS管124中的子MOS管1240～1244的栅极与Vbn相连，而子MOS管1245～1249的栅极与GND相连，并且Vo接近2V，迟滞产生单元可以通过控制子MOS管1240～1244中的3份子MOS管1240～1242的栅极与GND相连，将该Vo增大为2.2V，同样地，0.1V的扰动已经不足以使Vo在临界点2V翻转。那么该迟滞产生单元产生的迟滞范围为1.8～2.2V。应理解，该迟滞范围的产生可以基于该逆流开关受到的扰动大小设计。
可选地，在本申请实施例中，还可以通过调节该比较器单元中的其他MOS管的电流，以产生一定的迟滞范围。例如，可以将图4或图6中的第二MOS管由10个子MOS管替换，该每个子MOS管的电流可以为图4或图6中的第二MOS管的电流的1/10，同样地，假设逆流开关翻转的临界点电压Vo为2V，而该逆流开关受到的扰动为0.1V，在某一时刻，Vdda大于Vddb，5份子MOS管的栅极与Vbp相连，另外5份子MOS管的栅极与GND相连，并且Vo接近2V，迟滞产生单元可以通过控制接偏置单元的那5份子MOS管中的3份子MOS管的栅极与GND相连，将该Vo降低为1.8V，也就是说，0.1V的扰动已经不足以使Vo在临界点2V翻转。同样地，在某一时刻，Vdda小于Vdda，5份子MOS管的栅极与Vbp相连，另外5份子MOS管的栅极与GND相连，并且Vo接近2V，迟滞产生单元可以通过控制接GND的那5份子MOS管中的3份子MOS管的栅极与Vbp相连，将该Vo增大为2.2V，同样地，0.1V的扰动已经不足以使Vo在临界点2V翻转。那么该迟滞产生单元产生的迟滞范围为1.8～2.2V。
需要说明的是，迟滞产生单元还可以通过调整比较器单元中的其他MOS管的电流以产生一定的迟滞范围。本申请实施例并不限于上述技术方案。
可选地，该迟滞产生单元可以通过选择器来实现。例如，可以将图11中的子MOS管的栅极连接二选一的选择器，该选择器受第一输出端的电压Vo控制。
可选地，如图11所示，该逆流开关300还包括失调校正单元350。
通常，由第一MOS管、第二MOS管、第三MOS管以及第四MOS管组成的比较器单元可能会有失调，例如，在Vdda-Vos<Vddb的情况下，该逆 流开关才会断开。其中Vos可以看成该比较器单元的失调电压，在逆流开关关闭时，Vos与Vdda和Vddb之间的阻值之比就是未能检测到的盲区电流。Vos通常可能达到100mV，若Vdda与Vddb之间的阻值为1kΩ，那么将有100uA的盲区电流，这是该逆流开关无法忍受的。因此，本申请实施例的逆流开关还可以包括：失调校正单元；在该第一输入端的电压与该第二输入端的电压相等时，该失调校正单元对该逆流开关进行失调校正。
具体地，可以与开关电阻单元并联一个复位开关，或者与开关电阻单元和压控电阻单元并联一个复位开关，在该复位开关闭合时，可以使得Vdda与Vddb的电压相等，在此情况下，可以通过微调第三MOS管和第四MOS管的物理尺寸，例如，宽长比，使得该第四MOS管与第三MOS管的电流之比尽量与第二MOS管与第一MOS管的电流之比相等。或者也可以通过微调第二MOS管和第一MOS管的物理尺寸，使得该第二MOS管与第一MOS管的电流之比尽量与第四MOS管与第三MOS管的电流之比相等。或者也可以同时调整该比较器单元中的任何MOS管的物理尺寸，使之满足上述要求，通过对逆流开关的失调校正，可以极大地减小逆流检测的盲区。
可选地，在本申请实施例中，该第一输入端与供电电路相连，该第二输入端与负载电路相连；在该第一输入端的电压大于该第二输入端的电压时，该逆流开关关闭，该供电电路为该负载电路与该供电电路之间的储能电容充电；在该第一输入端的电压小于该第二输入端的电压时，该逆流开关断开，该储能电容向该负载电路放电。
可选地，该供电电路为线控耳机，该负载电路为心率传感器。
正如前面所述，该逆流开关并不限于在线控耳机供电的场景，可以适用于任何供电系统，例如弱供电系统。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及电路，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应 用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的电路、支路和单元，可以通过其它的方式实现。例如，以上所描述的支路是示意性的，例如，该单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到一个支路，或一些特征可以忽略，或不执行。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以该权利要求的保护范围为准。

Claims (13)

  1. 一种逆流开关，其特征在于，所述逆流开关包括：
    比较器单元，包括第一输入端、第二输入端和第一输出端；
    开关电阻单元，所述开关电阻单元的第一端与所述第一输入端相连，所述开关电阻单元的第二端与所述第二输入端相连，所述开关电阻单元的第三端与所述第一输出端相连，且所述开关电阻单元受控于所述第一输出端的电压；
    在所述第一输入端的电压大于所述第二输入端的电压时，所述第一输出端的电压控制所述开关电阻单元处于导通状态；
    在所述第一输入端的电压小于所述第二输入端的电压时，所述第一输出端的电压控制所述开关电阻单元处于断开状态。
  2. 根据权利要求1所述的逆流开关，其特征在于，所述逆流开关还包括：
    压控单元，包括压控电阻单元和压控电压产生单元，所述压控电阻单元与所述开关电阻单元串联在所述第一输入端和所述第二输入端之间，所述压控电压产生单元与所述比较器单元并联，所述压控电压产生单元包括第二输出端；
    在所述第一输入端的电压与所述第二输入端的电压之差增大时，所述第二输出端的电压控制所述压控电阻单元的阻值变小；
    在所述第一输入端的电压与所述第二输入端的电压之差减小时，所述第二输出端的电压控制所述压控电阻单元的阻值增大。
  3. 根据权利要求1或2所述的逆流开关，其特征在于，所述比较器单元包括：
    第一MOS管、第二MOS管、第三MOS管和第四MOS管，所述第一MOS管的栅极和所述第二MOS管的栅极相连，所述第三MOS管的栅极和所述第四MOS管的栅极相连且所述第三MOS管的源极和所述第四MOS管的源极相连，所述第一MOS管的漏极与所述第三MOS管的漏极相连，所述第二MOS管的漏极与所述第四MOS管的漏极分别与所述第一输出端相连，所述第一MOS管的源极与所述第一输入端相连，所述第二MOS管的源极与所述第二输入端相连。
  4. 根据权利要求3所述的逆流开关，其特征在于，所述第一MOS管和 所述第二MOS管为PMOS管，所述第三MOS管和所述第四MOS管为NMOS管，所述第三MOS管的栅极和所述第四MOS管的栅极分别与偏置单元相连，所述第一MOS管的源极与所述第一MOS管的漏极相连。
  5. 根据权利要求3所述的逆流开关，其特征在于，所述第一MOS管和所述第二MOS管为PMOS管，所述第三MOS管和所述第四MOS管为NMOS管，所述第一MOS管的栅极和所述第二MOS管的栅极分别与偏置单元相连，所述第三MOS管的源极与所述第三MOS管的漏极相连。
  6. 根据权利要求4所述的逆流开关，其特征在于，所述逆流开关还包括：
    压控单元，包括压控电阻单元和压控电压产生单元，所述压控电阻单元与所述开关电阻单元串联在所述第一输入端和所述第二MOS管的源极之间，所述压控电压产生单元包括第二输出端，所述压控电压产生单元包括第五MOS管和第一电阻，所述第五MOS管为PMOS管，所述第五MOS管的漏极与所述第一电阻的一端分别与所述第二输出端相连，所述第五MOS管的源极与所述第二输入端相连，所述第五MOS管的栅极与所述第一MOS管的栅极相连，所述第一电阻的另一端与所述第三MOS管的源极相连，所述压控电阻单元受所述第二输出端的电压控制。
  7. 根据权利要求5所述的逆流开关，其特征在于，所述逆流开关还包括：
    压控单元，包括压控电阻单元和压控电压产生单元，所述压控电阻单元与所述开关电阻单元串联在所述第一输入端和所述第二MOS管的源极之间，所述压控电压产生单元包括第二输出端，所述压控电压产生单元包括第五MOS管和第一电阻，所述第五MOS管为NMOS管，所述第五MOS管的漏极与所述第一电阻的一端分别与所述第二输出端相连，所述第一电阻的另一端与所述第二输入端相连，所述第五MOS管的栅极与所述第三MOS管的栅极相连，所述第五MOS管的源极与所述第三MOS管的源极相连，所述压控电阻单元受所述第二输出端的电压控制。
  8. 根据权利要求3至7中任一项所述的逆流开关，其特征在于，所述逆流开关还包括：
    迟滞产生单元；
    在所述第一输入端的电压大于所述第二输入端的电压时，所述迟滞产生 单元增加所述第四MOS管的电流和/或减小所述第二MOS管的电流；
    在所述第一输入端的电压小于所述第二输入端的电压时，所述迟滞产生单元减小所述第四MOS管的电流和/或增加所述第二MOS管的电流。
  9. 根据权利要求1至8中任一项所述的逆流开关，其特征在于，所述逆流开关还包括：
    失调校正单元；
    在所述第一输入端的电压与所述第二输入端的电压相等时，所述失调校正单元对所述逆流开关进行失调校正。
  10. 根据权利要求1至9中任一项所述的逆流开关，其特征在于，所述开关电阻单元由第六MOS管与第二电阻串联构成，所述第六MOS管的栅极受所述第一输出端的电压控制。
  11. 根据权利要求2、6和7中任一项所述的逆流开关，其特征在于，所述压控电阻单元由第七MOS管与第三电阻并联构成，所述第七MOS管的栅极受所述第二输出端的电压控制。
  12. 根据权利要求1至11中任一项所述的逆流开关，其特征在于，所述第一输入端与供电电路相连，所述第二输入端与负载电路相连；
    在所述第一输入端的电压大于所述第二输入端的电压时，所述供电电路为所述负载电路与所述供电电路之间的储能电容充电；
    在所述第一输入端的电压小于所述第二输入端的电压时，所述储能电容向所述负载电路放电。
  13. 根据权利要求12所述的逆流开关，其特征在于，所述供电电路为线控耳机，所述负载电路为心率传感器。
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