WO2020038406A1 - Wake-up circuit and battery management system - Google Patents

Abstract

A wake-up circuit and a battery management system, relating to the technical field of batteries. The wake-up circuit comprises: a switch circuit (30) comprising a switch input end (301) and a switch output end (302); a signal regulating circuit (10) comprising a signal input end (101) and a signal output end (102), the signal input end (101) of the signal regulating circuit (10) being connected to the switch output end (302) of the switch circuit (30), when an external power source being supplied to the switch input end (301) of the switch circuit (30), the switch circuit (30) working in a turn-on state to enable the external power source to be supplied to the signal input end (101) of the signal regulating circuit (10), and the signal regulating circuit (10) converting the external power source into a level trigger signal; and a charging and discharging circuit (20) connected to the signal output end (102) of the signal regulating circuit (10), and after the charging and discharging circuit (20) receives the level trigger signal, the charging and discharging circuit (20) entering an awake state. The present system can reduce potential safety hazards, thereby increasing the service life of a battery pack.

Description

Wake circuit and battery management system

Cross-reference to related applications

This application claims priority from a Chinese patent application with an application number of 201810974231.0 and an application date of August 24, 2018, the entire contents of which are incorporated herein by reference.

Technical field

The invention relates to the technical field of batteries, and in particular to a wake-up circuit and a battery management system.

Background technique

Battery Management System (BMS) is a system that manages the battery or battery pack. It usually has the ability to measure the battery pack voltage, manage the charge and discharge of the battery pack, and prevent or avoid abnormal conditions (overdischarge, overcharge, and overtemperature). Etc.) appeared. When the battery pack is in an unused or non-working state, usually in order to reduce power consumption, in order to reduce the loss of battery power, especially to avoid overdischarge damage to the battery pack when the remaining capacity of the battery pack is small, the battery Management systems usually enter low-power states, such as hibernation. Sometimes the battery management system even goes into deep sleep. When the battery management system enters the sleep state, the charge / discharge circuit or module for managing the battery pack in the battery management system will also be in the sleep state. After the charging and discharging circuit is in the sleep state, if the battery pack needs to be used normally, for example, the battery pack supplies power to external devices or the external device charges the battery pack, the charging or discharging circuit or module used to manage the battery pack must be awakened first, otherwise charging and discharging The circuit or module will always be in a sleep state, making the battery unable to work normally.

At present, the usual wake-up method is to wake up the charging and discharging circuit or module by detecting the current to charge and discharge the battery pack. For example, taking the charging of a battery pack as an example, when a charging current is detected, the charging and discharging circuit is awakened to charge the battery pack; when no charging current is detected, the charging and discharging circuit remains dormant until it is detected When charging current, the charging and discharging circuit is awakened to charge the battery pack.

In the process of implementing the present invention, the inventors found that the related art has at least the following problems: the method of detecting the current to wake up the charging and discharging circuit, because the current is to be detected, it is necessary to ensure that the current detected by the battery management system during sleep The path flowing through is continual, and this continuity can cause problems such as safety hazards during sleep. For example, when the battery pack is in a sleep state, the continuity may cause the battery pack to be discharged in the reverse direction to damage the battery pack.

Summary of the Invention

The purpose of the embodiments of the present invention is to provide a wake-up circuit and a battery management system, which can reduce potential safety hazards and thereby improve the service life of a battery pack.

To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

In a first aspect, an embodiment of the present invention provides a wake-up circuit, including:

A switching circuit, including a switch input terminal and a switch output terminal;

The signal conditioning circuit includes a signal input terminal and a signal output terminal. The signal input terminal of the signal conditioning circuit is connected to the switch output terminal of the switch circuit. When an external power source is applied to the switch input terminal of the switch circuit, the signal conditioning circuit The switching circuit works in a conducting state, so that the external power is applied to a signal input terminal of the signal conditioning circuit, and the signal conditioning circuit converts the external power into a level trigger signal;

The charge and discharge circuit is connected to the signal output terminal of the signal conditioning circuit. When the charge and discharge circuit receives the level trigger signal, the charge and discharge circuit enters an awake state.

In some embodiments, the level trigger signal is a high-level signal.

In some embodiments, the signal conditioning circuit includes a first voltage-dividing circuit, the first voltage-dividing circuit includes a first voltage-dividing input terminal and a first voltage-dividing output terminal, and the first voltage-dividing input terminal and the The switch output terminal is connected, and the first voltage-dividing output terminal is connected to the charging and discharging circuit;

The first voltage dividing circuit is configured to divide an external power source applied to a signal input terminal of the signal conditioning circuit to convert the external power source into a level trigger signal.

In some embodiments, the first voltage dividing circuit includes a first resistor and a second resistor;

One end of the first resistor is connected to the switch output terminal as the first voltage-dividing input terminal, the other end of the first resistor is connected to one end of the second resistor, and the The other end and one end of the second resistor are connected to the charging and discharging circuit as the first voltage-dividing output end;

The other end of the second resistor is grounded.

In some embodiments, the first voltage dividing circuit further includes a first voltage stabilizing tube, and a cathode of the first voltage stabilizing tube is connected to a first voltage dividing output terminal of the first voltage dividing circuit. The anode of a Zener tube is grounded.

In some embodiments, the charging and discharging circuit includes:

An analog front end includes an analog input end and an analog output end, and the analog input end is connected to a signal output end of the signal conditioning circuit;

A charge and discharge control circuit includes a charge and discharge input terminal and a charge and discharge output terminal, the charge and discharge input terminal is connected to the analog output terminal, and the charge and discharge output terminal is used to connect a battery pack;

When the level trigger signal is input to the analog front end, the analog front end enters an awake state, and the analog front end controls the charge and discharge of the battery pack by driving the charge and discharge control circuit.

In some embodiments, the charge and discharge control circuit includes a discharge control circuit and a charge control circuit, the discharge control circuit includes a discharge input control terminal, the charge control circuit includes a charge input control terminal, the discharge input control terminal and The charging input control terminal is connected to an analog output terminal of the analog front end;

The discharge control circuit and the charge control circuit are connected in series between a total negative terminal of the battery pack and an output negative electrode of the battery pack.

In some embodiments, the analog output end of the analog front end includes a first drive output end and a second drive output end;

The discharge control circuit includes a first MOS tube, and the charge control circuit includes a second MOS tube;

The gate of the first MOS tube is connected to the first driving output terminal, the source of the first MOS tube is connected to the total negative terminal of the battery pack through a detection resistor, and the source of the first MOS tube is The electrode is also grounded through a detection resistor, the drain of the first MOS transistor is connected to the drain of the second MOS transistor, the gate of the second MOS transistor is connected to the second driving output terminal, and the second MOS The source of the tube is connected to the output negative of the battery pack;

When the analog front end enters the awake state, the first MOS transistor and the second MOS transistor are turned on to make the battery pack enter a charging state.

In some embodiments, the switching circuit includes a second voltage dividing circuit, a third MOS transistor, and a fourth MOS transistor;

The second voltage-dividing circuit includes a second voltage-dividing input terminal, a second voltage-dividing output terminal, and a voltage-dividing input control terminal, and the second voltage-dividing input terminal is used to connect to the output positive electrode of the battery pack;

The gate of the third MOS tube is grounded via a third resistor, the source of the third MOS tube is connected to the output negative electrode of the battery pack, and the drain of the third MOS tube is connected to the second divided voltage. Output connection

The gate of the fourth MOS transistor is connected to the voltage dividing input control terminal, the source of the fourth MOS transistor is connected to the second voltage dividing input terminal, and the drain of the fourth MOS transistor is connected to all The signal input terminal of the signal conditioning circuit is connected;

When an external power source is applied to the switch input terminal of the switch circuit, the third MOS transistor and the fourth MOS transistor are turned on.

In some embodiments, the second voltage dividing circuit includes a fourth resistor and a fifth resistor,

One end of the fourth resistor is connected to the source of the fourth MOS transistor as the second divided voltage input terminal, the other end of the fourth resistor is connected to one end of the fifth resistor, and the The other end of the fourth resistor and one end of the fifth resistor are connected to the gate of the fourth MOS transistor as the voltage-dividing input control terminal;

The other end of the fifth resistor is connected to the drain of the third MOS transistor as the second divided voltage output terminal.

In some embodiments, the switching circuit further includes a second Zener tube, a cathode of the second Zener tube is connected to a gate of the third MOS tube, and an anode of the second Zener tube is connected to all The source connection of the third MOS transistor is described.

In some embodiments, the switching circuit further includes a third Zener tube, a cathode of the third Zener tube is connected to a source of the fourth MOS tube, and an anode of the third Zener tube is connected to all The gate connection of the fourth MOS transistor is described.

In a second aspect, an embodiment of the present invention provides a battery management system including the wake-up circuit as described above.

In various embodiments of the present invention, when an external power source is applied to the switch input terminal of the switch circuit, the switch circuit works in a conducting state, so that the external power source is applied to the signal input terminal of the signal conditioning circuit, and the external power source is applied through the signal conditioning circuit. The signal is converted to a level trigger signal and sent to the charge and discharge circuit. After the charge and discharge circuit receives the level trigger signal, the charge and discharge circuit can enter the awake state without having to wake up the charge and discharge circuit by detecting the current, which can reduce potential safety hazards. In order to increase the life of the battery pack.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplified by the pictures in the accompanying drawings. These exemplary descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the drawings in the drawings do not constitute a limitation on scale.

FIG. 1 is a schematic circuit configuration diagram of a wake-up circuit according to an embodiment of the present invention;

2 is a schematic diagram of a specific circuit structure of a wake-up circuit according to an embodiment of the present invention;

3 is a specific circuit diagram of a wake-up circuit provided by an embodiment of the present invention;

4 is a schematic diagram of a signal conditioning circuit in FIG. 1;

5 is a schematic diagram of the charge and discharge circuit in FIG. 1;

6 is a schematic diagram of a switching circuit in FIG. 1;

FIG. 7 is a schematic diagram of a battery management system according to an embodiment of the present invention.

detailed description

In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Obviously, the described embodiments are a part of embodiments of the present invention, but not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that when an element is referred to as being “fixed to” another element, it may be directly on the other element or there may be a centered element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and are not meant to be the only implementations.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

FIG. 1 is a schematic diagram of a wake-up circuit provided by an embodiment of the present invention. The wake-up circuit 100 includes a signal conditioning circuit 10, a charge-discharge circuit 20 and a switch circuit 30. The switching circuit 30 is connected to the signal conditioning circuit 10, and the signal conditioning circuit 10 is connected to the charge and discharge circuit 20.

Specifically, the switch circuit 30 includes a switch input terminal 301 and a switch output terminal 302; the signal conditioning circuit 10 includes a signal input terminal 101 and a signal output terminal 102. The signal input terminal 101 of the signal conditioning circuit 10 is connected to the switch output terminal 302 of the switch circuit 30, and the signal output terminal 102 of the signal conditioning circuit 10 is connected to the charge and discharge circuit 20.

When an external power source is applied to the switch input terminal 301 of the switch circuit 30, the switch circuit 30 operates in a conducting state, so that the external power source is applied to the signal input terminal 101 of the signal conditioning circuit 10, and the signal conditioning circuit 10 converts the external power source into a level The trigger signal is sent to the charge and discharge circuit 20. When the charge and discharge circuit 20 receives the level trigger signal, the charge and discharge circuit 20 enters the awake state so that the battery pack can be charged and discharged.

The external power source may be an external power source voltage or an external power source current. In addition, an external device can be connected to implement an external power supply to the switching input terminal 301 of the switching circuit 30. For example, taking charging of a battery pack as an example, a charger can be connected to implement the switching input to the switching circuit 30. The terminal 301 applies external power.

In the embodiment of the present invention, there is no need to wake up the charging and discharging circuit by detecting the current, so that the safety hazard can be reduced, so as to improve the service life of the battery pack.

The wake-up circuit 100 and the signal conditioning circuit 10, the charge-discharge circuit 20, and the switch circuit 30 in the wake-up circuit 100 according to the embodiments of the present invention will be described in detail below with reference to FIGS. 2 to 6. 2 is a schematic diagram of a specific structure of a wake-up circuit according to an embodiment of the present invention; FIG. 3 is a specific circuit diagram of a wake-up circuit provided by an embodiment of the present invention; FIG. 4 is a schematic diagram of a signal conditioning circuit; and FIG. 5 is a schematic diagram of a charging and discharging circuit ; Figure 6 is a schematic diagram of a switching circuit.

Please refer to FIGS. 2 to 4. The signal conditioning circuit 10 includes a first voltage dividing circuit 103. The first voltage dividing circuit 103 includes a first voltage dividing input terminal 1031 and a first voltage dividing output terminal 1032. The first voltage-dividing input terminal 1031 of the first voltage-dividing circuit 103 is connected to the switching output terminal 302 of the switching circuit 30. The first voltage-dividing output terminal 1032 of the first voltage-dividing circuit 103 is connected to the charge-discharge circuit 20. For example, the first voltage-dividing output terminal 1032 of the first voltage-dividing circuit 103 is connected to the input terminal of the charge-discharge circuit 20.

The first voltage dividing circuit 103 is used to divide the external power applied to the signal input terminal 101 of the signal conditioning circuit 10 to convert the external power into a level trigger signal.

In some implementations, the first voltage dividing circuit 103 includes a first resistor R1 and a second resistor R2. The first resistor R1 and the second resistor R2 are connected in series.

Specifically, one end of the first resistor R1 is connected to the switch output terminal 302 of the switch circuit 30 as a first voltage-dividing input terminal 1031, and the other end of the first resistor R1 is connected to one end of the second resistor R2. In addition, the other end of the first resistor R1 and one end of the second resistor R2 are connected to the charge / discharge circuit 20 as a first voltage-dividing output terminal 1032. The other end of the second resistor R2 is grounded to GND.

In some other embodiments, the first voltage dividing circuit 103 may also be other suitable voltage dividing circuits, as long as the external power applied to the signal input terminal 101 of the signal conditioning circuit 10 can be divided to convert the external power. The function of level trigger signal is sufficient. For example, a voltage divider circuit composed of three or more resistors connected in series.

In addition, the external power applied to the signal input terminal 101 of the signal conditioning circuit 10 is converted into a level trigger signal after the voltage is divided by the first voltage dividing circuit 103, which may be a high-level signal. The high-level signal refers to a level signal of logic "1". The high-level signal can trigger the charging and discharging circuit 20 to enter the awake state.

In some implementations, the signal conditioning circuit 10 further includes a first voltage regulator D1. The cathode of the first voltage regulator D1 is connected to the first voltage-dividing output terminal 1032 of the first voltage divider circuit 103, and the anode of the first voltage regulator D1 is grounded to GND.

The first voltage regulator D1 is used for voltage stabilization to ensure the stability of the level trigger signal input to the charge and discharge circuit 20. The first Zener diode D1 may be a Zener diode or the like. In addition, the voltage stabilization value of the first voltage regulator D1 is slightly larger than the voltage division value of the first resistor R1 and the second resistor R2 and does not exceed the withstand voltage value of the input terminal of the charge and discharge circuit 20.

Referring to FIG. 2, FIG. 3 and FIG. 5, the charging and discharging circuit 20 includes: an analog front end 203 and a charging and discharging control circuit 204. The analog front end 203 is connected to the charge and discharge control circuit 204.

The analog front end 203 includes an analog input terminal 2031 and an analog output terminal 2032. The charge-discharge control circuit 204 includes a charge-discharge input terminal 2041 and a charge-discharge output terminal 2042.

The analog input terminal 2031 of the analog front end 203 is connected to the signal output terminal 102 of the signal conditioning circuit 10. An analog output terminal 2032 of the analog front end 203 is connected to a charge / discharge input terminal 2041 of the charge / discharge control circuit 204. The analog front end 203 is used to control the charge and discharge control circuit 204.

For a battery management system, the analog front end 203 may be various suitable battery management chips. For example, the analog front end 203 may be a BQ769X0 series (such as BQ76920, BQ76930, BQ76940, etc.) battery management chips. The external power is divided by the first voltage dividing circuit 103 and combined with the voltage stabilization of the first voltage regulator D1, so that the input terminal (TS1 port) of the BQ769X0 chip can receive a high-level signal of 3.3V, thereby awakening the BQ769X0 chip . Among them, in order to protect the BQ769X0 chip, the voltage stabilization value of the first voltage regulator D1 does not exceed the withstand voltage value of the TS1 port of the BQ769X0 chip.

The charge-discharge input terminal 2041 of the charge-discharge control circuit 204 is connected to the analog output terminal 2032 of the analog front-end 203. The charge-discharge output terminal 2042 of the charge-discharge control circuit 204 is used to connect the battery pack to control the charge and discharge of the battery pack. The battery pack may be composed of multiple batteries connected in series.

When the signal conditioning circuit 10 inputs a level trigger signal to the analog front end 203, the analog front end 203 enters the awake state. After the analog front end 203 enters the awake state, the analog front end 203 controls the charge and discharge of the battery pack by driving the charge and discharge control circuit 204.

In the embodiment of the present invention, since the analog front end 203 enters the awake state by directly receiving the level trigger signal sent by the signal conditioning circuit 10, the charge / discharge control circuit 204 is driven, and the charge / discharge circuit 20 enters the awake state. By sending a control instruction through a microprocessor (such as an MCU, etc.) to wake up the analog front-end and then wake up the charging and discharging circuit. The wake-up circuit 100 provided by the embodiment of the present invention can prevent the microprocessor program from running, flying, crashing, latching and other failures. Caused by unawakened problems.

It should be noted that, in some other embodiments, the wake-up circuit 100 or the charging / discharging circuit 20 in the wake-up circuit 100 may also include a microprocessor (not shown). When the wake-up circuit 100 or the charging / discharging circuit 20 in the wake-up circuit 100 includes a microprocessor, the input terminal of the microprocessor is connected to the signal output terminal 102 of the signal conditioning circuit 10 to receive the level trigger signal sent by the signal conditioning circuit 10 And, the output end of the microprocessor is connected to the analog input end 2031 of the analog front end 203. After the microprocessor receives the level trigger signal, it sends a control instruction to the analog front end 203, so as to control the analog front end 203 to enter the awake state, and then The analog front end 203 controls the charge and discharge of the battery pack by driving the charge and discharge control circuit 204.

In some implementations, the charge and discharge control circuit 204 includes a discharge control circuit 2043 and a charge control circuit 2044. The discharge control circuit 2043 includes a discharge input control terminal 20431, and the charge control circuit 2044 includes a charge input control terminal 20441. The discharge input control terminal 20431 and the charge input control terminal 20441 are connected to the analog output terminal 2032 of the analog front end 203.

The analog output terminal 2032 of the analog front end 203 may include a first drive output terminal 20321 or a second drive output terminal 20322 to be connected to the corresponding discharge input control terminal 20431 or the charge input control terminal 20441, respectively.

Specifically, the first drive output terminal 20321 is connected to the discharge input control terminal 20431, and the second drive output terminal 20322 is connected to the charge input control terminal 20441. For example, the analog front end 203 uses a BQ769X0 chip as an example. The first driving output terminal 20321 is specifically a DSG pin of the BQ769X0 chip, and the second driving output terminal 20322 is specifically a CHG pin of the BQ769X0 chip.

The discharge control circuit 2043 and the charge control circuit 2044 are connected in series between the total negative terminal of the battery pack and the output negative electrode of the battery pack. Taking FIG. 2 as an example, the battery pack includes a total positive terminal B +, a total negative terminal B-, an output positive PACK +, and an output negative PACK-. The total positive terminal B + of the battery pack is the highest voltage end of the battery pack, the total negative terminal B- of the battery pack is the lowest voltage end of the battery pack, the positive output terminal PACK + of the battery pack is the positive output terminal of the battery pack, and the negative output terminal of the battery pack PACK- is the negative output terminal of the battery pack. In addition, the output positive PACK + of the battery pack is also the positive charging port of the battery pack, and the output negative PACK- of the battery pack is also the negative charging port of the battery pack.

In some other embodiments, the discharge control circuit 2043 and the charge control circuit 2044 may be connected in series between the total positive terminal B + of the battery pack and the output positive electrode PACK + of the battery pack.

Because the battery pack is composed of multiple batteries connected in series, the voltage of the battery pack is usually high. Therefore, the discharge control circuit 2043 and the charge control circuit 2044 are connected in series at the total negative terminal B of the battery pack and the output negative PACK of the battery pack. Compared with the method in which the discharge control circuit 2043 and the charge control circuit 2044 are connected in series between the positive terminal B + of the battery pack and the positive output terminal PACK + of the battery pack, the former is easier to control the charge and discharge of the battery pack.

In some other embodiments, the discharge control circuit 2043 and the charge control circuit 2044 may also be connected in parallel. In addition, the manner in which the discharge control circuit 2043 and the charge control circuit 2044 are connected in parallel is smaller than the series connection. When the battery pack is charged or discharged, the former consumes less power.

For example, if the discharge control circuit 2043 and the charge control circuit 2044 are connected in series, the current will flow through the discharge control circuit 2043 and the charge control circuit 2044 when the battery pack is charged or discharged, and the power consumption will be relatively large; 2043 is connected in parallel with the charge control circuit 2044. When the battery pack is charged, the charging current does not flow through the discharge control circuit 2043. When the battery pack is discharged, the discharge current does not need to flow through the charge control circuit 2044, and the power consumption is greatly reduced. So as to achieve cost savings.

In some implementations, the discharge control circuit 2043 includes a first MOS tube Q1, and the charge control circuit 2044 includes a second MOS tube Q2. The first MOS transistor Q1 is connected to the first driving output terminal 20321 of the analog front end 203, and the second MOS transistor Q2 is connected to the second driving output terminal 20322 of the analog front end 203.

Specifically, the gate of the first MOS tube Q1 is connected to the first driving output terminal 20321, the source of the first MOS tube Q1 is connected to the total negative terminal B- of the battery pack through a detection resistor RSENSE, and the source of the first MOS tube Q1 is The electrode is also grounded to GND through the detection resistor RSENSE. The drain of the first MOS tube Q1 is connected to the drain of the second MOS tube Q2, the gate of the second MOS tube Q2 is connected to the second drive output terminal 20322, and the second MOS tube Q2 The source is PACK- connected to the output negative pole of the battery pack. Among them, the gate is represented by G, the source is represented by S, and the drain is represented by D.

When the analog front end 203 enters the awake state, the first MOS transistor Q1 and the second MOS transistor Q2 are turned on to make the battery pack enter a charging state. For example, when the first MOS transistor Q1 and the second MOS transistor Q2 are turned on, the charger connected to the output positive PACK + and the output negative PACK- of the battery pack can charge the battery pack.

Referring to FIG. 2, FIG. 3 and FIG. 6, the switching circuit 30 includes a second voltage dividing circuit 303, a third MOS transistor Q3 and a fourth MOS transistor Q4. The second voltage dividing circuit 303 is connected to the third MOS transistor Q3 and the fourth MOS transistor Q4, respectively.

Specifically, the second voltage dividing circuit 303 includes a second voltage dividing input terminal 3031, a second voltage dividing output terminal 3032, and a voltage dividing input control terminal 3033. The second voltage-dividing input terminal 3031 is used to connect to the output positive pole PACK + of the battery pack; the gate of the third MOS transistor Q3 is grounded to GND through a third resistor R3, and the source of the third MOS transistor Q3 and the output negative pole PACK- Connected, the drain of the third MOS transistor Q3 is connected to the second voltage-dividing output terminal 3032 of the second voltage-dividing circuit 303; the gate of the fourth MOS transistor Q4 is connected to the voltage-dividing input control terminal of the second voltage-dividing circuit 303 3033 is connected, the source of the fourth MOS transistor Q4 is connected to the second voltage-dividing input terminal 3031 of the second voltage-dividing circuit 303, and the drain of the fourth MOS transistor Q4 is connected to the signal input terminal 101 of the signal conditioning circuit 10.

The third MOS transistor Q3 may be an N-channel MOS transistor, and the fourth MOS transistor Q4 may be a P-channel MOS transistor.

When an external power source is applied to the switch input terminal 301 of the switch circuit 30, the third MOS transistor Q3 and the fourth MOS transistor Q4 are turned on. After the third MOS transistor Q3 and the fourth MOS transistor Q4 are turned on, an external power source can be applied to the signal input terminal 101 of the signal conditioning circuit 10 to wake up the charge and discharge circuit 20.

In some implementations, the second voltage dividing circuit 303 includes a fourth resistor R4 and a fifth resistor R5. The fourth resistor R4 and the fifth resistor R5 are connected in series.

Specifically, one end of the fourth resistor R4 is connected to the source of the fourth MOS transistor Q4 as the second divided voltage input terminal 3031, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, and the fourth The other end of the resistor R4 and one end of the fifth resistor R5 serve as a voltage-dividing input control terminal 3033 and are connected to the gate of the fourth MOS transistor Q4. The other end of the fifth resistor R4 is used as the second voltage-dividing output terminal 3032 to be connected to the drain of the third MOS transistor Q3.

In some other embodiments, the second voltage dividing circuit 303 may also be other suitable voltage dividing circuits. For example, a voltage divider circuit composed of three or more resistors connected in series.

In some implementations, the switching circuit 30 further includes a second voltage regulator D2. The cathode of the second zener tube D2 is connected to the gate of the third MOS tube Q3, and the anode of the second zener tube D2 is connected to the source of the third MOS tube Q3. The second Zener diode D2 may be a Zener diode or the like. Among them, the voltage stabilization value of the second voltage regulator D2 does not exceed the gate-source withstand voltage value of the third MOS transistor Q3.

In some implementations, the switching circuit 30 further includes a third voltage regulator D3. The cathode of the third zener tube D3 is connected to the source of the fourth MOS tube Q4, and the anode of the third zener tube D3 is connected to the gate of the fourth MOS tube Q4. The third Zener diode D3 may be a Zener diode or the like. Among them, the voltage stabilization value of the third voltage regulator D3 does not exceed the gate-source withstand voltage value of the fourth MOS transistor Q4.

The following is the working principle of the wake-up circuit 100 provided by an embodiment of the present invention:

Please refer to FIG. 2 and FIG. 3, when the battery management system enters the sleep state, the DSG and CHG pins in the BQ769X0 chip output low-level signals, so that the charge and discharge circuit 20 is in the sleep state, that is, the first MOS tube Q1 and the first The two MOS tubes Q2 are turned off. At this time, the output negative pole PACK- of the battery pack is in a floating state (no current flows), and the gate of the third MOS transistor Q3 is grounded to GND through a third resistor R3, and the source of the third MOS transistor Q3 is connected to the battery pack. The output negative PACK- connection, so the third MOS tube Q3 is disconnected, so that the gate and source of the fourth MOS tube Q4 are at the same potential, the fourth MOS tube Q4 is also disconnected, and finally no voltage is input to the BQ769X0 chip. The TS1 port is also grounded to GND, so the input signal of the TS1 port is a low-level signal at this time, so that the BQ769X0 chip is in a sleep state, that is, the charging and discharging circuit 20 is in a sleep state.

When external power is applied when the battery management system is in a sleep state, such as when the charger is connected between the output positive PACK + and the output negative PACK- of the battery pack, since the third MOS tube Q3 and the fourth MOS tube Q4 are both disconnected, Therefore, the output negative pole PACK- of the battery pack is a low potential relative to the ground GND, that is, there is a potential difference between the output negative pole PACK- of the battery pack and the ground, and the potential difference is equal to the output voltage of the charger.

Because of the potential difference, and the gate of the third MOS transistor Q3 is grounded to GND through the third resistor R3, the source of the third MOS transistor Q3 is connected to the output negative electrode PACK- of the battery pack, so that the voltage difference exists in the third MOS transistor. As long as the voltage difference between the gate and source of Q3 is greater than the turn-on voltage of the third MOS transistor Q3, the third MOS transistor Q3 can be turned on.

When the third MOS transistor Q3 is turned on, the output negative pole PACK- connection of the battery pack is used as a reference. The gate voltage of the fourth MOS transistor Q4 is the fourth positive pole PACK + applied to the battery pack by the fourth resistor R4 and the fifth resistor R5. The source voltage of the fourth MOS transistor Q4 is the external power voltage. As long as the gate source of the third MOS transistor Q3 is greater than the turn-on voltage of the fourth MOS transistor Q4, the fourth MOS transistor Q4 can be made. Continuity.

When the fourth MOS transistor Q4 is turned on, the voltage applied to the output positive electrode PACK + of the battery pack is divided by the fourth resistor R4 and the fifth resistor R5 and then input to the first voltage dividing input terminal 1031 of the first voltage dividing circuit 103. That is, one end of the first resistor R1, and then a high-level signal is obtained by dividing the voltage between the first resistor R1 and the second resistor R2, and the high-level signal is input to the TS1 pin of the BQ769X0 chip, so that the BQ769X0 chip Awake.

When the BQ769X0 chip is in the awake state, the DSG and CHG pins in the BQ769X0 chip output high-level signals, so that the charge and discharge circuit 20 is in awake state, that is, the first MOS transistor Q1 and the second MOS transistor Q2 are turned on, thereby The charger starts charging the battery pack.

After the above process, the wake-up function of the wake-up circuit 100 can be realized.

It should be noted that, in some other embodiments, the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 may be implemented by other methods. The devices with the functions of the two MOS transistors Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 are replaced, for example, each of the above MOS transistors is replaced with a transistor.

In the wake-up circuit 100 provided by the embodiment of the present invention, when an external power source is applied to the switch input terminal 301 of the switch circuit 30, the switch circuit 30 operates in a conducting state, so that the external power source is applied to the signal input terminal 101 of the signal conditioning circuit 10, and The signal conditioning circuit 10 converts the external power into a level trigger signal and sends it to the charge and discharge circuit 20. After the charge and discharge circuit 20 receives the level trigger signal, the charge and discharge circuit 20 can enter the awake state without detecting the current. To wake up the charging and discharging circuit, which can reduce potential safety hazards. For example, the safety hazard can be caused by the conduction of the path through which the current detected during hibernation. When the battery pack should be charged, there is a battery pack reaction. Discharge and damage to the battery pack, etc., in order to improve the battery pack life.

Please refer to FIG. 7, which is a battery management system according to an embodiment of the present invention. The battery management system 200 is used to manage various battery packs, such as lithium batteries, nickel-cadmium batteries, or other storage batteries. The battery pack can be used to provide power to various electronic devices, such as aircraft, cars, terminal devices, wearable devices, and so on. The battery pack can also be charged by various devices, such as charging the battery pack through a charger. The battery management system 200 is used to manage the charge and discharge of a battery pack. The battery management system includes the aforementioned wake-up circuit 100. The wake-up circuit 100 can reduce potential safety hazards, thereby increasing the service life of the battery pack.

Finally, it should be noted that the above embodiments are only used to describe the technical solution of the present invention, but not limited thereto. Under the idea of the present invention, the technical features in the above embodiments or different embodiments can also be combined. The steps can be implemented in any order and there are many other variations of the different aspects of the invention as described above, for the sake of brevity they are not provided in the details; although the invention has been described in detail with reference to the foregoing embodiments, it is common in the art The skilled person should understand that they can still modify the technical solutions described in the foregoing embodiments, or equivalently replace some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions separate from the implementation of this application. Examples of technical solutions.

Claims (13)

1. A wake-up circuit, comprising:

   A switching circuit, including a switch input terminal and a switch output terminal;

   The signal conditioning circuit includes a signal input terminal and a signal output terminal. The signal input terminal of the signal conditioning circuit is connected to the switch output terminal of the switch circuit. When an external power source is applied to the switch input terminal of the switch circuit, the signal conditioning circuit The switching circuit works in a conducting state, so that the external power is applied to a signal input terminal of the signal conditioning circuit, and the signal conditioning circuit converts the external power into a level trigger signal;

   The charge and discharge circuit is connected to the signal output terminal of the signal conditioning circuit. When the charge and discharge circuit receives the level trigger signal, the charge and discharge circuit enters an awake state.
2. The wake-up circuit according to claim 1, wherein the level trigger signal is a high-level signal.
3. The wake-up circuit according to claim 1 or 2, wherein the signal conditioning circuit comprises a first voltage dividing circuit, and the first voltage dividing circuit comprises a first voltage dividing input terminal and a first voltage dividing output terminal, The first voltage dividing input terminal is connected to the switch output terminal, and the first voltage dividing output terminal is connected to the charging and discharging circuit;

   The first voltage dividing circuit is configured to divide an external power source applied to a signal input terminal of the signal conditioning circuit to convert the external power source into a level trigger signal.
4. The wake-up circuit according to claim 3, wherein the first voltage dividing circuit comprises a first resistor and a second resistor;

   One end of the first resistor is connected to the switch output terminal as the first voltage-dividing input terminal, the other end of the first resistor is connected to one end of the second resistor, and the The other end and one end of the second resistor are connected to the charging and discharging circuit as the first voltage-dividing output end;

   The other end of the second resistor is grounded.
5. The wake-up circuit according to claim 3, wherein the first voltage dividing circuit further comprises a first voltage stabilizing tube, a cathode of the first voltage stabilizing tube and a first voltage dividing part of the first voltage dividing circuit. The voltage output terminal is connected, and the anode of the first Zener tube is grounded.
6. The wake-up circuit according to any one of claims 1-5, wherein the charging and discharging circuit comprises:

   An analog front end includes an analog input end and an analog output end, and the analog input end is connected to a signal output end of the signal conditioning circuit;

   A charge and discharge control circuit includes a charge and discharge input terminal and a charge and discharge output terminal, the charge and discharge input terminal is connected to the analog output terminal, and the charge and discharge output terminal is used to connect a battery pack;

   When the level trigger signal is input to the analog front end, the analog front end enters an awake state, and the analog front end controls the charge and discharge of the battery pack by driving the charge and discharge control circuit.
7. The wake-up circuit according to claim 6, wherein the charge-discharge control circuit includes a discharge control circuit and a charge control circuit, the discharge control circuit includes a discharge input control terminal, and the charge control circuit includes a charge input control terminal The discharge input control terminal and the charge input control terminal are both connected to an analog output terminal of the analog front end;

   The discharge control circuit and the charge control circuit are connected in series between a total negative terminal of the battery pack and an output negative electrode of the battery pack.
8. The wake-up circuit according to claim 7, wherein the analog output end of the analog front end comprises a first drive output end and a second drive output end;

   The discharge control circuit includes a first MOS tube, and the charge control circuit includes a second MOS tube;

   The gate of the first MOS tube is connected to the first driving output terminal, the source of the first MOS tube is connected to the total negative terminal of the battery pack through a detection resistor, and the source of the first MOS tube is The electrode is also grounded through a detection resistor, the drain of the first MOS tube is connected to the drain of the second MOS tube, the gate of the second MOS tube is connected to the second driving output terminal, and the second MOS The source of the tube is connected to the output negative of the battery pack;

   When the analog front end enters the awake state, the first MOS transistor and the second MOS transistor are turned on to make the battery pack enter a charging state.
9. The wake-up circuit according to any one of claims 1 to 8, wherein the switch circuit comprises a second voltage dividing circuit, a third MOS transistor, and a fourth MOS transistor;

   The second voltage-dividing circuit includes a second voltage-dividing input terminal, a second voltage-dividing output terminal, and a voltage-dividing input control terminal, and the second voltage-dividing input terminal is used to connect to the output positive electrode of the battery pack;

   The gate of the third MOS tube is grounded via a third resistor, the source of the third MOS tube is connected to the output negative electrode of the battery pack, and the drain of the third MOS tube is connected to the second divided voltage. Output connection

   The gate of the fourth MOS transistor is connected to the voltage dividing input control terminal, the source of the fourth MOS transistor is connected to the second voltage dividing input terminal, and the drain of the fourth MOS transistor is connected to all The signal input terminal of the signal conditioning circuit is connected;

   When an external power source is applied to the switch input terminal of the switch circuit, the third MOS transistor and the fourth MOS transistor are turned on.
10. The wake-up circuit according to claim 9, wherein:

    The second voltage dividing circuit includes a fourth resistor and a fifth resistor,

    One end of the fourth resistor is connected to the source of the fourth MOS transistor as the second divided voltage input terminal, the other end of the fourth resistor is connected to one end of the fifth resistor, and the The other end of the fourth resistor and one end of the fifth resistor are connected to the gate of the fourth MOS transistor as the voltage-dividing input control terminal;

    The other end of the fifth resistor is connected to the drain of the third MOS transistor as the second divided voltage output terminal.
11. The wake-up circuit according to claim 9, wherein:

    The switching circuit further includes a second zener tube, a cathode of the second zener tube is connected to a gate of the third MOS tube, and an anode of the second zener tube is connected to the third MOS tube. Source connection.
12. The wake-up circuit according to claim 9, wherein:

    The switching circuit further includes a third zener tube, a cathode of the third zener tube is connected to a source of the fourth MOS tube, and an anode of the third zener tube is connected to the fourth MOS tube. Gate connection.
13. A battery management system, comprising a wake-up circuit according to any one of claims 1-12.

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