WO2020026550A1 - Power supply device and electronic control unit - Google Patents

Power supply device and electronic control unit Download PDF

Info

Publication number
WO2020026550A1
WO2020026550A1 PCT/JP2019/018641 JP2019018641W WO2020026550A1 WO 2020026550 A1 WO2020026550 A1 WO 2020026550A1 JP 2019018641 W JP2019018641 W JP 2019018641W WO 2020026550 A1 WO2020026550 A1 WO 2020026550A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
phase
condition setting
current
setting unit
Prior art date
Application number
PCT/JP2019/018641
Other languages
French (fr)
Japanese (ja)
Inventor
鳴 劉
純之 荒田
泰志 杉山
豪一 小野
Original Assignee
日立オートモティブシステムズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Publication of WO2020026550A1 publication Critical patent/WO2020026550A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to a power supply device and an electronic control device, for example, a power supply device that generates a high voltage required for an in-vehicle injector and an electronic control device (ECU: Electronic Control Unit) including the power supply device.
  • a power supply device that generates a high voltage required for an in-vehicle injector and an electronic control device (ECU: Electronic Control Unit) including the power supply device.
  • ECU Electronic Control Unit
  • Patent Literature 1 discloses a method of changing an upper limit threshold value of an inductor current for a predetermined phase to a value higher than usual in a predetermined period in a multi-phase DC / DC converter according to a decrease in output voltage. Is shown.
  • Patent Literature 2 discloses a method of switching between the number of phases to be used and an upper limit threshold value of an inductor current according to an engine speed in a multi-phase DC / DC converter mounted on an electronic control unit (ECU). .
  • ECU electronice control unit
  • an electronic control unit that drives an in-vehicle injector is equipped with a boost converter that generates a predetermined high voltage from a battery power supply voltage so that a current exceeding 10 A or the like flows through the injector.
  • a boost converter that generates a predetermined high voltage from a battery power supply voltage so that a current exceeding 10 A or the like flows through the injector.
  • a multi-phase configuration as shown in Patent Literature 1 or Patent Literature 2 may be used as a boost converter.
  • the battery power supply voltage supplied to the boost converter can change according to various conditions. When the battery power supply voltage changes, in the multi-phase boost converter, the current balance of each phase may be lost, and the ripple may increase.
  • the present invention has been made in view of such circumstances, and one of its objects is to provide a power supply device capable of reducing ripples and an electronic control device including the power supply device.
  • the power supply device includes a multi-phase booster circuit, a condition setting unit, and a current control circuit.
  • the multi-phase booster circuit includes an inductor and a switching element controlled by a switching signal for each phase, boosts a battery power supply voltage supplied from a battery, and supplies the boosted voltage to a load.
  • the condition setting unit variably sets the number of phases to be activated from the booster circuit and the current threshold value of the inductor current in each phase based on the battery power supply voltage.
  • the current control circuit generates a switching signal for a predetermined phase based on a current threshold of the inductor current set by the condition setting unit.
  • FIG. 1 is a schematic diagram illustrating a configuration example of a main part of an electronic control device according to a first embodiment of the present invention.
  • FIG. 4 is a waveform chart showing a schematic operation example of the power supply device according to the first embodiment of the present invention.
  • FIG. 3 is a waveform diagram illustrating a schematic operation example different from FIG. 2.
  • FIG. 2 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram illustrating a configuration example of a condition setting table provided in a condition setting unit in FIG. 4.
  • FIG. 4 is a waveform chart showing a schematic operation example of the power supply device according to the first embodiment of the present invention.
  • FIG. 3 is a waveform diagram illustrating a schematic operation example different from FIG. 2.
  • FIG. 2 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to
  • FIG. 9 is a schematic diagram illustrating a configuration example of a main part of a power supply device (boost converter) according to a second embodiment of the present invention.
  • FIG. 7 is a waveform diagram illustrating an example of operation contents of the power supply device of FIG. 6.
  • FIG. 7 is a schematic diagram illustrating a configuration example of an initial value table provided in the condition setting unit of FIG. 6.
  • FIG. 7 is a waveform diagram illustrating an operation example of a main part of the power supply device (step-up converter) in FIG. 6.
  • FIG. 9 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a third embodiment of the present invention.
  • FIG. 14 is a waveform chart showing a schematic operation example of the power supply device according to Embodiment 4 of the present invention.
  • FIG. 13 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a fourth embodiment of the present invention.
  • FIG. 14 is a schematic diagram illustrating a configuration example of a condition setting table provided in the condition setting unit in FIG. 13.
  • FIG. 14 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a fifth embodiment of the present invention.
  • FIG. 5 is a schematic diagram illustrating a configuration example of a main part around a power supply device (boost converter) as a comparative example of the present invention.
  • FIG. 17 is a waveform diagram illustrating a schematic operation example of the electronic control unit (ECU) of FIG. 1 including the boost converter of FIG. 16.
  • FIG. 17 is a waveform diagram illustrating a schematic operation example of the power supply device of FIG. 16.
  • the constituent elements are not necessarily essential unless otherwise specified or considered to be essential in principle. Needless to say.
  • the shapes when referring to the shapes, positional relationships, and the like of the components, the shapes are substantially the same unless otherwise specified, and in cases where it is clearly considered in principle not to be so. And the like. This is the same for the above numerical values and ranges.
  • FIG. 1 is a schematic diagram showing a configuration example of a main part of an electronic control device according to Embodiment 1 of the present invention.
  • the electronic control unit 1 illustrated in FIG. 1 is, for example, an ECU that drives an in-vehicle injector.
  • the electronic control unit (ECU) 1 includes, for example, a wiring board on which various components are mounted, and includes an input filter 10, a boost converter (power supply device) 11, a driver 12, a control device 13, and a step-down converter 14. And
  • the input filter 10 generates the input voltage VI by smoothing the battery power supply voltage VB (typically 12 V) supplied from a battery (not shown).
  • the boost converter 11 boosts the input voltage VI (in other words, the battery power supply voltage VB supplied from the battery via the input filter 10), and uses the boosted voltage as the boosted power supply voltage Vinj (for example, 65 V). Supply to 12.
  • the driver 12 drives a vehicle-mounted injector. Specifically, the driver 12 causes a predetermined injector current (load current) Ild to flow through the solenoid coil Linj of the injector using the boosted power supply voltage Vinj.
  • the step-down converter 14 generates the internal power supply voltage Vdd (for example, 3.3 V or the like) by stepping down the input voltage VI.
  • the control device 13 is, for example, a microcontroller that operates with the internal power supply voltage Vdd.
  • the control device 13 drives the injector via the driver 12 according to various control signals Sctl from outside the device.
  • Control device 13 controls boost converter 11 as appropriate.
  • FIG. 16 is a schematic diagram showing a configuration example of a main part around a power supply device (boost converter) as a comparative example of the present invention.
  • the input filter 10 is configured by, for example, an LC filter or the like.
  • the boost converter (power supply device) 11 ′ includes a multi-phase (n-phase) booster circuit 20a [1], 20b [2] to 20b [n], a current detector 21, and n boost controller 62 [1].
  • n-1 fixed delay units 23 [1], 23 [2],..., 23 [n-1] (not shown), a current control circuit 64, and an output capacitor Co.
  • a boosted power supply voltage Vinj is generated in the output capacitor Co by an n-phase booster circuit.
  • the booster circuit 20a [1] includes an inductor L [1], a switching element SW [1] whose on / off is controlled by a switching signal SS [1], and a diode D [1] having the output capacitor Co side as a cathode. And a current detection resistor R [1].
  • the switching element SW [1] When the switching element SW [1] is turned on, the inductor L [1] accumulates power when substantially the input voltage VI is applied to both ends.
  • the switching element SW [1] is off, the inductor L [1] charges the output capacitor Co via the diode D [1] by the inductor current IL [1] having the accumulated power as an electromotive force. I do.
  • the current detection resistor R [1] converts the inductor current IL [1] flowing through the inductor L [1] into a voltage.
  • the current detector 21 detects the inductor voltage IL [1] by detecting the converted voltage.
  • booster circuits 20b [2] to 20b [n] has the same configuration as the booster circuit 20a [1] and performs the same operation, except that the current detection resistor is not provided. That is, the booster circuit 20b [2] includes the inductor L [2] through which the inductor current IL [2] flows, the switching element SW [2] controlled by the switching signal SS [2], and the diode D [2]. And charges the output capacitor Co with the inductor current IL [2]. Similarly, the booster circuit 20b [n] includes an inductor L [n] through which the inductor current IL [n] flows, a switching element SW [n] controlled by a switching signal SS [n], and a diode D [n]. And charges the output capacitor Co with the inductor current IL [n].
  • the current control circuit 64 generates a switching signal SS for a predetermined phase (here, the first phase) based on a current threshold of an inductor current fixedly set in advance.
  • the current control circuit 64 includes a hysteresis comparator CMP that compares the detected current value from the current detector 21 with the upper limit current threshold IthH and the lower limit current threshold IthL.
  • the current control circuit 64 raises the switching signal SS when the detected current value is lower than the lower limit current threshold IthL, and lowers the switching signal SS when the detected current value is higher than the upper limit current threshold IthH.
  • the difference value between the upper limit current threshold IthH and the lower limit current threshold IthL (that is, the hysteresis width) is always kept constant.
  • the boosting control unit 62 [1] includes, for example, a switch driver and the like, receives the switching signal SS from the current control circuit 64, generates a switching signal SS [1], and uses the switching signal SS [1] to generate the switching signal SS [1].
  • the switching element SW [1] in [1] is controlled.
  • the fixed delay unit 23 [1] delays the switching signal SS [1] by a predetermined fixed delay time.
  • the boost controller 62 [2] generates the switching signal SS [2] based on the output signal from the fixed delay unit 23 [1].
  • the fixed delay unit 23 [n-1] delays the switching signal SS [n-1] (not shown) by a predetermined fixed delay time, and increases the voltage of the boosting control unit 62 [n-1].
  • the “n ⁇ 1” fixed delayers 23 [1] to 23 [n ⁇ 1] delay the switching signal for the immediately preceding phase by the fixed delay time, and delay the switching signal for the immediately preceding phase. Output as a switching signal.
  • FIG. 17 is a waveform diagram showing a schematic operation example of the electronic control unit (ECU) of FIG. 1 including the boost converter of FIG.
  • the electronic control unit (ECU) 1 of FIG. 1 opens the fuel injection valve by flowing an instantaneous injector current (load current) Ild to the solenoid coil Linj at every predetermined injection interval T1.
  • load current instantaneous injector current
  • Ild load current
  • the injector current Ild from zero at a required rising rate to a predetermined current value (for example, 15 A).
  • the rising rate depends on the boosted power supply voltage Vinj. Therefore, the boost converter 11 needs to boost the boosted power supply voltage Vinj to a specified boost value before the injection is performed.
  • the boosted power supply voltage Vinj held by the output capacitor Co decreases every time the injector current Ild flows.
  • the boost converter 11 'in FIG. 16 is enabled when the boost power supply voltage Vinj decreases to a predetermined threshold (for example, 63 V) and starts the boost operation. Thereafter, the boost converter 11 'is invalidated when the boosted power supply voltage Vinj returns to a specified boosted value (for example, 65 V or the like) by the boosting operation, and ends the boosting operation. Thereafter, the boosted power supply voltage Vinj is held by the output capacitor Co.
  • the period from the start to the end of the boost operation (in other words, the effective period of the boost converter 11 ') is the boost period T2.
  • the boost period T2 is required to be shorter than the injection interval T1 as described above.
  • the inductor current IL [1] is controlled by the switching signal SS from the current control circuit 64 (equivalent to the switching signal SS [1] from the boost controller 62 [1]).
  • the average value of each of the inductor currents IL [2] to IL [n] is determined by using the switching signals SS [2] to SS [n] having the same duty ratio as the switching signal SS [1]. Control is performed so as to be equal to the average value of IL [1].
  • the injection interval T1 is generally set to several ms or the like, but may be set to a value of less than 1 ms particularly when the injector performs multi-stage injection.
  • the injection interval T1 becomes short, it may be difficult to maintain the relationship of the boosting period T2 ⁇ the injection interval T1. Therefore, if a multi-phase boost converter 11 ′ as shown in FIG. 16 is used, the charging current of the output capacitor Co can be increased by the number of phases (N) to be enabled, so that the boosting period T2 ⁇ injection The relationship of the interval T1 can be easily maintained.
  • FIG. 18 is a waveform diagram showing a schematic operation example of the power supply device of FIG.
  • the battery power supply voltage VB (and thus the input voltage VI) has a width of, for example, 10 V to 35 V depending on, for example, the internal resistance value of the battery and the output current value of the battery associated with the operation state of each unit in the vehicle. have.
  • the boosting period T2 shown in FIG. 17 becomes longer, and the relationship of the boosting period T2 ⁇ the injection interval T1 may not be satisfied.
  • the number of valid phases (N) is set such that the number of phases to be activated (hereinafter referred to as the number of valid phases (N)) is decreased (increased) as the battery power supply voltage VB becomes higher (lower).
  • FIG. 18 shows the inductor current IL [1] when the input voltage VI is high and the number of effective phases (N) is set to 2 and when the input voltage VI is low and the number of effective phases (N) is set to 3 To IL [3] and the input current Ivb to the boost converter 11 ′.
  • the fixed delay time TdF of each fixed delay unit 23 [1], 23 [2],... And the hysteresis width ⁇ IthF ( IthH ⁇ IthL) of the current control circuit 64 in FIG.
  • the inductor currents IL [1] and IL [2] are determined so as to be balanced.
  • the fixed delay time TdF and the hysteresis width ⁇ IthF are always kept constant.
  • variable method of the number of effective phases (N) is applied, but for example, a method of fixing the number of effective phases (N) to the maximum value (n) regardless of the input voltage VI is also conceivable.
  • the input voltage VI when the input voltage VI is tripled, it is desirable to change the target current of each phase to, for example, about 3.
  • the input power to the boost converter 11 ' is constant to some extent.
  • the target current (the intermediate value between the upper limit current threshold IthH and the lower limit current threshold IthL) Itg2 when the number of effective phases (N) in FIG. 18 is 2 and the target current when the number of effective phases (N) is 3
  • the target current Itg3 may be the same. However, needless to say, the target current Itg2 and the target current Itg3 can be set to values slightly different from each other.
  • FIG. 2 is a waveform diagram showing a schematic operation example of the power supply device according to the first embodiment of the present invention.
  • FIG. 2 shows the case where the variable method of the number of effective phases (N) described in FIG. 18 is applied.
  • the input voltage is set to such an extent that it is not necessary to switch the number of effective phases (N) such as several V levels.
  • An operation example when VI changes is shown. Here, it is assumed that the number of effective phases (N) is 2, and the input voltage VI is high and low.
  • the multiplication value “N ⁇ TdF” of the number of effective phases (N) and the fixed delay time TdF is obtained.
  • the switching cycle of each phase may be determined as the target switching cycle.
  • the switching cycle Tcyc2 of each phase may be set to the target switching cycle “2 ⁇ TdF”.
  • the switching period Tcyc2 is determined by the input voltage VI and the hysteresis width (IthH-IthL). Specifically, the switching cycle Tcyc2 becomes longer as the input voltage VI becomes lower because the slope of the inductor current becomes gentler, and becomes shorter as the hysteresis width becomes narrower. Therefore, if the hysteresis width is reduced so as to offset the extension of the switching cycle Tcyc2 due to the decrease in the input voltage VI, the switching cycle Tcyc2 is maintained at the target switching cycle “2 ⁇ TdF” regardless of the input voltage VI. .
  • the hysteresis width ⁇ Ith1 is determined when the input voltage VI is high
  • the hysteresis width ⁇ Ith2 ( ⁇ Ith1) is determined when the input voltage VI is low.
  • FIG. 3 is a waveform diagram showing a schematic operation example different from FIG. FIG. 3 shows an operation example in a case where the input voltage VI changes to such an extent that it is necessary to switch the number of effective phases (N) such as 6 V or more, unlike FIG.
  • N the number of effective phases
  • the switching cycle Tcyc2 of each phase may be set to the target switching cycle “2 ⁇ TdF” as in the case of FIG.
  • the switching cycle Tcyc3 of each phase may be set to the target switching cycle “3 ⁇ TdF”.
  • switching the number of effective phases (N) from 2 to 3 means that the input voltage VI has decreased to some extent, and when the input voltage VI decreases, the switching cycle Tcyc3 of each phase becomes longer.
  • the target switching period itself becomes longer by “TdF”. Therefore, taking into account the extension of the switching cycle Tcyc3 due to the decrease in the input voltage VI and the extension of the target switching cycle due to the increase in the number of effective phases (N), the switching cycle Tcyc3 is set to the target switching cycle “3 ⁇ TdF”. ”Is determined.
  • the hysteresis width ⁇ Ith1 is determined when the number of effective phases (N) is 2
  • the hysteresis width ⁇ Ith3 ( ⁇ ⁇ Ith1) is determined when the number of effective phases (N) is 3.
  • the hysteresis width is variably set in addition to the number of effective phases (N) in accordance with the input voltage VI, so that the inductor of each phase is independent of the input voltage VI.
  • the currents IL [1] to IL [n] can be balanced.
  • the ripple of the input current Ivb can be reduced. Accordingly, the size of the input filter 10 can be reduced, and the electronic control unit (ECU) 1 can be reduced in size and cost.
  • FIG. 4 is a schematic diagram showing a configuration example of a main part of the power supply device (boost converter) according to the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing a configuration example of a condition setting table provided in the condition setting unit in FIG.
  • the power supply device (boost converter) 11a shown in FIG. 4 is applied to the boost converter 11 of FIG.
  • the boost converter 11a differs from the configuration example of FIG. 16 in the following point.
  • a boost execution control unit 25, a condition setting unit 26, and voltage detectors 27 and 28 are added.
  • the configurations of the current control circuit 24 and the n boost control units 22 [1] to 22 [n] are slightly changed.
  • the voltage detector 27 detects the boosted power supply voltage Vinj, and the voltage detector 28 detects the input voltage VI.
  • the boosting execution control unit 25 responds to the boosting enable signal UCEN from the outside (for example, the control device 13 in FIG. 1) and the boosting power supply voltage Vinj detected by the voltage detector 27 to increase the boosting control unit 22 [1]. And outputs an enable signal EN [1] to the CPU. For example, when the boost enable signal UCEN is at the negated level, the boost execution control unit 25 keeps the enable signal EN [1] at the negated level.
  • the boost execution control unit 25 controls the enable signal EN [1] using a hysteresis comparator or the like. Specifically, as shown in FIG. 17, when the boosted power supply voltage Vinj is lower than the lower limit voltage threshold VthL (eg, 63 V), the boosting execution control unit 25 asserts the enable signal EN [1] to increase the boosted voltage. Start the operation. When the boost power supply voltage Vinj is higher than the upper limit voltage threshold VthH (for example, 65 V), the boost execution control unit 25 negates the enable signal EN [1] to end the boost operation.
  • VthL eg, 63 V
  • the condition setting unit 26 activates the voltage boosting circuits 20a [1] and 20b [2] to 20b [n] based on the input voltage VI (and the battery power supply voltage VB) detected by the voltage detector 28.
  • the number of phases (that is, the number of effective phases (N)) and the current threshold of the inductor current of each phase are variably set.
  • the condition setting unit 26 includes a condition setting table CTBLa as shown in FIG.
  • the condition setting table CTBLa includes correspondences between the input voltage VI (therefore, the battery power supply voltage VB), the number of effective phases (N), and the current threshold of the inductor current (specifically, the upper limit current threshold IthH and the lower limit current threshold IthL). The relationship is held in advance.
  • the number of effective phases (N) is determined to be 5.
  • the number of effective phases (N) is set. Is set to 4. That is, the number of effective phases (N) is set to decrease as the battery power supply voltage VB increases.
  • the switching cycle is set to “N ⁇ TdF” (TdF is a fixed delay time).
  • An upper limit current threshold IthH and a lower limit current threshold IthL of the inductor current are determined.
  • each value in FIG. 5 has a relationship of “I1H-I1L” ⁇ “I2H-I2L” ⁇ “I3H-I3L” as can be seen from FIG. It should be noted that specific values in the condition setting table CTBLa are actually determined in advance using simulation or the like. Further, the condition setting unit 26 outputs enable signals EN [2] to EN [n] to the boost control units 22 [2] to 22 [n] according to the number of valid phases (N).
  • the current control circuit 24 includes a hysteresis comparator CMP similar to that of FIG. However, the upper limit current threshold IthH and the lower limit current threshold IthL of the hysteresis comparator CMP are not fixed as in the case of FIG. 16, but are variably set by the condition setting unit 26.
  • the boost control units 22 [1] to 22 [n] perform AND operation of, for example, a switching signal from the current control circuit 24 or the fixed delay unit of the immediately preceding phase and an enable signal from the condition setting unit 26. It includes a gate and a switch driver provided at a subsequent stage.
  • condition setting unit 26 detects the input voltage VI of 18 V using the voltage detector 28.
  • condition setting unit 26 sets the number of valid phases (N) to 4 based on the condition setting table CTBLa in FIG. 5, asserts enable signals EN [2] to EN [4] (not shown), and enables The signals EN [5] (not shown) to EN [n] are negated.
  • the boost control units 22 [5] (not shown) to 22 [n] fix the switching signals SS [5] (not shown) to SS [n] at the off level.
  • the condition setting unit 26 outputs “I5H” as the upper limit current threshold IthH and “I5L” as the lower limit current threshold IthL to the current control circuit 24 based on the condition setting table CTBLa.
  • the current control circuit 24 generates the switching signal SS by comparing the “I5H” and “I5L” with the inductor current IL [1] detected by the current detector 21.
  • the boost controller 22 [1] receives the switching signal SS and generates a switching signal SS [1].
  • the switching signal SS [1] is sequentially delayed by fixed delay units 23 [1] to 23 [3] (not shown), and the boost control units 22 [2] to 22 [4] (not shown) are delayed.
  • the switching signals SS [2] to SS [4] (not shown) are sequentially generated based on the received signals.
  • Each unit except for the booster circuits 20a [1], 20b [2] to 20b [n] and the output capacitor Co in FIG. 4 may be constituted by a dedicated circuit. Control device 13).
  • the current detector 21 and the voltage detectors 27 and 28 can be realized by an analog-digital converter or a configuration in which a voltage dividing resistor is added thereto.
  • the current control circuit 24 and the boost execution control unit 25 can be realized by, for example, a digital comparator based on software processing.
  • the boost control units 22 [1] to 22 [n] can be realized by software processing, and the fixed delay units 23 [1], 23 [2],... Can be realized by using a timer circuit or the like.
  • the condition setting unit 26 can be realized by, for example, a combination of a nonvolatile memory that stores the condition setting table CTBLa and software processing.
  • Embodiment 1 Main effects of Embodiment 1 >> As described above, by using the method of the first embodiment, typically, reduction of ripples can be realized regardless of battery power supply voltage VB. Accordingly, the size of the input filter 10 can be reduced, and the electronic control unit (ECU) 1 can be reduced in size and cost.
  • ECU electronice control unit
  • the current threshold value (upper limit current threshold value IthH and lower limit current threshold value IthL) for each input voltage VI is determined using the condition setting table CTBLa, but in some cases, an arithmetic expression using the input voltage VI as a parameter is used. It is also possible to determine the current threshold value by using That is, as can be seen from FIG. 2, if the number of effective phases (N) does not change, the hysteresis width may be changed to some extent regularly in accordance with the input voltage VI. It is possible.
  • condition setting unit 26 variably sets both the upper limit current threshold IthH and the lower limit current threshold IthL as the current threshold.
  • a method of variably setting either one may be used. That is, in principle, the switching cycle can be changed by variably setting either one. For example, in a case where the switching cycle and the target current are changed according to the input voltage VI, one of them may be variably set.
  • the condition setting table CTBLa may be configured to determine, for example, a target current and a hysteresis width, instead of the upper limit current threshold IthH and the lower limit current threshold IthL.
  • FIG. 6 is a schematic diagram illustrating a configuration example of a main part of a power supply device (boost converter) according to a second embodiment of the present invention.
  • FIG. 7 is a waveform diagram showing an example of the operation content of the power supply device of FIG. 6 is different from the configuration example of FIG. 4 in the following point.
  • a phase comparator 35 is provided, and a fixed delay unit 23 [n] is added.
  • the voltage detector 28 is not provided, and instead, a condition setting unit 36 to which the number of effective phases (N) is input is provided.
  • the control device 13 of FIG. 1 determines the number of effective phases (N) by monitoring the battery power supply voltage VB, and notifies the condition setting unit 36.
  • the fixed delay unit 23 [n] delays the switching signal SS [n] by a fixed delay time.
  • the phase comparator 35 converts the signal phase PHr of the switching signal SS [1] for the first phase and the switching signal SS [N] for the Nth (N: number of valid phases) phase by the fixed delay unit 23 [N].
  • a phase error with the delayed signal phase PHd [N] is sequentially detected.
  • the condition setting unit 36 sequentially and variably controls the current thresholds (for example, the upper current threshold IthH and the lower current threshold IthL) such that the phase error by the phase comparator 35 approaches zero.
  • This state is a state where the inductor currents IL [1] to IL [3] are balanced by setting the switching cycle to the target switching cycle “N ⁇ TdF” (TdF: fixed delay time).
  • the condition setting unit 36 searches for a current threshold value (in other words, a switching cycle) that causes this state by feedback control using the phase comparator 35.
  • FIG. 8 is a schematic diagram showing a configuration example of an initial value table provided in the condition setting unit of FIG.
  • FIG. 9 is a waveform diagram showing an operation example of a main part of the power supply device (step-up converter) of FIG.
  • the condition setting unit 36 is provided with an initial value table ITBL in which initial values of an upper limit current threshold IthH and a lower limit current threshold IthL are determined for each valid phase number (N).
  • the upper limit current threshold IthH and the lower limit current threshold IthL in the initial value table ITBL determine a target current for each number of effective phases (N) by an intermediate value.
  • the hysteresis width (IthH-IthL) is set in advance to a value estimated to be close to the convergence value of the search operation to some extent by simulation or the like.
  • the condition setting unit 36 determines an initial value of the search operation based on the initial value table ITBL.
  • the signal phase PHd [3] rises, and at time t2, the signal phase PHr rises.
  • the phase comparator 35 detects a rising edge of the signal phases PHr and PHd [3], and indicates a phase delay indicating that the signal phase PHr is behind the signal phase PHd [3] in a period from time t1 to time t2.
  • a detection signal (phase error signal) DWN is output.
  • the condition setting unit 36 reduces the hysteresis width (IthH-IthL) by a preset unit step width (2 ⁇ I) without changing the target current Itg according to the phase delay detection signal DWN. As a result, the switching cycle of the switching signal SS [1] (in other words, the signal phase PHr) is shortened, and the phase error is controlled to approach zero.
  • phase comparator 35 outputs a phase lead detection signal (phase error signal) UP indicating that signal phase PHr is ahead of signal phase PHd [3] during a period from time t5 to time t6. I do.
  • the condition setting unit 36 increases the hysteresis width by a preset unit step width (2 ⁇ I) without changing the target current Itg according to the phase advance detection signal UP. As a result, the switching cycle of the switching signal SS [1] (signal phase PHr) is lengthened, and the phase error is controlled to approach zero.
  • the phase comparator 35 and the condition setting unit 36 execute such feedback control at every predetermined control cycle (in this example, every two switching cycles).
  • FIG. 10 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a third embodiment of the present invention.
  • the power supply device (step-up converter) 11c shown in FIG. 10 includes a pulse width measuring device 40 and an input voltage estimator 41 as compared with the configuration example in FIG. A part 46 is provided.
  • the input voltage estimator 41 estimates the input voltage VI based on the inductor current IL [1] detected by the current detector 21. More specifically, for example, the rate of change of the inductor current IL [1] when the switching element SW [1] is turned on depends on the input voltage VI. Therefore, the input voltage estimator 41 can estimate the input voltage VI based on the change rate of the inductor current IL [1] detected by the current detector 21.
  • the pulse width measuring device 40 measures the pulse width of the phase delay detection signal DWN from the phase comparator 35, and outputs a phase delay amount detection signal NDWN representing the magnitude. Similarly, the pulse width measuring device 40 measures the pulse width of the phase lead detection signal UP from the phase comparator 35 and outputs a phase lead amount detection signal NUP representing the magnitude.
  • the condition setting unit 46 includes, for example, an initial value table having a configuration as shown in the condition setting table CTBLa in FIG. 5, instead of the initial value table ITBL as shown in FIG. The condition setting unit 46 determines the initial values of the current thresholds (the upper limit current threshold IthH and the lower limit current threshold IthL) by referring to the initial value table based on the input voltage VI estimated by the input voltage estimator 41.
  • condition setting unit 46 determines the number of steps (K) based on the unit step width (2 ⁇ I) according to the phase delay amount detection signal NDWN from the pulse width measuring device 40, and sets the hysteresis width (IthH ⁇ IthL). Narrow by “K ⁇ 2 ⁇ I”. Similarly, the condition setting unit 46 determines the number of steps (K) according to the phase lead amount detection signal NUP from the pulse width measuring device 40, and widens the hysteresis width by “K ⁇ 2 ⁇ I”. Thereby, the hysteresis width in FIG.
  • phase delay detection signal DWN in the period from time t1 to time t2
  • phase advance detection signal UP in the period from time t5 to time t6. Will be relatively small.
  • FIG. 11 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) obtained by modifying FIG.
  • a power supply device (boost converter) 11d shown in FIG. 11 includes a voltage detector 28 as shown in FIG. 4 instead of the input voltage estimator 41 in FIG.
  • the voltage detector 28 includes, for example, an external resistor element for dividing the input voltage VI and an analog-to-digital converter for detecting the divided voltage value.
  • the input voltage estimator 41 is configured by, for example, a calculator. For this reason, for example, as described in FIG.
  • the input voltage estimator 41 when each unit is mainly mounted on a microcontroller or the like, the input voltage estimator 41 is used from the viewpoint of reducing external components and resources of the analog-to-digital converter. It is desirable to provide. On the other hand, from the viewpoint of voltage detection accuracy, it is desirable to provide the voltage detector 28.
  • the state becomes somewhat close to the ideal, and by adding the feedback control to the state, the control that further approximates the ideal is performed.
  • the unit step width (2 ⁇ I) is set to a sufficiently small value, and that the resolution of the pulse width measuring device 40 is also sufficiently high.
  • a configuration in which only the pulse width measuring device 40 in FIG. 10 is added to the configuration in FIG. 6 can be used. Also in this case, the convergence time of the feedback control can be shortened.
  • FIG. 12 is a waveform chart showing a schematic operation example of the power supply device according to the fourth embodiment of the present invention.
  • FIG. 12 shows an operation example in the case where the input voltage VI changes to such an extent that the number of effective phases (N) needs to be switched, as in the case of FIG.
  • the case where the input voltage VI is high and the number of effective phases (N) is set to 2 and the case where the input voltage VI is low and the number of effective phases (N) are 3 are set. Assume the case.
  • the delay time between the phases is variably set on the assumption that the current threshold value of the inductor current is fixed.
  • the switching cycle changes according to the input voltage VI.
  • the delay time is variably set according to the change in the switching cycle Tcyc, the above-described relationship can be satisfied.
  • FIG. 13 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a fourth embodiment of the present invention.
  • FIG. 14 is a schematic diagram showing a configuration example of a condition setting table provided in the condition setting unit in FIG.
  • a variable delay device 43 [1] is used instead of the fixed delay devices 23 [1] to 23 [n-1] (not shown) as compared with the configuration example of FIG. To 43 [n-1] (not shown), and a current control circuit 54 and a condition setting unit 56 different from those in FIG.
  • the “n ⁇ 1” variable delay devices 43 [1] to 43 [n ⁇ 1] delay the switching signal for the immediately preceding phase by the variable delay time TdV, as in the case of the fixed delay device. Output as a switching signal for the next phase.
  • the current control circuit 54 has, for example, the same configuration as the current control circuit 64 in FIG. However, the current control circuit 54 may be configured to change the intermediate value (target current) without changing the hysteresis width (IthH-IthL) according to the number of effective phases (N) from the condition setting unit 56. Good.
  • the condition setting unit 56 sets the booster circuits 20a [1], 20b [2] to 20b [20] based on the input voltage VI (and thus the battery power supply voltage VB) detected by the voltage detector 28.
  • n the number of phases to be activated (that is, the number of valid phases (N)) is variably set.
  • the condition setting unit 56 variably sets the variable delay times TdV of the variable delay units 43 [1] to 43 [n-1] based on the input voltage VI.
  • the condition setting unit 56 includes a condition setting table CTBLb as shown in FIG.
  • the condition setting table CTBLb holds in advance a correspondence relationship among the input voltage VI (and, consequently, the battery power supply voltage VB), the number of effective phases (N), and the variable delay time TdV.
  • the condition setting table CTBLb holds in advance a correspondence relationship among the input voltage VI (and, consequently, the battery power supply voltage VB), the number of effective phases (N), and the variable delay time TdV.
  • T1> T2> T3 the number of effective phases
  • the method of the first embodiment is useful from the viewpoint of easily removing the switching noise. Further, with the difference between the fixed delay unit and the variable delay unit, the method of the first embodiment is useful from the viewpoint of the rotation area. On the other hand, in applications where the change of the hysteresis width is not preferred, the method of the fourth embodiment is useful.
  • FIG. 15 is a schematic diagram showing a configuration example of a main part of a power supply device (step-up converter) according to the fifth embodiment of the present invention.
  • a boost period setting unit 67 is provided in the condition setting unit 66 as compared with the configuration example in FIG.
  • the boosting period setting section 67 shifts the current threshold value of the inductor current variably set based on the condition setting table CTBLa by an amount corresponding to the set value of the boosting period T2 input from the outside.
  • the boosting period setting unit 67 shifts the current thresholds (for example, the upper limit current threshold IthH and the lower limit current threshold IthH) based on the condition setting table CTBLa by an amount corresponding to the set value of the boosting period T2 while maintaining the hysteresis width. I do.
  • the boosting period setting section 67 variably sets the target current (hence, the boosting period T2).
  • the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention.
  • the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described above.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of one embodiment can be added to the configuration of another embodiment. .
  • the method of the fourth embodiment can be combined with the method of the second or third embodiment.
  • the power supply device according to each of the embodiments is not limited to the in-vehicle ECU, and can be widely applied as a ripple reduction technology to various multi-phase boost converters whose input voltage VI can change.
  • the present invention can be similarly applied to a multi-phase step-down converter.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Provided are: a power supply device than can realize reduction of ripples; and an electronic control unit that is provided with the power supply device. A condition setting unit 26 variably sets the number of phases to be enabled from among booster circuits 20a[1] and 20b[2]-20b[n] having n-number of phases, and current threshold values (current upper-limit threshold value IthH and current lower-limit threshold value IthL) of an inductor current of each of the phases, on the basis of a battery power supply voltage (input voltage VI). A current control circuit 24 generates a switching signal SS for a prescribed phase (e.g., the first phase) on the basis of the current threshold values set by the condition setting unit 26.

Description

電源装置および電子制御装置Power supply and electronic control unit
 本発明は、電源装置および電子制御装置に関し、例えば、車載用のインジェクタに必要な高電圧を生成する電源装置およびそれを含んだ電子制御装置(ECU:Electronic Control Unit)に関する。 The present invention relates to a power supply device and an electronic control device, for example, a power supply device that generates a high voltage required for an in-vehicle injector and an electronic control device (ECU: Electronic Control Unit) including the power supply device.
 特許文献1には、マルチフェーズのDC/DCコンバータにおいて、出力電圧の低下に応じて、予め定めたフェーズに対するインダクタ電流の上限閾値を、予め定めた期間で通常時よりも高い値に変更する方式が示される。特許文献2には、電子制御装置(ECU)に搭載されるマルチフェーズのDC/DCコンバータにおいて、エンジン回転数に応じて、使用するフェーズの数とインダクタ電流の上限閾値とを切り替える方式が示される。 Patent Literature 1 discloses a method of changing an upper limit threshold value of an inductor current for a predetermined phase to a value higher than usual in a predetermined period in a multi-phase DC / DC converter according to a decrease in output voltage. Is shown. Patent Literature 2 discloses a method of switching between the number of phases to be used and an upper limit threshold value of an inductor current according to an engine speed in a multi-phase DC / DC converter mounted on an electronic control unit (ECU). .
米国特許出願公開第2015/0288285号明細書US Patent Application Publication No. 2015/0288285 特開2017-125417号公報JP 2017-125417 A
 例えば、車載用のインジェクタを駆動する電子制御装置(ECU)には、10A等を超えるような電流をインジェクタに流すため、バッテリ電源電圧から所定の高電圧を生成する昇圧コンバータが搭載される。近年では、昇圧コンバータとして、特許文献1や特許文献2に示されるようなマルチフェーズ型の構成が用いられる場合がある。一方、昇圧コンバータに供給されるバッテリ電源電圧は、各種条件に応じて変化し得る。バッテリ電源電圧が変化した場合、マルチフェーズ型の昇圧コンバータでは、各フェーズの電流バランスが崩れ、リップルが増大する恐れがある。 For example, an electronic control unit (ECU) that drives an in-vehicle injector is equipped with a boost converter that generates a predetermined high voltage from a battery power supply voltage so that a current exceeding 10 A or the like flows through the injector. In recent years, a multi-phase configuration as shown in Patent Literature 1 or Patent Literature 2 may be used as a boost converter. On the other hand, the battery power supply voltage supplied to the boost converter can change according to various conditions. When the battery power supply voltage changes, in the multi-phase boost converter, the current balance of each phase may be lost, and the ripple may increase.
 本発明は、このようなことに鑑みてなされたものであり、その目的の一つは、リップルの低減を実現可能な電源装置、および当該電源装置を備える電子制御装置を提供することにある。 The present invention has been made in view of such circumstances, and one of its objects is to provide a power supply device capable of reducing ripples and an electronic control device including the power supply device.
 本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
 本願において開示される実施の形態のうち代表的なものの概要を簡単に説明すれば下記の通りである。 概要 The following is a brief description of an outline of a typical embodiment disclosed in the present application.
 一実施の形態による電源装置は、マルチフェーズの昇圧回路と、条件設定部と、電流制御回路とを有する。マルチフェーズの昇圧回路は、インダクタ、およびスイッチング信号で制御されるスイッチング素子をフェーズ毎に含み、バッテリから供給されるバッテリ電源電圧を昇圧し、当該昇圧された電圧を負荷へ供給する。条件設定部は、バッテリ電源電圧に基づいて、昇圧回路の中から有効化するフェーズ数と、各フェーズのインダクタ電流の電流閾値とを可変設定する。電流制御回路は、条件設定部で設定されるインダクタ電流の電流閾値に基づいて、所定のフェーズに対するスイッチング信号を生成する。 The power supply device according to one embodiment includes a multi-phase booster circuit, a condition setting unit, and a current control circuit. The multi-phase booster circuit includes an inductor and a switching element controlled by a switching signal for each phase, boosts a battery power supply voltage supplied from a battery, and supplies the boosted voltage to a load. The condition setting unit variably sets the number of phases to be activated from the booster circuit and the current threshold value of the inductor current in each phase based on the battery power supply voltage. The current control circuit generates a switching signal for a predetermined phase based on a current threshold of the inductor current set by the condition setting unit.
 本願において開示される発明のうち、代表的な実施の形態によって得られる効果を簡単に説明すると、リップルの低減が実現可能になる。 効果 Of the inventions disclosed in the present application, the effect obtained by the representative embodiment will be briefly described.
本発明の実施の形態1による電子制御装置の主要部の構成例を示す概略図である。FIG. 1 is a schematic diagram illustrating a configuration example of a main part of an electronic control device according to a first embodiment of the present invention. 本発明の実施の形態1による電源装置の概略的な動作例を示す波形図である。FIG. 4 is a waveform chart showing a schematic operation example of the power supply device according to the first embodiment of the present invention. 図2とは異なる概略的な動作例を示す波形図である。FIG. 3 is a waveform diagram illustrating a schematic operation example different from FIG. 2. 本発明の実施の形態1による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。FIG. 2 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to the first embodiment of the present invention. 図4における条件設定部が備える条件設定テーブルの構成例を示す概略図である。FIG. 5 is a schematic diagram illustrating a configuration example of a condition setting table provided in a condition setting unit in FIG. 4. 本発明の実施の形態2による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。FIG. 9 is a schematic diagram illustrating a configuration example of a main part of a power supply device (boost converter) according to a second embodiment of the present invention. 図6の電源装置の動作内容の一例を示す波形図である。FIG. 7 is a waveform diagram illustrating an example of operation contents of the power supply device of FIG. 6. 図6の条件設定部が備える初期値テーブルの構成例を示す概略図である。FIG. 7 is a schematic diagram illustrating a configuration example of an initial value table provided in the condition setting unit of FIG. 6. 図6の電源装置(昇圧コンバータ)の主要部の動作例を示す波形図である。FIG. 7 is a waveform diagram illustrating an operation example of a main part of the power supply device (step-up converter) in FIG. 6. 本発明の実施の形態3による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。FIG. 9 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a third embodiment of the present invention. 図10を変形した電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。It is the schematic which shows the structural example of the principal part of the power supply device (boost converter) which deformed FIG. 本発明の実施の形態4による電源装置の概略的な動作例を示す波形図である。FIG. 14 is a waveform chart showing a schematic operation example of the power supply device according to Embodiment 4 of the present invention. 本発明の実施の形態4による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。FIG. 13 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a fourth embodiment of the present invention. 図13における条件設定部が備える条件設定テーブルの構成例を示す概略図である。FIG. 14 is a schematic diagram illustrating a configuration example of a condition setting table provided in the condition setting unit in FIG. 13. 本発明の実施の形態5による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。FIG. 14 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a fifth embodiment of the present invention. 本発明の比較例となる電源装置(昇圧コンバータ)周りの主要部の構成例を示す概略図である。FIG. 5 is a schematic diagram illustrating a configuration example of a main part around a power supply device (boost converter) as a comparative example of the present invention. 図16の昇圧コンバータを含む図1の電子制御装置(ECU)の概略的な動作例を示す波形図である。FIG. 17 is a waveform diagram illustrating a schematic operation example of the electronic control unit (ECU) of FIG. 1 including the boost converter of FIG. 16. 図16の電源装置の概略的な動作例を示す波形図である。FIG. 17 is a waveform diagram illustrating a schematic operation example of the power supply device of FIG. 16.
 以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらは互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。また、以下の実施の形態において、要素の数等(個数、数値、量、範囲等を含む)に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。 In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to one another, and one is the other. Some or all of the modifications, details, supplementary explanations and the like are provided. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), a case where it is particularly specified and a case where it is clearly limited to a specific number in principle, etc. However, the number is not limited to the specific number, and may be more than or less than the specific number.
 さらに、以下の実施の形態において、その構成要素(要素ステップ等も含む)は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the components, the shapes are substantially the same unless otherwise specified, and in cases where it is clearly considered in principle not to be so. And the like. This is the same for the above numerical values and ranges.
 以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals in principle, and the repeated description thereof will be omitted.
 (実施の形態1)
 《電子制御装置の概略》
 図1は、本発明の実施の形態1による電子制御装置の主要部の構成例を示す概略図である。図1に示す電子制御装置1は、例えば、車載用のインジェクタを駆動するECUである。当該電子制御装置(ECU)1は、例えば、各種部品が実装された配線基板によって構成され、入力フィルタ10と、昇圧コンバータ(電源装置)11と、ドライバ12と、制御装置13と、降圧コンバータ14とを有する。
(Embodiment 1)
《Outline of electronic control unit》
FIG. 1 is a schematic diagram showing a configuration example of a main part of an electronic control device according to Embodiment 1 of the present invention. The electronic control unit 1 illustrated in FIG. 1 is, for example, an ECU that drives an in-vehicle injector. The electronic control unit (ECU) 1 includes, for example, a wiring board on which various components are mounted, and includes an input filter 10, a boost converter (power supply device) 11, a driver 12, a control device 13, and a step-down converter 14. And
 入力フィルタ10は、バッテリ(図示せず)から供給されるバッテリ電源電圧VB(代表的には12V)を平滑化することで入力電圧VIを生成する。昇圧コンバータ11は、入力電圧VI(言い換えれば、バッテリから入力フィルタ10を介して供給されるバッテリ電源電圧VB)を昇圧し、当該昇圧された電圧を昇圧電源電圧Vinj(例えば、65V等)としてドライバ12へ供給する。ドライバ12は、車載用のインジェクタを駆動する。具体的には、ドライバ12は、昇圧電源電圧Vinjを用いてインジェクタのソレノイドコイルLinjに所定のインジェクタ電流(負荷電流)Ildを流す。 The input filter 10 generates the input voltage VI by smoothing the battery power supply voltage VB (typically 12 V) supplied from a battery (not shown). The boost converter 11 boosts the input voltage VI (in other words, the battery power supply voltage VB supplied from the battery via the input filter 10), and uses the boosted voltage as the boosted power supply voltage Vinj (for example, 65 V). Supply to 12. The driver 12 drives a vehicle-mounted injector. Specifically, the driver 12 causes a predetermined injector current (load current) Ild to flow through the solenoid coil Linj of the injector using the boosted power supply voltage Vinj.
 降圧コンバータ14は、入力電圧VIを降圧することで内部電源電圧Vdd(例えば、3.3V等)を生成する。制御装置13は、例えば、内部電源電圧Vddで動作するマイクロコントローラ等である。制御装置13は、装置外部からの各種制御信号Sctlに応じてドライバ12を介してインジェクタを駆動する。また、制御装置13は、昇圧コンバータ11を適宜制御する。 (4) The step-down converter 14 generates the internal power supply voltage Vdd (for example, 3.3 V or the like) by stepping down the input voltage VI. The control device 13 is, for example, a microcontroller that operates with the internal power supply voltage Vdd. The control device 13 drives the injector via the driver 12 according to various control signals Sctl from outside the device. Control device 13 controls boost converter 11 as appropriate.
 《電源装置(比較例)の概略および問題点》
 ここで、実施の形態1の電源装置の説明に先立ち、比較例となる電源装置について説明する。図16は、本発明の比較例となる電源装置(昇圧コンバータ)周りの主要部の構成例を示す概略図である。図16において、入力フィルタ10は、例えば、LCフィルタ等で構成される。昇圧コンバータ(電源装置)11’は、マルチフェーズ(nフェーズ)の昇圧回路20a[1],20b[2]~20b[n]と、電流検出器21と、n個の昇圧制御部62[1]~62[n]と、“n-1”個の固定遅延器23[1],23[2],…,23[n-1](図示省略)と、電流制御回路64と、出力コンデンサCoとを有する。出力コンデンサCoには、nフェーズの昇圧回路によって昇圧電源電圧Vinjが生成される。
<< Outline and problems of power supply device (comparative example) >>
Here, prior to the description of the power supply device of the first embodiment, a power supply device as a comparative example will be described. FIG. 16 is a schematic diagram showing a configuration example of a main part around a power supply device (boost converter) as a comparative example of the present invention. In FIG. 16, the input filter 10 is configured by, for example, an LC filter or the like. The boost converter (power supply device) 11 ′ includes a multi-phase (n-phase) booster circuit 20a [1], 20b [2] to 20b [n], a current detector 21, and n boost controller 62 [1]. To 62 [n], "n-1" fixed delay units 23 [1], 23 [2],..., 23 [n-1] (not shown), a current control circuit 64, and an output capacitor Co. A boosted power supply voltage Vinj is generated in the output capacitor Co by an n-phase booster circuit.
 昇圧回路20a[1]は、インダクタL[1]と、スイッチング信号SS[1]でオン・オフが制御されるスイッチング素子SW[1]と、出力コンデンサCo側をカソードとするダイオードD[1]と、電流検出用抵抗R[1]とを備える。スイッチング素子SW[1]がオンの際、インダクタL[1]は、両端に略入力電圧VIが印加されることで電力を蓄積する。一方、スイッチング素子SW[1]がオフの際、インダクタL[1]は、蓄積された電力を起電力とするインダクタ電流IL[1]によって、ダイオードD[1]を介して出力コンデンサCoを充電する。電流検出用抵抗R[1]は、インダクタL[1]に流れるインダクタ電流IL[1]を電圧に変換する。電流検出器21は、当該変換された電圧を検出することでインダクタ電流IL[1]を検出する。 The booster circuit 20a [1] includes an inductor L [1], a switching element SW [1] whose on / off is controlled by a switching signal SS [1], and a diode D [1] having the output capacitor Co side as a cathode. And a current detection resistor R [1]. When the switching element SW [1] is turned on, the inductor L [1] accumulates power when substantially the input voltage VI is applied to both ends. On the other hand, when the switching element SW [1] is off, the inductor L [1] charges the output capacitor Co via the diode D [1] by the inductor current IL [1] having the accumulated power as an electromotive force. I do. The current detection resistor R [1] converts the inductor current IL [1] flowing through the inductor L [1] into a voltage. The current detector 21 detects the inductor voltage IL [1] by detecting the converted voltage.
 昇圧回路20b[2]~20b[n]のそれぞれは、電流検出用抵抗が設けられないことを除いて昇圧回路20a[1]と同様の構成を備え、同様の動作を行う。すなわち、昇圧回路20b[2]は、インダクタ電流IL[2]が流れるインダクタL[2]と、スイッチング信号SS[2]で制御されるスイッチング素子SW[2]と、ダイオードD[2]とを備え、出力コンデンサCoをインダクタ電流IL[2]で充電する。同様に、昇圧回路20b[n]は、インダクタ電流IL[n]が流れるインダクタL[n]と、スイッチング信号SS[n]で制御されるスイッチング素子SW[n]と、ダイオードD[n]とを備え、出力コンデンサCoをインダクタ電流IL[n]で充電する。 Each of the booster circuits 20b [2] to 20b [n] has the same configuration as the booster circuit 20a [1] and performs the same operation, except that the current detection resistor is not provided. That is, the booster circuit 20b [2] includes the inductor L [2] through which the inductor current IL [2] flows, the switching element SW [2] controlled by the switching signal SS [2], and the diode D [2]. And charges the output capacitor Co with the inductor current IL [2]. Similarly, the booster circuit 20b [n] includes an inductor L [n] through which the inductor current IL [n] flows, a switching element SW [n] controlled by a switching signal SS [n], and a diode D [n]. And charges the output capacitor Co with the inductor current IL [n].
 電流制御回路64は、予め固定的に設定されるインダクタ電流の電流閾値に基づいて、所定のフェーズ(ここでは1番目のフェーズ)に対するスイッチング信号SSを生成する。具体的には、電流制御回路64は、電流検出器21からの検出電流値と、上限電流閾値IthHおよび下限電流閾値IthLとを比較するヒステリシスコンパレータCMPを含む。電流制御回路64は、当該検出電流値が下限電流閾値IthLよりも低い場合にスイッチング信号SSを立ち上げ、上限電流閾値IthHよりも高い場合にスイッチング信号SSを立ち下げる。上限電流閾値IthHと下限電流閾値IthLの差分値(すなわちヒステリシス幅)は、常に一定に保たれる。 The current control circuit 64 generates a switching signal SS for a predetermined phase (here, the first phase) based on a current threshold of an inductor current fixedly set in advance. Specifically, the current control circuit 64 includes a hysteresis comparator CMP that compares the detected current value from the current detector 21 with the upper limit current threshold IthH and the lower limit current threshold IthL. The current control circuit 64 raises the switching signal SS when the detected current value is lower than the lower limit current threshold IthL, and lowers the switching signal SS when the detected current value is higher than the upper limit current threshold IthH. The difference value between the upper limit current threshold IthH and the lower limit current threshold IthL (that is, the hysteresis width) is always kept constant.
 昇圧制御部62[1]は、例えば、スイッチドライバ等を含み、電流制御回路64からのスイッチング信号SSを受けてスイッチング信号SS[1]を生成し、当該スイッチング信号SS[1]で昇圧回路20a[1]内のスイッチング素子SW[1]を制御する。固定遅延器23[1]は、スイッチング信号SS[1]を予め定めた固定遅延時間だけ遅延させる。昇圧制御部62[2]は、固定遅延器23[1]からの出力信号に基づいてスイッチング信号SS[2]を生成する。 The boosting control unit 62 [1] includes, for example, a switch driver and the like, receives the switching signal SS from the current control circuit 64, generates a switching signal SS [1], and uses the switching signal SS [1] to generate the switching signal SS [1]. The switching element SW [1] in [1] is controlled. The fixed delay unit 23 [1] delays the switching signal SS [1] by a predetermined fixed delay time. The boost controller 62 [2] generates the switching signal SS [2] based on the output signal from the fixed delay unit 23 [1].
 以降、同様にして、固定遅延器23[n-1](図示省略)は、スイッチング信号SS[n-1](図示省略)を予め定めた固定遅延時間だけ遅延させ、昇圧制御部62[n]は、固定遅延器23[n-1]からの出力信号に基づいてスイッチング信号SS[n]を生成する。このように、“n-1”個の固定遅延器23[1]~23[n-1]は、一つ前のフェーズに対するスイッチング信号を固定遅延時間だけ遅延させて、一つ後のフェーズに対するスイッチング信号として出力する。 Thereafter, similarly, the fixed delay unit 23 [n-1] (not shown) delays the switching signal SS [n-1] (not shown) by a predetermined fixed delay time, and increases the voltage of the boosting control unit 62 [n-1]. ] Generates the switching signal SS [n] based on the output signal from the fixed delay unit 23 [n-1]. As described above, the “n−1” fixed delayers 23 [1] to 23 [n−1] delay the switching signal for the immediately preceding phase by the fixed delay time, and delay the switching signal for the immediately preceding phase. Output as a switching signal.
 図17は、図16の昇圧コンバータを含む図1の電子制御装置(ECU)の概略的な動作例を示す波形図である。図1の電子制御装置(ECU)1は、所定の噴射間隔T1毎に、ソレノイドコイルLinjに瞬時的なインジェクタ電流(負荷電流)Ildを流すことで燃料噴射弁を開弁する。燃料噴射弁が開弁すると、燃焼室に燃料が噴射される。一方、燃料噴射弁を適切に制御するためには、インジェクタ電流Ildを、要求される立ち上がりレートでゼロから所定の電流値(例えば15A等)まで上昇させる必要がある。当該立ち上がりレートは、昇圧電源電圧Vinjに依存する。このため、昇圧コンバータ11は、噴射が行われる前に、昇圧電源電圧Vinjを規定の昇圧値まで昇圧する必要がある。 FIG. 17 is a waveform diagram showing a schematic operation example of the electronic control unit (ECU) of FIG. 1 including the boost converter of FIG. The electronic control unit (ECU) 1 of FIG. 1 opens the fuel injection valve by flowing an instantaneous injector current (load current) Ild to the solenoid coil Linj at every predetermined injection interval T1. When the fuel injection valve opens, fuel is injected into the combustion chamber. On the other hand, in order to properly control the fuel injection valve, it is necessary to increase the injector current Ild from zero at a required rising rate to a predetermined current value (for example, 15 A). The rising rate depends on the boosted power supply voltage Vinj. Therefore, the boost converter 11 needs to boost the boosted power supply voltage Vinj to a specified boost value before the injection is performed.
 具体的に説明すると、図17に示されるように、出力コンデンサCoで保持される昇圧電源電圧Vinjは、インジェクタ電流Ildが流れる度に低下する。図16の昇圧コンバータ11’は、昇圧電源電圧Vinjが所定の閾値(例えば63V等)まで低下した際に有効化され、昇圧動作を開始する。その後、昇圧コンバータ11’は、昇圧動作によって昇圧電源電圧Vinjが規定の昇圧値(例えば65V等)に戻った際に無効化され、昇圧動作を終了する。その後、昇圧電源電圧Vinjは、出力コンデンサCoによって保持される。昇圧動作の開始から終了までの期間(言い換えれば昇圧コンバータ11’の有効期間)は、昇圧期間T2となる。昇圧期間T2は、前述したように噴射間隔T1よりも短いことが求められる。 説明 Specifically, as shown in FIG. 17, the boosted power supply voltage Vinj held by the output capacitor Co decreases every time the injector current Ild flows. The boost converter 11 'in FIG. 16 is enabled when the boost power supply voltage Vinj decreases to a predetermined threshold (for example, 63 V) and starts the boost operation. Thereafter, the boost converter 11 'is invalidated when the boosted power supply voltage Vinj returns to a specified boosted value (for example, 65 V or the like) by the boosting operation, and ends the boosting operation. Thereafter, the boosted power supply voltage Vinj is held by the output capacitor Co. The period from the start to the end of the boost operation (in other words, the effective period of the boost converter 11 ') is the boost period T2. The boost period T2 is required to be shorter than the injection interval T1 as described above.
 なお、この昇圧期間T2では、インダクタ電流IL[1]は、電流制御回路64からのスイッチング信号SS(これに等しい昇圧制御部62[1]からのスイッチング信号SS[1])によって制御される。また、インダクタ電流IL[2]~IL[n]のそれぞれの平均値は、スイッチング信号SS[1]と同じデューティ比を持つスイッチング信号SS[2]~SS[n]を用いることで、インダクタ電流IL[1]の平均値と等しくなるように制御される。 In the boost period T2, the inductor current IL [1] is controlled by the switching signal SS from the current control circuit 64 (equivalent to the switching signal SS [1] from the boost controller 62 [1]). The average value of each of the inductor currents IL [2] to IL [n] is determined by using the switching signals SS [2] to SS [n] having the same duty ratio as the switching signal SS [1]. Control is performed so as to be equal to the average value of IL [1].
 ここで、噴射間隔T1は、一般的には、数ms等に定められるが、特に、インジェクタに多段噴射を行わせるような場合には、1ms未満の値に定められることがある。噴射間隔T1が短くなると、昇圧期間T2<噴射間隔T1の関係を保つことが困難になり得る。そこで、図16に示したようなマルチフェーズ型の昇圧コンバータ11’を用いると、出力コンデンサCoの充電電流を、有効化するフェーズ数(N)だけ増加させることができるため、昇圧期間T2<噴射間隔T1の関係を容易に保つことができる。 Here, the injection interval T1 is generally set to several ms or the like, but may be set to a value of less than 1 ms particularly when the injector performs multi-stage injection. When the injection interval T1 becomes short, it may be difficult to maintain the relationship of the boosting period T2 <the injection interval T1. Therefore, if a multi-phase boost converter 11 ′ as shown in FIG. 16 is used, the charging current of the output capacitor Co can be increased by the number of phases (N) to be enabled, so that the boosting period T2 <injection The relationship of the interval T1 can be easily maintained.
 しかし、図16のような構成では、図18に示されるような問題が生じ得る。図18は、図16の電源装置の概略的な動作例を示す波形図である。バッテリ電源電圧VB(ひいては入力電圧VI)は、例えば、バッテリの内部抵抗値や、車両内の各ユニットの動作状態に伴うバッテリの出力電流値等に応じて、例えば、10V~35Vといったような幅を持つ。入力電圧VIが低い場合、図17に示した昇圧期間T2が長くなり、昇圧期間T2<噴射間隔T1の関係を満たせなくなる恐れがある。そこで、ここでは、バッテリ電源電圧VBが高くなる(低くなる)につれて有効化するフェーズ数(以降、有効フェーズ数(N)と呼ぶ)を減少させる(増加させる)ような有効フェーズ数(N)の可変方式を適用することを考える。 However, the configuration shown in FIG. 16 may cause a problem as shown in FIG. FIG. 18 is a waveform diagram showing a schematic operation example of the power supply device of FIG. The battery power supply voltage VB (and thus the input voltage VI) has a width of, for example, 10 V to 35 V depending on, for example, the internal resistance value of the battery and the output current value of the battery associated with the operation state of each unit in the vehicle. have. When the input voltage VI is low, the boosting period T2 shown in FIG. 17 becomes longer, and the relationship of the boosting period T2 <the injection interval T1 may not be satisfied. Therefore, here, the number of valid phases (N) is set such that the number of phases to be activated (hereinafter referred to as the number of valid phases (N)) is decreased (increased) as the battery power supply voltage VB becomes higher (lower). Consider applying a variable scheme.
 図18には、入力電圧VIが高く、有効フェーズ数(N)を2に設定した場合と、入力電圧VIが低く、有効フェーズ数(N)を3に設定した場合におけるインダクタ電流IL[1]~IL[3]と、昇圧コンバータ11’への入力電流Ivbとが示される。図16における各固定遅延器23[1],23[2],…の固定遅延時間TdFと、電流制御回路64のヒステリシス幅ΔIthF(=IthH-IthL)は、ある入力電圧VIを前提として有効フェーズ数(N)が2の場合に、インダクタ電流IL[1],IL[2]がバランスするように定められる。そして、この固定遅延時間TdFおよびヒステリシス幅ΔIthFは、常に、一定に保たれる。 FIG. 18 shows the inductor current IL [1] when the input voltage VI is high and the number of effective phases (N) is set to 2 and when the input voltage VI is low and the number of effective phases (N) is set to 3 To IL [3] and the input current Ivb to the boost converter 11 ′. The fixed delay time TdF of each fixed delay unit 23 [1], 23 [2],... And the hysteresis width ΔIthF (= IthH−IthL) of the current control circuit 64 in FIG. When the number (N) is 2, the inductor currents IL [1] and IL [2] are determined so as to be balanced. The fixed delay time TdF and the hysteresis width ΔIthF are always kept constant.
 このように、インダクタ電流IL[1],IL[2]がバランスしている状態では、合計インダクタ電流(IL[1]+IL[2])の電流リップル(ひいては入力電流Ivbの電流リップル)を低減することができる。一方、この状態で入力電圧VIが低くなると、有効フェーズ数(N)が3に変わり、さらに、インダクタ電流IL[1]~IL[3]の傾きが緩やかになることで各フェーズのスイッチング周期は延びる。その結果、各インダクタ電流IL[1]~IL[3]の電流バランスが崩れ、入力電流Ivbの電流リップルが増大する。この場合、電流リップルを低減するため、例えば、サイズが大きい入力フィルタ10が必要となり、電子制御装置(ECU)1の小型化や低コスト化が困難となる恐れがある。 As described above, when the inductor currents IL [1] and IL [2] are balanced, the current ripple of the total inductor current (IL [1] + IL [2]) (and the current ripple of the input current Ivb) is reduced. can do. On the other hand, if the input voltage VI decreases in this state, the number of effective phases (N) changes to 3, and the switching cycle of each phase becomes slower because the slope of the inductor currents IL [1] to IL [3] becomes gentler. Extend. As a result, the current balance of the inductor currents IL [1] to IL [3] is lost, and the current ripple of the input current Ivb increases. In this case, in order to reduce the current ripple, for example, an input filter 10 having a large size is required, and it may be difficult to reduce the size and cost of the electronic control unit (ECU) 1.
 なお、ここでは、有効フェーズ数(N)の可変方式を適用したが、例えば、入力電圧VIに関わらず有効フェーズ数(N)を最大値(n)に固定するような方式も考えられる。この場合、例えば、入力電圧VIが3倍になると、各フェーズの目標電流を例えば1/3倍程度に変更することが望ましい。言い換えれば、昇圧コンバータ11’への入力電力は、ある程度一定であることが望ましい。 Note that, here, the variable method of the number of effective phases (N) is applied, but for example, a method of fixing the number of effective phases (N) to the maximum value (n) regardless of the input voltage VI is also conceivable. In this case, for example, when the input voltage VI is tripled, it is desirable to change the target current of each phase to, for example, about 3. In other words, it is desirable that the input power to the boost converter 11 'is constant to some extent.
 これは、入力電力が大きく変化すると、昇圧期間T2の長さも大きく変化し、例えば、出力コンデンサCoのリーク等によって噴射開始時点の昇圧電源電圧Vinjがばらつく等、インジェクタの安定動作が阻害される恐れがあるためである。このような問題は、前述したように目標電流を1/3倍程度に変更することで解決できるが、この場合、別の問題が生じ得る。すなわち、目標電流を1/3倍程度に変更した場合、それに応じて下限電流閾値IthLを下げる必要があり、これに伴い、下限電流閾値IthLがゼロよりも低くなるような事態が生じ得る。 This is because if the input power greatly changes, the length of the boosting period T2 also greatly changes, and for example, the boosting power supply voltage Vinj at the start of injection varies due to leakage of the output capacitor Co or the like, which may hinder stable operation of the injector. Because there is. Such a problem can be solved by changing the target current to about 1/3 as described above, but in this case, another problem may occur. That is, when the target current is changed to about 1/3, it is necessary to lower the lower limit current threshold IthL accordingly, and accordingly, a situation may occur in which the lower limit current threshold IthL becomes lower than zero.
 このようなことから、有効フェーズ数(N)の可変方式を適用することが望ましい。例えば、入力電圧VIが3倍になった場合に有効フェーズ数(N)を1/3倍程度に切り替えると、目標電流を変更することなく入力電力をある程度一定に保てる。このような観点から、図18における有効フェーズ数(N)が2の場合の目標電流(上限電流閾値IthHと下限電流閾値IthLの中間値)Itg2と、有効フェーズ数(N)が3の場合の目標電流Itg3は、同じであってもよい。ただし、勿論、目標電流Itg2と目標電流Itg3を互いに若干異なる値に定めることも可能である。 In view of the above, it is desirable to apply a variable method of the number of effective phases (N). For example, if the number of effective phases (N) is switched to about 1/3 when the input voltage VI is tripled, the input power can be kept constant to some extent without changing the target current. From such a viewpoint, the target current (the intermediate value between the upper limit current threshold IthH and the lower limit current threshold IthL) Itg2 when the number of effective phases (N) in FIG. 18 is 2 and the target current when the number of effective phases (N) is 3 The target current Itg3 may be the same. However, needless to say, the target current Itg2 and the target current Itg3 can be set to values slightly different from each other.
 《電源装置(実施の形態1)の概略動作》
 図2は、本発明の実施の形態1による電源装置の概略的な動作例を示す波形図である。図2には、図18で述べた有効フェーズ数(N)の可変方式を適用した場合で、例えば、数Vレベルといったように有効フェーズ数(N)を切り替える必要性が生じない程度に入力電圧VIが変化した場合の動作例が示される。ここでは、有効フェーズ数(N)を2として、入力電圧VIが高い場合と低い場合とを想定する。
<< Schematic Operation of Power Supply Device (Embodiment 1) >>
FIG. 2 is a waveform diagram showing a schematic operation example of the power supply device according to the first embodiment of the present invention. FIG. 2 shows the case where the variable method of the number of effective phases (N) described in FIG. 18 is applied. For example, the input voltage is set to such an extent that it is not necessary to switch the number of effective phases (N) such as several V levels. An operation example when VI changes is shown. Here, it is assumed that the number of effective phases (N) is 2, and the input voltage VI is high and low.
 まず、各フェーズのインダクタ電流IL[1],IL[2]をバランスさせるためには、図2から分かるように、有効フェーズ数(N)と固定遅延時間TdFの乗算値“N×TdF”を目標スイッチング周期として、各フェーズのスイッチング周期を当該目標スイッチング周期に定めればよい。図2の例では、有効フェーズ数(N)は2であるため、各フェーズのスイッチング周期Tcyc2を目標スイッチング周期“2×TdF”に定めればよい。 First, in order to balance the inductor currents IL [1] and IL [2] of each phase, as can be seen from FIG. 2, the multiplication value “N × TdF” of the number of effective phases (N) and the fixed delay time TdF is obtained. The switching cycle of each phase may be determined as the target switching cycle. In the example of FIG. 2, since the number of effective phases (N) is 2, the switching cycle Tcyc2 of each phase may be set to the target switching cycle “2 × TdF”.
 スイッチング周期Tcyc2は、入力電圧VIと、ヒステリシス幅(IthH-IthL)とによって定められる。具体的には、スイッチング周期Tcyc2は、入力電圧VIが低くなるほど、インダクタ電流の傾きが緩やかになることで長くなり、また、ヒステリシス幅が狭くなるほど短くなる。したがって、入力電圧VIの低下に伴うスイッチング周期Tcyc2の延長分を相殺するようにヒステリシス幅を狭めれば、スイッチング周期Tcyc2は、入力電圧VIに関わらず目標スイッチング周期“2×TdF”に保たれる。図2の例では、入力電圧VIが高い場合にヒステリシス幅ΔIth1が定められ、入力電圧VIが低い場合にヒステリシス幅ΔIth2(<ΔIth1)が定められる。 The switching period Tcyc2 is determined by the input voltage VI and the hysteresis width (IthH-IthL). Specifically, the switching cycle Tcyc2 becomes longer as the input voltage VI becomes lower because the slope of the inductor current becomes gentler, and becomes shorter as the hysteresis width becomes narrower. Therefore, if the hysteresis width is reduced so as to offset the extension of the switching cycle Tcyc2 due to the decrease in the input voltage VI, the switching cycle Tcyc2 is maintained at the target switching cycle “2 × TdF” regardless of the input voltage VI. . In the example of FIG. 2, the hysteresis width ΔIth1 is determined when the input voltage VI is high, and the hysteresis width ΔIth2 (<ΔIth1) is determined when the input voltage VI is low.
 図3は、図2とは異なる概略的な動作例を示す波形図である。図3には、図2とは異なり、例えば、6V以上といったように有効フェーズ数(N)を切り替える必要性が生じる程度に入力電圧VIが変化した場合の動作例が示される。ここでは、図18の場合と同様に、入力電圧VIが高く、有効フェーズ数(N)が2に設定される場合と、入力電圧VIが低く、有効フェーズ数(N)が3に設定される場合とを想定する。有効フェーズ数(N)が2の場合、図2の場合と同様に、各フェーズのスイッチング周期Tcyc2は、目標スイッチング周期“2×TdF”に定められればよい。また、有効フェーズ数(N)が3の場合、各フェーズのスイッチング周期Tcyc3は、目標スイッチング周期“3×TdF”に定められればよい。 FIG. 3 is a waveform diagram showing a schematic operation example different from FIG. FIG. 3 shows an operation example in a case where the input voltage VI changes to such an extent that it is necessary to switch the number of effective phases (N) such as 6 V or more, unlike FIG. Here, as in the case of FIG. 18, the case where the input voltage VI is high and the number of effective phases (N) is set to 2 and the case where the input voltage VI is low and the number of effective phases (N) are set to 3 Assume the case. When the number of effective phases (N) is 2, the switching cycle Tcyc2 of each phase may be set to the target switching cycle “2 × TdF” as in the case of FIG. When the number of effective phases (N) is 3, the switching cycle Tcyc3 of each phase may be set to the target switching cycle “3 × TdF”.
 ここで、有効フェーズ数(N)を2から3に切り替えるということは、入力電圧VIがある程度低下したことを意味し、入力電圧VIが低下すると、各フェーズのスイッチング周期Tcyc3は長くなる。また、有効フェーズ数(N)を2から3に切り替えると、目標スイッチング周期自体が“TdF”だけ長くなる。そこで、この入力電圧VIの低下に伴うスイッチング周期Tcyc3の延長分と、有効フェーズ数(N)の増加に伴う目標スイッチング周期の延長分とを勘案し、スイッチング周期Tcyc3が目標スイッチング周期“3×TdF”となるようにヒステリシス幅が定められる。図3の例では、有効フェーズ数(N)が2の場合にヒステリシス幅ΔIth1が定められ、有効フェーズ数(N)が3の場合にヒステリシス幅ΔIth3(≠ΔIth1)が定められる。 Here, switching the number of effective phases (N) from 2 to 3 means that the input voltage VI has decreased to some extent, and when the input voltage VI decreases, the switching cycle Tcyc3 of each phase becomes longer. When the number of effective phases (N) is switched from 2 to 3, the target switching period itself becomes longer by “TdF”. Therefore, taking into account the extension of the switching cycle Tcyc3 due to the decrease in the input voltage VI and the extension of the target switching cycle due to the increase in the number of effective phases (N), the switching cycle Tcyc3 is set to the target switching cycle “3 × TdF”. ”Is determined. In the example of FIG. 3, the hysteresis width ΔIth1 is determined when the number of effective phases (N) is 2, and the hysteresis width ΔIth3 (≠ ΔIth1) is determined when the number of effective phases (N) is 3.
 このように、有効フェーズ数(N)の可変方式を適用することで、図18で述べたように電源装置(昇圧コンバータ)への入力電力をほぼ一定に保つことが可能になる。その前提で、図2および図3に示されるように、入力電圧VIに応じて有効フェーズ数(N)に加えてヒステリシス幅を可変設定することで、入力電圧VIに関わらず、各フェーズのインダクタ電流IL[1]~IL[n]をバランスさせることが可能になる。その結果、入力電流Ivbのリップルを低減できる。また、これに伴い、入力フィルタ10のサイズを小さくすることができ、電子制御装置(ECU)1の小型化や低コスト化が図れる。 As described above, by applying the variable method of the number of effective phases (N), it is possible to keep the input power to the power supply device (the boost converter) substantially constant as described in FIG. On the premise, as shown in FIGS. 2 and 3, the hysteresis width is variably set in addition to the number of effective phases (N) in accordance with the input voltage VI, so that the inductor of each phase is independent of the input voltage VI. The currents IL [1] to IL [n] can be balanced. As a result, the ripple of the input current Ivb can be reduced. Accordingly, the size of the input filter 10 can be reduced, and the electronic control unit (ECU) 1 can be reduced in size and cost.
 《電源装置(実施の形態1)の概略構成》
 図4は、本発明の実施の形態1による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。図5は、図4における条件設定部が備える条件設定テーブルの構成例を示す概略図である。図4に示す電源装置(昇圧コンバータ)11aは、図1の昇圧コンバータ11に適用される。当該昇圧コンバータ11aは、図16の構成例と比較して、次の点が異なっている。まず、昇圧実行制御部25、条件設定部26および電圧検出器27,28が追加される。また、電流制御回路24およびn個の昇圧制御部22[1]~22[n]の構成が若干変更される。
<< Schematic Configuration of Power Supply Device (Embodiment 1) >>
FIG. 4 is a schematic diagram showing a configuration example of a main part of the power supply device (boost converter) according to the first embodiment of the present invention. FIG. 5 is a schematic diagram showing a configuration example of a condition setting table provided in the condition setting unit in FIG. The power supply device (boost converter) 11a shown in FIG. 4 is applied to the boost converter 11 of FIG. The boost converter 11a differs from the configuration example of FIG. 16 in the following point. First, a boost execution control unit 25, a condition setting unit 26, and voltage detectors 27 and 28 are added. Also, the configurations of the current control circuit 24 and the n boost control units 22 [1] to 22 [n] are slightly changed.
 電圧検出器27は、昇圧電源電圧Vinjを検出し、電圧検出部28は、入力電圧VIを検出する。昇圧実行制御部25は、外部(例えば、図1の制御装置13)からの昇圧イネーブル信号UCENと、電圧検出器27で検出される昇圧電源電圧Vinjとに応じて、昇圧制御部22[1]へイネーブル信号EN[1]を出力する。例えば、昇圧実行制御部25は、昇圧イネーブル信号UCENがネゲートレベルの場合には、イネーブル信号EN[1]をネゲートレベルに保つ。 (4) The voltage detector 27 detects the boosted power supply voltage Vinj, and the voltage detector 28 detects the input voltage VI. The boosting execution control unit 25 responds to the boosting enable signal UCEN from the outside (for example, the control device 13 in FIG. 1) and the boosting power supply voltage Vinj detected by the voltage detector 27 to increase the boosting control unit 22 [1]. And outputs an enable signal EN [1] to the CPU. For example, when the boost enable signal UCEN is at the negated level, the boost execution control unit 25 keeps the enable signal EN [1] at the negated level.
 一方、昇圧実行制御部25は、昇圧イネーブル信号UCENがアサートレベルの場合、ヒステリシスコンパレータ等を用いてイネーブル信号EN[1]を制御する。具体的には、昇圧実行制御部25は、図17に示したように、昇圧電源電圧Vinjが下限電圧閾値VthL(例えば63V)よりも低い場合にイネーブル信号EN[1]をアサートすることで昇圧動作を開始させる。また、昇圧実行制御部25は、昇圧電源電圧Vinjが上限電圧閾値VthH(例えば65V)よりも高い場合にイネーブル信号EN[1]をネゲートすることで昇圧動作を終了させる。 On the other hand, when the boost enable signal UCEN is at the assert level, the boost execution control unit 25 controls the enable signal EN [1] using a hysteresis comparator or the like. Specifically, as shown in FIG. 17, when the boosted power supply voltage Vinj is lower than the lower limit voltage threshold VthL (eg, 63 V), the boosting execution control unit 25 asserts the enable signal EN [1] to increase the boosted voltage. Start the operation. When the boost power supply voltage Vinj is higher than the upper limit voltage threshold VthH (for example, 65 V), the boost execution control unit 25 negates the enable signal EN [1] to end the boost operation.
 条件設定部26は、電圧検出器28で検出される入力電圧VI(ひいてはバッテリ電源電圧VB)に基づいて、昇圧回路20a[1],20b[2]~20b[n]の中から有効化するフェーズ数(すなわち、有効フェーズ数(N))と、各フェーズのインダクタ電流の電流閾値とを可変設定する。具体的には、条件設定部26は、図5に示されるような条件設定テーブルCTBLaを備える。条件設定テーブルCTBLaは、入力電圧VI(ひいてはバッテリ電源電圧VB)と、有効フェーズ数(N)と、インダクタ電流の電流閾値(具体的には、上限電流閾値IthHと下限電流閾値IthL)との対応関係を予め保持する。 The condition setting unit 26 activates the voltage boosting circuits 20a [1] and 20b [2] to 20b [n] based on the input voltage VI (and the battery power supply voltage VB) detected by the voltage detector 28. The number of phases (that is, the number of effective phases (N)) and the current threshold of the inductor current of each phase are variably set. Specifically, the condition setting unit 26 includes a condition setting table CTBLa as shown in FIG. The condition setting table CTBLa includes correspondences between the input voltage VI (therefore, the battery power supply voltage VB), the number of effective phases (N), and the current threshold of the inductor current (specifically, the upper limit current threshold IthH and the lower limit current threshold IthL). The relationship is held in advance.
 図5の例では、例えば、入力電圧VIが10V以上かつ16V未満の場合、有効フェーズ数(N)は5に定められ、入力電圧VIが16V以上かつ22V未満の場合、有効フェーズ数(N)は4に定められる。すなわち、バッテリ電源電圧VBが高くなるにつれて有効フェーズ数(N)が減少するように設定される。そして、この入力電圧VIと有効フェーズ数(N)との組み合わせに応じて、図2や図3に示したように、スイッチング周期が“N×TdF”(TdFは固定遅延時間)となるようにインダクタ電流の上限電流閾値IthHおよび下限電流閾値IthLが定められる。 In the example of FIG. 5, for example, when the input voltage VI is 10 V or more and less than 16 V, the number of effective phases (N) is determined to be 5. When the input voltage VI is 16 V or more and less than 22 V, the number of effective phases (N) is set. Is set to 4. That is, the number of effective phases (N) is set to decrease as the battery power supply voltage VB increases. Then, according to the combination of the input voltage VI and the number of effective phases (N), as shown in FIGS. 2 and 3, the switching cycle is set to “N × TdF” (TdF is a fixed delay time). An upper limit current threshold IthH and a lower limit current threshold IthL of the inductor current are determined.
 例えば、有効フェーズ数(N)が5の場合、図5の各値は、図2から分かるように、“I1H-I1L”<“I2H-I2L”<“I3H-I3L”の関係となる。なお、条件設定テーブルCTBLa内の具体的な値は、実際には、予めシミュレーション等を用いて定められる。また、条件設定部26は、有効フェーズ数(N)に応じて昇圧制御部22[2]~22[n]へそれぞれイネーブル信号EN[2]~EN[n]を出力する。 For example, when the number of effective phases (N) is 5, each value in FIG. 5 has a relationship of “I1H-I1L” <“I2H-I2L” <“I3H-I3L” as can be seen from FIG. It should be noted that specific values in the condition setting table CTBLa are actually determined in advance using simulation or the like. Further, the condition setting unit 26 outputs enable signals EN [2] to EN [n] to the boost control units 22 [2] to 22 [n] according to the number of valid phases (N).
 電流制御回路24は、図16の場合と同様のヒステリシスコンパレータCMPを備える。ただし、当該ヒステリシスコンパレータCMPの上限電流閾値IthHおよび下限電流閾値IthLは、図16の場合のように固定ではなく、条件設定部26によって可変設定される。昇圧制御部22[1]~22[n]は、例えば、電流制御回路24または一つ前のフェーズの固定遅延器からのスイッチング信号と、条件設定部26からのイネーブル信号とをアンド演算するアンドゲートと、その後段に設けられるスイッチドライバとを備える。 The current control circuit 24 includes a hysteresis comparator CMP similar to that of FIG. However, the upper limit current threshold IthH and the lower limit current threshold IthL of the hysteresis comparator CMP are not fixed as in the case of FIG. 16, but are variably set by the condition setting unit 26. The boost control units 22 [1] to 22 [n] perform AND operation of, for example, a switching signal from the current control circuit 24 or the fixed delay unit of the immediately preceding phase and an enable signal from the condition setting unit 26. It includes a gate and a switch driver provided at a subsequent stage.
 具体的な動作例として、例えば、条件設定部26が、電圧検出器28を用いて18Vの入力電圧VIを検出した場合を想定する。この場合、条件設定部26は、図5の条件設定テーブルCTBLaに基づき、有効フェーズ数(N)を4に定め、イネーブル信号EN[2]~EN[4](図示省略)をアサートし、イネーブル信号EN[5](図示省略)~EN[n]をネゲートする。これに伴い、昇圧制御部22[5](図示省略)~22[n]は、スイッチング信号SS[5](図示省略)~SS[n]をオフレベルに固定する。 {As a specific operation example, for example, it is assumed that the condition setting unit 26 detects the input voltage VI of 18 V using the voltage detector 28. In this case, the condition setting unit 26 sets the number of valid phases (N) to 4 based on the condition setting table CTBLa in FIG. 5, asserts enable signals EN [2] to EN [4] (not shown), and enables The signals EN [5] (not shown) to EN [n] are negated. Accordingly, the boost control units 22 [5] (not shown) to 22 [n] fix the switching signals SS [5] (not shown) to SS [n] at the off level.
 また、条件設定部26は、条件設定テーブルCTBLaに基づき、電流制御回路24へ、上限電流閾値IthHとして“I5H”を、下限電流閾値IthLとして“I5L”を出力する。電流制御回路24は、当該“I5H”および“I5L”と、電流検出器21で検出されるインダクタ電流IL[1]とを比較することでスイッチング信号SSを生成する。昇圧制御部22[1]は、当該スイッチング信号SSを受けてスイッチング信号SS[1]を生成する。スイッチング信号SS[1]は、固定遅延器23[1]~23[3](図示省略)で順次遅延され、昇圧制御部22[2]~22[4](図示省略)は、当該遅延された信号に基づいてスイッチング信号SS[2]~SS[4](図示省略)を順次生成する。 The condition setting unit 26 outputs “I5H” as the upper limit current threshold IthH and “I5L” as the lower limit current threshold IthL to the current control circuit 24 based on the condition setting table CTBLa. The current control circuit 24 generates the switching signal SS by comparing the “I5H” and “I5L” with the inductor current IL [1] detected by the current detector 21. The boost controller 22 [1] receives the switching signal SS and generates a switching signal SS [1]. The switching signal SS [1] is sequentially delayed by fixed delay units 23 [1] to 23 [3] (not shown), and the boost control units 22 [2] to 22 [4] (not shown) are delayed. The switching signals SS [2] to SS [4] (not shown) are sequentially generated based on the received signals.
 なお、図4における昇圧回路20a[1],20b[2]~20b[n]および出力コンデンサCoを除く各部は、専用の回路で構成されてもよく、適宜、マイクロコントローラ(例えば、図1の制御装置13等)に実装されてもよい。後者の場合、電流検出器21や、電圧検出器27,28は、アナログディジタル変換器や、または、それに分圧抵抗を付加した構成等で実現できる。電流制御回路24や昇圧実行制御部25は、例えば、ソフトウェア処理に基づくディジタルコンパレータ等で実現できる。昇圧制御部22[1]~22[n]は、ソフトウェア処理によって実現でき、固定遅延器23[1],23[2],…は、タイマ回路等を用いて実現できる。条件設定部26は、例えば、条件設定テーブルCTBLaを記憶する不揮発性メモリと、ソフトウェア処理との組み合わせによって実現できる。 Each unit except for the booster circuits 20a [1], 20b [2] to 20b [n] and the output capacitor Co in FIG. 4 may be constituted by a dedicated circuit. Control device 13). In the latter case, the current detector 21 and the voltage detectors 27 and 28 can be realized by an analog-digital converter or a configuration in which a voltage dividing resistor is added thereto. The current control circuit 24 and the boost execution control unit 25 can be realized by, for example, a digital comparator based on software processing. The boost control units 22 [1] to 22 [n] can be realized by software processing, and the fixed delay units 23 [1], 23 [2],... Can be realized by using a timer circuit or the like. The condition setting unit 26 can be realized by, for example, a combination of a nonvolatile memory that stores the condition setting table CTBLa and software processing.
 《実施の形態1の主要な効果》
 以上、実施の形態1の方式を用いることで、代表的には、バッテリ電源電圧VBに関わらず、リップルの低減が実現可能になる。また、これに伴い、入力フィルタ10のサイズを小さくすることができ、電子制御装置(ECU)1の小型化や低コスト化が図れる。
<< Main effects of Embodiment 1 >>
As described above, by using the method of the first embodiment, typically, reduction of ripples can be realized regardless of battery power supply voltage VB. Accordingly, the size of the input filter 10 can be reduced, and the electronic control unit (ECU) 1 can be reduced in size and cost.
 なお、ここでは、条件設定テーブルCTBLaを用いて入力電圧VI毎の電流閾値(上限電流閾値IthHおよび下限電流閾値IthL)を定めたが、場合によっては、入力電圧VIをパラメータとする演算式を用いて電流閾値を定めることも可能である。すなわち、図2から分かるように、有効フェーズ数(N)が変わらなければ、ヒステリシス幅は、入力電圧VIに応じてある程度規則的に変化させればよいため、この規則を演算式で定めることも可能である。 Here, the current threshold value (upper limit current threshold value IthH and lower limit current threshold value IthL) for each input voltage VI is determined using the condition setting table CTBLa, but in some cases, an arithmetic expression using the input voltage VI as a parameter is used. It is also possible to determine the current threshold value by using That is, as can be seen from FIG. 2, if the number of effective phases (N) does not change, the hysteresis width may be changed to some extent regularly in accordance with the input voltage VI. It is possible.
 また、ここでは、条件設定部26は、電流閾値として、上限電流閾値IthHと下限電流閾値IthLの両方を可変設定したが、場合によっては、いずれか一方を可変設定する方式であってもよい。すなわち、原理上、いずれか一方を可変設定することで、スイッチング周期を変えることができる。例えば、入力電圧VIに応じてスイッチング周期と目標電流とを変えるような場合には、いずれか一方を可変設定すればよい。また、条件設定テーブルCTBLaは、上限電流閾値IthHおよび下限電流閾値IthLの代わりに、例えば、目標電流とヒステリシス幅とを定めるような構成であってもよい。 In addition, here, the condition setting unit 26 variably sets both the upper limit current threshold IthH and the lower limit current threshold IthL as the current threshold. However, in some cases, a method of variably setting either one may be used. That is, in principle, the switching cycle can be changed by variably setting either one. For example, in a case where the switching cycle and the target current are changed according to the input voltage VI, one of them may be variably set. Further, the condition setting table CTBLa may be configured to determine, for example, a target current and a hysteresis width, instead of the upper limit current threshold IthH and the lower limit current threshold IthL.
 (実施の形態2)
 《電源装置(実施の形態2)の概略》
 図6は、本発明の実施の形態2による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。図7は、図6の電源装置の動作内容の一例を示す波形図である。図6に示す電源装置(昇圧コンバータ)11bは、図4の構成例と比較して次の点が異なる。まず、図6では、位相比較器35が設けられ、固定遅延器23[n]が追加される。また、図6では、電圧検出器28が設けられず、その代わりに有効フェーズ数(N)が入力される条件設定部36が設けられる。例えば、図1の制御装置13は、バッテリ電源電圧VBを監視することで有効フェーズ数(N)を定め、条件設定部36へ通知する。
(Embodiment 2)
<< Outline of Power Supply Device (Embodiment 2) >>
FIG. 6 is a schematic diagram illustrating a configuration example of a main part of a power supply device (boost converter) according to a second embodiment of the present invention. FIG. 7 is a waveform diagram showing an example of the operation content of the power supply device of FIG. The power supply device (boost converter) 11b shown in FIG. 6 is different from the configuration example of FIG. 4 in the following point. First, in FIG. 6, a phase comparator 35 is provided, and a fixed delay unit 23 [n] is added. In FIG. 6, the voltage detector 28 is not provided, and instead, a condition setting unit 36 to which the number of effective phases (N) is input is provided. For example, the control device 13 of FIG. 1 determines the number of effective phases (N) by monitoring the battery power supply voltage VB, and notifies the condition setting unit 36.
 固定遅延器23[n]は、スイッチング信号SS[n]を固定遅延時間だけ遅延させる。位相比較器35は、1番目のフェーズに対するスイッチング信号SS[1]の信号位相PHrと、N番目(N:有効フェーズ数)のフェーズに対するスイッチング信号SS[N]を固定遅延器23[N]で遅延させた後の信号位相PHd[N]との位相誤差を順次検出する。条件設定部36は、位相比較器35による位相誤差がゼロに近づくように電流閾値(例えば、上限電流閾値IthHおよび下限電流閾値IthL)を順次可変制御する。 The fixed delay unit 23 [n] delays the switching signal SS [n] by a fixed delay time. The phase comparator 35 converts the signal phase PHr of the switching signal SS [1] for the first phase and the switching signal SS [N] for the Nth (N: number of valid phases) phase by the fixed delay unit 23 [N]. A phase error with the delayed signal phase PHd [N] is sequentially detected. The condition setting unit 36 sequentially and variably controls the current thresholds (for example, the upper current threshold IthH and the lower current threshold IthL) such that the phase error by the phase comparator 35 approaches zero.
 図7に示されるように、例えば、N=3の場合、スイッチング信号SS[1]の信号位相PHrと、スイッチング信号SS[3]を固定遅延器(23[3])で遅延させた後の信号位相PHd[3]との位相誤差は、ゼロであればよい。この状態は、スイッチング周期が目標スイッチング周期“N×TdF”(TdF:固定遅延時間)に設定されることで、インダクタ電流IL[1]~IL[3]がバランスする状態となる。条件設定部36は、この状態となるような電流閾値(言い換えればスイッチング周期)を位相比較器35を用いたフィードバック制御によって探索する。 As shown in FIG. 7, for example, when N = 3, the signal phase PHr of the switching signal SS [1] and the switching signal SS [3] after being delayed by the fixed delay unit (23 [3]). The phase error with the signal phase PHd [3] may be zero. This state is a state where the inductor currents IL [1] to IL [3] are balanced by setting the switching cycle to the target switching cycle “N × TdF” (TdF: fixed delay time). The condition setting unit 36 searches for a current threshold value (in other words, a switching cycle) that causes this state by feedback control using the phase comparator 35.
 図8は、図6の条件設定部が備える初期値テーブルの構成例を示す概略図である。図9は、図6の電源装置(昇圧コンバータ)の主要部の動作例を示す波形図である。条件設定部36は、例えば、図8に示されるように、有効フェーズ数(N)毎の上限電流閾値IthHおよび下限電流閾値IthLの各初期値が定められる初期値テーブルITBLを予め備える。初期値テーブルITBL内の上限電流閾値IthHおよび下限電流閾値IthLは、その中間値によって有効フェーズ数(N)毎の目標電流を定める。また、ヒステリシス幅(IthH-IthL)は、予めシミュレーション等によって、ある程度、探索動作の収束値に近いと推定される値に定められる。条件設定部36は、探索動作の初期値を初期値テーブルITBLに基づいて定める。 FIG. 8 is a schematic diagram showing a configuration example of an initial value table provided in the condition setting unit of FIG. FIG. 9 is a waveform diagram showing an operation example of a main part of the power supply device (step-up converter) of FIG. For example, as shown in FIG. 8, the condition setting unit 36 is provided with an initial value table ITBL in which initial values of an upper limit current threshold IthH and a lower limit current threshold IthL are determined for each valid phase number (N). The upper limit current threshold IthH and the lower limit current threshold IthL in the initial value table ITBL determine a target current for each number of effective phases (N) by an intermediate value. Further, the hysteresis width (IthH-IthL) is set in advance to a value estimated to be close to the convergence value of the search operation to some extent by simulation or the like. The condition setting unit 36 determines an initial value of the search operation based on the initial value table ITBL.
 図9において、時刻t1では、信号位相PHd[3]が立ち上がり、時刻t2では、信号位相PHrが立ち上がっている。位相比較器35は、信号位相PHr,PHd[3]の立ち上がりエッジを検出し、時刻t1から時刻t2の期間で、信号位相PHrが信号位相PHd[3]よりも遅れていることを表す位相遅れ検出信号(位相誤差信号)DWNを出力する。条件設定部36は、当該位相遅れ検出信号DWNに応じて、目標電流Itgを変えずにヒステリシス幅(IthH-IthL)を予め設定された単位ステップ幅(2ΔI)だけ狭める。その結果、スイッチング信号SS[1](言い換えれば、信号位相PHr)のスイッチング周期が短くなり、位相誤差がゼロに近づく方向に制御される。 In FIG. 9, at time t1, the signal phase PHd [3] rises, and at time t2, the signal phase PHr rises. The phase comparator 35 detects a rising edge of the signal phases PHr and PHd [3], and indicates a phase delay indicating that the signal phase PHr is behind the signal phase PHd [3] in a period from time t1 to time t2. A detection signal (phase error signal) DWN is output. The condition setting unit 36 reduces the hysteresis width (IthH-IthL) by a preset unit step width (2ΔI) without changing the target current Itg according to the phase delay detection signal DWN. As a result, the switching cycle of the switching signal SS [1] (in other words, the signal phase PHr) is shortened, and the phase error is controlled to approach zero.
 一方、時刻t5では、信号位相PHrが立ち上がり、時刻t6では、信号位相PHd[3]が立ち上がっている。これに応じて、位相比較器35は、時刻t5から時刻t6の期間で、信号位相PHrが信号位相PHd[3]よりも進んでいることを表す位相進み検出信号(位相誤差信号)UPを出力する。条件設定部36は、当該位相進み検出信号UPに応じて、目標電流Itgを変えずにヒステリシス幅を予め設定された単位ステップ幅(2ΔI)だけ広げる。その結果、スイッチング信号SS[1](信号位相PHr)のスイッチング周期が長くなり、位相誤差がゼロに近づく方向に制御される。位相比較器35および条件設定部36は、このようなフィードバック制御を所定の制御周期毎(この例では、2回のスイッチング周期毎)に実行する。 On the other hand, at time t5, the signal phase PHr rises, and at time t6, the signal phase PHd [3] rises. In response, phase comparator 35 outputs a phase lead detection signal (phase error signal) UP indicating that signal phase PHr is ahead of signal phase PHd [3] during a period from time t5 to time t6. I do. The condition setting unit 36 increases the hysteresis width by a preset unit step width (2ΔI) without changing the target current Itg according to the phase advance detection signal UP. As a result, the switching cycle of the switching signal SS [1] (signal phase PHr) is lengthened, and the phase error is controlled to approach zero. The phase comparator 35 and the condition setting unit 36 execute such feedback control at every predetermined control cycle (in this example, every two switching cycles).
 《実施の形態2の主要な効果および各実施の形態との比較》
 以上、実施の形態2の方式を用いることで、実施の形態1で述べた各種効果と同様の効果が得られる。また、観測に基づいて電流閾値(言い換えればスイッチング周期)の制御が行われるため、実施の形態1の方式と比較して、スイッチング周期を、より高精度に目標スイッチング周期に定めることができる。その結果、リップルの更なる低減が実現可能となる。一方、実施の形態1の方式と比較して、フィードバック制御が収束するのにある程度の時間を要するため、この観点では、実施の形態1の方式が有益となる。
<< Main effects of the second embodiment and comparison with each embodiment >>
As described above, by using the method of the second embodiment, the same effects as the various effects described in the first embodiment can be obtained. In addition, since the current threshold (in other words, the switching cycle) is controlled based on the observation, the switching cycle can be set to the target switching cycle with higher accuracy than in the method of the first embodiment. As a result, it is possible to further reduce the ripple. On the other hand, since the feedback control requires a certain amount of time to converge as compared with the method of the first embodiment, the method of the first embodiment is useful from this viewpoint.
 (実施の形態3)
 《電源装置(実施の形態3)の概略》
 図10は、本発明の実施の形態3による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。図10に示す電源装置(昇圧コンバータ)11cでは、図6の構成例と比較して、パルス幅計測器40および入力電圧推定器41が設けられ、また、図6とは若干異なる構成の条件設定部46が設けられる。
(Embodiment 3)
<< Outline of Power Supply Device (Embodiment 3) >>
FIG. 10 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a third embodiment of the present invention. The power supply device (step-up converter) 11c shown in FIG. 10 includes a pulse width measuring device 40 and an input voltage estimator 41 as compared with the configuration example in FIG. A part 46 is provided.
 入力電圧推定器41は、電流検出器21で検出されるインダクタ電流IL[1]に基づいて、入力電圧VIを推定する。具体的に説明すると、例えば、スイッチング素子SW[1]がオンの際のインダクタ電流IL[1]の変化率は、入力電圧VIに依存する。このため、入力電圧推定器41は、電流検出器21で検出されるインダクタ電流IL[1]の変化率に基づいて、入力電圧VIを推定することができる。 The input voltage estimator 41 estimates the input voltage VI based on the inductor current IL [1] detected by the current detector 21. More specifically, for example, the rate of change of the inductor current IL [1] when the switching element SW [1] is turned on depends on the input voltage VI. Therefore, the input voltage estimator 41 can estimate the input voltage VI based on the change rate of the inductor current IL [1] detected by the current detector 21.
 パルス幅計測器40は、位相比較器35からの位相遅れ検出信号DWNのパルス幅を計測し、その大きさを表す位相遅れ量検出信号NDWNを出力する。同様に、パルス幅計測器40は、位相比較器35からの位相進み検出信号UPのパルス幅を計測し、その大きさを表す位相進み量検出信号NUPを出力する。条件設定部46は、図8に示したような初期値テーブルITBLの代わりに、例えば、図5の条件設定テーブルCTBLaに示したような構成の初期値テーブルを備える。条件設定部46は、入力電圧推定器41で推定された入力電圧VIに基づいて当該初期値テーブルを参照することで、電流閾値(上限電流閾値IthHおよび下限電流閾値IthL)の初期値を定める。 The pulse width measuring device 40 measures the pulse width of the phase delay detection signal DWN from the phase comparator 35, and outputs a phase delay amount detection signal NDWN representing the magnitude. Similarly, the pulse width measuring device 40 measures the pulse width of the phase lead detection signal UP from the phase comparator 35 and outputs a phase lead amount detection signal NUP representing the magnitude. The condition setting unit 46 includes, for example, an initial value table having a configuration as shown in the condition setting table CTBLa in FIG. 5, instead of the initial value table ITBL as shown in FIG. The condition setting unit 46 determines the initial values of the current thresholds (the upper limit current threshold IthH and the lower limit current threshold IthL) by referring to the initial value table based on the input voltage VI estimated by the input voltage estimator 41.
 また、条件設定部46は、パルス幅計測器40からの位相遅れ量検出信号NDWNに応じて単位ステップ幅(2ΔI)を基準とするステップ数(K)を定め、ヒステリシス幅(IthH-IthL)を“K×2ΔI”だけ狭める。同様に、条件設定部46は、パルス幅計測器40からの位相進み量検出信号NUPに応じてステップ数(K)を定め、ヒステリシス幅を“K×2ΔI”だけ広げる。これにより、図9におけるヒステリシス幅は、例えば、時刻t1から時刻t2の期間における位相遅れ検出信号DWNに応じて相対的に大きく狭められ、時刻t5から時刻t6の期間における位相進み検出信号UPに応じて相対的に小さく広げられることになる。 Further, the condition setting unit 46 determines the number of steps (K) based on the unit step width (2ΔI) according to the phase delay amount detection signal NDWN from the pulse width measuring device 40, and sets the hysteresis width (IthH−IthL). Narrow by “K × 2ΔI”. Similarly, the condition setting unit 46 determines the number of steps (K) according to the phase lead amount detection signal NUP from the pulse width measuring device 40, and widens the hysteresis width by “K × 2ΔI”. Thereby, the hysteresis width in FIG. 9 is relatively narrowed, for example, in accordance with the phase delay detection signal DWN in the period from time t1 to time t2, and in accordance with the phase advance detection signal UP in the period from time t5 to time t6. Will be relatively small.
 図11は、図10を変形した電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。図11に示す電源装置(昇圧コンバータ)11dは、図10における入力電圧推定器41の代わりに、図4に示したような電圧検出器28を備える。電圧検出器28は、例えば、入力電圧VIを分圧する外付けの抵抗素子と、その分圧値を検出するアナログディジタル変換器等で構成される。一方、入力電圧推定器41は、例えば、演算器等によって構成される。このため、例えば、図4で述べたように、各部を主にマイクロコントローラ等に実装する場合、外付け部品を減らす観点やアナログディジタル変換器のリソースを低減する観点からは、入力電圧推定器41を設ける方が望ましい。一方、電圧検出精度の観点では、電圧検出器28を設ける方が望ましい。 FIG. 11 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) obtained by modifying FIG. A power supply device (boost converter) 11d shown in FIG. 11 includes a voltage detector 28 as shown in FIG. 4 instead of the input voltage estimator 41 in FIG. The voltage detector 28 includes, for example, an external resistor element for dividing the input voltage VI and an analog-to-digital converter for detecting the divided voltage value. On the other hand, the input voltage estimator 41 is configured by, for example, a calculator. For this reason, for example, as described in FIG. 4, when each unit is mainly mounted on a microcontroller or the like, the input voltage estimator 41 is used from the viewpoint of reducing external components and resources of the analog-to-digital converter. It is desirable to provide. On the other hand, from the viewpoint of voltage detection accuracy, it is desirable to provide the voltage detector 28.
 《実施の形態3の主要な効果および各実施の形態との比較》
 以上、実施の形態3の方式を用いることで、実施の形態2で述べた各種効果と同様の効果が得られる。また、実施の形態2の方式と比較して、位相誤差の量に応じてヒステリシス幅の制御量を調整できるため、フィードバック制御が収束するのに要する時間を短縮できる。さらに、条件設定部46における初期値を入力電圧VI毎に設定することで、初期値の精度がより高まり、その結果として、フィードバック制御の収束時間の短縮や、リップルの更なる低減が図れる。
<< Main effects of Embodiment 3 and comparison with Embodiments >>
As described above, by using the method of the third embodiment, the same effects as the various effects described in the second embodiment can be obtained. Further, as compared with the method of the second embodiment, since the control amount of the hysteresis width can be adjusted according to the amount of the phase error, the time required for the feedback control to converge can be reduced. Furthermore, by setting the initial value in the condition setting unit 46 for each input voltage VI, the accuracy of the initial value is further increased, and as a result, the convergence time of the feedback control can be shortened and the ripple can be further reduced.
 すなわち、この場合、初期値の段階で、ある程度理想に近い状態となり、それにフィードバック制御を加えることで、更に理想に近づけるような制御が行われることになる。この観点から、単位ステップ幅(2ΔI)は、十分に小さい値に定められることが望ましく、パルス幅計測器40の分解能も十分に高いことが望ましい。なお、変形例として、図6の構成に対して、図10のパルス幅計測器40のみを追加したような構成を用いることも可能である。この場合も、フィードバック制御の収束時間を短縮できる。 That is, in this case, at the stage of the initial value, the state becomes somewhat close to the ideal, and by adding the feedback control to the state, the control that further approximates the ideal is performed. From this viewpoint, it is desirable that the unit step width (2ΔI) is set to a sufficiently small value, and that the resolution of the pulse width measuring device 40 is also sufficiently high. As a modification, a configuration in which only the pulse width measuring device 40 in FIG. 10 is added to the configuration in FIG. 6 can be used. Also in this case, the convergence time of the feedback control can be shortened.
 (実施の形態4)
 《電源装置(実施の形態4)の概略動作》
 図12は、本発明の実施の形態4による電源装置の概略的な動作例を示す波形図である。図12には、図3の場合と同様に、有効フェーズ数(N)を切り替える必要性が生じる程度に入力電圧VIが変化した場合の動作例が示される。ここでは、図3の場合と同様に、入力電圧VIが高く、有効フェーズ数(N)が2に設定される場合と、入力電圧VIが低く、有効フェーズ数(N)が3に設定される場合とを想定する。
(Embodiment 4)
<< Schematic Operation of Power Supply Device (Embodiment 4) >>
FIG. 12 is a waveform chart showing a schematic operation example of the power supply device according to the fourth embodiment of the present invention. FIG. 12 shows an operation example in the case where the input voltage VI changes to such an extent that the number of effective phases (N) needs to be switched, as in the case of FIG. Here, similarly to the case of FIG. 3, the case where the input voltage VI is high and the number of effective phases (N) is set to 2 and the case where the input voltage VI is low and the number of effective phases (N) are 3 are set. Assume the case.
 図3では、各フェーズ間の遅延時間が固定であることを前提とし、インダクタ電流の電流閾値を可変設定することで、“Tcyc=N×TdF”(Tcyc:スイッチング周期、N:有効フェーズ数、TdF:固定遅延時間)の関係を満たすようなスイッチング周期Tcycが定められた。一方、図12では、インダクタ電流の電流閾値が固定であることを前提とし、各フェーズ間の遅延時間が可変設定される。電流閾値を固定した場合、入力電圧VIに応じてスイッチング周期が変わるが、そのスイッチング周期Tcycの変化に応じて遅延時間を可変設定すれば前述した関係を満たせるようになる。 In FIG. 3, assuming that the delay time between the phases is fixed, the current threshold value of the inductor current is variably set, so that “Tcyc = N × TdF” (Tcyc: switching cycle, N: number of effective phases, A switching cycle Tcyc that satisfies the relationship of TdF (fixed delay time) has been determined. On the other hand, in FIG. 12, the delay time between the phases is variably set on the assumption that the current threshold value of the inductor current is fixed. When the current threshold is fixed, the switching cycle changes according to the input voltage VI. However, if the delay time is variably set according to the change in the switching cycle Tcyc, the above-described relationship can be satisfied.
 具体的には、可変遅延時間を“TdV”とし、入力電圧VIに応じて変化するスイッチング周期を“Tcyc”とした場合、“Tcyc=N×TdV”を満たすように可変遅延時間TdVを可変設定すればよい。図12の例では、N=2の場合とN=3の場合とで、ヒステリシス幅ΔIthFは同じである。このヒステリシス幅ΔIthFと入力電圧VIとに応じて、N=2の場合のスイッチング周期Tcyc2は自動的に定まり、N=3の場合のスイッチング周期Tcyc3も自動的に定まる。 Specifically, when the variable delay time is “TdV” and the switching cycle that changes according to the input voltage VI is “Tcyc”, the variable delay time TdV is variably set so as to satisfy “Tcyc = N × TdV”. do it. In the example of FIG. 12, the hysteresis width ΔIthF is the same between N = 2 and N = 3. The switching cycle Tcyc2 when N = 2 is automatically determined according to the hysteresis width ΔIthF and the input voltage VI, and the switching cycle Tcyc3 when N = 3 is automatically determined.
 ここで、可変遅延時間TdV1を可変設定すれば、N=2の場合のスイッチング周期Tcyc2は“Tcyc2=2×TdV1”を満たせるようになる。また、可変遅延時間TdV2を可変設定すれば、N=3の場合のスイッチング周期Tcyc3は“Tcyc3=3×TdV2”を満たせるようになる。その結果、図12に示されるように、入力電圧VI(およびフェーズ数(N))に関わらず、各フェーズのインダクタ電流IL[1]~IL[3]をバランスさせることができ、入力電流Ivbのリップルを低減することが可能になる。 Here, if the variable delay time TdV1 is variably set, the switching cycle Tcyc2 in the case of N = 2 can satisfy “Tcyc2 = 2 × TdV1”. If the variable delay time TdV2 is variably set, the switching cycle Tcyc3 in the case of N = 3 can satisfy “Tcyc3 = 3 × TdV2”. As a result, as shown in FIG. 12, regardless of the input voltage VI (and the number of phases (N)), the inductor currents IL [1] to IL [3] of each phase can be balanced, and the input current Ivb Can be reduced.
 《電源装置(実施の形態4)の概略構成》
 図13は、本発明の実施の形態4による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。図14は、図13における条件設定部が備える条件設定テーブルの構成例を示す概略図である。図13に示す電源装置(昇圧コンバータ)11eでは、図4の構成例と比較して、固定遅延器23[1]~23[n-1](図示省略)の代わりに可変遅延器43[1]~43[n-1](図示省略)が設けられ、また、図4とは異なる電流制御回路54および条件設定部56が設けられる。“n-1”個の可変遅延器43[1]~43[n-1]は、固定遅延器の場合と同様に、一つ前のフェーズに対するスイッチング信号を可変遅延時間TdVだけ遅延させて、一つ後のフェーズに対するスイッチング信号として出力する。
<< Schematic Configuration of Power Supply Device (Embodiment 4) >>
FIG. 13 is a schematic diagram showing a configuration example of a main part of a power supply device (boost converter) according to a fourth embodiment of the present invention. FIG. 14 is a schematic diagram showing a configuration example of a condition setting table provided in the condition setting unit in FIG. In the power supply device (step-up converter) 11e shown in FIG. 13, a variable delay device 43 [1] is used instead of the fixed delay devices 23 [1] to 23 [n-1] (not shown) as compared with the configuration example of FIG. To 43 [n-1] (not shown), and a current control circuit 54 and a condition setting unit 56 different from those in FIG. The “n−1” variable delay devices 43 [1] to 43 [n−1] delay the switching signal for the immediately preceding phase by the variable delay time TdV, as in the case of the fixed delay device. Output as a switching signal for the next phase.
 電流制御回路54は、例えば、図16の電流制御回路64と同様の構成を備える。ただし、電流制御回路54は、条件設定部56からの有効フェーズ数(N)に応じて、ヒステリシス幅(IthH-IthL)を変えずに中間値(目標電流)を変えるような構成であってもよい。条件設定部56は、図4の場合と同様に、電圧検出器28で検出される入力電圧VI(ひいてはバッテリ電源電圧VB)に基づいて、昇圧回路20a[1],20b[2]~20b[n]の中から有効化するフェーズ数(すなわち有効フェーズ数(N))を可変設定する。また、条件設定部56は、図4の場合と異なり、入力電圧VIに基づいて、可変遅延器43[1]~43[n-1]の可変遅延時間TdVを可変設定する。 The current control circuit 54 has, for example, the same configuration as the current control circuit 64 in FIG. However, the current control circuit 54 may be configured to change the intermediate value (target current) without changing the hysteresis width (IthH-IthL) according to the number of effective phases (N) from the condition setting unit 56. Good. As in the case of FIG. 4, the condition setting unit 56 sets the booster circuits 20a [1], 20b [2] to 20b [20] based on the input voltage VI (and thus the battery power supply voltage VB) detected by the voltage detector 28. n], the number of phases to be activated (that is, the number of valid phases (N)) is variably set. Also, unlike the case of FIG. 4, the condition setting unit 56 variably sets the variable delay times TdV of the variable delay units 43 [1] to 43 [n-1] based on the input voltage VI.
 具体的には、条件設定部56は、図14に示されるような条件設定テーブルCTBLbを備える。条件設定テーブルCTBLbは、入力電圧VI(ひいてはバッテリ電源電圧VB)と、有効フェーズ数(N)と、可変遅延時間TdVとの対応関係を予め保持する。図14において、例えば、有効フェーズ数(N)が5の場合、入力電圧VIが高くなるほどスイッチング周期が短くなるため、図14の各値は、T1>T2>T3の関係となる。なお、条件設定テーブルCTBLb内の具体的な値は、実際には、予めシミュレーション等を用いて定められる。 Specifically, the condition setting unit 56 includes a condition setting table CTBLb as shown in FIG. The condition setting table CTBLb holds in advance a correspondence relationship among the input voltage VI (and, consequently, the battery power supply voltage VB), the number of effective phases (N), and the variable delay time TdV. In FIG. 14, for example, when the number of effective phases (N) is 5, the higher the input voltage VI, the shorter the switching period. Therefore, each value in FIG. 14 has a relationship of T1> T2> T3. It should be noted that specific values in the condition setting table CTBLb are actually determined in advance using simulation or the like.
 《実施の形態4の主要な効果および各実施の形態との比較》
 以上、実施の形態4の方式を用いることで、実施の形態1で述べた各種効果と同様の効果が得られる。また、“Tcyc=N×Td”(Tcyc:スイッチング周期、N:有効フェーズ数、Td:遅延時間)の関係において、実施の形態1の方式は、“N×Td”となるように“Tcyc”を制御する方式であるのに対して、実施の形態4の方式は、“Tcyc/N”となるように、“Td”を制御する方式である。この方式の違いに伴い、スイッチングノイズは、実施の形態1の方式では限られた周波数で生じるのに対して、実施の形態3の方式では広い周波数帯で生じ得る。したがって、スイッチングノイズの除去を容易にする観点では、実施の形態1の方式が有益となる。また、固定遅延器と可変遅延器の違いに伴い、回転面積の観点では、実施の形態1の方式が有益となる。一方、ヒステリシス幅の変更が好まれない用途では、実施の形態4の方式が有益となる。
<< Main effects of Embodiment 4 and comparison with each embodiment >>
As described above, by using the method of the fourth embodiment, the same effects as the various effects described in the first embodiment can be obtained. Further, in the relationship of “Tcyc = N × Td” (Tcyc: switching cycle, N: number of effective phases, Td: delay time), the method of the first embodiment uses “Tcyc” such that “N × Td”. In contrast to this, the method of the fourth embodiment is a method of controlling “Td” so as to be “Tcyc / N”. Due to the difference between the methods, the switching noise occurs at a limited frequency in the method of the first embodiment, but may occur in a wide frequency band in the method of the third embodiment. Therefore, the method of the first embodiment is useful from the viewpoint of easily removing the switching noise. Further, with the difference between the fixed delay unit and the variable delay unit, the method of the first embodiment is useful from the viewpoint of the rotation area. On the other hand, in applications where the change of the hysteresis width is not preferred, the method of the fourth embodiment is useful.
 (実施の形態5)
 《電源装置(実施の形態5)の概略》
 図15は、本発明の実施の形態5による電源装置(昇圧コンバータ)の主要部の構成例を示す概略図である。図15に示す電源装置(昇圧コンバータ)11fでは、図4の構成例と比較して、条件設定部66に昇圧期間設定部67が設けられる。昇圧期間設定部67は、条件設定テーブルCTBLaに基づき可変設定されたインダクタ電流の電流閾値を、外部から入力された昇圧期間T2の設定値に応じた量だけシフトする。
(Embodiment 5)
<< Outline of Power Supply Device (Embodiment 5) >>
FIG. 15 is a schematic diagram showing a configuration example of a main part of a power supply device (step-up converter) according to the fifth embodiment of the present invention. In the power supply device (boost converter) 11f shown in FIG. 15, a boost period setting unit 67 is provided in the condition setting unit 66 as compared with the configuration example in FIG. The boosting period setting section 67 shifts the current threshold value of the inductor current variably set based on the condition setting table CTBLa by an amount corresponding to the set value of the boosting period T2 input from the outside.
 図17において、噴射間隔T1を変える場合、これに応じて昇圧期間T2も変える必要がある。例えば、昇圧期間T2を短くする場合、その分だけ目標電流を増やせばよい。そこで、昇圧期間設定部67は、条件設定テーブルCTBLaに基づく電流閾値(例えば、上限電流閾値IthHおよび下限電流閾値IthH)を、ヒステリシス幅を保ったまま昇圧期間T2の設定値に応じた量だけシフトする。これによって、昇圧期間設定部67は、目標電流(ひいては昇圧期間T2)を可変設定する。 In FIG. 17, if the injection interval T1 is changed, the boosting period T2 must be changed accordingly. For example, when shortening the boosting period T2, the target current may be increased by that amount. Therefore, the boosting period setting unit 67 shifts the current thresholds (for example, the upper limit current threshold IthH and the lower limit current threshold IthH) based on the condition setting table CTBLa by an amount corresponding to the set value of the boosting period T2 while maintaining the hysteresis width. I do. As a result, the boosting period setting section 67 variably sets the target current (hence, the boosting period T2).
 以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能である。例えば、前述した実施の形態は、本発明を分かり易く説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能であり、また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described above. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of one embodiment can be added to the configuration of another embodiment. . In addition, for a part of the configuration of each embodiment, it is possible to add, delete, or replace another configuration.
 例えば、実施の形態4の方式は、実施の形態2や実施の形態3の方式と組み合わせることも可能である。また、各実施の形態の電源装置は、車載用のECUに限らず、入力電圧VIが変化し得る様々なマルチフェーズ型の昇圧コンバータを対象に、そのリップル低減技術として広く適用可能である。また、場合によって、マルチフェーズ型の降圧コンバータに対して同様に適用することも可能である。 For example, the method of the fourth embodiment can be combined with the method of the second or third embodiment. Further, the power supply device according to each of the embodiments is not limited to the in-vehicle ECU, and can be widely applied as a ripple reduction technology to various multi-phase boost converters whose input voltage VI can change. In some cases, the present invention can be similarly applied to a multi-phase step-down converter.
 1 電子制御装置(ECU)
 10 入力フィルタ
 11 電源装置(昇圧コンバータ)
 12 ドライバ
 20a,20b 昇圧回路
 23 固定遅延器
 24 電源制御回路
 26,36,46,56,66 条件設定部
 35 位相比較器
 43 可変遅延器
 67 昇圧期間設定部
 CMP ヒステリシスコンパレータ
 CTBL 条件設定テーブル
 D ダイオード
 EN イネーブル信号
 IL インダクタ電流
 IthH 上限電流閾値
 IthL 下限電流閾値
 L インダクタ
 Linj ソレノイドコイル
 N 有効化するフェーズ数
 PH 信号位相
 SS スイッチング信号
 SW スイッチング素子
 T2 昇圧期間
 Tcyc スイッチング周期
 TdF 固定遅延時間
 TdV 可変遅延時間
 VB バッテリ電源電圧
 VI 入力電圧
 Vinj 昇圧電源電圧
1 Electronic control unit (ECU)
10 Input filter 11 Power supply unit (boost converter)
12 Driver 20a, 20b Booster circuit 23 Fixed delay unit 24 Power control circuit 26, 36, 46, 56, 66 Condition setting unit 35 Phase comparator 43 Variable delay unit 67 Boost period setting unit CMP Hysteresis comparator CTBL Condition setting table D Diode EN Enable signal IL Inductor current IthH Upper current threshold IthL Lower current threshold L Inductor Linj Solenoid coil N Number of phases to be activated PH Signal phase SS Switching signal SW Switching element T2 Boost period Tcyc Switching cycle TdF Fixed delay time TdV Variable delay time VB Battery power supply Voltage VI Input voltage Vinj Boost power supply voltage

Claims (15)

  1.  インダクタ、およびスイッチング信号で制御されるスイッチング素子をフェーズ毎に含み、バッテリから供給されるバッテリ電源電圧を昇圧し、当該昇圧された電圧を負荷へ供給するマルチフェーズの昇圧回路と、
     前記バッテリ電源電圧に基づいて、前記昇圧回路の中から有効化するフェーズ数と、各フェーズのインダクタ電流の電流閾値とを可変設定する条件設定部と、
     前記条件設定部で設定される前記インダクタ電流の電流閾値に基づいて、所定のフェーズに対する前記スイッチング信号を生成する電流制御回路と、
    を有する電源装置。
    A multi-phase booster circuit including an inductor, and a switching element controlled by a switching signal for each phase, boosting a battery power supply voltage supplied from a battery, and supplying the boosted voltage to a load;
    A condition setting unit configured to variably set the number of phases to be activated from the booster circuit based on the battery power supply voltage and a current threshold value of an inductor current of each phase;
    A current control circuit that generates the switching signal for a predetermined phase based on a current threshold value of the inductor current set by the condition setting unit;
    Power supply device having a.
  2.  請求項1記載の電源装置において、
     さらに、一つ前のフェーズに対する前記スイッチング信号を固定遅延時間だけ遅延させて、一つ後のフェーズに対する前記スイッチング信号として出力する複数の固定遅延器を有する、
    電源装置。
    The power supply device according to claim 1,
    Further, a plurality of fixed delay units that delay the switching signal for the previous phase by a fixed delay time and output the switching signal as the switching signal for the next phase,
    Power supply.
  3.  請求項2記載の電源装置において、
     前記条件設定部は、前記インダクタ電流の電流閾値として上限電流閾値と下限電流閾値とを可変設定する、
    電源装置。
    The power supply device according to claim 2,
    The condition setting unit variably sets an upper limit current threshold and a lower limit current threshold as a current threshold of the inductor current,
    Power supply.
  4.  請求項2記載の電源装置において、
     前記条件設定部は、前記バッテリ電源電圧が高くなるにつれて前記有効化するフェーズ数が減少するように設定する、
    電源装置。
    The power supply device according to claim 2,
    The condition setting unit sets the number of enabled phases to be reduced as the battery power supply voltage increases,
    Power supply.
  5.  請求項4記載の電源装置において、
     前記条件設定部は、前記固定遅延時間を“TdF”とし、前記有効化するフェーズ数を“N”として、前記スイッチング信号のスイッチング周期が“N×TdF”となるように前記インダクタ電流の電流閾値を可変設定する、
    電源装置。
    The power supply device according to claim 4,
    The condition setting unit sets the fixed delay time to “TdF”, sets the number of phases to be enabled to “N”, and sets a current threshold value of the inductor current such that a switching cycle of the switching signal becomes “N × TdF”. Variably set,
    Power supply.
  6.  請求項5記載の電源装置において、
     前記条件設定部は、前記バッテリ電源電圧と、前記有効化するフェーズ数と、前記インダクタ電流の電流閾値との対応関係を予め保持する条件設定テーブルを備える、
    電源装置。
    The power supply device according to claim 5,
    The condition setting unit includes a condition setting table that holds a correspondence relationship between the battery power supply voltage, the number of phases to be activated, and a current threshold value of the inductor current in advance.
    Power supply.
  7.  請求項5記載の電源装置において、さらに、
     1番目のフェーズに対する前記スイッチング信号の信号位相と、N番目のフェーズに対する前記スイッチング信号を前記固定遅延器で遅延させた後の信号位相との位相誤差を順次検出する位相比較器を有し、
     前記条件設定部は、前記位相比較器による前記位相誤差がゼロに近づくように前記電流閾値を順次可変制御する、
    電源装置。
    The power supply device according to claim 5, further comprising:
    A phase comparator for sequentially detecting a phase error between a signal phase of the switching signal for the first phase and a signal phase after delaying the switching signal for the Nth phase by the fixed delay device;
    The condition setting unit sequentially controls the current threshold so that the phase error by the phase comparator approaches zero,
    Power supply.
  8.  請求項2記載の電源装置において、
     前記条件設定部は、さらに、可変設定した前記インダクタ電流の電流閾値を、入力された昇圧期間の設定値に応じた量だけシフトする昇圧期間設定部を有する、
    電源装置。
    The power supply device according to claim 2,
    The condition setting unit further includes a boosting period setting unit that shifts the current threshold value of the variably set inductor current by an amount corresponding to a set value of the input boosting period.
    Power supply.
  9.  インダクタ、およびスイッチング信号で制御されるスイッチング素子をフェーズ毎に含み、バッテリから供給されるバッテリ電源電圧を昇圧し、当該昇圧された電圧を負荷へ供給するマルチフェーズの昇圧回路と、
     一つ前のフェーズに対する前記スイッチング信号を可変遅延時間だけ遅延させて、一つ後のフェーズに対する前記スイッチング信号として出力する複数の可変遅延器と、
     前記バッテリ電源電圧に基づいて、前記昇圧回路の中から有効化するフェーズ数と、前記可変遅延時間とを可変設定する条件設定部と、
     予め固定的に設定されるインダクタ電流の電流閾値に基づいて、所定のフェーズに対する前記スイッチング信号を生成する電流制御回路と、
    を有する電源装置。
    A multi-phase booster circuit including an inductor, and a switching element controlled by a switching signal for each phase, boosting a battery power supply voltage supplied from a battery, and supplying the boosted voltage to a load;
    A plurality of variable delay units that delay the switching signal for the immediately preceding phase by a variable delay time and output the switching signal for the immediately succeeding phase as the switching signal;
    A condition setting unit that variably sets the number of phases to be activated from the booster circuit and the variable delay time based on the battery power supply voltage;
    A current control circuit that generates the switching signal for a predetermined phase based on a current threshold of an inductor current that is fixedly set in advance;
    Power supply device having a.
  10.  請求項9記載の電源装置において、
     前記条件設定部は、前記バッテリ電源電圧が高くなるにつれて前記有効化するフェーズ数が減少するように設定する、
    電源装置。
    The power supply device according to claim 9,
    The condition setting unit sets the number of enabled phases to be reduced as the battery power supply voltage increases,
    Power supply.
  11.  請求項10記載の電源装置において、
     前記条件設定部は、前記可変遅延時間を“TdV”とし、前記有効化するフェーズ数を“N”とし、前記バッテリ電源電圧に応じて変化する前記スイッチング信号のスイッチング周期を“Tcyc”として、“Tcyc=N×TdV”を満たすように前記可変遅延時間を可変設定する、
    電源装置。
    The power supply device according to claim 10,
    The condition setting unit sets the variable delay time to “TdV”, sets the number of enabled phases to “N”, sets a switching cycle of the switching signal that changes according to the battery power supply voltage to “Tcyc”, Variably setting the variable delay time so as to satisfy Tcyc = N × TdV ″,
    Power supply.
  12.  請求項11記載の電源装置において、
     前記条件設定部は、前記バッテリ電源電圧と、前記有効化するフェーズ数と、前記可変遅延時間との対応関係を予め保持する条件設定テーブルを備える、
    電源装置。
    The power supply device according to claim 11,
    The condition setting unit includes a condition setting table that previously holds a correspondence relationship between the battery power supply voltage, the number of phases to be activated, and the variable delay time,
    Power supply.
  13.  バッテリから供給されるバッテリ電源電圧を平滑化する入力フィルタと、
     車載用のインジェクタを駆動するドライバと、
     インダクタ、およびスイッチング信号で制御されるスイッチング素子をフェーズ毎に含み、前記バッテリから前記入力フィルタを介して供給される前記バッテリ電源電圧を昇圧し、当該昇圧された電圧を電源電圧として前記ドライバへ供給するマルチフェーズの昇圧回路と、
     一つ前のフェーズに対する前記スイッチング信号を固定の遅延時間だけ遅延させて、一つ後のフェーズに対する前記スイッチング信号として出力する複数の固定遅延器と、
     前記バッテリ電源電圧に基づいて、前記昇圧回路の中から有効化するフェーズ数と、各フェーズのインダクタ電流の電流閾値とを可変設定する条件設定部と、
     前記条件設定部で設定される前記インダクタ電流の電流閾値に基づいて、所定のフェーズに対する前記スイッチング信号を生成する電流制御回路と、
    を有する電子制御装置。
    An input filter for smoothing a battery power supply voltage supplied from a battery,
    A driver for driving an in-vehicle injector;
    An inductor and a switching element controlled by a switching signal for each phase, boosting the battery power supply voltage supplied from the battery via the input filter, and supplying the boosted voltage to the driver as a power supply voltage Multi-phase booster circuit
    A plurality of fixed delay units that delay the switching signal for the previous phase by a fixed delay time and output the switching signal as the switching signal for the next phase;
    A condition setting unit configured to variably set the number of phases to be activated from the booster circuit based on the battery power supply voltage and a current threshold value of an inductor current of each phase;
    A current control circuit that generates the switching signal for a predetermined phase based on a current threshold value of the inductor current set by the condition setting unit;
    Electronic control device having
  14.  請求項13記載の電子制御装置において、
     前記条件設定部は、前記インダクタ電流の電流閾値として上限電流閾値と下限電流閾値とを可変設定する、
    電子制御装置。
    The electronic control device according to claim 13,
    The condition setting unit variably sets an upper limit current threshold and a lower limit current threshold as a current threshold of the inductor current,
    Electronic control unit.
  15.  請求項14記載の電子制御装置において、
     前記条件設定部は、前記バッテリ電源電圧が高くなるにつれて前記有効化するフェーズ数が減少するように設定する、
    電子制御装置。
    The electronic control device according to claim 14,
    The condition setting unit sets the number of enabled phases to be reduced as the battery power supply voltage increases,
    Electronic control unit.
PCT/JP2019/018641 2018-07-31 2019-05-09 Power supply device and electronic control unit WO2020026550A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-143614 2018-07-31
JP2018143614A JP6966982B2 (en) 2018-07-31 2018-07-31 Power supply and electronic control

Publications (1)

Publication Number Publication Date
WO2020026550A1 true WO2020026550A1 (en) 2020-02-06

Family

ID=69231195

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/018641 WO2020026550A1 (en) 2018-07-31 2019-05-09 Power supply device and electronic control unit

Country Status (2)

Country Link
JP (1) JP6966982B2 (en)
WO (1) WO2020026550A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7496607B2 (en) 2020-08-19 2024-06-07 学校法人幾徳学園 Power estimation device, computing device, and power supply control system

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110007532A1 (en) * 2009-07-08 2011-01-13 Tse-Hsine Liao PWM Control Device and Driving Method thereof
JP2011244534A (en) * 2010-05-14 2011-12-01 Toyota Industries Corp Power circuit
JP2012050207A (en) * 2010-08-25 2012-03-08 Denso Corp Multiphase dc/dc converter circuit
JP2013115977A (en) * 2011-11-30 2013-06-10 Renesas Electronics Corp Controller
JP2015015785A (en) * 2013-07-03 2015-01-22 株式会社ソニー・コンピュータエンタテインメント Buck dc/dc converter, controller for and method of controlling the same, and electronic apparatus using the same
JP2015226340A (en) * 2014-05-26 2015-12-14 株式会社リコー Multiphase power supply device
JP2017153238A (en) * 2016-02-24 2017-08-31 本田技研工業株式会社 Power supply device, equipment, and control method
JP2017188988A (en) * 2016-04-04 2017-10-12 富士通株式会社 Power supply controlling device and power supply controlling method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110007532A1 (en) * 2009-07-08 2011-01-13 Tse-Hsine Liao PWM Control Device and Driving Method thereof
JP2011244534A (en) * 2010-05-14 2011-12-01 Toyota Industries Corp Power circuit
JP2012050207A (en) * 2010-08-25 2012-03-08 Denso Corp Multiphase dc/dc converter circuit
JP2013115977A (en) * 2011-11-30 2013-06-10 Renesas Electronics Corp Controller
JP2015015785A (en) * 2013-07-03 2015-01-22 株式会社ソニー・コンピュータエンタテインメント Buck dc/dc converter, controller for and method of controlling the same, and electronic apparatus using the same
JP2015226340A (en) * 2014-05-26 2015-12-14 株式会社リコー Multiphase power supply device
JP2017153238A (en) * 2016-02-24 2017-08-31 本田技研工業株式会社 Power supply device, equipment, and control method
JP2017188988A (en) * 2016-04-04 2017-10-12 富士通株式会社 Power supply controlling device and power supply controlling method

Also Published As

Publication number Publication date
JP2020022254A (en) 2020-02-06
JP6966982B2 (en) 2021-11-17

Similar Documents

Publication Publication Date Title
US10263518B2 (en) System and method for switched power supply with delay measurement
EP2920872B1 (en) Feed forward current mode switching regulator with improved transient response
US7804285B2 (en) Control of operation of switching regulator to select PWM control or PFM control based on phase comparison
US9742302B2 (en) Zero-crossing detection circuit and switching power supply thereof
US7453250B2 (en) PWM controller with dual-edge modulation using dual ramps
US9065339B2 (en) Methods and apparatus for voltage regulation with dynamic transient optimization
US8994352B2 (en) Switching regulator and control method for same
EP2885861B1 (en) A current-mode controller for step-down (buck) converter
US9071125B2 (en) Switching regulator, control method thereof and power-supply device
US20190393784A1 (en) Systems and methods for adjusting one or more thresholds in power converters
US20180062511A1 (en) Control Method, Control Circuit and Device for Switching Circuit
CN104849538A (en) Switching power converter current sensing with phase current estimator
WO2008066068A1 (en) Comparator type dc-dc converter
US8344711B2 (en) Power supply device, control circuit and method for controlling power supply device
WO2008041722A1 (en) Comparator type dc-dc converter
JP6015370B2 (en) Switching power supply
KR101540858B1 (en) LDO regulator controlled by digital type using SDM
WO2020026550A1 (en) Power supply device and electronic control unit
JP6779182B2 (en) Power supply and electronic control
CN114793061A (en) Control circuit and control method of DC/DC converter and power management circuit
JP7399739B2 (en) switching power supply
US11456668B2 (en) Method and device for switching regulator control
JP2013198253A (en) Dc/dc converter
JP2019017149A (en) Multiphase converter
CN113410989A (en) Digital booster circuit, control method thereof and electronic equipment

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19844599

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19844599

Country of ref document: EP

Kind code of ref document: A1