JP2019017149A - Multiphase converter - Google Patents

Abstract

To provide a multiphase converter that does not require balance control of output currents of respective phases.SOLUTION: A multiphase converter 1 includes a hard switch converter 10 that performs power conversion between an input unit and an output unit, at least one soft switch converters 20(1) to 20(n) connected in parallel with the hard switch converter 10, a voltage detection unit 40 that generates a voltage detection signal DET1 by detecting an output voltage Vo having appeared in the output unit, an output voltage control unit 31 that performs drive-control of the hard switch converter 10 according to the voltage detection signal DET1 such that the output voltage Vo becomes equal to a target value, a current detection unit 50 that generates a current detection signal DET2 by detecting a load current Io flowing through the output unit, and a driving-phase-number switching control unit 32 that performs switching control of the number of driving phases of the soft switch converters 20(1) to 20(n) according to the current detection signal DET2.SELECTED DRAWING: Figure 1

Description

  The invention disclosed herein relates to a polyphase converter.

  In recent years, multiphase converters have been used as power supply means for various electronic devices (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2015-220976

  A multiphase converter that drives a plurality of phase switch converters in parallel can suppress a conduction loss at a heavy load as compared with a single phase switch converter, so that high conversion efficiency can be realized.

  However, in the conventional multiphase converter, if the balance of the output currents flowing through the switch converters of each phase (hereinafter abbreviated as each phase output current) is lost, the loss for each phase will increase. Therefore, it is necessary to provide a plurality of current sensors to detect each phase output current and perform respective balance control, and there is room for further improvement in terms of circuit scale and cost.

  An object of the invention disclosed in the present specification is to provide a multiphase converter that does not require balanced control of each phase output current in view of the above-mentioned problems found by the inventors of the present application.

  A polyphase converter disclosed in the present specification includes a hard switch converter that performs power conversion between an input unit and an output unit, and at least one soft switch converter connected in parallel to the hard switch converter. It is set as the structure (1st structure) to have.

  The multi-phase converter having the first configuration includes a voltage detection unit that detects an output voltage appearing in the output unit and generates a voltage detection signal, and the output voltage is a target value according to the voltage detection signal. An output voltage control unit that performs drive control of the hard switch converter may be further configured (second configuration).

  The multiphase converter having the second configuration includes a current detection unit that detects a load current flowing through the output unit and generates a current detection signal, and a driving phase of the soft switch converter according to the current detection signal. A configuration (third configuration) that further includes a drive phase number switching control unit that performs number switching control is preferable.

  Further, in the multiphase converter having the third configuration, the drive phase number switching control unit is configured so that the total of the soft switching output currents flowing through the soft switch converter being driven does not exceed the load current. A configuration (fourth configuration) for performing switching phase switching control of the switch converter is preferable.

  Further, in the multiphase converter having the fourth configuration, the drive phase number switching control unit includes a comparator that generates a comparison signal by comparing the current detection signal with a predetermined threshold signal, and according to the comparison signal. Thus, a configuration (fifth configuration) for performing the drive phase number switching control of the soft switch converter is preferable.

  In the multiphase converter having the fifth configuration, the comparator may be a hysteresis comparator (sixth configuration).

  In the multiphase converter having the fourth configuration, when the load current is Io, the soft switching output current is Isf, and hysteresis setting currents are Ix and Iy (where 0 ≦ Iy <Ix), the drive The phase number switching control unit determines the number of drive phases according to (Io−Ix) / Isf when the load current increases, and sets the number of drive phases according to (Io−Iy) / Isf when the load current decreases. The configuration to be determined (seventh configuration) may be used.

  Further, in the multiphase converter having any one of the first to seventh configurations, the soft switch converter includes an output transistor, a coil, and a capacitor, and a voltage across the output transistor or both ends of the output transistor by LC resonance. A configuration (eighth configuration) may be employed in which the output transistor is switched at a timing when the inter-current becomes a zero value.

  An electronic device disclosed in the present specification includes a multiphase converter having any one of the first to eighth configurations, and a load that operates by receiving power supply from the multiphase converter. (Ninth configuration).

  In addition, the vehicle disclosed in the present specification has a configuration (tenth configuration) including a battery and the electronic apparatus having the ninth configuration that operates by receiving power supply from the battery. Yes.

  According to the invention disclosed in the present specification, it is possible to provide a multiphase converter that does not require balanced control of each phase output current.

Diagram showing the overall configuration of the polyphase converter Correlation diagram between soft switching output current and output voltage Output waveform diagram when the number of phases is fixed (Io = 40A) Output waveform diagram when the number of phases is fixed (Io = 20A) Output waveform when the number of phases is fixed (Io = 5A) Correlation diagram between load current and number of drive phases Output waveform diagram during drive phase switching control The figure which shows one structural example of each switch converter The figure which shows one structural example of an output voltage control part The figure which shows the example of 1 structure of a drive phase number switching control part Timing chart showing an example of drive phase number switching control Timing chart showing a variation of drive phase number switching control External view showing a configuration example of a vehicle

<Multi-phase converter>
FIG. 1 is a diagram illustrating an overall configuration of a multiphase converter. The multiphase converter 1 of the present configuration example is a non-insulated DC / DC converter that converts an input voltage Vi supplied from a DC voltage source E into a desired output voltage Vo and supplies it to a load Z. The hard switch converter 10 And n-phase (where n ≧ 1) soft switch converters 20 (1) to 20 (n), a control unit 30, a voltage detection unit 40, and a current detection unit 50. In this figure, the solid line indicates the power line, and the broken line indicates the signal line.

  The hard switch converter 10 converts the output voltage Vo and the hard switching output current IH by performing power conversion between the input unit (= the positive terminal of the DC voltage source E) and the output unit (= the high potential terminal of the load Z). Is generated.

  Soft switch converters 20 (1) to 20 (n) are connected in parallel to hard switch converter 10 and generate soft switching output currents IS1 to ISn, respectively.

  The control unit 30 is a main body that comprehensively controls the operations of the hard switch converter 10 and the soft switch converters 20 (1) to 20 (n), and includes an output voltage control unit 31, a drive phase number switching control unit 32, and the like. ,including.

  The output voltage control unit 31 performs drive control of the hard switch converter 10 so that the output voltage Vo becomes a target value according to the voltage detection signal DET1. Thus, the voltage detection signal DET1 is only used for drive control of the hard switch converter 10, and is not used for drive control of each of the soft switch converters 20 (1) to 20 (n).

  The drive phase number switching control unit 32 performs drive phase number switching control of the soft switch converters 20 (1) to 20 (n) according to the current detection signal DET2. This point will be described later.

  The voltage detection unit 40 detects the output voltage Vo appearing at the output unit and generates a voltage detection signal DET1. For example, the voltage detection signal DET1 may be a divided voltage of the output voltage Vo.

  The current detection unit 50 detects a load current Io (≈IH + IS1 +... + ISn) flowing through the output unit and generates a current detection signal DET2. For example, the current detection signal DET1 may be a sense voltage obtained by current / voltage conversion of the load current Io.

  Thus, the polyphase converter 1 of this configuration example is configured to operate the hard switch converter 10 and the soft switch converters 20 (1) to 20 (n) in parallel. Below, the technical significance is explained in full detail.

  FIG. 2 shows a soft switching output current IS * and an output voltage Vo when a non-insulated step-down DC / DC converter is used as the soft switch converter 20 (*) (* = 1, 2,..., N). FIG.

  As shown in the figure, there is a clear correlation between the soft switching output current IS * and the output voltage Vo. If the output voltage Vo is fixed, the soft switching output current IS (*) is also fixed. . In the example of this figure, if the output voltage Vo is fixed at 20V, the soft switching output current IS (*) is fixed at about 11A.

  In view of the above knowledge, the hard switch converter 10 and the soft switch converters 20 (1) to 20 (n) are operated in parallel, and the hard switch converter 10 is used to fix the output voltage Vo. 1) to 20 (n) can be used as constant current sources, respectively.

  Therefore, the circuit design of the soft switch converters 20 (1) to 20 (n) is performed so that the conversion efficiency becomes the highest when the soft switching output current Is (*) determined according to the output voltage Vo flows. In this case, high conversion efficiency can be realized without requiring any balanced control of the output current of each phase.

<Drive phase switching control>
Next, the technical significance of the drive phase number switching control of the soft switch converters 20 (1) to 20 (n) will be described.

  3 to 5 are output waveform diagrams in the case where the drive phase number Pnum of the soft switch converters 20 (1) to 20 (n) is fixed to "1", respectively. The output voltage Vo is depicted in the upper part of each figure, and the load current Io, the hard switching output current IH, and the soft switching output current IS (= soft switching output currents IS1 to IS1) are shown in the lower part of each figure. Equivalent to the total ISn).

  As simulation conditions, the target value of the output voltage Vo is 20 V (common to all drawings), and the load current Io is 40 A (FIG. 3), 20 A (FIG. 4), and 5 A (FIG. 5), respectively.

  As described above, the soft switch converter 20 basically has a constant soft switching current IS corresponding to the output voltage Vo without depending on the weight of the load Z (= the magnitude of the load current Io). Try to flush. For example, when the output voltage Vo is fixed at the target value of 20V, the soft switching output current IS is fixed at about 10A.

  When the load current Io is larger than the soft switching current IS, the hard switching current IH flows, so that the hard switch converter 10 operates normally and the output voltage Vo is fixed to the target value (= 20V).

  For example, as shown in FIG. 3, when Io = 40A (> IS), IH≈30A and IS≈10A. As shown in FIG. 4, when Io = 20A (> IS), IH≈IS≈10A.

  However, when the load current Io is smaller than the soft switching current IS, the hard switching current IH does not flow, so the hard switch converter 10 does not operate normally, and the output voltage Vo may be fixed to the target value (= 20V). become unable.

  For example, as shown in FIG. 5, when Io = 5A (<IS), IH≈0A and IS≈Io. As a result, the output feedback control of the hard switch converter 10 does not work, and the output voltage Vo rises from the target value (= 20V).

  In view of the above knowledge, the drive phase number switching control unit 32 prevents the total of the soft switching output currents IS1 to ISn flowing in the driven soft switch converters 20 (1) to 20 (n) from exceeding the load current Io. Next, the drive phase number switching control of the soft switch converters 20 (1) to 20 (n) is performed.

  FIG. 6 is a correlation diagram between the load current Io and the drive phase number Pnum. The specifications of the soft switch converters 20 (1) to 20 (n) assume that the soft switching output currents IS1 to ISn are fixed at 10A when the output voltage Vo is fixed at 20V.

  For example, as shown in the figure, the soft switch is set so that Pnum = 0 when Io = 8A, Pnum = 1 when Io = 16A, and Pnum = 2 when Io = 24A. If the drive phase number switching control of the converters 20 (1) to 20 (n) is performed, the hard switching output current IH does not become 0A. Therefore, since the output feedback control of the hard switch converter 10 is always applied regardless of the magnitude of the load current Io, the output voltage Vo can be maintained at the target value.

  FIG. 7 is an output waveform diagram during drive phase number switching control. The output voltage Vo is depicted in the upper part of the figure, and the load current Io (solid line), the hard switching output current IH (dashed line), and the soft switching output currents IS1 and IS2 are shown in the lower part of the figure. (Dash-dot and two-dot chain lines). In addition, the number of drive phases Pnum is also drawn together with the time axis.

  Prior to time t1, since the load current Io is 8 A, the drive phase number Pnum is set to “0”. Accordingly, since the soft switching output currents IS1 and IS2 are both 0 A, the load current Io is all covered by the hard switching output current IH (Io≈IH).

  When the load current Io increases from 8A to 16A at time t1, the drive phase number Pnum switches from “0” to “1”. Therefore, the soft switching output current IS1 increases to 10A. On the other hand, the hard switching output current IH increases transiently, but then decreases to 6 A as the soft switching output current IS1 increases. Thereafter, at time t1 to t2, the load current Io is covered by the hard switching output current IH and the soft switching output current IS1 (= Io≈IH + IS1). Note that the soft switching output current IS2 remains 0A.

  When the load current Io increases from 16A to 24A at time t2, the drive phase number Pnum is switched from “1” to “2”. Therefore, the soft switching output current IS2 increases to 10A. On the other hand, the hard switching output current IH increases transiently, but then decreases to 4 A as the soft switching output current IS2 increases. Thereafter, at times t2 to t3, the load current Io is covered by the hard switching output current IH and the soft switching output currents IS1 and IS2 (= Io≈IH + IS1 + IS2). The soft switching output current IS1 remains 10A.

  When the load current Io decreases from 24A to 16A at time t3, the number of drive phases Pnum switches from “2” to “1”. Therefore, the soft switching output current IS2 returns to 0A. On the other hand, the hard switching output current IH decreases transiently, but then increases to 6 A as the soft switching output current IS2 decreases. Thereafter, at times t3 to t4, the load current Io is covered by the hard switching output current IH and the soft switching output current IS1 (= Io≈IH + IS1). The soft switching output current IS1 remains 10A.

  When the load current Io decreases from 16A to 8A at time t4, the drive phase number Pnum switches from “1” to “0”. Therefore, the soft switching output current IS1 returns to 0A. On the other hand, the hard switching output current IH decreases transiently, but then increases to 8 A as the soft switching output current IS1 decreases. After time t4, both the soft switching output currents IS1 and IS2 become 0A, so that the load current Io returns to the state covered by the hard switching output current IH (Io≈IH).

  As described above, since the multiphase converter 1 of this configuration example does not require the balance control of the hard switching output current IH and the soft switching output currents IS1 to ISn, the soft switch converters 20 (1) to 20 ( Even if the number of phases of n) is increased, only one current sensor (only the current detection unit 50) is required. Therefore, it is advantageous in terms of circuit scale and cost.

  Below, the specific circuit structure and operation | movement of each part of the polyphase converter 1 are demonstrated.

<Switch converter>
FIG. 8 is a diagram illustrating a configuration example of each of the hard switch converter 10 and the soft switch converters 20 (1) and 20 (2).

  The hard switch converter 10 is a synchronous rectification step-down DC / DC converter, and includes an output transistor 11, a synchronous rectification transistor 12, and a coil 13. The source and back gate of the output transistor 11 are connected to the input terminal of the input voltage Vi. The drain of the output transistor 11 and the drain of the synchronous rectification transistor 12 are both connected to the first end of the coil 13. The source and back gate of the synchronous rectification transistor 12 are both connected to the ground terminal. The second end of the coil 13 is connected to the output end of the output voltage Vo.

  The hard switch converter 10 of this configuration example generates the output voltage Vo from the input voltage Vi by turning on and off the output transistor 11 and the synchronous rectification transistor 12 in a complementary manner. In the present specification, the term “complementary” means that the on / off state of the output transistor 11 and the synchronous rectifying transistor 12 is completely reversed, and from the viewpoint of preventing a through current, both are turned off simultaneously. It is used to include the case where a period is provided.

  Each of the soft switch converters 20 (1) and 20 (2) is a diode rectification step-down DC / DC converter, and includes an output transistor 21, a capacitor 22, coils 23 and 24, and a rectifier diode 25. . The source and back gate of the output transistor 21 and the first terminal of the capacitor 22 are connected to the input terminal of the input voltage Vi. The drain of the output transistor 21 and the second end of the capacitor 22 are connected to the first end of the coil 23. The second end of the coil 23 is connected to the first end of the coil 24 and the cathode of the rectifier diode 25. The anode of the rectifier diode 25 is connected to the ground terminal. The second end of the coil 24 is connected to the output end of the output voltage Vo.

  The soft switch converters 20 (1) and 20 (2) of this configuration example switch the output transistor 21 at a timing when the voltage across the output transistor 21 or the current across the output transistor 21 becomes zero due to LC resonance.

  Basically, the period of the LC resonance is determined by the capacitance value C of the capacitor 22, the inductance value L of the coil 23, and the load Z (other elements are not irrelevant, but are ignored here). . Since the capacitance value C and the inductance value L are element parameters, they are constant regardless of the circuit operation. Further, in this operation method, since the soft switching currents IS1 and IS2 are constant even when the load Z changes, the load Z is considered constant when the soft switch converters 20 (1) and 20 (2) are viewed individually. Can be tricked. Therefore, since it can be considered that the above three parameters (L, C, Z) are all constant, the period of the LC resonance is always constant regardless of the entire system.

  Therefore, clock signals CLK1 and CLK2 having a constant switching frequency so that the output transistor 21 is switched at the timing when the voltage across the output transistor 21 or the current across the output transistor becomes zero due to LC resonance (see FIG. 10). If it is set, soft switching operation can be realized without requiring special control.

  When the output voltage Vo is fixed, the circuit design as described above is possible. However, when the output voltage Vo is to be changed, the load Z also changes accordingly, so some timing control is required.

  A capacitor C1 is connected between the input terminal of the input voltage Vi and the ground terminal as input smoothing means common to each converter. A capacitor C2 is connected between the output terminal of the output voltage Vo and the ground terminal as an output smoothing means common to each converter.

<Output voltage controller>
FIG. 9 is a diagram illustrating a configuration example of the output voltage control unit 31. The output voltage control unit 31 of this configuration example includes resistors R1 to R4, a comparator CMP, and a driver DRV.

  The first end of the resistor R1 is connected to the input end of the output voltage Vo (= corresponding to the voltage detection signal DET1). The second end of the resistor R1 and the first end of the resistor R2 are connected to the inverting input terminal (−) of the comparator CMP. A second end of the resistor R2 is connected to the ground end. A first end of the resistor R3 is connected to an input end of the reference voltage Vref. The second end of the resistor R3 and the first end of the resistor R4 are connected to the non-inverting input terminal (+) of the comparator CMP. The second end of the resistor R4 is connected to the output end of the comparator CMP.

  The comparator CMP compares the non-inverted input signal (+) and the inverted input signal (−) to generate a comparison signal S1. The comparison signal S1 is at a high level when the non-inverting input signal (+) is higher than the inverting input signal (−), and is at a low level when the non-inverting input signal (+) is lower than the inverting input signal (−). Become.

  The resistors R1 to R4 and the comparator CMP function as a hysteresis comparator whose threshold is switched according to the logic level of the comparison signal S1.

  The driver DRV generates a gate signal G1 corresponding to the comparison signal S1 and outputs it to the hard switch converter 10. In the hard switch converter 10, the output transistor 11 and the synchronous rectification transistor 12 are switched according to the gate signal G1. For example, when the comparison signal S1 is at a high level, the output transistor 11 is turned on and the synchronous rectification transistor 12 is turned off. Conversely, when the comparison signal S1 is at a low level, the output transistor 11 is turned off and the synchronous rectification transistor is turned off. 12 may be turned on.

  In this figure, the hysteresis method is exemplified as the output feedback control method of the output voltage control unit 31, but other output feedback control methods (for example, linear control methods such as a voltage mode control method and a current mode control method, or Alternatively, a non-linear control method such as a fixed on-time method or a fixed off-time method may be employed.

<Drive phase number switching control unit>
FIG. 10 is a diagram illustrating a configuration example of the drive phase number switching control unit 32. Resistors R11 to R14 and R21 to R24, comparators CMP1 and CMP2, drivers DRV1 and DRV2, and AND operators AND1 and AND2.

  A first end of the resistor R11 is connected to an input end of a voltage signal corresponding to the load current Io (= corresponding to the current detection signal DET2 in FIG. 1). The second end of the resistor R11 and the first end of the resistor R12 are connected to the inverting input terminal (−) of the comparator CMP1. A second end of the resistor R12 is connected to the ground end. A first end of the resistor R13 is connected to an input end of a voltage signal corresponding to the reference current Iref1. The second end of the resistor R13 and the first end of the resistor R14 are connected to the non-inverting input terminal (+) of the comparator CMP1. The second end of the resistor R14 is connected to the output end of the comparator CMP1.

  The comparator CMP1 compares the non-inverted input signal (+) and the inverted input signal (−) to generate a comparison signal S11. The comparison signal S11 is at a high level when the non-inverting input signal (+) is higher than the inverting input signal (−), and is at a low level when the non-inverting input signal (+) is lower than the inverting input signal (−). Become.

  The resistors R11 to R14 and the comparator CMP1 function as a hysteresis comparator whose threshold is switched according to the logic level of the comparison signal S11.

  The AND operator AND1 generates a logical product signal S12 of the logical inversion signal of the comparison signal S11 and the clock signal CLK1. Therefore, when the comparison signal S11 is at a high level, the logical product signal S12 is fixed at a low level. On the other hand, when the comparison signal S11 is at a low level, the clock signal CLK1 is output through as the logical product signal S12.

  The driver DRV1 generates a gate signal G11 corresponding to the logical product signal S12 and outputs it to the soft switch converter 20 (1). In the soft switch converter 20 (1), the output transistor 21 is switched according to the gate signal G11. For example, when the logical product signal S12 is at a high level, the output transistor 21 is turned on. Conversely, when the logical product signal S12 is at a low level, the output transistor 21 is turned off.

  A first end of the resistor R21 is connected to an input end of a voltage signal corresponding to the load current Io (= corresponding to the current detection signal DET2 in FIG. 1). The second end of the resistor R21 and the first end of the resistor R22 are connected to the inverting input terminal (−) of the comparator CMP2. A second end of the resistor R22 is connected to the ground end. A first end of the resistor R23 is connected to an input end of a voltage signal corresponding to the reference current Iref2 (> Iref1). The second end of the resistor R23 and the first end of the resistor R24 are connected to the non-inverting input terminal (+) of the comparator CMP2. The second end of the resistor R24 is connected to the output end of the comparator CMP2.

  The comparator CMP2 compares the non-inverting input signal (+) and the inverting input signal (−) to generate a comparison signal S21. The comparison signal S21 is at a high level when the non-inverting input signal (+) is higher than the inverting input signal (−), and is at a low level when the non-inverting input signal (+) is lower than the inverting input signal (−). Become.

  The resistors R21 to R24 and the comparator CMP2 function as a hysteresis comparator whose threshold is switched according to the logic level of the comparison signal S21.

  The AND operator AND2 generates a logical product signal S22 of the logical inversion signal of the comparison signal S21 and the clock signal CLK2. Therefore, when the comparison signal S21 is at a high level, the logical product signal S22 is fixed at a low level. On the other hand, when the comparison signal S21 is at a low level, the clock signal CLK2 is output through as the logical product signal S22.

  The clock signals CLK1 and CLK2 may be the same signal or different signals. For example, when it is necessary to suppress the ripple component of the output voltage Vo, it is also optional to perform the interleave control by inverting the phases of the clock signals CLK1 and CLK2.

  The driver DRV2 generates a gate signal G21 corresponding to the logical product signal S22 and outputs it to the soft switch converter 20 (2). In the soft switch converter 20 (2), the output transistor 21 is switched according to the gate signal G21. For example, when the logical product signal S22 is at a high level, the output transistor 21 is turned on. Conversely, when the logical product signal S22 is at a low level, the output transistor 21 is turned off.

  As described above, the drive phase number switching control unit 32 of this configuration example compares the current detection signal DET2 (= corresponding to the output current Io) and the predetermined threshold signal (= corresponding to the reference currents Iref1 and Iref2) for comparison. The comparators CMP1 and CMP2 that generate the signals S11 and S21 are included, and the drive phase number switching control of the soft switch converters 20 (1) and 20 (2) is performed according to the comparison signals S11 and S21. Hereinafter, the operation will be described in detail with reference to the drawings.

  FIG. 11 is a timing chart showing an example of drive phase number switching control. From the top, load current Io (solid line), reference currents Iref1 and Iref2 (one-dot chain line and two-dot chain line), comparison signals S11 and S21, logic The product signals S12 and S22 and the drive phase number Pnum are depicted.

  In the drawing, for convenience of explanation, the reference currents Iref1 and Iref2 are depicted so as to fluctuate with hysteresis. That is, the reference current Iref1 varies between the upper reference current Iref1H and the lower reference current Iref1L in accordance with the comparison signal S11. Further, the reference current Iref2 varies between the upper reference current Iref2H and the lower reference current Iref2L in accordance with the comparison signal S21.

  Prior to time t11, since Io <Iref1H <Iref2H, both comparison signals S11 and S21 are at a high level. Accordingly, since both the logical product signals S12 and S22 are fixed at the low level, the output transistor 21 remains off in both the soft switch converters 20 (1) and 20 (2). Such a state corresponds to a state where the drive phase number Pnum is “0”.

  When Iref1H <Io <Iref2H at time t11, the comparison signal S11 falls to a low level. Accordingly, since the clock signal CLK1 is output through as the logical product signal S12, switching of the output transistor 21 is started in the soft switch converter 20 (1). On the other hand, since the logical product signal S22 is maintained at the low level, in the soft switch converter 20 (2), the output transistor 21 remains off. Such a state corresponds to a state where the drive phase number Pnum is switched from “0” to “1”. After time t11, the reference current Iref1 is pulled down from the upper reference current Iref1H to the lower reference current Iref1L. Therefore, even if the load current Io fluctuates in the vicinity of the upper reference current Iref1H due to the influence of the output ripple or the like, the logic level of the comparison signal S11 does not react sensitively, so that the drive phase number Pnum is not switched unnecessarily. Absent.

  When Iref2H <Io at time t12, the comparison signal S21 also falls to a low level. Accordingly, since the clock signal CLK2 is output through as the logical product signal S22, the switching of the output transistor 21 is started also in the soft switch converter 20 (2). Such a state corresponds to a state where the drive phase number Pnum is switched from “1” to “2”. After time t12, the reference current Iref2 is pulled down from the upper reference current Iref2H to the lower reference current Iref2L. Therefore, even if the load current Io fluctuates in the vicinity of the upper reference current Iref2H due to the influence of the output ripple or the like, the logic level of the comparison signal S21 does not react sensitively, so that the drive phase number Pnum is switched unnecessarily. Absent.

  When Iref1L <Io <Iref2L at time t13, the comparison signal S21 rises to a high level. Accordingly, since the logical product signal S22 is fixed at the low level, the switching of the output transistor 21 is stopped in the soft switch converter 20 (2). On the other hand, since the through output of the clock signal CLK1 is maintained as the logical product signal S12, the switching of the output transistor 21 is continued in the soft switch converter 20 (1). Such a state corresponds to a state where the drive phase number Pnum is switched from “2” to “1”. After time t13, the reference current Iref2 is raised from the lower reference current Iref2L to the upper reference current Iref2H. Therefore, even if the load current Io fluctuates in the vicinity of the lower reference current Iref2L due to the influence of the output ripple or the like, the logic level of the comparison signal S21 does not react sensitively, so the drive phase number Pnum is switched unnecessarily. There is no.

  When Io <Iref1L at time t14, the comparison signal S11 rises to a high level. Therefore, since the logical product signal S12 is fixed at the low level, the switching of the output transistor 21 is also stopped in the soft switch converter 20 (1). Such a state corresponds to a state where the drive phase number Pnum is switched from “1” to “0”. After time t14, the reference current Iref1 is raised from the lower reference current Iref1L to the upper reference current Iref1H. Therefore, even if the load current Io fluctuates in the vicinity of the lower reference current Iref1L due to the influence of the output ripple or the like, the logic level of the comparison signal S11 does not react sensitively, so that the drive phase number Pnum is switched unnecessarily. There is no.

  In the above, an example in which the drive phase number switching control unit 32 is configured by an analog circuit has been described. However, a similar operation can be implemented by arithmetic processing. Hereinafter, it will be described in detail with reference to the drawings.

  FIG. 12 is a timing chart showing a modified example of the drive phase number switching control. In order from the top, the load current Io, the upper reference current Iref2H (= 2Isf + Ix), the lower reference current Iref2L (= 2Isf + Iy), and the drive phase A number Pnum is depicted.

  In this figure, the load current is Io, the soft switching output current determined according to the output voltage Vo is Isf, and the hysteresis setting currents are Ix and Iy (where 0 ≦ Iy <Ix). In particular, a specific description will be given below assuming that Isf = 10A, Ix = 3A, and Iy = 1A.

  At time t21, the load current Io increases from 22A to 24A. As described above, when the load current Io increases, the drive phase number switching control unit 32 performs a calculation process of (Io−Ix) / Isf and uses the calculation result (truncated after the decimal point) as the drive phase number Pnum. More specifically, when Io = 22A, (Io−Ix) / Isf = (22−3) /10=1.9, and the calculation result is “1”. On the other hand, when Io = 24A, (Io−Ix) / Isf = (24-3) /10=2.1, and the calculation result is “2”. Therefore, the drive phase number Pnum is switched from “1” to “2” at the time t21.

  At time t22, the load current Io decreases from 24A to 22A. As described above, when the load current Io decreases, the drive phase number switching control unit 32 performs the calculation process of (Io−Iy) / Isf, and adopts the calculation result (truncated after the decimal point) as the drive phase number Pnum. . More specifically, when Io = 24A, (Io−Iy) / Isf = (24−1) /10=2.3, and the calculation result is “2”. On the other hand, when Io = 22A, (Io−Iy) / Isf = (22-1) /10=2.1, and the calculation result is “2”. Therefore, at time t22, the drive phase number Pnum is maintained at “2”.

  At time t23, the load current Io decreases from 22A to 18A. As described above, when the load current Io is decreased, the drive phase number switching control unit 32 performs the calculation process of (Io−Iy) / Isf, and the calculation result (truncated after the decimal point). Is adopted as the drive phase number Pnum. More specifically, when Io = 22A, (Io−Iy) / Isf = (22-1) /10=2.1, and the calculation result is “2”. On the other hand, when Io = 18A, (Io−Iy) / Isf = (18−3) /10=1.5, and the calculation result is “1”. Therefore, the drive phase number Pnum is switched from “2” to “1” at time t23.

  In the above description, the example of switching the drive phase number Pnum between “1” and “2” has been described. However, the drive phase number switching control by the above arithmetic processing is performed by changing the drive phase number Pnum to “ It can be generalized and applied when switching between “k” and “k + 1” (k = 0, 1, 2,..., n−1).

<Application to vehicles>
FIG. 13 is an external view showing a configuration example of the vehicle X. The vehicle X of this configuration example includes various electronic devices X11 to X18 that operate by receiving an input voltage Vi from a battery (not shown) (corresponding to the DC voltage source E in FIG. 1). In addition, about the mounting position of the electronic devices X11-X18 in this figure, it may differ from the actual for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a braking unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is an electronic device that is incorporated into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.

  The electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device that includes a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

  In addition, the multiphase converter 1 demonstrated previously can be integrated in any of the electronic devices X11-X18.

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not limited to the above-described embodiment, and It should be understood that all modifications that fall within the meaning and range are included.

  The invention disclosed in the present specification can be suitably used, for example, as a power source for an electronic device mounted on a vehicle.

DESCRIPTION OF SYMBOLS 1 Multiphase converter 10 Hard switch converter 11 Output transistor 12 Synchronous rectification transistor 13 Coil 20 (1) -20 (n) Soft switch converter 21 Output transistor 22 Capacitor 23, 24 Coil 25 Rectifier diode 30 Control unit 31 Output voltage control part 32 Drive phase number switching control unit 40 Voltage detection unit 50 Current detection unit E DC voltage source Z Load R1-R4, R11-R14, R21-R24 Resistance C1, C2 Capacitor CMP, CMP1, CMP2 Comparator DRV, DRV1, DRV2 Driver AND1, AND2 AND operator X Vehicle X11-X18 Electronic equipment

Claims (10)

A hard switch converter that performs power conversion between the input unit and the output unit;
At least one soft switch converter connected in parallel to the hard switch converter;
A multiphase converter characterized by comprising: A voltage detection unit that detects an output voltage appearing in the output unit and generates a voltage detection signal;
An output voltage control unit that performs drive control of the hard switch converter so that the output voltage becomes a target value according to the voltage detection signal;
The multiphase converter according to claim 1, further comprising: A current detection unit that detects a load current flowing through the output unit and generates a current detection signal;
A drive phase number switching control unit for performing drive phase number switching control of the soft switch converter according to the current detection signal;
The multiphase converter according to claim 2, further comprising:   The drive phase number switching control unit performs drive phase number switching control of the soft switch converter so that the total of the soft switching output currents flowing through the soft switch converter being driven does not exceed the load current. The multiphase converter according to claim 3.   The drive phase number switching control unit includes a comparator that generates a comparison signal by comparing the current detection signal with a predetermined threshold signal, and performs drive phase number switching control of the soft switch converter according to the comparison signal. The multiphase converter according to claim 4.   The multi-phase converter according to claim 5, wherein the comparator is a hysteresis comparator.   When the load current is Io, the soft switching output current is Isf, and the hysteresis setting currents are Ix and Iy (where 0 ≦ Iy <Ix), the drive phase number switching control unit ( 5. The number of drive phases is determined according to (Io−Ix) / Isf, and the number of drive phases is determined according to (Io−Iy) / Isf when the load current decreases. Phase converter.   The soft switch converter includes an output transistor, a coil, and a capacitor, and switches the output transistor at a timing at which a voltage or current between both ends of the output transistor becomes zero by LC resonance. The multiphase converter according to any one of claims 1 to 7. The multiphase converter according to any one of claims 1 to 8,
A load that operates by receiving power supply from the multiphase converter;
An electronic device comprising: Battery,
The electronic device according to claim 9, which operates by receiving power supply from the battery;
The vehicle characterized by having.

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