WO2020020157A1 - 视频信号识别方法、装置、电子设备及可读存储介质 - Google Patents

视频信号识别方法、装置、电子设备及可读存储介质 Download PDF

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Publication number
WO2020020157A1
WO2020020157A1 PCT/CN2019/097293 CN2019097293W WO2020020157A1 WO 2020020157 A1 WO2020020157 A1 WO 2020020157A1 CN 2019097293 W CN2019097293 W CN 2019097293W WO 2020020157 A1 WO2020020157 A1 WO 2020020157A1
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Prior art keywords
video signal
target
line
type
ptz
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PCT/CN2019/097293
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English (en)
French (fr)
Inventor
卞学飞
张海龙
王军
马强
Original Assignee
杭州海康威视数字技术股份有限公司
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Priority claimed from CN201810827448.9A external-priority patent/CN110769180B/zh
Priority claimed from CN201810827466.7A external-priority patent/CN110769181B/zh
Priority claimed from CN201810827454.4A external-priority patent/CN110769176B/zh
Application filed by 杭州海康威视数字技术股份有限公司 filed Critical 杭州海康威视数字技术股份有限公司
Publication of WO2020020157A1 publication Critical patent/WO2020020157A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/004—Diagnosis, testing or measuring for television systems or their details for digital television systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

Definitions

  • the present application relates to video surveillance technology, and in particular, to a video signal identification method, device, electronic device, and readable storage medium.
  • the traditional video surveillance industry mainly includes video capture devices, such as analog cameras, and video storage devices, such as DVR (Digital Video Recorder, Hard Disk Video Recorder), and other products. External scenes are collected by video capture devices and transmitted to video storage devices for storage and video. Analysis and other processing.
  • video capture devices such as analog cameras
  • video storage devices such as DVR (Digital Video Recorder, Hard Disk Video Recorder), and other products.
  • DVR Digital Video Recorder, Hard Disk Video Recorder
  • External scenes are collected by video capture devices and transmitted to video storage devices for storage and video. Analysis and other processing.
  • the video capture device For video signal transmission between a video capture device and a video storage device, the video capture device needs to modulate the output video signal, and the video storage device needs to demodulate the input video signal. Because there are many types of video capture devices, the corresponding video signal formats also differ. Therefore, in order to ensure compatible access to video signals, video storage devices need to be able to accurately identify the received video signals.
  • the present application provides a video signal identification method, device, electronic device, and readable storage medium.
  • a video signal identification method including: when a video signal is received, using the PTZ protocol to read a PTZ signal in a blanking line of the video signal to obtain the read data Identifying the type of the video signal based on the read data.
  • a video signal identification device including: a PTZ protocol reading unit, configured to read a video signal in a blanking line of the video signal using the PTZ protocol when a video signal is received.
  • the PTZ signal obtains the read data;
  • a type identification unit is configured to identify the type of the video signal according to the read data.
  • an electronic device including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete each other through the communication bus.
  • the memory is used to store a computer program; and the processor is used to implement the video signal identification method when the computer program stored in the memory is executed.
  • a computer-readable storage medium stores a computer program, and the computer program implements the foregoing video signal identification method when executed by a processor.
  • the PTZ signal in the blanking line of the video signal is read using the PTZ protocol to obtain the read data; the read data is identified based on the read data. Describe the type of video signal.
  • the video signal identification method provided by the present application improves the accuracy of video signal identification.
  • FIG. 1 is a flowchart of a method for identifying a video signal system according to an exemplary embodiment of the present application
  • FIG. 2 is a schematic diagram showing one frame of a 4M12.5 video signal and two frames of a 720P25 video signal, according to an exemplary embodiment of the present application;
  • FIG. 3 is a flowchart of a method for identifying a video signal system according to another exemplary embodiment of the present application.
  • FIG. 4 is a schematic diagram illustrating a system for identifying a received video signal by using a priority polling method according to an exemplary embodiment of the present application
  • FIG. 5 is a flowchart of a method for identifying a video signal type according to an exemplary embodiment of the present application
  • Fig. 6 is a flow chart showing a method for identifying a video signal type according to still another exemplary embodiment of the present application.
  • FIG. 7 is a flowchart of a method for identifying a video signal type according to still another exemplary embodiment of the present application.
  • FIG. 8 is a flowchart of a method for identifying a video signal type according to another exemplary embodiment of the present application.
  • FIG. 9 is a flowchart illustrating a method for identifying a video signal by false lock according to an exemplary embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a video signal identification device according to an exemplary embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a video signal identification device according to another exemplary embodiment of the present application.
  • FIG. 12 is a schematic diagram of a hardware structure of an electronic device according to an exemplary embodiment of the present application.
  • FIG. 1 is a schematic flowchart of a video signal identification method according to an embodiment of the present application.
  • the video signal identification method can be applied to a video processing device having an AD (Analog-to-Digital, analog-to-digital) chip.
  • AD Analog-to-Digital, analog-to-digital
  • a video processing device is a DVR as an example
  • the method may include the following steps.
  • Step S100 Read the first register to obtain a standard value of the received video signal.
  • the AD chip when the AD chip receives a video signal, it will configure the value of the video signal's format information in a specific register address according to the format information in the video signal, which is simply referred to as the format value in this document.
  • the register can be called the first register.
  • the AD chip can record the format information of the received video signal in bit0-bit2 of the register at address 0x3.
  • the video signal system can include, but is not limited to: NTSC (National Television Standards Committee), PAL (Phase Alteration Line), 720P25 / 30, 720P50 / 60, 1080P25 / 30, 1080P HALF25 / 30, 3M18, 4M12.5 / 15, 4M25 / 30, 4M HALF 25/30, 5M12, 5M20, 5M HALF 20, 8M12.5 / 15, 8M HALF 12.5 / 15, etc .; video signals of all standards are There is a corresponding standard value.
  • NTSC National Television Standards Committee
  • PAL Phase Alteration Line
  • the SoC (System-on-a-Chip) chip of the DVR can obtain the system value by reading the first register of the AD chip.
  • the DVR can also use the CPU (Central Processing Unit), DSP (Digital Signal Processing) and other chips to read the register value of the AD chip, which is not limited in this application.
  • the standard value in some cases, the standard of the received video signal can be directly determined.
  • the SoC chip can read the value of bit0-bit2 of the 0x3 register.
  • Step S110 When the value of the system is shared by the target video signals of multiple systems, configure the second register according to the system of at least one target video signal of the multiple systems, and detect whether the received video signal is in a locked state.
  • the format of the video signal corresponding to this value may be NTSC or PAL; when the format value is 0x7, the format of the video signal corresponding to this value may be 3M18, 5M12, or 5M20.
  • the DVR's SoC chip reads the format value of the first register, it can be determined whether the format value is shared by the target video signals of multiple formats, and when it is determined that the format value is shared by the target video signals of multiple formats At the same time, the format of the received video signal is further identified according to other strategies.
  • the SoC chip when it is determined that the read standard value is shared by video signals of multiple standards (referred to herein as a target video signal), the SoC chip may be configured according to the standard of at least one target video signal among the multiple standards.
  • the second register of the AD chip and detects whether the received video signal is locked.
  • a polling method may be used to select the target video signal format separately, configure the second register according to the selected target video signal format, and detect whether the received video signal is in a locked state.
  • the SoC chip can follow the order of format 1-3 from front to back, first Select system 1, configure its corresponding second register according to system 1, and detect whether the received video signal is locked. If it is unlocked, then select system 2 and configure its corresponding second register according to system 2. And detect whether the received video signal is in a locked state; if it is in an unlocked state, then select system 3, configure its corresponding second register according to system 3, and detect whether the received video signal is in a locked state.
  • the specific address of the second register corresponding to various standards may be different, and may also include multiple register addresses. However, since the functions implemented are similar, this application collectively refers to them as the second register.
  • Step S120 When the second register is configured according to the first target system and it is detected that the received video signal is in a locked state, it is determined that the system of the received video signal is the first target system.
  • the first target system does not specifically refer to a certain fixed system, but may refer to any one of the above-mentioned multiple target video signals (referred to herein as the first target video signal). Format.
  • the SoC chip may stop the system selection and the configuration of the second register and determine the system of the received video signal. For the first target system.
  • detecting that the received video signal is in a locked state may include detecting a state of a line synchronization signal lock (HLOCK) and a field synchronization signal lock (VLOCK, also referred to as a frame synchronization signal lock) of the received video signal.
  • the states are all locked.
  • configuring the second register corresponding to the target video signal format of at least one of the multiple formats and detecting whether the received video signal is in a locked state may include: determining multiple formats Priority of each target video signal format; in order of priority from high to low, configure a second register corresponding to at least one target video signal format and detect whether the received video signal is in a locked state; when it is detected When the received video signal is in a locked state, the standard of the received video signal is the first target standard.
  • the priority of the system of each target video signal may be determined.
  • the user may determine the priority of each target video signal system according to the usage probability of each target video signal system.
  • the usage probability of each target video signal format may be an empirical value and may be pre-configured in an AD chip or SoC chip; the higher the target video signal usage probability, the higher its priority.
  • the SoC chip may poll each target video signal in order of priority from high to low, and configure a second corresponding to the standard of at least one target video signal. Register, and detect whether the received video signal is locked. When it is detected that the received video signal is in a locked state, the SoC chip determines the system configured with the second register at this time as the first target system, and stops polling.
  • the SoC chip can determine the priority of system 1 The level is higher than the priority of the system 2 and accordingly, the corresponding second register can be configured according to the system 1 and it is detected whether the received video signal is in a locked state. If the video signal is in the locked state, it is determined that the received video signal format is the format 1 and the step of configuring the second register is ended. If the video signal is in an unlocked state, then configure its corresponding second register according to system 2 and detect whether the received video signal is locked. If it is in the locked state, determine that the system of the received video signal is system 2.
  • the AD chip when the SoC chip configures the second register of the AD chip according to the target video signal format, and it is detected that the received video signal is not in the locked state, the AD chip may re-
  • the method described in step S100 to step S120 identifies the standard of the received video signal a certain number of times (can be set according to the actual scene), or identifies the standard of the received video signal according to other strategies, and the specific implementation thereof is not limited in this application.
  • the SoC chip may configure the second register multiple times according to the same system and determine whether the received video signal is in the locked state multiple times.
  • the foregoing configures the second register corresponding to at least one target video signal format in order of priority from high to low, and detects whether the received video signal is in a locked state.
  • the second register is configured according to the priority of the i-th target video signal format.
  • the target video signal format is determined to be the i-th target video signal format.
  • exit the process of configuring the second register if the received video signal is in an unlocked state, continue to configure the second register according to the priority order of the i-th target video signal system, and increase the number of times of configuration by 1.
  • the standard of the target video signal is determined to be the standard of the i-th target video signal, and the process of configuring the second register is exited.
  • the initial value of i may be 1, and i is a natural number. In another optional embodiment, the initial value of i may be 0, and i is a natural number.
  • different configurations of the target video signal system can be set according to different priorities, that is, the value of Ni can be different.
  • the order of the i-th target video signal according to the priority order is that the configuration number of the second register is Ni; the larger the i, the lower the priority (that is, the priority order is from high to low).
  • 1 ⁇ i ⁇ n where n is the number of standards of the target video signal.
  • 0 ⁇ i ⁇ n-1 where n is the number of standards of the target video signal.
  • the second register may be first configured according to the priority of the target video signal format (that is, the highest priority).
  • the number of configurations is less than or equal to N1
  • if the received video signal is in a locked state then Determine the standard of the target video signal as the standard of the first target video signal, and exit the configuration process.
  • each time the second register is configured it can be determined whether the received video signal is in a locked state, and when it is detected that the received video signal is in an unlocked state, the next configuration and judgment is continued.
  • the SoC chip may sort the second (ie The second register is configured by the target video signal format of the second highest priority).
  • the second register is configured by the target video signal format of the second highest priority.
  • the SoC chip sorts the nth (that is, the lowest priority) target video signal according to the priority, the number of times the second register is configured to Nn and the received video signal is still unlocked.
  • the described method identifies the standard of the received video signal a certain number of times (can be set according to the actual scene), or identifies the standard of the received video signal according to other strategies, and the specific implementation thereof is not limited in this application.
  • the priority of format 1 can be determined.
  • the level is higher than the standard 2 priority.
  • the number of times the SoC chip configures the second register according to the format 1 is greater than the number of times the second register is configured according to the format 2. For example, the number of times to configure the second register according to the format 1 is six times, and the number of times to configure the second register according to the format 2 is 3 times.
  • the line lengths of the multiple video signals may be different.
  • the multiple Line length of each video signal to identify the format of the multiple video signals.
  • the read format value when the read format value is shared by target video signals of multiple formats, before the second register is configured according to the target video signal format of at least one of the multiple formats, It may also include: determining the line lengths of multiple target video signals; if at least two of the multiple target video signals have the same line length, performing the above-mentioned configuration according to at least one of the multiple video formats Step of the second register; if the line lengths of the multiple target video signals are different, determine the format of the received video signal according to the respective line lengths of the multiple target video signals and the line length of the received video signal.
  • the line lengths of the multiple target video signals may be determined separately.
  • the format of the target video signal may be identified by using the method described in step S110-step S120.
  • the SoC chip may determine the format of the received video signal according to the line lengths of the multiple target video signals and the line length of the received video signal.
  • the SoC chip may also identify the format of the target video signal in the manner described in step S110-step S120.
  • the SoC chip can first identify the received video signal format based on the line length.
  • the line length cannot identify the received video signal format (that is, there are at least two types of target video signals with the same line length as the received video signal). )
  • the video signal system identification is further performed in the manner described in step S110-step S120; or, the video signal system identification may be performed directly in the manner described in step S110-step S120.
  • the foregoing determining the format of the received video signal according to the line length of multiple target video signals and the line length of the received video signal includes: reading a third register to obtain a line Long value; comparing the line length value and the respective line lengths of the various target video signals; when the line length value is the same as the line length of a target video signal, determining the standard of the target video signal as the The format of the received video signal is the first target format.
  • the SoC chip can determine the line length of the received video signal by reading the line length value obtained from the third register of the AD chip, and compare the line length of the received video signal with the line of each target video signal. Long, and determine the standard of the target video signal as the standard of the received video signal as the standard of the received video signal.
  • the format of the video signal includes NTSC, PAL, 720P25 / 30, 720P50 / 60, 1080P25 / 30, 1080P HALF25 / 30, 3M18, 4M12.5 / 15, 4M25 / 30, 4M HALF 25/30 , 5M12, 5M20, 5M HALF 20, 8M12.5 / 15, 8M HALF 12.5 / 15 as examples.
  • 3M18, 5M12, and 5M20 share a standard value
  • the line lengths of the video signals of the three formats are the same
  • the remaining formats Up to two formats in China share a standard value, such as 4M25 and 720P50; 4M30 and 720P60; 1080P25 and 8M12.5; 1080P30 and 8M15; NTSC and PAL; 4M12.5 and 720P25; 4M15 and 720P30, of which these share a standard value
  • the line lengths of the video signals of the two formats are the same.
  • the implementation process of the video signal system identification scheme may be as shown in FIG. 3, which may include the following steps.
  • Step S300 Read the first register to obtain the standard value of the received video signal.
  • Step S310 Determine whether the value of the standard is shared by the video signals of the three standards. If yes, go to step S320; otherwise, go to step S330.
  • Step S320 Identify a standard of the received video signal by using a line length judgment method.
  • the SoC chip may determine that the format of the received video signal is 3M18, 5M12, or 5M20.
  • the line length method can be used to identify the format of the received video signal, that is, the SoC chip can read the third register to obtain the line length value, determine the line length of the received video signal, and determine the length of the received video signal.
  • the line length is compared with the line length of the video signals of 3M18, 5M12, and 5M20. When the comparison result is the same, the format of the video signal corresponding to the line length is determined as the format of the received video signal, which is the first target format. .
  • Step S330 Determine whether the standard value is shared by the video signals of the two standards. If yes, go to step S340; otherwise, go to step S350.
  • Step S340 Use the priority polling method to identify the format of the received video signal.
  • the SoC chip when it is determined that the read format value is shared by two types of video signals, can identify the format of the received video signal by using the priority polling method, that is, it can first determine that the format value corresponds to Priority of the video signals of the two formats, and first configure the second register according to the video signal format of the higher priority, and detect whether the received video signal is locked, and if it is unlocked, then according to the priority
  • the low video signal format configures the second register and detects whether the received video signal is in a locked state.
  • the SoC chip can determine that the format value is shared by 4M25 and 720P50.
  • the AD chip uses the priority polling method to identify the format of the received video signal.
  • the specific implementation can be as follows: As shown in FIG. 4, it may include the following steps.
  • step S400 it is determined whether the count value of the counter is less than 6; if the count value is less than 6, go to step S410; otherwise, go to step S430.
  • Step S410 Configure the second register according to 4M25, and increase the count value of the counter by one.
  • Step S420 Detect whether the received video signal is in a locked state. If it is in the locked state, it is determined that the format of the received video signal is 4M25, and the priority polling is ended; otherwise, go to step S400.
  • Step S430 Configure the second register according to 720P50, and increase the count value of the counter by one.
  • Step S440 Detect whether the received video signal is in a locked state. If it is in the locked state, it is determined that the received video signal format is 720P50 and the priority polling is ended; otherwise, go to step S450.
  • Step S450 Determine whether the count value of the counter is less than 9; if the count value is less than 9, go to step S430; otherwise, end the priority polling.
  • the SoC chip can configure the second register according to 720P50 and detect whether the received video signal is locked status. If it is still unlocked at this time, continue to configure the second register according to 720P50 and detect whether the received video signal is locked.
  • the priority polling ends.
  • the SoC chip can also clear the counter to 0, re-determine the received video signal system value, and start a new video signal system identification in the above manner, or implement the video signal system according to other strategies. It is recognized that this embodiment of the present application does not limit this.
  • Step S350 Configure the second register according to the format corresponding to the format value, and detect whether the received video signal is in a locked state. If it is in the locked state, it is determined that the received signal system is the system corresponding to the system value; otherwise, the video signal system identification is ended.
  • the SoC chip may directly configure the second register according to the format corresponding to the format value and detect whether the received video signal is in In the locked state, if it is in the locked state, it is determined that the standard of the received signal is the standard corresponding to the standard value. That is, even if only one system uses the system value, it is necessary to determine whether it is locked. Because in actual use, the video signal format is correct, but the video signal content is abnormal.
  • the SoC chip may perform a new video signal in the manner described in S300-S350 again.
  • System identification, or identification of video signal systems according to other strategies, is not limited in this embodiment of the present application.
  • the first register is first read to obtain the standard value of the received video signal; when the standard value is shared by the target video signals of multiple formats, the target video signal according to at least one of the multiple formats is used. Configure the second register in the format and detect whether the received video signal is in the locked state; when the second register is configured in accordance with the first target format and it is detected that the received video signal is in the locked state, determine the format of the received video signal For the first target system.
  • the SoC chip of the DVR determines the format of the received video signal, since the video signal of one format may also correspond to multiple types, it is necessary to further determine the type of the video signal. For example, for a video signal whose format is 1080P25 / 30, the types include a TVI (Transport Video Interface), AHD (Analog High Definition), and the like.
  • TVI Transport Video Interface
  • AHD Analog High Definition
  • FIG. 5 is a schematic flowchart of a method for identifying a video signal type according to an embodiment of the present application.
  • the method may include the following steps.
  • Step S500 When a video signal is received, use the PTZ protocol to read the PTZ signal in the blanking line of the video signal to obtain the read data.
  • the PTZ (Pan / Tilt / Zoom, pan / tilt / zoom lens) protocol is developed to enable video capture devices and video storage devices to communicate.
  • the video capture device can exchange language information with the video storage device through the PTZ protocol.
  • the video capture device can control the video capture device to adjust the focus through the PTZ protocol.
  • the PTZ protocol inserts different signals in different blanking lines, so that there is a relatively obvious difference between the amplitude values of the related blanking lines. Therefore, after the DVR receives the video signal and determines that the video signal is the first target format, the DVR first determines whether the first target format includes multiple types, such as whether it includes two or more of multiple signal types such as TVI and AHD. Three. When the first target system includes multiple types, the AD chip can use the PTZ protocol to read the PTZ signal in the blanking line amplitude of the video signal, such as reading the blanking line of the video signal according to a preset PTZ signal receiving parameter. PTZ signal.
  • the preset PTZ signal receiving parameters can be set according to the blanking line characteristics of the video signal, including, but not limited to, the number of the blanking line read, the start bit of the blanking line read, and the read The number of bits (such as 24 bits) and pulse width of the blanking line taken.
  • each frame of a video signal is composed of an image information area and a blanking area.
  • the image information area stores one frame of valid image data.
  • the blanking area can store specific information at a specific location, and the signal amplitude at a location where no specific information is stored can be zero.
  • the first few lines of the blanking area may include a field synchronization signal, and some lines may include a PTZ signal and the like.
  • the PTZ signal may be a signal of several bytes located at a certain position in a certain line of the blanking area.
  • the PTZ signal can generally be considered as a digital signal, that is, in the video signal, the high level of the PTZ signal can always be a level that exceeds the high level discrimination threshold, and the low level can always be a less than low level discrimination Threshold level.
  • the specific format of the PTZ signal is determined by the PTZ protocol, which is not limited in this application.
  • using the PTZ protocol to read the PTZ signal in the blanking line of the video signal can start from the blanking line specified by the parameter and the start bit of the blanking line, and read the bit specified by the parameter according to the pulse width determined by the parameter Number (such as 24 bits) to obtain the value of multiple bits.
  • the multi-bit value can be further analyzed according to the PTZ protocol to obtain the read specific data.
  • Step S510 Identify the type of the video signal according to the read data.
  • the type of the video signal can be identified according to the value obtained after the reading.
  • a sine wave exists for the penultimate blanking line of a certain type of video signal (referred to herein as a target type), and the duration is usually about one line, while other types of video signals There is no sine wave in the penultimate blanking line of. Therefore, it can also be determined whether the video signal is the target type according to whether there is a sine wave in the penultimate blanking line of the video signal.
  • the target type is a TVI type.
  • the method may further include: detecting whether a sine wave exists in a penultimate blanking line of the video signal; The type of the video signal is the target type; otherwise, the step of reading the PTZ signal in the blanking line of the video signal using the PTZ protocol described above is determined to be performed.
  • the DVR when the DVR receives a video signal, the DVR can detect whether a sine wave exists in the penultimate blanking line of the received video signal through the AD chip.
  • a certain bit value of the fourth register can be set to 1. . If it is detected that a sine wave does not exist in the penultimate blanking line of the video signal, that is, it is determined that the type of the received video signal is not the target type, the value of this bit in the register can be set to 0.
  • the fourth register address may be 0x4, and the bit may be bit2.
  • the SoC chip of the DVR can determine whether the type of the received video signal is the target type by reading the value of the bit in the register of the AD chip.
  • the SoC chip may determine that the type of the video signal is the target type.
  • the AD chip of the DVR detects that the sine wave does not exist in the penultimate blanking line of the received video signal
  • the AD chip can further use the PTZ protocol to read the PTZ signal in the blanking line of the video signal and obtain the read.
  • the SoC chip identifies the type of video signal based on the read data.
  • reading the PTZ signal in the blanking line of the video signal using the PTZ protocol to obtain the read data may include: reading the first target blanking line of the video signal using the PTZ protocol. PTZ signal to get the first data read.
  • the above-mentioned identifying the type of the video signal according to the data obtained after reading may include: identifying the type of the video signal according to the first data obtained after reading.
  • the blanking line is located in a specific partial blanking line (any blanking line in this specific partial blanking line is referred to as a first target blanking line in this document), so that the There is a significant difference in the amplitude of the blanking line in a specific part. Therefore, the PTZ protocol can be used to read the PTZ signal in the first target blanking line to identify the type of the video signal.
  • the first target blanking line may be any blanking line from the 23-26th blanking line of the video signal.
  • the AD chip can read any blanking line (ie, the first target blanking line) in the 23-26 blanking lines of the received video signal, and according to the first target blanking line, Get the first data read from the PTZ signal, and then the SoC chip identifies the type of the video signal according to the first data.
  • any blanking line ie, the first target blanking line
  • Get the first data read from the PTZ signal Get the first data read from the PTZ signal
  • the SoC chip identifies the type of the video signal according to the first data.
  • the above-mentioned identifying the type of the video signal according to the read first data may include: if the first data is 0x00, identifying the type of the video signal as the first type; if the first data If it is greater than 0x00, the type of the video signal is identified as the second type.
  • the first type and the second type are different from the target type.
  • the first data of the first type of video signal is usually 0x00
  • the first data of the second type of video signal is usually data greater than 0x00
  • the first data is a video signal of 0x00
  • the type of is the first type
  • the type of the video signal with the first data greater than 0x00 is the second type.
  • the SoC chip when the first data of the video signal read by the AD chip is 0x00, the SoC chip can identify the type of the video signal as the first type; when the first data of the video signal read by the AD chip is the first type When the data is greater than 0x00, the SoC chip can identify the type of the video signal as the second type.
  • the PTZ protocol is used to read the PTZ signal in the blanking line of the video signal to obtain the read data, which may include: reading the video signal using the PTZ protocol.
  • the PTZ signal of the two target blanking lines is used to obtain the read second data.
  • the above-mentioned identifying the type of the video signal according to the data obtained after reading may include: identifying the type of the video signal according to the second data obtained after reading.
  • the first target blanking line is different from the second target blanking line.
  • the second target blanking line may be any blanking line in the 6-7th blanking line of the video signal.
  • the SoC chip may instruct the AD chip to read any blanking line in the 6-7th blanking line of the received video signal (that is, the second target blanking line), and according to the second target blanking line,
  • the PTZ signal obtains the read second data, and then the SoC chip identifies whether the type of the video signal is the first type or the second type according to the second data.
  • the above-mentioned identifying the type of the video signal based on the second data obtained after reading may include: if the second data is 0xff, identifying the type of the video signal as the first type; if If the second data is greater than 0x00 and less than 0xff, the type of the identified video signal is the second type.
  • the second data of the first type of video signal is usually 0xff or 0x00
  • the second data of most of the second type of video signal is usually data between 0x00 and 0xff, that is, greater than 0x00 And less than 0xff
  • the type of the video signal whose second data is 0xff is the first type
  • the type of the video signal whose data is the data between 0x00 and 0xff is the second type.
  • the SoC chip when the second data of the video signal read by the AD chip is 0xff, the SoC chip can identify the type of the video signal as the second type; when the second data of the video signal read by the AD chip is The data is any data between 0x00 and 0xff, that is, when it is greater than 0x00 and less than 0xff, the SoC chip can recognize that the type of the video signal is the second type.
  • the second data of the second type of video signal may be 0x00, so when the second data of the video signal read by the AD chip is 0x00, at this time, the video signal The type may be the second type or the first type, and the SoC chip needs to further identify the type of the video signal according to other strategies.
  • the above-mentioned identifying the type of the video signal according to the second data may include: if the second data is 0x00, identifying the video signal according to a color carrier detection state and a locked state of the video signal type.
  • the SoC chip may further identify the type of the video signal according to the detection state and the locked state of the color carrier of the video signal.
  • the above-mentioned identifying the type of the video signal according to the color carrier detection state and the locked state of the video signal may include: determining an EQ (EQualizer) value of the video signal; configuring a gain multiple according to the EQ value of the video signal; The first type configures the fifth register of the AD chip and detects the video signal; if the detection state of the color carrier is detected and the locked state of the color carrier is locked, it is determined that the type of the video signal is the first type.
  • EQ EQualizer
  • the SoC chip may first determine the EQ value of the video signal, that is, determine the attenuation degree of the video signal after transmission.
  • the EQ value of the video signal is calculated according to the attenuation degree of the color carrier of the video signal, and the specific implementation thereof can be referred to the related description in the existing related scheme, which is not described in this embodiment of the present application.
  • the SoC chip can configure the corresponding gain multiple of the AD chip according to the EQ value, and perform attenuation compensation on the video signal by adjusting the gain.
  • the fifth register can be configured in turn according to the first type and the second type, and the color carrier detection can be performed, so that the type of the video signal can be identified.
  • the SoC chip may first configure the fifth register according to the first type and detect the video signal. If the detection state of the color carrier is detected and the locked state of the color carrier is locked, it is determined that the type of the video signal is the first type.
  • the SoC chip may be configured according to the second type. Register, and detect the video signal again; at this time, if the detection state of the color carrier is detected and the locked state of the color carrier is locked, it is determined that the type of the video signal is the second type.
  • the AD chip when the SoC chip configures the fifth register according to the first type or the second type, the AD chip does not detect a color carrier, or detects a color carrier but the color carrier is not locked.
  • the SoC chip may determine that an unknown signal is received, or perform attenuation compensation and type recognition on the video signal again, and its specific implementation is not limited here.
  • the SoC chip in addition to configuring the fifth register according to the first type and then the fifth register according to the second type, may also first configure the fifth register according to the second type and then according to the first type.
  • One type configures the fifth register, and its specific implementation is not described in detail here.
  • the implementation manner of identifying the type of the video signal based on the PTZ signal in the single blanking line (the first target blanking line or the second target blanking line) of the video signal is only in the embodiment of the present application.
  • the type of the video signal may also be identified based on the PTZ signals in multiple blanking lines of the video signal.
  • the AD chip can read the PTZ signal in the 23-26 blanking line of the video signal separately.
  • the NVR can Identify the type of the video signal as the first type; if the data read from the PTZ signal in the 23-26 blanking line of the video signal are all data greater than 0x00, the NVR can identify the type of the video signal as the second type Type, its specific implementation is not repeated here.
  • the 24th blanking behavior example of the first target blanking behavior is described.
  • the implementation process of the video signal recognition scheme may be as shown in FIG. 7 and may include the following steps.
  • Step S700 When it is determined that the video signal of the first target system includes multiple types, it is detected whether a sine wave exists in the fourth blanking line of the video signal. If a sine wave exists, it is determined that the type of the video signal is the target type; otherwise, go to step S710.
  • the SoC chip may determine whether the type of the video signal is the target type according to whether a sine wave exists in the penultimate blanking line of the video signal.
  • the type of the video signal is determined as the target type; when a sine wave does not exist in the penultimate blanking line of the video signal, the The type is not the target type.
  • Step S710 Use the PTZ protocol to read the PTZ signal in the 24th blanking line of the video signal to obtain the read first data. If the first data is 0x00, the type of the video signal is determined to be the first type; otherwise, the type of the video signal is determined to be the second type.
  • the AD chip may use the PTZ protocol to read the PTZ signal in the 24th blanking line of the video signal to obtain the first data. If the first data is 0x00, the SoC chip may determine that the type of the video signal is the first type. If the first data is not 0x00, that is, the first data read according to the PTZ signal in the 24th blanking line of the video signal is greater than 0x00, the SoC chip may determine that the type of the video signal is the second type.
  • the sixth blanking behavior example of the second target blanking behavior is described.
  • the implementation process of the video signal recognition scheme may be as shown in FIG. 8 and may include the following steps.
  • Step S800 When it is determined that the video signal of the first target system includes multiple types, it is detected whether a sine wave exists in a penultimate blanking line of the video signal. If a sine wave exists, it is determined that the type of the video signal is the target type; otherwise, go to step S810.
  • the SoC chip may determine whether the type of the video signal is the target type according to whether a sine wave exists in the penultimate blanking line of the video signal.
  • the type of the video signal is determined as the target type; when a sine wave does not exist in the penultimate blanking line of the video signal, the The type is not the target type.
  • Step S810 Use the PTZ protocol to read the PTZ signal in the sixth blanking line of the video signal to obtain the read second data. If the second data is 0xff, the type of the video signal is determined to be the first type; if the second data is 0x00, the type of the video signal is identified according to the color carrier detection state and the locked state of the video signal; if the second data is neither 0x00 If it is not 0xff, it is determined that the type of the video signal is the second type.
  • the AD chip PTZ signal receiving parameter reads the PTZ signal in the sixth blanking line of the video signal to obtain the second data. If the second data is 0xff, the SoC chip may determine that the type of the video signal is the first type. If the second data is 0x00, the SoC chip can further identify the type of the video signal according to the color carrier detection state and the locked state of the video signal, and its specific implementation can refer to the flow shown in FIG. 6. If the second data is neither 0x00 nor 0xff, that is, the second data of the video signal is data between 0x00 and 0xff, the SoC chip may determine that the type of the video signal is the second type.
  • the PTZ signal in the blanking line of the video signal is read using the PTZ protocol to obtain the read data, and the type of the video signal is identified based on the read data, thereby improving the video The accuracy of the signal type identification, and finally the format and type of the video signal.
  • the two standards share the same standard value, and the video signals of the two standards have the same line length.
  • the SoC chip configures its corresponding second register according to the standard 720P25, it is detected that the HLOCK and VLOCK of the received video signal are both locked. At this time, the SoC chip will It is considered that the standard of the received signal is 720P25, and a misjudgment occurs. Furthermore, in the subsequent process, because the video signal system identification error will cause abnormal video signal processing, it is necessary to determine the video signal system identification in the above manner. Whether the video signal is misjudged.
  • the method may further include: detecting whether a color carrier of the received video signal is in a locked state; if the received If the color carrier of the video signal is in an unlocked state, it is determined that the received video signal is locked by mistake.
  • the color carrier of the video signal cannot be locked (ie, the state of SLOCK is unlocked). Therefore, it can be determined whether the video signal is locked by mistake according to whether the color carrier is in the locked state.
  • the locked state of the color carrier of the received video signal is locked; if the locked state of the color carrier is locked, determine the system of the received video signal It is the first target system; if the locked state of the color carrier is unlocked, it is determined that the received video signal is locked by mistake.
  • the SoC chip when the SoC chip determines that the received video signal is locked incorrectly, the SoC chip may re-identify the received video signal according to the method described in FIG. 1, or identify the received video according to other strategies.
  • the specific implementation of the signal system is not described in detail here.
  • the method may further include: setting the range of gain adjustment to the maximum, And adjust the gain to the maximum; detect whether the locked state of the color carrier of the received video signal is locked; if the locked state of the color carrier of the received video signal is unlocked, perform the above steps of determining the video signal is locked by mistake .
  • the SoC chip when it is determined that the locked state of the color carrier of the received video signal is unlocked, the SoC chip can set the range of gain adjustment to the maximum and the gain to the maximum to avoid SLOCK being unable to fail due to signal attenuation. Lock, and detect whether the locked state of the color carrier of the received video signal is locked.
  • the SoC chip can determine that the received video signal is locked by mistake; if the color carrier of the received video signal is locked, the SoC chip can Make sure that the format of the received video signal is correct.
  • the type of video signal is AHD
  • the frame rates of target video signals of multiple different standards sharing the same standard value may be different, that is, the duration of one frame of the target video signals of the multiple different standards may be different.
  • the duration of one frame of one of the target video signals of different standards is an even multiple of the duration of one frame of the other video signals, for the duration of one frame of the target video signal, there will be even numbers of other target video signals.
  • the middle line and a certain number of lines above and below a frame of the target video signal are image information areas for the target video signal and blanking areas for other target video signals. At this time, the The difference between the voltage values in the image information area and the blanking area can be used to distinguish different systems.
  • the second register when the second register is configured according to the first target system and it is detected that the received video signal is in a locked state, before the foregoing determining that the system of the received video signal is the first target system, It may include: if the frame rate of the first target video signal is half of the frame rate of the other target video signals, reading the voltage value of the target row of the first target video signal of one frame, where the target is the first target video signal of one frame Any of the lines between the positive middle line and the preset number of lines; if the voltage value of the target line is positive, determine the standard of the received video signal as the first target system; if the voltage value of the target line is negative or Zero, it is determined that the received video signal is locked by mistake.
  • the foregoing determining that the system of the received video signal is before the first target system, It may further include: if the frame rate of the first target video signal is twice the frame rate of other target video signals, reading the voltage value of the target row of the first target video signal of one frame, where the target is the first target of one frame Any line between the upper and lower preset lines of the video signal; if the voltage value of the target line is negative or zero, determine the standard of the received video signal as the first target system; if the voltage value of the target line A positive value determines that the received video signal is locked by mistake.
  • the frame rate of the first target video signal is half the frame rate of the other target video signals, that is, the length of each frame of the first target video signal is twice the length of each frame of the other target video signals, the first frame of a frame During the duration of the target video signal, there will be two other frames of the target video signal.
  • the middle of the first target video signal of a frame corresponds to the beginning of one frame of other target video signals.
  • the field sync signal Since the beginning of a frame of video signal is a field sync signal, the field sync signal is a low level (ie, the voltage value is negative).
  • the middle of a frame of video signal is image information, and the voltage is a positive level value (that is, the voltage value is a positive value). Due to several blanking areas at the beginning and end of a frame of video signal, the level of the blanking area is zero by default, except that some specific lines will have synchronization signals, that is, the voltage value is zero. Therefore, it is possible to set a preset number (which can be determined according to the number of image information area lines and the number of blanking area lines of the first target video signal and other target video signals) according to the preset middle video line.
  • the voltage value (referred to herein as the target line) determines whether the format of the received video signal is the first target format, and further determines whether the received video signal is locked by mistake.
  • the 4M12.5 signal is 12.5 frames per second, that is, one frame is 80ms in length
  • the 720P25 signal is 25 frames per second, that is, one frame is 40ms in length. Therefore, in 80ms, there is one frame of 4M12.5 video signal or two frames of 720P25 video signal.
  • the middle of the 4M12.5 frame corresponds to the beginning of a frame of 720P25.
  • the schematic diagram can be shown in Figure 2.
  • the SoC chip configures the second register according to 4M12.5 (that is, the first target system is 4M12.5) and detects that the received video signal is in a locked state. At this time, the AD chip reads a frame of the first target video signal. Voltage value in the middle row.
  • the SoC chip can determine the format of the received video signal is 4M12.5; if the voltage value of the positive middle row is negative, the SoC chip can determine the received video signal The standard is not 4M12.5, which means that the received video signal is locked by mistake.
  • the above-mentioned method for judging mislock by using a voltage value may also be performed after the video signal system is determined, or after the type of the video signal is determined. This application does not limit this.
  • FIG. 9 is a schematic flowchart of a method for identifying a video signal false lock according to an embodiment of the present application.
  • the method may include the following steps.
  • Step S900 If the system and type of the received video signal are determined, determine whether the duration of the first target video signal in one frame is an even multiple of the duration of the other target video signal in one frame. If yes, go to step S910; otherwise, go to step S940.
  • the SoC chip can determine whether the duration of the first target video signal of a frame is an even multiple of the duration of one target video signal.
  • Step S910 Read the voltage value of the target line of the first target video signal of one frame. If it is a positive value, go to step S920; if it is a negative value or zero, go to step S930.
  • Step S920 Determine the format of the received video signal as the first target format.
  • Step S930 Determine that the received video signal is locked by mistake.
  • the duration of one frame of the first target video signal is an even multiple of the duration of one frame of the other target video signal, even in the duration of the frame of the first target video signal, there are even other frames of the target video. signal.
  • the middle of the first target video signal of a frame corresponds to the beginning of one frame of other target video signals.
  • the SoC chip reads the voltage value in the middle row of the first target video signal of one frame.
  • the DVR can determine the format of the received video signal is 4M12.5; if the voltage value of the positive middle row is negative or zero, the DVR can determine the received video signal The standard is not 4M12.5, which means that the received video signal is locked by mistake.
  • Step S940 Detect whether the color carrier of the received video signal is in a locked state. If it is in the locked state, go to step S950; otherwise, go to step S960.
  • Step S950 Determine the format of the received video signal as the first target format.
  • Step S960 Determine that the received video signal is locked by mistake.
  • steps S940 to S960 in this embodiment of the present application reference may be made to the related description of color carrier determination in the foregoing embodiments, and details are not described herein again.
  • step S930 and step S960 when it is determined that the received video signal is locked by mistake, the SoC chip may go to step S300 in FIG. 3 to perform system identification on the received video signal again, or identify the received video signal according to other strategies.
  • the format of the video signal may go to step S300 in FIG. 3 to perform system identification on the received video signal again, or identify the received video signal according to other strategies.
  • FIG. 10 is a schematic structural diagram of a video signal identification device according to an embodiment of the present application.
  • the video signal identification device can be applied to an SoC chip in the foregoing method embodiment.
  • the video signal The identification device may include the following units.
  • the PTZ protocol reading unit 1010 is configured to read a PTZ signal in a blanking line of the video signal by using the PTZ protocol when a video signal is received to obtain the read data.
  • a type identification unit 1020 is configured to identify a type of the video signal according to the read data.
  • the device further includes: a sine wave detection unit 1030, configured to detect whether a sine wave exists in a penultimate blanking line of the video signal.
  • the type identification unit 1020 is further configured to determine the type of the video signal as the target type if the sine wave exists in the penultimate blanking line of the video signal; the PTZ protocol reading unit 1010 Specifically, if the sine wave does not exist in the penultimate blanking line of the video signal, use the PTZ protocol to read the PTZ signal in the blanking line of the video signal.
  • the PTZ protocol reading unit 1010 is specifically configured to use the PTZ protocol to read the PTZ signal in a first target blanking line of the video signal to obtain a read.
  • the first data of the type; the type identifying unit 1020 is specifically configured to identify the type of the video signal according to the first data; wherein the first target blanking is the 23-26th blanking of the video signal Any blanking line in the line.
  • the PTZ protocol reading unit 1010 is specifically configured to use the PTZ protocol to read the PTZ signal in a second target blanking line of the video signal to obtain a read.
  • the second data; the type identifying unit 1020 is specifically configured to identify the type of the video signal according to the second data; wherein the second target blanking is the 6-7th blanking of the video signal Any blanking line in the line.
  • the type identification unit 1020 is further configured to identify the video signal according to a detection state and a locked state of a color carrier of the video signal if the second data is 0x00. Types of.
  • the device before the PTZ signal in the blanking line of the video signal is read using the PTZ protocol, and before the read data is obtained, as shown in FIG. 11, the device further Includes the following units.
  • the reading unit 1110 is configured to read a first register to obtain a standard value of the video signal.
  • the configuration unit 1120 is configured to configure a second register according to a standard of at least one of the target video signals in the multiple standards when the standard value is shared by target video signals in multiple standards.
  • the lock detection unit 1130 is configured to detect whether a video signal is in a locked state.
  • a first system determination unit 1140 is configured to determine that the video signal system is the first target when the configuration unit 1120 configures the second register according to the first target system and the lock detection unit 1130 detects that the video signal is in a locked state.
  • the format, wherein the first target format is a format of a first target video signal among the multiple target video signals.
  • the device further includes a priority determining unit 1150, configured to determine a priority of a system of each target video signal of the multiple systems; the configuration unit 1120, specifically configured to configure a second register of the at least one target video signal format in order of priority from high to low.
  • a priority determining unit 1150 configured to determine a priority of a system of each target video signal of the multiple systems
  • the configuration unit 1120 specifically configured to configure a second register of the at least one target video signal format in order of priority from high to low.
  • the configuration unit 1120 is specifically configured to configure the second register according to the priority order of the i-th target video signal.
  • the number of configuration is less than Ni, if the video If the signal is in an unlocked state, the second register is continuously configured according to the priority order of the i-th target video signal, and the number of times of the configuration is increased by 1.
  • the larger i is, the smaller Ni is.
  • the device further includes: a line length determining unit 1160, configured to determine the line length of the multiple target video signals; and a second system determination unit 1170, If the line lengths of the plurality of target video signals are different, the video signal format is determined according to the line lengths of the plurality of target video signals and the line length of the video signal.
  • the configuration unit 1120 is further configured to: if at least two kinds of target video signals have the same line length, according to the at least one target video signal format of the multiple formats Configure the second register.
  • the second system determination unit 1170 is specifically configured to: read the third register to obtain a line length value; compare the line length value and the line length of each of the plurality of target video signals; When the line length value is the same as the line length of a target video signal, determining the standard of the target video signal as the first target standard.
  • the device further includes the following units.
  • a color carrier detection unit 1210 is configured to detect whether the color carrier of the video signal is in a locked state after identifying the type of the video signal according to the read data.
  • a false lock determination unit 1220 is configured to determine that the video signal is locked incorrectly if the color carrier of the video signal is in an unlocked state.
  • the device further includes an adjustment unit 1230, configured to set a range of gain adjustment to the maximum before determining that the video signal is erroneously locked, and set the The gain is adjusted to the maximum.
  • an adjustment unit 1230 configured to set a range of gain adjustment to the maximum before determining that the video signal is erroneously locked, and set the The gain is adjusted to the maximum.
  • the device further includes a voltage reading unit 1240, configured to determine, before the video signal format is the first target format, if the first If the frame rate of a target video signal is half of the frame rate of other target video signals, the voltage value of the target row of the first target video signal is read.
  • the target line is any one of a preset number of lines above and below a middle line of the first target video signal of the one frame.
  • the mis-lock determination unit 1220 is further configured to determine that the video signal is mis-locked if the voltage value of the target row is negative or zero.
  • the PTZ protocol is used to read the PTZ signal in the blanking line of the video signal to obtain the read data; the read data is identified based on the read data. Describe the type of video signal.
  • the video signal identification device provided by the present application improves the accuracy of video signal identification.
  • FIG. 12 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.
  • the electronic device may include a processor 1201, a communication interface 1202, a memory 1203, and a communication bus 1204.
  • the processor 1201, the communication interface 1202, and the memory 1203 complete communication with each other through the communication bus 1204.
  • a computer program is stored in the memory 1203; the processor 1201 can execute the video signal recognition method described above by executing the program stored in the memory 1203.
  • the memory 1203 mentioned herein may be any electronic, magnetic, optical or other physical storage device, and may contain or store information such as executable instructions, data, and so on.
  • the memory 1203 may be: RAM (Radom Access Memory), volatile memory, nonvolatile memory, flash memory, storage drive (such as hard drive), solid state hard disk, any type of storage disk (such as optical disk , Dvd, etc.), or similar storage media, or a combination thereof.
  • the embodiment of the present application further provides a machine-readable storage medium storing a computer program, such as the memory 1203 in FIG. 12, and the computer program may be executed by the processor 1201 in the electronic device shown in FIG. 12 to implement the foregoing description Video signal recognition method.
  • a computer program such as the memory 1203 in FIG. 12
  • the computer program may be executed by the processor 1201 in the electronic device shown in FIG. 12 to implement the foregoing description Video signal recognition method.

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Abstract

本申请提供一种视频信号识别方法、装置、电子设备及可读存储介质，该方法包括：当接收到所述视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；根据所述读取的数据识别所述视频信号的类型。

Description

视频信号识别方法、装置、电子设备及可读存储介质 技术领域
本申请涉及视频监控技术，尤其涉及一种视频信号识别方法、装置、电子设备及可读存储介质。
背景技术
传统视频监控行业主要包含视频采集设备，如模拟摄像机，和视频存储设备，如DVR(Digital Video Recorder，硬盘录像机)，等产品，外部场景经过视频采集设备采集后传输给视频存储设备进行存储和视频分析等处理。
对于视频采集设备和视频存储设备之间的视频信号传输，视频采集设备需要对输出的视频信号进行调制，视频存储设备需要对输入的视频信号进行解调。由于存在多种类型的视频采集设备，其对应的视频信号的制式也存在不同，因此，为了保证视频信号的兼容接入，视频存储设备需要能准确识别接收到的视频信号。
发明内容
有鉴于此，本申请提供一种视频信号识别方法、装置、电子设备及可读存储介质。
具体地，本申请是通过如下技术方案实现的。
根据本申请实施例的第一方面，提供一种视频信号识别方法，包括：当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；根据所述读取的数据识别所述视频信号的类型。
根据本申请实施例的第二方面，提供一种视频信号识别装置，包括：PTZ协议读取单元，用于当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；类型识别单元，用于根据所述读取的数据识别所述视频信号的类型。
根据本申请实施例的第三方面，提供一种电子设备，包括处理器、通信接口、存储器和通信总线，其中，所述处理器，所述通信接口，所述存储器通过所述通信总线完成相互间的通信；所述存储器，用于存放计算机程序；所述处理器，用于执行所述存储器上所存放的所述计算机程序时，实现上述视频信号识别方法。
根据本申请实施例的第四方面，提供一种计算机可读存储介质，所述计算机可读存储介质内存储有计算机程序，所述计算机程序被处理器执行时实现上述视频信号识别方法。
本申请实施例的视频信号识别方法，当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；根据所述读取的数据识别所述视频信号的类型。本申请提供的视频信号识别方法，提高了视频信号识别的准确率。
附图说明
图1是本申请一示例性实施例示出的一种视频信号制式识别方法的流程图；
图2是本申请一示例性实施例示出的一帧4M12.5视频信号和两帧720P25视频信号的示意图；
图3是本申请又一示例性实施例示出的一种视频信号制式识别方法的流程图；
图4是本申请一示例性实施例示出的一种利用优先级轮询法识别接收到的视频信号的制式的示意图；
图5是本申请一示例性实施例示出的一种视频信号类型识别方法的流程图；
图6是本申请又一示例性实施例示出的一种视频信号类型识别方法的流程图；
图7是本申请再一示例性实施例示出的一种视频信号类型识别方法的流程图；
图8是本申请另一示例性实施例示出的一种视频信号类型识别方法的流程图；
图9是本申请一示例性实施例示出的一种视频信号误锁定识别方法的流程图；
图10是本申请一示例性实施例示出的一种视频信号识别装置的结构示意图；
图11是本申请又一示例性实施例示出的一种视频信号识别装置的结构示意图；
图12是本申请一示例性实施例示出的一种电子设备的硬件结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如 所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
为了使本领域技术人员更好地理解本申请实施例提供的技术方案，并使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请实施例中技术方案作进一步详细的说明。
请参见图1，为本申请实施例提供的一种视频信号识别方法的流程示意图，其中，该视频信号识别方法可以应用于具有AD(Analog-to-Digital，模数转换)芯片的视频处理设备，如DVR的AD芯片(下文中以视频处理设备为DVR为例)，如图1所示，该方法可以包括以下步骤。
需要说明的是，在本申请实施例中，若未特殊说明，所提及的视频信号均为模拟视频信号，本申请实施例后续对此不再复述。
步骤S100、读取第一寄存器，得到接收到的视频信号的制式值。
本申请实施例中，AD芯片接收到视频信号时，会根据该视频信号中的制式信息，在特定的寄存器地址中，配置该视频信号的制式信息的值，本文中简称为制式值，该特定的寄存器可以称为第一寄存器。
例如，AD芯片可以将接收到视频信号的制式信息记录在地址为0x3的寄存器的bit0-bit2位。
其中，视频信号的制式可以包括但不限于：NTSC(National Television Standards Committee，国家电视标准委员会)、PAL(Phase Alteration Line，逐行倒相制式)、720P25/30、720P50/60、1080P25/30、1080P HALF25/30、3M18、4M12.5/15、4M25/30、4M HALF 25/30、5M12、5M20、5M HALF 20、8M12.5/15、8M HALF 12.5/15等；各制式的视频信号均存在对应的制式值。
相应地，当需要进行视频信号制式识别时，DVR的SoC(System-on-a-Chip，片上系统)芯片可以通过读取AD芯片的第一寄存器，得到制式值。当然DVR还可以用CPU(Central Processing Unit，中央处理器)、DSP(Digital Signal Processing，数字信号处理)等芯片读取AD芯片的寄存器值，本申请对此不作限制。通过该制式值，在某些情况下，可以直接确定接收到的视频信号的制式。
例如，SoC芯片可以读取0x3寄存器的bit0-bit2位的值。
步骤S110、当该制式值由多种制式的目标视频信号共用时，按照多种制式中至少一种目标视频信号的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态。
本申请实施例中，考虑到在实际应用场景中，可能会存在多种制式的视频信号的制式值相同，即可能会存在多种制式的视频信号共用同一个制式值的情况，因此，仅根据制式值并不一定能够准确地识别视频信号的制式。
例如，当制式值为0x6，则该值对应的视频信号的制式可能为NTSC或PAL；当制式值为0x7，则该值对应的视频信号的制式可能为3M18、5M12或5M20。
相应地，当DVR的SoC芯片读取到第一寄存器的制式值时，可以判断该制式值是否由多种制式的目标视频信号共用，并当确定该制式值由多种制式的目标视频信号共用时，进一步根据其它策略识别接收到的视频信号的制式。
本申请实施例中，当确定所读取的制式值由多种制式的视频信号(本文中称为目标视频信号)共用时，SoC芯片可以按照多种制式中至少一种目标视频信号的制式配置AD芯片的第二寄存器，并检测接收到的视频信号是否锁定。
例如，可以采用轮询的方式，分别选择各目标视频信号的制式，按照所选择的目标视频信号的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态。
其中，按照所选择的制式配置AD芯片的第二寄存器的具体实现可以参见现有相关技术中的相关描述，本申请实施例在此不做赘述。
举例来说，假设SoC芯片所读取的制式值对应制式1-3的目标视频信号(假设分别为目标视频信号1-3)，则SoC芯片可以按照制式1-3从前到后的顺序，先选择制式1，按照制式1配置其对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态；若处于未锁定状态，则再选择制式2，按照制式2配置其对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态；若处于未锁定状态，则再选择制式3，按照制式3配置其对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态。需要说明的是，各种制式对应的第二寄存器的具体地址可能不同，也可能包括多个寄存器地址，但是由于其实现的功能类似，因此本申请将其统一称为第二寄存器。
步骤S120、当按照第一目标制式配置第二寄存器，且检测到接收到的视频信号处于锁定状态时，确定接收到的视频信号的制式为第一目标制式。
本申请实施例中，第一目标制式并不特指某一固定制式，而是可以指代上述多种目标视频信号中的任一种目标视频信号(本文中称为第一目标视频信号)的制式。
本申请实施例中，当按照第一目标制式配置第二寄存器，且检测到接收到的视频信号锁定时，SoC芯片可以停止制式选择和第二寄存器的配置，并确定接收到的视频信号的制式为第一目标制式。
其中，检测到接收到的视频信号处于锁定状态，可以包括检测到接收到的视频信号的行同步信号锁(HLOCK)的状态和场同步信号锁(VLOCK，也可以称为帧同步信号锁)的状态均为锁定状态。
其中，确定视频信号的行同步信号锁的状态或场同步信号锁的状态是否处于锁定状态的具体实现可以参见现有相关技术中的相关描述，本申请实施例在此不做赘述。
在本申请其中一个实施例中，上述按照多种制式中的至少一种目标视频信号的制式配置对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态，可以包括：确定多种制式的各目标视频信号的制式的优先级；按照优先级从高到低的顺序，配置至少一个目标视频信号的制式对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态；当检测到接收到的视频信号处于锁定状态，则接收到的视频信号的制式为第一目标制式。
在该实施例中，当确定所读取的制式值由多种制式的目标视频信号共用时，可以确定各目标视频信号的制式的优先级。
例如，用户可以按照各目标视频信号的制式的使用概率确定各目标视频信号的制式的优先级。其中，各目标视频信号的制式的使用概率可以为经验值，可以预先配置在AD芯片或SoC芯片中；目标视频信号的使用概率越高，其优先级也越高。
在该实施例中，在确定了各目标视频信号的优先级之后，SoC芯片可以按照优先级从高到低的顺序，轮询各目标视频信号，配置至少一个目标视频信号的制式对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态。当检测到接收到的视频信号处于锁定状态，则SoC芯片将此时配置第二寄存器的制式确定为第一目标制式，并且停止轮询。
举例来说，假设读取的制式值为V1，该制式值被制式1和制式2的视频信号共用，且制式1的使用概率高于制式2的使用概率，则SoC芯片可以确定制式1的优先级高于制式2的优先级，相应地，可以先按照制式1配置其对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态。若视频信号处于锁定状态，则确定接收到的视频信号的 制式为制式1，并且结束配置第二寄存器的步骤。若视频信号处于未锁定状态，则再按照制式2配置其对应的第二寄存器，并检测接收到的视频信号是否锁定，若处于锁定状态，则确定接收到的视频信号的制式为制式2。
需要说明的是，在本申请实施例中，当SoC芯片按照各目标视频信号的制式配置AD芯片的第二寄存器时，均检测到接收到的视频信号未处于锁定状态时，AD芯片可以重新按照步骤S100～步骤S120描述的方式识别接收到的视频信号的制式一定次数(可以根据实际场景设定)，或按照其它策略识别接收到的视频信号的制式，其具体实现方式本申请不做限定。
进一步地，在该实施例中，考虑到按照某制式配置第二寄存器后，即使AD芯片接收到的视频信号的制式与该制式相同，也会需要一定的时间才能检测到该视频信号处于锁定状态，因此，为了提高检测到视频信号处于锁定状态的正确率，SoC芯片可以按照同一制式多次配置第二寄存器，并多次判断接收到的视频信号是否处于锁定状态。
相应地，在该实施例的一种实施方式中，上述按照优先级从高到低的顺序，配置至少一个目标视频信号的制式对应的第二寄存器，并检测接收到的视频信号是否处于锁定状态，可以包括：
按照优先级排序第i的目标视频信号的制式配置第二寄存器，当配置的次数小于Ni时，若接收到的视频信号处于锁定状态，则确定目标视频信号的制式为第i目标视频信号的制式，并退出配置第二寄存器的过程；若接收到的视频信号处于未锁定状态，则继续按照优先级排序第i的目标视频信号的制式配置第二寄存器，并且将配置的次数加1。
当配置次数达到Ni并且接收到的视频信号处于锁定状态时，确定目标视频信号的制式为第i目标视频信号的制式，并退出配置第二寄存器的过程。
当配置次数达到Ni并且接收到的视频信号仍处于未锁定状态；则令i＝i+1，并重复上述配置并检查锁定状态的步骤，直至接收到的视频信号处于锁定状态，或已经遍历所有目标视频信号制式，但接收到的视频信号仍处于未锁定状态。在一种可选的实施例中，i的初始值可以为1，i为自然数。在另一种可选的实施例中，i的初始值可以为0，i为自然数。
在该实施方式中，对各目标视频信号的制式按照其优先级的不同可以设置不同的配置次数，也就是Ni的值可以各不相同。
其中，按照优先级排序第i的目标视频信号的制式，其对第二寄存器的配置次数为 Ni；i越大，优先级越低(即按照优先级从高到低的顺序排序)。在一种可选的实施例中，1≤i≤n，n为目标视频信号的制式的数量。在另一种可选的实施例中，0≤i≤n-1，n为目标视频信号的制式的数量。
在该实施方式中，可以先按照优先级排序第1(即优先级最高)的目标视频信号制式配置第二寄存器，当配置的次数小于等于N1时，若接收到的视频信号处于锁定状态，则确定目标视频信号的制式为优先级排序第1的目标视频信号的制式，并退出该配置过程。
其中，每一次配置第二寄存器之后，均可以判断接收到的视频信号是否处于锁定状态，当检测到接收到的视频信号处于未锁定状态时，继续下一次配置和判断。
在该实施方式中，当按照优先级排序第1的目标视频信号制式配置第二寄存器的次数达到N1且接收到的视频信号仍处于未锁定状态时，SoC芯片可以按照优先级排序第2(即优先级次高)的目标视频信号制式配置第二寄存器。当配置的次数小于等于N2时，若接收到的视频信号处于锁定状态，则确定目标视频信号的制式为优先级排序第2的目标视频信号的制式，并退出该配置过程。当配置次数达到N2且接收到的视频信号仍处于未锁定状态时，按照优先级排序第3的目标视频信号制式配置第二寄存器。
依次类推，直至SoC芯片按照优先级排序第n(即优先级最低)的目标视频信号配置第二寄存器的次数达到Nn且接收到的视频信号仍处于未锁定状态时，可以重新按照该实施方式中描述的方式识别接收到的视频信号的制式一定次数(可以根据实际场景设定)，或按照其它策略识别接收到的视频信号的制式，其具体实现方式本申请不做限定。
优选地，Ni＞1。
在一个示例中，i越小，Ni越大，即优先级越高的目标视频信号的制式，按照该目标视频信号的制式配置第二寄存器的次数越多。
举例来说，假设SoC芯片读取的制式值为V1，该制式值被制式1和制式2的视频信号共用，且制式1的使用概率高于制式2的使用概率，则可以确定制式1的优先级高于制式2的优先级。相应地，SoC芯片按照制式1配置第二寄存器的次数大于按照制式2配置第二寄存器的次数，例如，按照制式1配置第二寄存器的次数为6次，按照制式2配置第二寄存器的次数为3次。
进一步地，在本申请实施例中，考虑到在实际应用场景中，当多个制式的视频信号共用同一个制式值时，该多个视频信号的行长可能不同，此时，可以根据该多个视频信 号的行长来识别该多个视频信号的制式。
相应地，在本申请其中一个实施例中，当所读取的制式值由多种制式的目标视频信号共用时，上述按照多种制式中至少一种目标视频信号的制式配置其第二寄存器之前，还可以包括：确定多种目标视频信号的行长；若多种目标视频信号中至少有两种目标视频信号的行长相同，则执行上述按照多种制式中至少一种目标视频信号的制式配置第二寄存器的步骤；若多种目标视频信号的行长都不同，则根据多种目标视频信号各自的行长、以及接收到的视频信号的行长确定接收到的视频信号的制式。
在该实施例中，当SoC芯片确定所读取的制式值由多种制式的目标视频信号共用时，可以分别确定多种目标视频信号各自的行长。
若多种目标视频信号中至少有两种目标视频信号的行长相同，则可以利用步骤S110-步骤S120中描述的方式识别目标视频信号的制式。
若多种目标视频信号的行长都不同，则SoC芯片可以根据该多种目标视频信号各自的行长、以及接收到的视频信号的行长确定接收到的视频信号的制式。
需要说明的是，在本申请实施例中，当多种目标视频信号的行长不同时，SoC芯片也可以按照步骤S110-步骤S120中描述的方式识别目标视频信号的制式。
此外，当目标视频信号的数量为三种或三种以上，且该多种目标视频信号的行长不完全相同(即部分目标视频信号的行长相同，部分目标视频信号的行长不同)时，SoC芯片可以先根据行长识别接收到的视频信号的制式，当按照行长无法识别接收到的视频信号的制式(即与接收到的视频信号的行长相同的目标视频信号存在至少两种)时，进一步按照步骤S110-步骤S120中描述的方式进行视频信号制式识别；或者，可以直接按照步骤S110-步骤S120中描述的方式进行视频信号制式识别。
在该实施例的一种实施方式中，上述根据多种目标视频信号的行长，以及接收到的视频信号的行长确定接收到的视频信号的制式，包括：读取第三寄存器，得到行长值；比较所述行长值以及所述多种目标视频信号各自的行长；当所述行长值和某一目标视频信号的行长相同时，将该目标视频信号的制式确定为所述接收到的视频信号的制式，即为第一目标制式。
在该实施方式中，SoC芯片可以通过读取AD芯片的第三寄存器得到的行长值来确定接收到的视频信号的行长，比较接收到的视频信号的行长和各目标视频信号的行长，并将与接收到的视频信号的行长相同的目标视频信号的制式确定为接收到的视频信号 的制式。
其中，通过读取AD芯片的第三寄存器得到行长值来确定接收到的视频信号的行长的具体实现可以参见现有相关技术中的相关描述，本申请实施例在此不做赘述。
为了使本领域技术人员更好地理解申请实施例提供的技术方案，下面结合具体实例对本申请实施例提供的技术方案进行说明。
在该实施例中，以视频信号的制式包括NTSC、PAL、720P25/30、720P50/60、1080P25/30、1080P HALF25/30、3M18、4M12.5/15、4M25/30、4M HALF 25/30、5M12、5M20、5M HALF 20、8M12.5/15、8M HALF 12.5/15为例，其中，3M18、5M12和5M20共用一个制式值，且该三种制式的视频信号的行长相同，剩余制式中最多两种制式共用一个制式值，例如4M25和720P50；4M30和720P60；1080P25和8M12.5；1080P30和8M15；NTSC和PAL；4M12.5和720P25；4M15和720P30，其中，这些共用一个制式值的两种制式的视频信号的行长相同。
在该实施例中，视频信号制式识别方案实现流程可以如图3所示，其可以包括以下步骤。
步骤S300、读取第一寄存器，得到接收到的视频信号的制式值。
步骤S310、判断该制式值是否被三种制式的视频信号共用。若是，则转至步骤S320；否则，转至步骤S330。
步骤S320、利用行长判断法识别接收到的视频信号的制式。
在该实施例中，当确定所读取的制式值由三种制式的视频信号共用时，SoC芯片可以确定接收到的视频信号的制式为3M18、5M12或5M20。
此时，可以利用行长法识别接收到的视频信号的制式，即SoC芯片可以读取第三寄存器，得到行长值，确定接收到的视频信号的行长，并将接收到的视频信号的行长与3M18、5M12和5M20的视频信号的行长分别进行比较，当比较结果为相同时，该行长对应的视频信号的制式确定为接收到的视频信号的制式，即为第一目标制式。
步骤S330、判断该制式值是否被两种制式的视频信号共用。若是，则转至步骤S340；否则，转至步骤S350。
步骤S340、利用优先级轮询法识别接收到的视频信号的制式。
在该实施例中，当确定所读取的制式值由两种制式的视频信号共用时，SoC芯片可 以利用优先级轮询法识别接收到的视频信号的制式，即可以先确定该制式值对应的两种制式的视频信号的优先级，并先按照优先级高的视频信号的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态，若处于未锁定状态，则再按照优先级低的视频信号的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态。
举例来说，以制式4M25和720P50为例(假设这两个制式的制式值为v1)，由于4M25的使用概率远高于720P50，因此，4M25的优先级高于720P50。当获取到的第一寄存器的值为v1时，SoC芯片可以确定该制式值由4M25和720P50共用，此时，AD芯片利用优先级轮询法识别接收到的视频信号的制式的具体实现可以如图4所示，其可以包括以下步骤。
步骤S400、判断计数器的计数值是否小于6；若计数值小于6，则转至步骤S410；否则，转至步骤S430。
步骤S410、按照4M25配置第二寄存器，并将计数器的计数值加1。
步骤S420、检测接收到的视频信号是否处于锁定状态。若处于锁定状态，则确定接收到的视频信号的制式为4M25，并结束优先级轮询；否则，转至步骤S400。
在该示例中，假设一次优先级轮询过程中，先按照4M25配置寄存器，并检测接收到的视频信号是否处于锁定状态；若处于未锁定状态，则继续按照4M25配置第二寄存器，并检测接收到的视频信号是否处于锁定状态，或，按照4M25配置寄存器的次数达到6次时，接收到的视频信号仍未锁定。
步骤S430、按照720P50配置第二寄存器，并将计数器的计数值加1。
步骤S440、检测接收到的视频信号是否处于锁定状态。若处于锁定状态，则确定接收到的视频信号的制式为720P50，并结束优先级轮询；否则，转至步骤S450。
步骤S450、判断计数器的计数值是否小于9；若计数值小于9，则转至步骤S430；否则，结束此次优先级轮询。
在该示例中，若按照4M25配置第二寄存器的次数达到6次且接收到的视频信号仍处于未锁定状态，则SoC芯片可以按照720P50配置第二寄存器，并检测接收到的视频信号是否处于锁定状态。若此时，仍处于未锁定状态，则继续按照720P50配置第二寄存器，并检测接收到的视频信号是否处于锁定状态。当按照720P50配置第二寄存器的次数达到3次且接收到的视频信号仍处于未锁定状态，结束此次优先级轮询。
需要说明的是，在该示例中，当计数器的计数值达到9(即按照4M25配置第二寄存器的次数达到6次，按照720P50配置第二寄存器的次数达到3次)且接收到的视频信号仍处于未锁定状态时，SoC芯片还可以将计数器清0，重新确定接收到的视频信号的制式值，并按照上述方式开始新的一次视频信号制式的识别，或，按照其它策略实现视频信号制式的识别，本申请实施例对此不做限定。
此外，当SoC芯片检测到接收到的视频信号锁定时，结束本次优先级轮询，也可以将计数器清零。
步骤S350、按照该制式值对应的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态。若处于锁定状态，则确定接收到的信号的制式为该制式值对应的制式；否则，结束此次视频信号制式识别。
在该实施例中，若确定所读取的制式值未被多个制式的视频信号共用，则SoC芯片可以直接根据该制式值对应的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态，若处于锁定状态，则确定接收到的信号的制式为该制式值对应的制式。也就是说，即便只有一个制式使用该制式值，也需要判断是否锁定。因为在实际使用中，存在视频信号制式正确，但是视频信号内容异常的情况。
需要说明的是，在该实施例中，当按照步骤S300-步骤S350描述的方式未识别出接收到的视频信号的制式时，SoC芯片可以重新按照S300-S350描述的方式进行新一次的视频信号制式识别，或按照其它策略实现视频信号制式的识别，本申请实施例对此不做限定。
本申请实施例中，首先读取第一寄存器，得到接收到的视频信号的制式值；当该制式值由多种制式的目标视频信号共用时，按照多种制式中至少一种目标视频信号的制式配置第二寄存器，并检测接收到的视频信号是否处于锁定状态；当按照第一目标制式配置第二寄存器，且检测到接收到的视频信号处于锁定状态时，确定接收到的视频信号的制式为第一目标制式。通过本申请提供的方法，可以提高视频信号识别的准确率。
当DVR的SoC芯片确定出接收到的视频信号的制式之后，由于一种制式的视频信号还可能对应多种类型，因此还需要进一步确定视频信号的类型。例如，对于制式为1080P25/30的视频信号，其包括的类型有TVI(Transport Video Interface，传输视频接口)、AHD(Analog High Definition，模拟高清)等。
请参见图5，为本申请实施例提供的一种视频信号类型的识别方法的流程示意图， 该方法可以包括以下步骤。
步骤S500、当接收到视频信号时，使用PTZ协议读取视频信号的消隐行中的PTZ信号，得到读取的数据。
PTZ(Pan/Tilt/Zoom，平移/倾斜/变焦镜头)协议是为了使视频采集设备和视频存储设备进行通信而制定的。视频采集设备可以通过PTZ协议与视频存储设备交互语言信息，例如，视频采集设备可以通过PTZ协议控制视频采集设备调节焦距。
本申请实施例中，考虑到不同的视频信号，PTZ协议在不同消隐行插入不同的信号，从而使得相关消隐行幅值之间存在较为明显的差异。因此，当DVR接收到视频信号并且确定了该视频信号为第一目标制式后，DVR首先判断该第一目标制式是否包括多个类型，比如是否包括TVI、AHD等多种信号类型的两种或三种。当该第一目标制式包括多个类型时，AD芯片可以使用PTZ协议读取视频信号的消隐行幅值中的PTZ信号，如按照预设PTZ信号接收参数读取视频信号的消隐行中的PTZ信号。
其中，预设PTZ信号接收参数可以根据视频信号的消隐行特征设定，其包括但不限于，所读取的消隐行的序号、所读取的消隐行的起始位、所读取的消隐行的比特数(如24个比特)以及脉宽等。
参见图2，每帧视频信号由图像信息区和消隐区组成。图像信息区存放一帧有效的图像数据。消隐区可以在特定位置存放特定信息，未存放特定信息的位置的信号幅度可以为零。例如，消隐区的开始几行可以包括场同步信号，部分行可以包括PTZ信号等。PTZ信号可以是位于消隐区的某一行的某一特定位置的若干字节的信号。PTZ信号一般可以认为是数字信号，也就是说，在视频信号中，PTZ信号的高电平可以一直为一个超过高电平判别门限的电平，低电平可以一直为一个小于低电平判别门限的电平。PTZ信号的具体格式由PTZ协议确定，本申请对此不作限制。
具体来讲，使用PTZ协议读取视频信号的消隐行中的PTZ信号，可以从参数指定的消隐行和消隐行的起始位开始，根据参数确定的脉宽读取参数指定的比特数(如24个比特)，从而得到多个比特的数值。该多比特的数值可以进一步根据PTZ协议进行解析，得到读取的具体数据。
步骤S510、根据读取的数据识别该视频信号的类型。
本申请实施例中，使用PTZ协议读取到视频信号中的PTZ信号之后，可以根据读取后得到的数值识别该视频信号的类型。
进一步地，在本申请实施例中，对于某一特定类型的视频信号(本文中称为目标类型)的倒数第4个消隐行存在正弦波，时长通常约为一行，而其它类型的视频信号的倒数第4个消隐行则不存在正弦波，因此，还可以根据视频信号的倒数第4个消隐行是否存在正弦波确定视频信号是否为目标类型。在一个例子中，该目标类型为TVI类型。
相应地，上述使用PTZ协议读取视频信号的消隐行中的PTZ信号之前，还可以包括：检测该视频信号的倒数第4个消隐行中是否存在正弦波；若存在正弦波，则确定该视频信号的类型为目标类型；否则，确定执行上述使用PTZ协议读取视频信号的消隐行中的PTZ信号的步骤。
本申请实施例中，当DVR接收到视频信号时，DVR可以通过AD芯片检测接收到的视频信号的倒数第4个消隐行中是否存在正弦波。
其中，AD芯片检测到视频信号的倒数第4个消隐行存在正弦波时，即确定接收到的视频信号的类型为目标类型时，可以将第四寄存器的某一比特位的值设置为1。若检测到视频信号的倒数第4个消隐行不存在正弦波，即确定接收到的视频信号的类型不是目标类型，则可以将该寄存器的该比特位的值设置为0。例如，第四寄存器地址可以是0x4，该比特位可以是bit2。进而，DVR的SoC芯片可以通过读取AD芯片的该寄存器的该比特位的值确定接收到的视频信号的类型是否为目标类型。
当DVR的AD芯片检测到接收到的视频信号的倒数第4个消隐行中存在正弦波时，则SoC芯片可以确定该视频信号的类型为目标类型。
当DVR的AD芯片检测到接收到的视频信号的倒数第4个消隐行中不存在正弦波时，AD芯片可以进一步使用PTZ协议读取视频信号的消隐行中的PTZ信号，得到读取的数据，SoC芯片根据读取的数据识别视频信号的类型。
在本申请其中一个实施例中，上述使用PTZ协议读取视频信号的消隐行中的PTZ信号，得到读取的数据，可以包括：使用PTZ协议读取视频信号的第一目标消隐行的PTZ信号，得到读取的第一数据。相应地，上述根据读取后得到的数据识别视频信号的类型，可以包括：根据读取后得到的第一数据识别视频信号的类型。
在该实施例中，考虑到不同视频信号的PTZ信号，位于特定部分消隐行(本文中将该特定部分消隐行中的任一消隐行称为第一目标消隐行)，这样该特定部分消隐行的幅值存在明显差异。因此，可以使用PTZ协议读取第一目标消隐行中的PTZ信号来识别视频信号的类型。
在一个示例中，第一目标消隐行可以为视频信号的第23-26消隐行中的任一消隐行。
在该示例中，AD芯片可以读取接收到的视频信号的第23-26消隐行中的任一消隐行(即第一目标消隐行)，并根据该第一目标消隐行中的PTZ信号，得到读取的第一数据，然后SoC芯片根据该第一数据识别该视频信号的类型。
在该实施例其中一个实施方式中，上述根据读取的第一数据识别视频信号的类型，可以包括：若第一数据为0x00，则识别该视频信号的类型为第一类型；若第一数据大于0x00，则识别视频信号的类型为第二类型。
其中，第一类型、第二类型均与目标类型不同。
在该实施方式中，考虑到第一类型的视频信号的第一数据通常为0x00，而第二类型的视频信号的第一数据通常为大于0x00的数据，因此，第一数据为0x00的视频信号的类型为第一类型，第一数据大于0x00的视频信号的类型为第二类型。
相应地，在该实施方式中，当AD芯片读取的视频信号的第一数据为0x00时，SoC芯片可以识别该视频信号的类型为第一类型；当AD芯片读取的视频信号的第一数据大于0x00时，SoC芯片可以识别该视频信号的类型为第二类型。
在本申请另一个实施例中，上述根据视频信号的制式，使用PTZ协议读取视频信号的消隐行中的PTZ信号，得到读取的数据，可以包括：使用PTZ协议读取视频信号的第二目标消隐行的PTZ信号，得到读取的第二数据。相应地，上述根据读取后得到的数据识别视频信号的类型，可以包括：根据读取后得到的第二数据识别视频信号的类型。
在该实施例中，考虑到视频信号的制式比较多，不同制式的视频信号可能会使用不用的消隐行区分视频信号的类型。因此只使用第一目标消隐行进行区分的话，在某些视频信号的制式下可能无法正确判断出该视频信号的具体类型，因此引入第二目标消隐行。第一类型的视频信号和第二类型的视频信号除了可能在第一目标消隐行插入PTZ信号之外，还可能在其它部分消隐行(本文中将该其它部分消隐行中的任一消隐行称为第二目标消隐行)插入PTZ信号，使得该部分消隐行的幅值存在明显差异，因此，可以使用PTZ协议读取第二目标消隐行中的PTZ信号来识别视频信号的类型。
第一目标消隐行与第二目标消隐行不同。在一个示例中，第二目标消隐行可以为视频信号的第6-7消隐行中的任一消隐行。
在该示例中，考虑到第一类型视频信号和第二类型视频信号的第6-7消隐行幅值上存在明显差异，因此，当SoC芯片确定接收到的视频信号的类型不是目标类型时，SoC芯片可以指示AD芯片读取接收到的视频信号的第6-7消隐行中的任一消隐行(即第二目标消隐行)，并根据该第二目标消隐行中的PTZ信号，得到读取的第二数据，然后SoC芯片根据该第二数据识别该视频信号的类型为第一类型或第二类型。
在该实施例其中一个实施方式中，上述根据读取后得到的第二数据识别视频信号的类型，可以包括：若第二数据为0xff，则识别该视频信号的类型为第一类型；若第二数据大于0x00且小于0xff，则识别视频信号的类型为第二类型。
在该实施方式中，考虑到第一类型的视频信号的第二数据通常为0xff或0x00，而大部分第二类型的视频信号的第二数据通常为0x00～0xff之间的数据，即大于0x00，且小于0xff的数据，因此，第二数据为0xff的视频信号的类型为第一类型，第二数据为0x00～0xff之间的数据的视频信号的类型为第二类型。
相应地，在该实施方式中，当AD芯片读取的视频信号的第二数据为0xff时，SoC芯片可以识别该视频信号的类型为第二类型；当AD芯片读取的视频信号的第二数据为0x00～0xff之间的任一数据，即大于0x00且小于0xff时，SoC芯片可以识别该视频信号的类型为第二类型。
进一步地，考虑到在某些情况下，第二类型的视频信号的第二数据可能为0x00，因此，当AD芯片读取到的视频信号的第二数据为0x00时，此时，该视频信号的类型可能为第二类型或第一类型，SoC芯片需要按照其它策略进一步识别该视频信号的类型。
相应地，在该实施例另一种实施方式中，上述根据第二数据识别视频信号的类型，可以包括：若第二数据为0x00，则根据视频信号的色载波检测状态和锁定状态识别视频信号的类型。
在该实施方式中，当AD芯片读取的视频信号的第二数据为0x00时，SoC芯片可以进一步根据视频信号的色载波的检测状态和锁定状态识别视频信号的类型。
在一个示例中，上述根据视频信号的色载波检测状态和锁定状态识别视频信号的类型，可以包括：确定视频信号的EQ(EQualizer，均衡器)值；根据视频信号的EQ值配置增益倍数；按照第一类型配置AD芯片的第五寄存器，并对视频信号进行检测；若色载波的检测状态为已检测到且色载波的锁定状态为已锁定，则确定视频信号的类型为第一类型。
具体地，在该示例中，当AD芯片读取的视频信号的第二数据为0x00时，SoC芯片可以先确定视频信号的EQ值，即确定视频信号经过传输后的衰减程度。
例如，根据视频信号的色载波衰减程度等计算视频信号的EQ值，其具体实现可以参见现有相关方案中的相关描述，本申请实施例在此不做赘述。
确定了视频信号的EQ值之后，SoC芯片可以根据该EQ值配置AD芯片相应的增益倍数，通过调节增益对视频信号进行衰减补偿。
考虑到视频信号完成衰减补偿之后，通常只需要按照正确的视频信号类型配置第五寄存器，就能从视频信号中检测到色载波，也就是色载波的检测状态为已检测到且色载波的锁定状态为已锁定，即SLOCK为锁定状态，因此，可以轮流按照第一类型和第二类型配置第五寄存器，并进行色载波检测，从而可以识别视频信号的类型。
相应地，SoC芯片可以先按照第一类型配置第五寄存器，并对视频信号进行检测。若色载波的检测状态为已检测到且色载波的锁定状态为已锁定，则确定视频信号的类型为第一类型。
进一步地，若AD芯片未检测到色载波，也就是色载波的检测状态为未检测到，或检测到色载波但色载波的锁定状态为未锁定，则SoC芯片可以按照第二类型配置第五寄存器，并再次对视频信号进行检测；此时，若色载波的检测状态为已检测到且色载波的锁定状态为已锁定，则确定视频信号的类型为第二类型。
其中，根据视频信号的色载波的检测状态和锁定状态识别视频信号的类型的实现流程图可以如图6所示。
需要说明的是，在本申请实施例中，当SoC芯片按照第一类型或第二类型配置第五寄存器后，AD芯片均未检测到色载波，或检测到色载波但色载波均未锁定时，SoC芯片可以确定接收到未知信号，或重新对视频信号进行衰减补偿和类型识别，其具体实现在此不做限定。
此外，在本申请实施例中，SoC芯片除了可以先按照第一类型配置第五寄存器，后按照第二类型配置第五寄存器之外，也可以先按照第二类型配置第五寄存器，后按照第一类型配置第五寄存器，其具体实现在此不做赘述。
在本申请实施例中，上述根据视频信号的单个消隐行(第一目标消隐行或第二目标消隐行)中的PTZ信号识别视频信号的类型的实现方式仅仅是本申请实施例中一种具体示例，而并不是对本申请保护范围的限定。在本申请实施例中，也可以根据视频信 号的多个消隐行中的PTZ信号识别视频信号的类型。例如，AD芯片可以分别读取视频信号的第23-26消隐行中的PTZ信号，若根据视频信号的第23-26消隐行中的PTZ信号读出的数据均为0x00，则NVR可以识别该视频信号的类型为第一类型；若该视频信号的第23-26消隐行中的PTZ信号读出的数据均为大于0x00的数据，则NVR可以识别该视频信号的类型为第二类型，其具体实现在此不做赘述。
为了使本领域技术人员更好地理解申请实施例提供的技术方案，下面结合具体实例对本申请实施例提供的技术方案进行说明。
在一个例子中，以第一目标消隐行为第24消隐行为例进行说明，视频信号识别方案实现流程可以如图7所示，可以包括以下步骤。
步骤S700、当确定第一目标制式的视频信号包括多个类型时，检测该视频信号的倒数第4个消隐行中是否存在正弦波。若存在正弦波，则确定该视频信号的类型为目标类型；否则，转至步骤S710。
在该实施例中，SoC芯片可以根据视频信号的倒数第4个消隐行中是否存在正弦波的方式确定视频信号的类型是否为目标类型。
其中，当视频信号的倒数第4个消隐行中存在正弦波时，确定视频信号的类型为目标类型；当视频信号的倒数第4个消隐行中不存在正弦波时，确定视频信号的类型不是目标类型。
步骤S710、使用PTZ协议读取视频信号的第24消隐行中的PTZ信号，得到读取的第一数据。若第一数据为0x00，则确定视频信号的类型为第一类型；否则，确定视频信号的类型为第二类型。
在该实施例中，当确定视频信号的类型不是目标类型时，AD芯片可以使用PTZ协议读取视频信号的第24消隐行中的PTZ信号，得到第一数据。若第一数据为0x00，则SoC芯片可以确定该视频信号的类型为第一类型。若第一数据不是0x00，即根据视频信号的第24消隐行中的PTZ信号读出的第一数据大于0x00，则SoC芯片可以确定该视频信号的类型为第二类型。
在该实施例中，以第二目标消隐行为第6消隐行为例进行说明，视频信号识别方案实现流程可以如图8所示，可以包括以下步骤。
步骤S800、当确定第一目标制式的视频信号包括多个类型，检测该视频信号的倒数第4个消隐行中是否存在正弦波。若存在正弦波，则确定该视频信号的类型为目标 类型；否则，转至步骤S810。
在该实施例中，SoC芯片可以根据视频信号的倒数第4个消隐行中是否存在正弦波的方式确定视频信号的类型是否为目标类型。
其中，当视频信号的倒数第4个消隐行中存在正弦波时，确定视频信号的类型为目标类型；当视频信号的倒数第4个消隐行中不存在正弦波时，确定视频信号的类型不是目标类型。
步骤S810、使用PTZ协议读取视频信号的第6消隐行中PTZ信号，得到读取的第二数据。若第二数据为0xff，则确定视频信号的类型为第一类型；若第二数据为0x00，则根据视频信号的色载波检测状态和锁定状态识别视频信号的类型；若第二数据既不是0x00也不是0xff，则确定该视频信号的类型为第二类型。
在该实施例中，当该视频信号的第一目标制式不是4M25/30或5M20时，AD芯片PTZ信号接收参数读取视频信号的第6消隐行中的PTZ信号，得到第二数据。若第二数据为0xff，则SoC芯片可以确定视频信号的类型为第一类型。若第二数据为0x00，则SoC芯片可以进一步根据视频信号的色载波检测状态和锁定状态识别该视频信号的类型，其具体实现可以参见图6所示流程。若第二数据既不是0x00也不是0xff，即视频信号的第二数据为0x00～0xff之间的数据，则SoC芯片可以确定视频信号的类型为第二类型。
本申请实施例中，当接收到视频信号时，使用PTZ协议读取视频信号的消隐行中的PTZ信号，得到读取的数据，根据读取的数据识别视频信号的类型，从而提高了视频信号类型识别的准确率，并且最终得到了该视频信号的制式和类型。
进一步地，在本申请实施例中，在实际应用中，当按照上述方式确定了视频信号的制式和类型后，还存在该视频信号制式判断错误的可能性，也就是说可能会出现视频信号误锁定的情况。可以在完成视频信号的制式和类型的判断之后再加入误锁的判断。
例如，以制式4M12.5和720P25为例，该两个制式共用同一个制式值，且该两个制式的视频信号的行长相同。
若当前接收到的视频信号制式是4M12.5，但SoC芯片按照制式720P25配置其对应的第二寄存器后，检测到接收到的视频信号的HLOCK和VLOCK均处于锁定状态，此时，SoC芯片会认为接收到的信号的制式为720P25，发生误判，进而，在后续流程中，由于视频信号制式识别错误会导致视频信号处理异常，因此，在按照上述方式进行视频 信号制式识别时，还需要确定是否存在视频信号误判的情况。
相应地，在本申请其中一个实施例中，在根据读取的数据识别接收到的视频信号的类型之后，还可以包括：检测接收到的视频信号的色载波是否处于锁定状态；若接收到的视频信号的色载波处于未锁定状态，则确定接收到的视频信号误锁定。
在该实施例中，考虑到视频信号误锁定时，视频信号的色载波通常无法锁定(即SLOCK的状态为未锁定)，因此，可以根据色载波是否处于锁定状态确定视频信号是否误锁定。
相应地，当确定视频信号的制式和类型之后，可以检测接收到的视频信号的色载波的锁定状态是否为已锁定；若色载波的锁定状态为已锁定，则确定接收到的视频信号的制式为第一目标制式；若色载波的锁定状态为未锁定，则确定接收到的视频信号误锁定。
本申请实施例中，当SoC芯片确定接收到的视频信号误锁定时，SoC芯片可以重新按照图1中所述的方法对接收到的视频信号进行制式识别，或按照其它策略识别接收到的视频信号的制式，其具体实现在此不做赘述。
进一步地，在该实施例中，考虑到当信号通过长线接入时，由于信号的衰减，SLOCK无法立刻锁定，需要在自动或手动调整增益来补偿衰减之后，SLOCK才能锁定。因此，在衰减补偿完成前，无法确定是因为视频信号误锁定导致SLOCK没有锁定，还是因为信号衰减导致SLOCK没有锁定。
当视频信号的类型为TVI时，若接收到的视频信号的色载波的锁定状态为未锁定，则上述确定接收到的视频信号误锁定之前，还可以包括：将增益调整的范围设置为最大，并将增益调整到最大；检测接收到的视频信号的色载波的锁定状态是否为已锁定；若接收到的视频信号的色载波的锁定状态为未锁定，则执行上述确定视频信号误锁定的步骤。
在该实施例中在确定接收到的视频信号的色载波的锁定状态为未锁定时，SoC芯片可以将增益调整的范围设置为最大，并将增益调整到最大，以避免SLOCK由于信号衰减而无法锁定，并检测接收到的视频信号的色载波的锁定状态是否为已锁定。
若接收到的视频信号的色载波仍的锁定状态为未锁定，则SoC芯片可以确定接收到的视频信号误锁定；若接收到的视频信号的色载波的锁定状态为已锁定，则SoC芯片可以确定接收到的视频信号的制式判断正确。
当视频信号的类型为AHD时，由于这种类型的视频信号无法自动调整增益，因此可以首先确定该视频信号的EQ值，根据视频信号的EQ值配置增益倍数，然后检测接收到的视频信号的色载波的检测状态是否为已检测到并且色载波的锁定状态是否为已锁定，若色载波的检测状态为已检测到并且色载波的锁定状态为已锁定，则可以确定接收到的视频信号的制式判断正确，否则执行上述确定视频信号误锁定的步骤。
在本申请另一个实施例中，考虑到共用同一制式值的多种不同制式的目标视频信号的帧率可能不同，即该多种不同制式的目标视频信号一帧的时长可能不同，当该多种不同制式的目标视频信号中的其中一种视频信号的一帧的时长是其它视频信号的一帧时长的偶数倍时，对于该目标视频信号的一帧的时长，其它目标视频信号会存在偶数帧视频信号，该目标视频信号的一帧的中间行以及中间行上下一定数量行对于该目标视频信号而言是图像信息区，而对于其它目标视频信号而言是消隐区，此时，还可以利用图像信息区和消隐区的电压值的区别来区分不同的制式。
在本申请另一个实施例中，当按照第一目标制式配置第二寄存器，且检测到接收到的视频信号处于锁定状态时，上述确定接收到的视频信号的制式为第一目标制式之前，还可以包括：若第一目标视频信号的帧率为其它目标视频信号的帧率一半，则读取一帧第一目标视频信号的目标行的电压值，其中，目标行为一帧第一目标视频信号的正中间行上下预设数量行之间的任一行；若目标行的电压值为正值，则确定接收到的视频信号的制式为第一目标制式；若目标行的电压值为负值或零，则确定接收到的视频信号误锁定。
在本申请的再一个实施例中，当按照第一目标制式配置第二寄存器，且检测到接收到的视频信号处于锁定状态时，上述确定接收到的视频信号的制式为第一目标制式之前，还可以包括：若第一目标视频信号的帧率为其它目标视频信号的帧率两倍，则读取一帧第一目标视频信号的目标行的电压值，其中，目标行为一帧第一目标视频信号的正中间行上下预设数量行之间的任一行；若目标行的电压值为负值或零，则确定接收到的视频信号的制式为第一目标制式；若目标行的电压值为正值，则确定接收到的视频信号误锁定。
当第一目标视频信号的帧率为其它目标视频信号的帧率的一半，即第一目标视频信号每一帧的时长为其它目标视频信号每一帧的时长的两倍时，一帧第一目标视频信号的时长里，会存在两帧其它目标视频信号。一帧第一目标视频信号的正中间，对应的是其它目标视频信号的一帧的开始。
由于一帧视频信号的开始是场同步信号，场同步信号是一段低电平(即电压值为负值)。而一帧视频信号的正中间是图像信息，电压为正电平值(即电压值为正值)。由于一帧视频信号的开始和结尾处的若干行为消隐区，除了某些特定行会有同步信号外，消隐区的电平默认为零，即电压值为零。因此，可以根据第一目标视频信号的正中间行上下预设数量(可以根据第一目标视频信号和其它目标视频信号的图像信息区行数和消隐区行数确定)之间的任一行(本文中称为目标行)的电压值确定接收到的视频信号的制式是否为第一目标制式，进而，确定接收到的视频信号是否误锁定。
举例来说，以制式4M12.5和720P25为例，4M12.5信号每秒钟12.5帧，即一帧的时长为80ms，720P25信号每秒钟25帧，即一帧的时长为40ms。因此，80ms的时长里，有一帧4M12.5视频信号或者两帧720P25视频信号。4M12.5帧的正中间，对应是720P25一帧的开始，其示意图可以如图2所示。
假设SoC芯片按照4M12.5(即第一目标制式为4M12.5)配置第二寄存器，并检测到接收到的视频信号处于锁定状态，此时，AD芯片读取一帧第一目标视频信号的正中间行的电压值。
若该正中间行的电压值为正值，则SoC芯片可以确定接收到的视频信号的制式为4M12.5；若该正中间的电压值为负值，则SoC芯片可以确定接收到的视频信号的制式不是4M12.5，即接收到的视频信号发生误锁定。
需要注意的是，上述使用电压值判断误锁的方法，还可以在视频信号的制式确定之后进行，也可以在视频信号的类型确定之后进行。本申请对此不作限定。
进一步的，请参见图9，为本申请实施例提供的一种视频信号误锁定识别方法的流程示意图，该方法可以包括以下步骤。
步骤S900、若接收到的视频信号的制式和类型被确定，则判断一帧第一目标视频信号的时长是否为一帧其它目标视频信号的时长的偶数倍。若是，则转至步骤S910；否则，转至步骤S940。
本申请实施例中，SoC芯片确定接收到的视频信号的制式和类型的具体实现可以参见图1和图5所示方法流程中的相关描述。
本申请实施例中，当确定了接收到的视频信号的制式和类型后，SoC芯片可以判断一帧第一目标视频信号的时长是否为一帧其它目标视频信号的偶数倍。
步骤S910、读取一帧第一目标视频信号的目标行的电压值。若为正值，则转至 步骤S920；若为负值或零，则转至步骤S930。
步骤S920、确定接收到的视频信号的制式为第一目标制式。
步骤S930、确定接收到的视频信号误锁定。
本申请实施例中，考虑到当一帧第一目标视频信号的时长为一帧其它目标视频信号的时长的偶数倍时，一帧第一目标视频信号的时长里，会存在偶数帧其它目标视频信号。一帧第一目标视频信号的正中间，对应的是其它目标视频信号的一帧的开始。
假设SoC芯片确定的第一目标制式为4M12.5，并确定了视频信号的类型为目标类型，此时，SoC芯片读取一帧第一目标视频信号的正中间行的电压值。
若该正中间行的电压值为正值，则DVR可以确定接收到的视频信号的制式为4M12.5；若该正中间的电压值为负值或零，则DVR可以确定接收到的视频信号的制式不是4M12.5，即接收到的视频信号发生误锁定。
步骤S940、检测接收到的视频信号的色载波是否处于锁定状态。若处于锁定状态，则转至步骤S950；否则，转至步骤S960。
步骤S950、确定接收到的视频信号的制式为第一目标制式。
步骤S960、确定接收到的视频信号误锁定。
本申请实施例中，步骤S940～步骤S960的具体实现可以参见前述实施例中关于色载波判断的相关描述，在此不再赘述。
在步骤S930和步骤S960中，当确定接收到的视频信号误锁定时，SoC芯片可以转到图3中的步骤S300，对接收到的视频信号重新进行制式识别，或按照其它策略识别接收到的视频信号的制式。
以上对本申请提供的方法进行了描述。下面对本申请提供的装置进行描述。
请参见图10，为本申请实施例提供的一种视频信号识别装置的结构示意图，其中，该视频信号识别装置可以应用于上述方法实施例中的SoC芯片，如图10所示，该视频信号识别装置可以包括以下单元。
PTZ协议读取单元1010，用于当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据。
类型识别单元1020，用于根据所述读取的数据识别所述视频信号的类型。
在一种可选的实施方式中，如图10所示，所述装置还包括：正弦波检测单元1030，用于检测所述视频信号的倒数第4个消隐行中是否存在正弦波。所述类型识别单元1020，还用于若所述视频信号的倒数第4个消隐行中存在所述正弦波，则确定所述视频信号的类型为目标类型；所述PTZ协议读取单元1010，具体用于若所述视频信号的倒数第4个消隐行中不存在所述正弦波，则使用所述PTZ协议读取所述视频信号的所述消隐行中的所述PTZ信号。
在一种可选的实施方式中，所述PTZ协议读取单元1010，具体用于使用所述PTZ协议读取所述视频信号的第一目标消隐行中的所述PTZ信号，得到读取的第一数据；所述类型识别单元1020，具体用于根据所述第一数据识别所述视频信号的类型；其中，所述第一目标消隐行为所述视频信号的第23-26消隐行中的任一消隐行。
在一种可选的实施方式中，所述PTZ协议读取单元1010，具体用于使用所述PTZ协议读取所述视频信号的第二目标消隐行中的所述PTZ信号，得到读取的第二数据；所述类型识别单元1020，具体用于根据所述第二数据识别所述视频信号的类型；其中，所述第二目标消隐行为所述视频信号的第6-7消隐行中的任一消隐行。
在一种可选的实施方式中，所述类型识别单元1020，还用于若所述第二数据为0x00，则根据所述视频信号的色载波的检测状态和锁定状态识别所述视频信号的类型。
在一种可选的实施方式中，在使用所述PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到所述读取的数据之前，如图11所示，所述装置还包括以下单元。
读取单元1110，用于读取第一寄存器，得到所述视频信号的制式值。
配置单元1120，用于当所述制式值由多种制式的目标视频信号共用时，按照所述多种制式中至少一个所述目标视频信号的制式配置第二寄存器。
锁定检测单元1130，用于检测视频信号是否处于锁定状态。
第一制式确定单元1140，用于当配置单元1120按照第一目标制式配置第二寄存器，且锁定检测单元1130检测到视频信号处于锁定状态时，确定所述视频信号的制式为所述第一目标制式，其中，所述第一目标制式为所述多种目标视频信号中的第一目标视频信号的制式。
在一种可选的实施方式中，如图11所示，所述装置还包括优先级确定单元1150，用于确定所述多种制式的各目标视频信号的制式的优先级；所述配置单元1120，具体用于按照优先级从高到低的顺序，配置所述至少一种所述目标视频信号的制式的第二寄存 器。
在一种可选的实施方式中，所述配置单元1120，具体用于按照所述优先级排序第i的目标视频信号的制式配置第二寄存器，当配置的次数小于Ni时，若所述视频信号处于未锁定状态，则继续按照所述优先级排序第i的目标视频信号的制式配置第二寄存器，并且将所述配置的次数加1；当所述配置次数等于Ni时，若所述视频信号处于未锁定状态，令i＝i+1，并重复按照所述优先级排序第i的目标视频信号的制式配置第二寄存器的步骤；其中，i越大，优先级越低。
在一种可选的实施方式中，i越大，Ni越小。
在一种可选的实施方式中，如图11所示，所述装置还包括：行长确定单元1160，用于确定所述多种目标视频信号的行长；第二制式确定单元1170，用于若所述多种目标视频信号的行长均不同，则根据所述多种目标视频信号各自的行长、以及所述视频信号的行长确定所述视频信号的制式。所述配置单元1120，还用于若所述多种目标视频信号中至少有两种目标视频信号的行长相同，则按照所述多种制式中所述至少一种所述目标视频信号的制式配置第二寄存器。
在一种可选的实施方式中，第二制式确定单元1170具体用于：读取第三寄存器，得到行长值；比较所述行长值以及所述多种目标视频信号各自的行长；当所述行长值和某一目标视频信号的行长相同时，将该目标视频信号的制式确定为所述第一目标制式。
在一种可选的实施方式中，如图11所示，所述装置还包括以下单元。
色载波检测单元1210，用于在根据所述读取的数据识别所述视频信号的类型之后，检测所述视频信号的色载波是否处于锁定状态。
误锁定确定单元1220，用于若所述视频信号的所述色载波处于未锁定状态，则确定所述视频信号误锁定。
在一种可选的实施方式中，如图11所示，所述装置还包括调整单元1230，用于在确定所述视频信号误锁定之前，将增益调整的范围设置为最大，并将所述增益调整到最大。
在一种可选的实施方式中，如图11所示，所述装置还包括电压读取单元1240，用于在确定所述视频信号的制式为所述第一目标制式之前，若所述第一目标视频信号的帧率为其它目标视频信号的帧率一半，则读取一帧所述第一目标视频信号的目标行的电压值。其中，所述目标行为所述一帧所述第一目标视频信号的正中间行上下预设数量行 之间的任一行。所述误锁定确定单元1220，还用于若所述目标行的电压值为负值或零，则确定所述视频信号误锁定。
本申请实施例的视频信号识别装置，当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；根据所述读取的数据识别所述视频信号的类型。本申请提供的视频信号识别装置，提高了视频信号识别的准确率。
请参见图12，为本申请实施例提供的一种电子设备的硬件结构示意图。该电子设备可以包括处理器1201、通信接口1202、存储器1203和通信总线1204。处理器1201、通信接口1202以及存储器1203通过通信总线1204完成相互间的通信。其中，存储器1203上存放有计算机程序；处理器1201可以通过执行存储器1203上所存放的程序，执行上文描述的视频信号识别方法。
本文中提到的存储器1203可以是任何电子、磁性、光学或其它物理存储装置，可以包含或存储信息，如可执行指令、数据，等等。例如，存储器1203可以是：RAM(Radom Access Memory，随机存取存储器)、易失存储器、非易失性存储器、闪存、存储驱动器(如硬盘驱动器)、固态硬盘、任何类型的存储盘(如光盘、dvd等)，或者类似的存储介质，或者它们的组合。
本申请实施例还提供了一种存储有计算机程序的机器可读存储介质，例如图12中的存储器1203，所述计算机程序可由图12所示电子设备中的处理器1201执行以实现上文描述的视频信号识别方法。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (30)

  1. 一种视频信号识别方法，其特征在于，包括：
    当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；
    根据所述读取的数据识别所述视频信号的类型。
  2. 根据权利要求1所述的方法，其特征在于，在使用所述PTZ协议读取所述视频信号的所述消隐行中的所述PTZ信号之前，还包括：
    检测所述视频信号的倒数第4个消隐行中是否存在正弦波；
    若存在所述正弦波，则确定所述视频信号的类型为目标类型；
    若不存在所述正弦波，则执行使用所述PTZ协议读取所述视频信号的所述消隐行中的所述PTZ信号的步骤。
  3. 根据权利要求1所述的方法，其特征在于，
    使用所述PTZ协议读取所述视频信号的所述消隐行中的所述PTZ信号，得到所述读取的数据，包括：用所述PTZ协议读取所述视频信号的第一目标消隐行中的所述PTZ信号，得到读取的第一数据；
    根据所述读取的数据识别所述视频信号的类型，包括：根据所述第一数据识别所述视频信号的类型；
    其中，所述第一目标消隐行为所述视频信号的第23-26消隐行中的任一消隐行。
  4. 根据权利要求1所述的方法，其特征在于，
    使用所述PTZ协议读取所述视频信号的所述消隐行中的所述PTZ信号，得到所述读取的数据，包括：使用所述PTZ协议读取所述视频信号的第二目标消隐行中的所述PTZ信号，得到读取的第二数据；
    根据所述读取的数据识别所述视频信号的类型，包括：根据所述第二数据识别所述视频信号的类型；
    其中，所述第二目标消隐行为所述视频信号的第6-7消隐行中的任一消隐行。
  5. 根据权利要求6所述的方法，其特征在于，根据所述第二数据识别所述视频信号的类型，还包括：
    若所述第二数据为0x00，则根据所述视频信号的色载波的检测状态和锁定状态识别所述视频信号的类型。
  6. 根据权利要求1所述的方法，其特征在于，在使用所述PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到所述读取的数据之前，所述方法还包括：
    读取第一寄存器，得到所述视频信号的制式值；
    当所述制式值由多种制式的目标视频信号共用时，按照所述多种制式中至少一种所述目标视频信号的制式配置第二寄存器，并检测所述视频信号是否处于锁定状态；
    当按照第一目标制式配置第二寄存器，且检测到所述视频信号处于锁定状态时，确定所述视频信号的制式为所述第一目标制式，其中，所述第一目标制式为所述多种目标视频信号中的第一目标视频信号的制式。
  7. 根据权利要求6所述的方法，其特征在于，按照所述多种制式中至少一种所述目标视频信号的制式配置第二寄存器，并检测所述视频信号是否处于锁定状态，包括：
    确定所述多种制式的各所述目标视频信号的制式的优先级；
    按照所述优先级从高到低的顺序，配置第二寄存器，并检测所述视频信号是否处于锁定状态；
    当检测到所述视频信号处于锁定状态，执行确定所述视频信号的制式为所述第一目标制式的步骤。
  8. 根据权利要求7所述的方法，其特征在于，按照所述优先级从高到低的顺序，配置第二寄存器，并检测所述视频信号是否处于锁定状态，包括：
    按照优先级排序第i的目标视频信号的制式配置第二寄存器，
    当配置的次数小于Ni时，若所述视频信号处于未锁定状态，则继续按照所述优先级排序第i的目标视频信号的制式配置第二寄存器，并且将所述配置的次数加1；
    当所述配置次数等于Ni时，若所述视频信号处于未锁定状态，令i＝i+1，并返回执行按照所述优先级排序第i的目标视频信号的制式配置第二寄存器的步骤；
    其中，i越大，优先级越低。
  9. 根据权利要求8所述的方法，其特征在于，i越大，Ni越小。
  10. 根据权利要求6-9任一项所述的方法，其特征在于，按照所述多种制式中所述至少一种所述目标视频信号的制式配置第二寄存器之前，还包括：
    确定所述多种目标视频信号的行长；
    若所述多种目标视频信号中至少有两种目标视频信号的行长相同，则执行按照所述多种制式中所述至少一种所述目标视频信号的制式配置第二寄存器的步骤；
    若所述多种目标视频信号的行长均不同，则根据所述多种目标视频信号各自的行长、以及所述视频信号的行长确定所述视频信号的制式。
  11. 根据权利要求10所述的方法，其特征在于，根据所述多种目标视频信号各自的行长、以及所述视频信号的行长确定所述视频信号的制式，包括：
    读取第三寄存器，得到行长值；
    比较所述行长值以及所述多种目标视频信号各自的行长；
    当所述行长值和某一目标视频信号的行长相同时，将该目标视频信号的制式确定为所述视频信号第一目标制式。
  12. 根据权利要求1所述的方法，其特征在于，在根据所述读取的数据识别所述视频信号的类型之后，还包括：
    检测所述视频信号的色载波是否处于锁定状态；
    若所述视频信号的所述色载波处于未锁定状态，则确定所述视频信号误锁定。
  13. 根据权利要求12所述的方法，其特征在于，确定所述视频信号误锁定之前，还包括：
    将增益调整的范围设置为最大，并将所述增益调整到最大；
    检测所述视频信号的所述色载波是否处于锁定状态；
    若所述视频信号的所述色载波处于所述未锁定状态，则执行确定所述视频信号误锁定的步骤。
  14. 根据权利要求6-9任一项所述的方法，其特征在于，在确定所述视频信号的制式为所述第一目标制式之前，还包括：
    若所述第一目标视频信号的帧率为其它目标视频信号的帧率一半，则读取一帧所述第一目标视频信号的目标行的电压值，其中，所述目标行为所述一帧所述第一目标视频信号的正中间行上下预设数量行之间的任一行；
    若所述目标行的电压值为负值或零，则确定所述视频信号误锁定。
  15. 一种视频信号识别装置，其特征在于，包括：
    PTZ协议读取单元，用于当接收到视频信号时，使用PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到读取的数据；
    类型识别单元，用于根据所述读取的数据识别所述视频信号的类型。
  16. 根据权利要求15所述的装置，其特征在于，
    所述装置还包括：正弦波检测单元，用于检测所述视频信号的倒数第4个消隐行中是否存在正弦波；
    所述类型识别单元，还用于若所述视频信号的倒数第4个消隐行中存在所述正弦波，则确定所述视频信号的类型为目标类型；
    所述PTZ协议读取单元，具体用于若所述视频信号的倒数第4个消隐行中不存在所述正弦波，则使用所述PTZ协议读取所述视频信号的所述消隐行中的所述PTZ信号。
  17. 根据权利要求15所述的装置，其特征在于，
    所述PTZ协议读取单元，具体用于使用所述PTZ协议读取所述视频信号的第一目标消隐行中的所述PTZ信号，得到读取的第一数据；
    所述类型识别单元，具体用于根据所述第一数据识别所述视频信号的类型；
    其中，所述第一目标消隐行为所述视频信号的第23-26消隐行中的任一消隐行。
  18. 根据权利要求15所述的装置，其特征在于，
    所述PTZ协议读取单元，具体用于使用所述PTZ协议读取所述视频信号的第二目标消隐行中的所述PTZ信号，得到读取的第二数据；
    所述类型识别单元，具体用于根据所述第二数据识别所述视频信号的类型；
    其中，所述第二目标消隐行为所述视频信号的第6-7消隐行中的任一消隐行。
  19. 根据权利要求18所述的装置，其特征在于，
    所述类型识别单元，还用于若所述第二数据为0x00，则根据所述视频信号的色载波的检测状态和锁定状态识别所述视频信号的类型。
  20. 根据权利要求15所述的装置，其特征在于，在使用所述PTZ协议读取所述视频信号的消隐行中的PTZ信号，得到所述读取的数据之前，所述装置还包括：
    读取单元，用于读取第一寄存器，得到所述视频信号的制式值；
    配置单元，用于当所述制式值由多种制式的目标视频信号共用时，按照所述多种制式中至少一种所述目标视频信号的制式配置第二寄存器；
    锁定检测单元，用于检测所述视频信号是否处于锁定状态；
    第一制式确定单元，用于当所述配置单元按照第一目标制式配置第二寄存器，且所述锁定检测单元检测到所述视频信号处于锁定状态时，确定所述视频信号的制式为所述第一目标制式，其中，所述第一目标制式为所述多种目标视频信号中的第一目标视频信号的制式。
  21. 根据权利要求20所述的装置，其特征在于，
    所述装置还包括：优先级确定单元，用于确定所述多种制式的各目标视频信号的制式的优先级；
    所述配置单元，具体用于按照优先级从高到低的顺序，配置第二寄存器。
  22. 根据权利要求21所述的装置，其特征在于，所述配置单元，具体用于
    按照所述优先级排序第i的目标视频信号的制式配置第二寄存器，
    当配置的次数小于Ni时，若所述视频信号处于未锁定状态，则继续按照所述优先级排序第i的目标视频信号的制式配置第二寄存器，并且将所述配置的次数加1；
    当所述配置次数等于Ni时，若所述视频信号处于未锁定状态，令i＝i+1，并返回执行所述按照所述优先级排序第i的目标视频信号的制式配置第二寄存器的步骤；
    其中，i越大，优先级越低。
  23. 根据权利要求22所述的装置，其特征在于，i越大，Ni越小。
  24. 根据权利要求20-23任一项所述的装置，其特征在于，所述装置还包括：
    行长确定单元，用于确定所述多种目标视频信号的行长；
    第二制式确定单元，用于若所述多种目标视频信号的行长均不同，则根据所述多种目标视频信号各自的行长、以及所述视频信号的行长确定所述视频信号的制式；
    所述配置单元，还用于若所述多种目标视频信号中至少有两种目标视频信号的行长相同，则按照所述多种制式中所述至少一种所述目标视频信号的制式配置第二寄存器。
  25. 根据权利要求24所述的装置，其特征在于，第二制式确定单元具体用于：
    读取第三寄存器，得到行长值；
    比较所述行长值以及所述多种目标视频信号各自的行长；
    当所述行长值和某一目标视频信号的行长相同时，将该目标视频信号的制式确定为所述视频信号第一目标制式。
  26. 根据权利要求15所述的装置，其特征在于，所述装置还包括：
    色载波检测单元，用于在根据所述读取的数据识别所述视频信号的类型之后，检测所述视频信号的色载波是否处于锁定状态；
    误锁定确定单元，用于若所述视频信号的所述色载波处于未锁定状态，则确定所述视频信号误锁定。
  27. 根据权利要求26所述的装置，其特征在于，所述装置还包括：
    调整单元，用于在确定所述视频信号误锁定之前，将增益调整的范围设置为最大，并将所述增益调整到最大。
  28. 根据权利要求20-23任一项所述的装置，其特征在于，
    所述装置还包括：电压读取单元，用于在确定所述视频信号的制式为所述第一目标制式之前，若所述第一目标视频信号的帧率为其它目标视频信号的帧率一半，则读取一帧所述第一目标视频信号的目标行的电压值，其中，所述目标行为所述一帧所述第一目标视频信号的正中间行上下预设数量行之间的任一行；
    所述视频信号所述误锁定确定单元，还用于若所述目标行的电压值为负值或零，则确定所述视频信号误锁定。
  29. 一种电子设备，其特征在于，包括处理器、通信接口、存储器和通信总线，其 中，所述处理器，所述通信接口，所述存储器通过所述通信总线完成相互间的通信；
    所述存储器，用于存放计算机程序；
    所述处理器，用于执行所述存储器上所存放的所述计算机程序时，实现权利要求1-14任一项所述的方法步骤。
  30. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质内存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-14任一项所述的方法步骤。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113691755A (zh) * 2021-08-17 2021-11-23 杭州海康威视数字技术股份有限公司 硬盘录像机及同轴音频数据的检测方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020020157A1 (zh) * 2018-07-25 2020-01-30 杭州海康威视数字技术股份有限公司 视频信号识别方法、装置、电子设备及可读存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102318340A (zh) * 2011-06-17 2012-01-11 华为终端有限公司 一种确定需要输出的视频信号类型的方法及装置
US8866910B1 (en) * 2008-09-18 2014-10-21 Grandeye, Ltd. Unusual event detection in wide-angle video (based on moving object trajectories)
CN105828014A (zh) * 2016-05-06 2016-08-03 浙江宇视科技有限公司 一种音视频传输方法及装置
CN106454208A (zh) * 2015-08-04 2017-02-22 德信东源智能科技(北京)有限公司 一种三维视频引导监控技术
CN106506904A (zh) * 2016-11-16 2017-03-15 浙江大华技术股份有限公司 一种信号传输方法及设备

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111160A (en) 1991-04-30 1992-05-05 The Grass Valley Group Clock generation circuit for multistandard serial digital video with automatic format identification
US5812210A (en) * 1994-02-01 1998-09-22 Hitachi, Ltd. Display apparatus
JPH10336595A (ja) * 1997-06-05 1998-12-18 Mitsubishi Electric Corp デコーダ
US6330034B1 (en) * 1997-10-31 2001-12-11 Texas Instruments Incorporated Color phase-locked loop for video decoder
US6784943B1 (en) * 1997-12-23 2004-08-31 Thomson Licensing S.A. Auxiliary digital data extractor in a television
KR100251967B1 (ko) * 1998-02-28 2000-04-15 윤종용 비디오 포맷 변환을 위한 룩업 테이블 구성방법과 룩업테이블을 이용한 스캔 포맷 컨버터
JP3369469B2 (ja) 1998-05-22 2003-01-20 日本ビクター株式会社 複数映像再生装置及び複数映像再生方法
DE69934839T2 (de) * 1998-06-04 2007-05-16 Matsushita Electric Industrial Co., Ltd., Kadoma Videoproduktionssystem mit progressiver Abtastung und magnetisches Aufzeichnungs-/ Wiedergabegerät mit Zeilensprung.
US7385626B2 (en) * 2002-10-21 2008-06-10 Sarnoff Corporation Method and system for performing surveillance
CN100342734C (zh) 2003-03-04 2007-10-10 索尼株式会社 视频信号处理电路和视频信号处理方法
US20050091047A1 (en) 2003-10-27 2005-04-28 Gibbs Jonathan A. Method and apparatus for network communication
JP3969387B2 (ja) * 2003-12-05 2007-09-05 松下電器産業株式会社 映像信号出力装置
CN100493171C (zh) 2004-01-17 2009-05-27 深圳创维－Rgb电子有限公司 一种视频信号格式的转换方法
US20050219366A1 (en) * 2004-03-31 2005-10-06 Hollowbush Richard R Digital audio-video differential delay and channel analyzer
CN100379280C (zh) 2005-11-29 2008-04-02 天津三星电子显示器有限公司 模拟电视信号接收机对接收信号制式自动识别的方法
KR100844850B1 (ko) * 2006-10-12 2008-07-08 엘지전자 주식회사 디지털 비디오 레코더에서의 팬/틸트/줌 카메라 컨트롤장치 및 방법
US8169542B2 (en) 2006-10-27 2012-05-01 Broadcom Corporation Automatic format identification of analog video input signals
JP2009080171A (ja) 2007-09-25 2009-04-16 Nec Electronics Corp 信号処理装置
CN101510975B (zh) 2009-03-24 2014-10-29 北京中星微电子有限公司 影像数据识别处理方法及其装置
JP5322287B2 (ja) * 2009-05-28 2013-10-23 パナソニック株式会社 回転台付カメラ装置
CN101873464A (zh) 2009-06-01 2010-10-27 杭州海康威视数字技术股份有限公司 一种自动切换视频信号的方法和装置
CN101651534B (zh) 2009-09-17 2012-04-18 北京海尔集成电路设计有限公司 一种数据帧同步方法及其设备
CN102111625A (zh) 2009-12-24 2011-06-29 上海威乾视频技术有限公司 基于dvr的电视制式自动识别系统和方法
CN102123261B (zh) 2010-01-11 2015-06-10 康佳集团股份有限公司 一种电视机及其搜台方法、系统
CN102263981B (zh) 2010-05-25 2013-07-10 北京创毅视讯科技有限公司 一种自动检测模拟电视pal制式的方法和装置
CN102387327B (zh) 2010-08-30 2016-01-20 深圳艾科创新微电子有限公司 一种视频信号制式检测方法及装置
CN101977289A (zh) 2010-10-28 2011-02-16 中兴通讯股份有限公司 一种处理多电视制式信号的方法、装置、系统及设备
CN201910861U (zh) 2010-12-16 2011-07-27 天津三星光电子有限公司 可自动辨别制式的数字视频摄像机
JP2013031143A (ja) * 2011-04-08 2013-02-07 Sony Corp 映像処理装置及び映像処理方法
CN102740086B (zh) * 2012-06-26 2015-01-28 上海屹芯微电子有限公司 复合视频广播信号制式的自动识别方法和装置
CN104754272B (zh) 2013-12-25 2018-11-20 深圳开阳电子股份有限公司 一种vga全分辨率锁定显示系统及方法
US20150334186A1 (en) * 2014-05-15 2015-11-19 Safeciety LLC Coax Adaptor for Ethernet Physical Layer Transceiver
CN105530444B (zh) 2014-09-30 2019-08-23 三亚中兴软件有限责任公司 检测相同制式的视频信号的方法、装置及视频会议系统
CN106341575B (zh) 2015-12-16 2019-03-29 深圳开阳电子股份有限公司 一种视频信号实时输出处理系统
CN105656480A (zh) 2015-12-30 2016-06-08 合肥宏晶微电子科技股份有限公司 低噪声视频数字锁相环
CN106961598B (zh) 2017-03-17 2019-02-12 浙江大华技术股份有限公司 一种信号制式判断方法及装置
CN107094239B (zh) 2017-04-24 2019-11-15 浙江大华技术股份有限公司 一种确定视频格式信息的方法和设备
WO2020020157A1 (zh) * 2018-07-25 2020-01-30 杭州海康威视数字技术股份有限公司 视频信号识别方法、装置、电子设备及可读存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8866910B1 (en) * 2008-09-18 2014-10-21 Grandeye, Ltd. Unusual event detection in wide-angle video (based on moving object trajectories)
CN102318340A (zh) * 2011-06-17 2012-01-11 华为终端有限公司 一种确定需要输出的视频信号类型的方法及装置
CN106454208A (zh) * 2015-08-04 2017-02-22 德信东源智能科技(北京)有限公司 一种三维视频引导监控技术
CN105828014A (zh) * 2016-05-06 2016-08-03 浙江宇视科技有限公司 一种音视频传输方法及装置
CN106506904A (zh) * 2016-11-16 2017-03-15 浙江大华技术股份有限公司 一种信号传输方法及设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113691755A (zh) * 2021-08-17 2021-11-23 杭州海康威视数字技术股份有限公司 硬盘录像机及同轴音频数据的检测方法
WO2023020350A1 (zh) * 2021-08-17 2023-02-23 杭州海康威视数字技术股份有限公司 硬盘录像机及同轴音频数据的检测方法

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