WO2020015136A1

WO2020015136A1 - Method for increasing reaction rate employing flash memory pins

Info

Publication number: WO2020015136A1
Application number: PCT/CN2018/105895
Authority: WO
Inventors: 许豪江; 李庭育; 魏智汎; 黄中柱
Original assignee: 江苏华存电子科技有限公司
Priority date: 2018-07-20
Filing date: 2018-09-15
Publication date: 2020-01-23
Also published as: CN108932961A

Abstract

Disclosed is a method for increasing a reaction rate employing flash memory pins, comprising the following steps: step 1: switching a multiplexer to a chip enabling pin; step 2: a flash memory instruction control device in a memory control chip issuing a read, write/programming, or erase instruction to a flash memory chip; step 3: switching the multiplexer to a ready/busy pin; and step 4: inquiring whether a given signal on the ready/busy pin is a high level signal, and if so, reporting complete and switching the multiplexer to the chip enabling pin, and if not, continuing to inquire whether a given signal on the ready/busy pin is a high level signal. In the invention, a multiplexer is used to eliminate an additional ready/busy pin, thereby achieving high efficiency and a much improved response rate in comparison to conventional methods.

Description

Method for improving response rate by using flash pins

Technical field

The invention relates to the technical field of flash memory operation, and in particular to a method for improving response rate by using flash memory pins.

Background technique

Flash memory is a non-erasable memory device. It has three-level three-level cell (TLC), two-bit multi-level cell (MLC) flash, and one single-level cell (SLC) flash. No matter what kind of flash memory is required, The flash memory chip is controlled through the memory control chip. After the flash memory command (such as read command, write / program command, and erase command) is issued by the memory control chip, the flash memory chip performs corresponding actions to read or write data. Multiple pins are composed of address latch enable pin ALE, instruction latch enable pin CLE, data transfer pin DQS, read enable pin RE, write enable pin WE, and chip enable pin. Pin CE, ready busy pin RB. Control the flash chip through these pins,

Because the memory control chip cannot know the operating status of the flash memory chip, when the read or write command is issued, the memory chip will be busy and take corresponding actions. You need to issue a read flash status command to the flash memory chip to read it correctly. Flash memory status (success or failure) to determine the success of the flash operation. There are usually two ways to confirm in the traditional method. The first is to read the flash memory with the flash status command, and the second is to read the status of the busy pins on the flash chip. The former takes time, the latter will have one more pin. An extra pin will lead to a larger chip area and higher production costs.

In the traditional way, when the flash read status command is issued, if the flash reply is busy, continue to send the read status command until the read is completed. Because each channel will be connected to multiple flash memories, sharing the channel information width, frequent sending of read status instructions will occupy the channel information width, resulting in poor performance. Therefore, an improved technology is urgently needed to solve all the problems in the prior art. This problem exists.

Summary of the invention

The purpose of the present invention is to provide a method for improving the response rate by using a flash memory pin, using a multi-select switch to eliminate a ready busy pin and achieving high efficiency, and the response rate is greatly improved compared with the traditional method, so as to solve the above background technology the question raised.

To achieve the above object, the present invention provides the following technical solution: A method for improving a response rate by using a flash memory pin includes the following steps:

Step 1: Switch the multi-select switch to the chip enable pin;

Step 2: The flash memory instruction control device in the memory control chip issues read, write / program or erase instructions to the flash memory chip;

Step 3: Switch the multi-select switch to the ready busy pin;

Step 4: Ask whether the ready busy pin signal is high level. If yes, the report is completed. Switch the multi-select switch to the chip enable pin. If not, continue to ask if the ready busy pin signal is high level.

Preferably, in step 1, the memory control chip uses the address latch enable pin ALE, the instruction latch enable pin CLE, the data transfer pin DQS, the read enable pin RE, the write enable pin WE, The chip enable pin CE and the ready busy pin RB control the flash memory chip.

Preferably, a flash memory command control device is provided in the memory control chip in step 2, and the flash memory chip is controlled by a command issued by the flash memory command control device.

Preferably, a multi-channel selection switch is further provided in the memory control chip in step 2, and the multi-channel selection switch is a device with multiple inputs and one output.

Compared with the prior art, the beneficial effects of the present invention are:

The use of a multiplexer switch eliminates a ready busy pin and achieves high efficiency, which greatly improves the response rate compared to traditional methods.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flowchart of a method of the present invention.

FIG. 2 is a schematic diagram of a memory control chip structure and a connection structure with a flash memory.

detailed description

In the following, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Referring to FIG. 1, the present invention provides a technical solution: a method for improving response rate by using a flash memory pin, including the following steps:

Step 1: Switch the multi-select switch to the chip enable pin;

Step 3: Switch the multi-select switch to the ready busy pin;

As shown in Figure 2, the memory control chip uses the address latch enable pin ALE, the instruction latch enable pin CLE, the data transfer pin DQS, the read enable pin RE, the write enable pin WE, The chip enable pin CE and the ready busy pin RB control the flash memory chip. There is a flash memory instruction control device in the memory control chip. Through this device, instructions can be issued to control the flash memory chip, such as read, write, erase, and read. Status instructions control multiple pins. For example, when a flash read command is issued, the instruction latch enable pin is maintained at a high level, the address latch enable pin is maintained at a low level, and the write enable pin is maintained. The pin is a rising edge. The flash memory can receive the flash memory read instruction. The memory control chip has a multiplexer switch. The multiplexer switch has multiple inputs and an output device. The selector switch is switched to an appropriate signal to block the The selected signal, such as a four-way selector switch, has four input signals and one output signal. Assuming that the signal of signal three is to be selected, the multi-way selector switch is cut to signal three, and only three signals are allowed. Input to the output port to block the signals of signal one, signal two and signal four. The chip enable pin and ready busy pin are connected to this multi-select switch at the same time. The chip enable pin or ready-to-busy pin is used.

Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, and replacements of these embodiments can be made without departing from the principle and spirit of the present invention. And variations, the scope of the invention is defined by the appended claims and their equivalents.

Claims

A method for improving the response rate by using a flash memory pin is characterized in that it includes the following steps:

Step 1: Switch the multi-select switch to the chip enable pin;

Step 2: The flash memory instruction control device in the memory control chip issues read, write / program or erase instructions to the flash memory chip;

Step 3: Switch the multi-select switch to the ready busy pin;

Step 4: Ask whether the ready busy pin signal is high level. If yes, the report is completed. Switch the multi-select switch to the chip enable pin. If not, continue to ask if the ready busy pin signal is high level.
The method of claim 1, wherein the memory control chip in step 1 uses an address latch enable pin ALE, an instruction latch enable pin CLE, and data. The transfer pin DQS, read enable pin RE, write enable pin WE, chip enable pin CE, and ready busy pin RB control the flash memory chip.
The method of claim 1, wherein the memory control chip in step 2 is provided with a flash memory instruction control device, and the flash memory instruction control device sends instructions to control the flash memory chip.
The method for improving response rate by using a flash memory pin according to claim 1, characterized in that: in the step 2, the memory control chip is further provided with a multi-way selection switch, and the multi-way selection switch is a plurality of inputs An output device.