WO2019205452A1 - Management method for improving parallel write performance of a plurality of flash memories - Google Patents

Management method for improving parallel write performance of a plurality of flash memories Download PDF

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Publication number
WO2019205452A1
WO2019205452A1 PCT/CN2018/105884 CN2018105884W WO2019205452A1 WO 2019205452 A1 WO2019205452 A1 WO 2019205452A1 CN 2018105884 W CN2018105884 W CN 2018105884W WO 2019205452 A1 WO2019205452 A1 WO 2019205452A1
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flash
memory
channel
timer
flash memories
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PCT/CN2018/105884
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French (fr)
Chinese (zh)
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许豪江
李庭育
魏智汎
陈育鸣
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江苏华存电子科技有限公司
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Publication of WO2019205452A1 publication Critical patent/WO2019205452A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the invention relates to the field of flash memory technology, and in particular relates to a management method for improving parallel write writing energy of multiple flash memories.
  • Flash memory is a long-lived non-volatile memory that retains stored data information in the event of a power outage. Data deletion is not in a single byte but in a fixed block. The block size is typically 256KB to 20MB. Flash memory is a variant of electronically erasable read-only memory (EEPROM). Unlike flash memory, EEPROM can be erased and rewritten at the byte level instead of the entire chip eraser, while most chips in flash require a block erase. except. Since data can still be saved when it is powered off, flash memory is often used to save setup information, such as saving data in a computer's BIOS (basic program), PDA (personal digital assistant), digital camera, and so on.
  • BIOS basic program
  • PDA personal digital assistant
  • Flash memory is a non-disappearing memory device with a three-bit three-level cell (TLC), two-bit multi-level cell (MLC) flash memory, and a single-level cell (SLC) flash memory, regardless of the flash memory.
  • TLC three-bit three-level cell
  • MLC multi-level cell
  • SLC single-level cell
  • the traditional method usually has two ways to confirm, the first is to read the flash with the flash status command, and the second is through the state of the busy busy pin on the flash chip. Both need to poll the chip all the time, causing the delay of the flash master chip to wait too long, affecting efficiency.
  • a management method for improving parallel writing of a plurality of flash memories comprising a memory control chip, wherein the memory control chip is provided with a flash instruction control device, a plurality of timers, a plurality of channels, the memory control chip is connected to the external plurality of flash memories; the plurality of timers comprise a first timer, a second timer, an Nth timer, and N is an integer greater than 2.
  • the plurality of channels include a first channel, a second channel, and an Mth channel, and M is an integer greater than 2;
  • the plurality of flash memories include a first flash memory, a second flash memory, a P-th flash memory, and P is an integer greater than 2;
  • Channels can control one or more flash memories.
  • the method comprises the following steps:
  • A. issuing, writing/programming or erasing instructions to the flash memory chip by the flash instruction control device in the memory control chip;
  • a read status command is issued to the flash memory through the flash command control device to determine whether the flash read, write/program or erase command is completed.
  • the invention has the beneficial effects that the invention avoids the unnecessary waiting of the memory control chip and takes precious time. Moreover, the flash delay time in the multi-channel is reduced, and the timer time of each word can be processed by the timers of the respective channels, thereby improving the efficiency of the memory control chip.
  • Figure 1 is a schematic block diagram of the present invention
  • Figure 2 is a flow chart of the present invention.
  • the present invention provides a technical solution: a management method for improving parallel writing of a plurality of flash memories, comprising a memory control chip 1 , wherein the memory control chip 1 is provided with a flash instruction control device 2 .
  • a timer, a plurality of channels, the memory control chip 1 is connected to an external plurality of flash memories;
  • the plurality of timers include a first timer 3, a second timer 4, an Nth timer, and N is an integer greater than 2;
  • the channels include a first channel 5, a second channel 6, and an Mth channel, and M is an integer greater than 2;
  • the plurality of flash memories include a first flash memory 7, a second flash memory 8, a P-th flash memory, and P is an integer greater than 2;
  • Channels can control one or more flash memories.
  • the management method for improving the parallel writing of the plurality of flash memories includes the following steps:
  • A. issuing, writing/programming or erasing instructions to the flash memory chip by the flash instruction control device in the memory control chip;
  • a read status command is issued to the flash memory through the flash command control device to determine whether the flash read, write/program or erase command is completed.
  • the present invention avoids the unnecessary waiting of the memory control chip and takes precious time. Moreover, the flash delay time in the multi-channel is reduced, and the timer time of each word can be processed by the timers of the respective channels, thereby improving the efficiency of the memory control chip.

Abstract

Disclosed is a management method for improving parallel write performance of a plurality of flash memories, the method comprising a memory control chip. The memory control chip is provided with a flash memory instruction control device, a plurality of timers, and a plurality of channels, and is connected to a plurality of external flash memories. The plurality of timers comprise a first timer, a second timer and up to an Nth timer, wherein N is an integer greater than 2. The plurality of channels comprise a first channel, a second channel and up to an Mth channel, wherein M is an integer greater than 2. The plurality of flash memories comprise a first flash memory, a second flash memory and up to a Pth flash memory, wherein P is an integer greater than 2. Each channel can control one or more flash memories. The present invention means memory control chips can avoid wasting unnecessary amounts of time waiting. The time delay issue of flash memories associated with multiple channels is also alleviated since the timer of each channel can individually set time, thereby improving efficiency of memory control chips.

Description

一种提升多颗闪存平行写入校能的管理方法Management method for improving parallel writing power of multiple flash memories 技术领域Technical field
本发明涉及闪存技术领域，具体为一种提升多颗闪存平行写入校能的管理方法。The invention relates to the field of flash memory technology, and in particular relates to a management method for improving parallel write writing energy of multiple flash memories.
背景技术Background technique
闪存是一种长寿命的非易失性(在断电情况下仍能保持所存储的数据信息)的存储器，数据删除不是以单个的字节为单位而是以固定的区块为单位，区块大小一般为256KB到20MB。闪存是电子可擦除只读存储器(EEPROM)的变种，闪存与EEPROM不同的是，EEPROM能在字节水平上进行删除和重写而不是整个芯片擦写，而闪存的大部分芯片需要块擦除。由于其断电时仍能保存数据，闪存通常被用来保存设置信息，如在电脑的BIOS(基本程序)、PDA(个人数字助理)、数码相机中保存资料等。Flash memory is a long-lived non-volatile memory that retains stored data information in the event of a power outage. Data deletion is not in a single byte but in a fixed block. The block size is typically 256KB to 20MB. Flash memory is a variant of electronically erasable read-only memory (EEPROM). Unlike flash memory, EEPROM can be erased and rewritten at the byte level instead of the entire chip eraser, while most chips in flash require a block erase. except. Since data can still be saved when it is powered off, flash memory is often used to save setup information, such as saving data in a computer's BIOS (basic program), PDA (personal digital assistant), digital camera, and so on.
闪存为非消失性的存储器装置，有存储三个比特的三级单元(TLC)，两个比特的多级单元(MLC)闪存以及一个单级单元(SLC)闪存，不管何种闪存，都需要透过存储器控制芯片控置闪存芯片，存储器控制芯片发出闪存指令(例如读取指令、写入/编程指令和擦除指令)后，闪存芯片做出对应的行为读取或写入数据，由于存储器控制芯片无法得知闪存芯片的运行状况，因此对闪存芯片发出一个读取闪存状态指令，读取正确的闪存状态(成功或失败)，判断闪存动作成功与否。传统方式通常有两种方式可以确认，第一种是用闪存状态指令读取闪存，第二种是透过闪存芯片上的就绪忙碌针的状态。两种都需要一直轮流询问芯片，导致延迟闪存主控芯片过长的等待时间，影响效率。Flash memory is a non-disappearing memory device with a three-bit three-level cell (TLC), two-bit multi-level cell (MLC) flash memory, and a single-level cell (SLC) flash memory, regardless of the flash memory. After the memory chip is controlled by the memory control chip, after the memory control chip issues a flash command (such as a read command, a write/program command, and an erase command), the flash chip performs a corresponding behavior to read or write data due to the memory. The control chip cannot know the running status of the flash chip, so it issues a read flash status command to the flash chip, reads the correct flash status (success or failure), and determines whether the flash operation is successful or not. The traditional method usually has two ways to confirm, the first is to read the flash with the flash status command, and the second is through the state of the busy busy pin on the flash chip. Both need to poll the chip all the time, causing the delay of the flash master chip to wait too long, affecting efficiency.
发明内容Summary of the invention
本发明的目的在于提供一种提升多颗闪存平行写入校能的管理方法，以解决上述背景技术中提出的问题。It is an object of the present invention to provide a management method for improving the parallel writing of a plurality of flash memories to solve the problems raised in the above background art.
为实现上述目的，本发明提供如下技术方案：一种提升多颗闪存平行写 入校能的管理方法,包括存储器控制芯片，所述存储器控制芯片内设有闪存指令控制装置、多个定时器、多个通道，所述存储器控制芯片连接外部多个闪存；多个定时器包括第一定时器、第二定时器、第N定时器，N为大于2的整数。In order to achieve the above object, the present invention provides the following technical solution: a management method for improving parallel writing of a plurality of flash memories, comprising a memory control chip, wherein the memory control chip is provided with a flash instruction control device, a plurality of timers, a plurality of channels, the memory control chip is connected to the external plurality of flash memories; the plurality of timers comprise a first timer, a second timer, an Nth timer, and N is an integer greater than 2.
优选的，多个通道包括第一通道、第二通道、第M通道，M为大于2的整数；多个闪存包括第一闪存、第二闪存、第P闪存，P为大于2的整数；每个通道可以控制一颗或多颗闪存。Preferably, the plurality of channels include a first channel, a second channel, and an Mth channel, and M is an integer greater than 2; the plurality of flash memories include a first flash memory, a second flash memory, a P-th flash memory, and P is an integer greater than 2; Channels can control one or more flash memories.
优选的，包括以下步骤：Preferably, the method comprises the following steps:
A、由存储器控制芯片内的闪存指令控制装置对闪存芯片发出读取、写入/编程或擦除指令；A. issuing, writing/programming or erasing instructions to the flash memory chip by the flash instruction control device in the memory control chip;
B、启动对应通道的定时器，设定一个相对应的时间；B. Start the timer of the corresponding channel and set a corresponding time;
C、当定时器计时中止时，透过闪存指令控制装置对闪存发出读取状态指令，判断是否完成闪存读取、写入/编程或擦除指令。C. When the timer expires, a read status command is issued to the flash memory through the flash command control device to determine whether the flash read, write/program or erase command is completed.
与现有技术相比，本发明的有益效果是：本发明避免了存储器控制芯片无谓的等待，耗费宝贵的时间。并且减低多通道内的闪存延迟时间，可以由各个通道的定时器各别处理个字的定时器时间，进而提升存储器控制芯片的效率。Compared with the prior art, the invention has the beneficial effects that the invention avoids the unnecessary waiting of the memory control chip and takes precious time. Moreover, the flash delay time in the multi-channel is reduced, and the timer time of each word can be processed by the timers of the respective channels, thereby improving the efficiency of the memory control chip.
附图说明DRAWINGS
图1为本发明原理框图；Figure 1 is a schematic block diagram of the present invention;
图2为本发明流程图。Figure 2 is a flow chart of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
请参阅图1，本发明提供一种技术方案：一种提升多颗闪存平行写入校能的管理方法,包括存储器控制芯片1，所述存储器控制芯片1内设有闪存指令控制装置2、多个定时器、多个通道，所述存储器控制芯片1连接外部多个闪存；多个定时器包括第一定时器3、第二定时器4、第N定时器，N为大于2的整数；多个通道包括第一通道5、第二通道6、第M通道，M为大于2的整数；多个闪存包括第一闪存7、第二闪存8、第P闪存，P为大于2的整数；每个通道可以控制一颗或多颗闪存。Referring to FIG. 1 , the present invention provides a technical solution: a management method for improving parallel writing of a plurality of flash memories, comprising a memory control chip 1 , wherein the memory control chip 1 is provided with a flash instruction control device 2 . a timer, a plurality of channels, the memory control chip 1 is connected to an external plurality of flash memories; the plurality of timers include a first timer 3, a second timer 4, an Nth timer, and N is an integer greater than 2; The channels include a first channel 5, a second channel 6, and an Mth channel, and M is an integer greater than 2; the plurality of flash memories include a first flash memory 7, a second flash memory 8, a P-th flash memory, and P is an integer greater than 2; Channels can control one or more flash memories.
本发明中，提升多颗闪存平行写入校能的管理方法包括以下步骤：In the present invention, the management method for improving the parallel writing of the plurality of flash memories includes the following steps:
A、由存储器控制芯片内的闪存指令控制装置对闪存芯片发出读取、写入/编程或擦除指令；A. issuing, writing/programming or erasing instructions to the flash memory chip by the flash instruction control device in the memory control chip;
B、启动对应通道的定时器，设定一个相对应的时间；B. Start the timer of the corresponding channel and set a corresponding time;
C、当定时器计时中止时，透过闪存指令控制装置对闪存发出读取状态指令，判断是否完成闪存读取、写入/编程或擦除指令。C. When the timer expires, a read status command is issued to the flash memory through the flash command control device to determine whether the flash read, write/program or erase command is completed.
综上所述，本发明避免了存储器控制芯片无谓的等待，耗费宝贵的时间。并且减低多通道内的闪存延迟时间，可以由各个通道的定时器各别处理个字的定时器时间，进而提升存储器控制芯片的效率。In summary, the present invention avoids the unnecessary waiting of the memory control chip and takes precious time. Moreover, the flash delay time in the multi-channel is reduced, and the timer time of each word can be processed by the timers of the respective channels, thereby improving the efficiency of the memory control chip.
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the invention is defined by the appended claims and their equivalents.

Claims (3)

  1. 一种提升多颗闪存平行写入校能的管理方法,包括存储器控制芯片(1)，其特征在于：所述存储器控制芯片(1)内设有闪存指令控制装置(2)、多个定时器、多个通道，所述存储器控制芯片(1)连接外部多个闪存；多个定时器包括第一定时器(3)、第二定时器(4)、第N定时器，N为大于2的整数。A management method for improving parallel writing of a plurality of flash memories, comprising a memory control chip (1), wherein: the memory control chip (1) is provided with a flash instruction control device (2), and a plurality of timers a plurality of channels, the memory control chip (1) is connected to an external plurality of flash memories; the plurality of timers comprise a first timer (3), a second timer (4), an Nth timer, and N is greater than 2. Integer.
  2. 根据权利要求1所述的一种提升多颗闪存平行写入校能的管理方法，其特征在于：多个通道包括第一通道(5)、第二通道(6)、第M通道，M为大于2的整数；多个闪存包括第一闪存(7)、第二闪存(8)、第P闪存，P为大于2的整数；每个通道可以控制一颗或多颗闪存。The method for managing parallel write power of multiple flash memories according to claim 1, wherein the plurality of channels comprises a first channel (5), a second channel (6), and an M channel, where M is An integer greater than 2; the plurality of flash memories include a first flash memory (7), a second flash memory (8), a P-th flash memory, and P is an integer greater than 2; each channel can control one or more flash memories.
  3. 根据权利要求1所述的一种提升多颗闪存平行写入校能的管理方法，其特征在于：包括以下步骤：The method for managing parallel write power of multiple flash memories according to claim 1, comprising the steps of:
    A、由存储器控制芯片内的闪存指令控制装置对闪存芯片发出读取、写入/编程或擦除指令；A. issuing, writing/programming or erasing instructions to the flash memory chip by the flash instruction control device in the memory control chip;
    B、启动对应通道的定时器，设定一个相对应的时间；B. Start the timer of the corresponding channel and set a corresponding time;
    C、当定时器计时中止时，透过闪存指令控制装置对闪存发出读取状态指令，判断是否完成闪存读取、写入/编程或擦除指令。C. When the timer expires, a read status command is issued to the flash memory through the flash command control device to determine whether the flash read, write/program or erase command is completed.
PCT/CN2018/105884 2018-04-27 2018-09-15 Management method for improving parallel write performance of a plurality of flash memories WO2019205452A1 (en)

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CN114780032A (en) * 2022-04-22 2022-07-22 山东云海国创云计算装备产业创新中心有限公司 Data reading method, device, equipment and storage medium

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