CN109558336A - Quickly generate the method for flash interface signal sequence automatically for flash memory master control hardware - Google Patents
Quickly generate the method for flash interface signal sequence automatically for flash memory master control hardware Download PDFInfo
- Publication number
- CN109558336A CN109558336A CN201811499865.1A CN201811499865A CN109558336A CN 109558336 A CN109558336 A CN 109558336A CN 201811499865 A CN201811499865 A CN 201811499865A CN 109558336 A CN109558336 A CN 109558336A
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- China
- Prior art keywords
- flash memory
- flash
- master control
- controller
- signal sequence
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
Abstract
The invention discloses a kind of methods for quickly generating flash interface signal sequence automatically for flash memory master control hardware, configure flash memory command sequence generator controller, make main control end when needing to issue the arbitrary instructions such as reading or write-in to flash memory component, after only needing to give register by a small number of information of processor read-write, by calling directly any flash memory command sequence prestored in advance in sequence generator, it is quickly errorless that arbitrary instruction sequence is issued to flash memory component, use the task performance for effectively promoting flash memory main control module.
Description
Technical field
The present invention relates to flash memory technology fields, specially a kind of quickly to generate flash interface automatically for flash memory master control hardware
The method of signal sequence.
Background technique
Flash memory is a kind of depositing for non-volatile (stored data information being still able to maintain under power blackout situation) of long-life
Reservoir, data deletion is not as unit of single byte but as unit of fixed block, and block size is generally 256KB
To 20MB.Flash memory is the mutation of Electrical Erasable read-only memory, and for flash memory unlike EEPROM, EEPROM can be in byte water
It is deleted and is rewritten on flat rather than entire chip is erasable, and most of chip of flash memory needs block to wipe.Due to its power-off
When remain to save data, flash memory is usually used to preservation setting information, such as in the BIOS of computer (basic program), PDA, number phase
Preservation data etc. in machine.
Existing flash memory master control set design is needed by processor when carrying out issuing reading or write instruction operation to sudden strain of a muscle
The register for depositing main control module is done multiple read-write motion and is controlled with operation code needed for completing flash memory command sequence, this mode
Not only time-consuming there is not efficiency, and for the occupancy of processor resource, very huge can not when needing to do frequent operation to flash memory yet
Effectively promote operating characteristics.
Summary of the invention
The purpose of the present invention is to provide one kind quickly to generate flash interface signal sequence for flash memory master control hardware automatically
Method, to solve the problems mentioned in the above background technology.
To achieve the above object, the invention provides the following technical scheme: a kind of quickly produce automatically for flash memory master control hardware
The method of raw flash interface signal sequence, including main control chip, the interior setting flash memory store controller of the main control chip and flash memory
Physical layer is controlled, is equipped with flash control register and flash interface controller, the flash memory control in the flash memory store controller
Register processed connects flash interface controller, and the flash interface controller connection flash memory controls physical layer, the flash memory control
Physical layer is also connected with external multiple flash memory storage assemblies.
Preferably, multiple flash memory storage assemblies include the first flash memory storage assembly, the second flash memory storage assembly, third flash memory
Storage assembly, N flash memory storage assembly, N are the integer greater than 3.
Preferably, flash memory command sequence generator, the flash memory command sequence are additionally provided in the flash memory store controller
Generator is separately connected flash control register and flash interface controller.
Preferably, comprising the following steps:
A, flash memory command sequence generator controller is configured,；
B, make main control end when needing to issue the arbitrary instructions such as reading or write-in to flash memory component, it is only necessary to be read and write by processor
After a small number of information give register, by calling directly any flash memory command sequence prestored in advance in sequence generator,；
C, quickly errorless that arbitrary instruction sequence is issued to flash memory component.
Compared with prior art, the beneficial effects of the present invention are: the present invention configures flash memory command sequence generator controller,
Make main control end when needing to issue the arbitrary instructions such as reading or write-in to flash memory component, it is only necessary to read and write a small number of letters by processor
It is quickly errorless by calling directly any flash memory command sequence prestored in advance in sequence generator after breath gives register
To flash memory component issue arbitrary instruction sequence, use effectively promoted flash memory main control module task performance.
Detailed description of the invention
Fig. 1 is the flash memory control unit inside master control of the present invention, and flash memory command sequence generator schematic diagram is not configured；
Fig. 2 is the flash memory control unit inside master control of the present invention, configures flash memory command sequence generator schematic diagram；
Fig. 3 is the flash memory control unit inside master control of the present invention, and the situation schematic diagram of flash memory command sequence generator is not configured；
Fig. 4 is the flash memory control unit inside master control of the present invention, configures the situation schematic diagram of flash memory command sequence generator.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 1-4 is please referred to, the present invention provides a kind of technical solution: one kind quickly generating sudden strain of a muscle for flash memory master control hardware automatically
The method for depositing interface signals sequence, including main control chip 1, the interior setting flash memory store controller 2 of the main control chip 1 and flash memory control
Physical layer 3 processed, the flash memory store controller 2 is interior to be equipped with flash control register 4 and flash interface controller 5, the flash memory
It controls register 4 and connects flash interface controller 5, the flash interface controller 5 connects flash memory and controls physical layer 3, the sudden strain of a muscle
It deposits control physical layer 3 and is also connected with external multiple flash memory storage assemblies；Multiple flash memory storage assemblies include the first flash memory storage assembly
6, the second flash memory storage assembly 7, third flash memory storage assembly 8, N flash memory storage assembly, N are the integer greater than 3.
In the present invention, flash memory command sequence generator 9, the flash memory command sequence are additionally provided in flash memory store controller 2
Generator 9 is separately connected flash control register 4 and flash interface controller 5.
In the present invention, it is a kind of for flash memory master control hardware automatically quickly generate flash interface signal sequence method include with
Lower step:
A, flash memory command sequence generator controller is configured,；
B, make main control end when needing to issue the arbitrary instructions such as reading or write-in to flash memory component, it is only necessary to be read and write by processor
After a small number of information give register, by calling directly any flash memory command sequence prestored in advance in sequence generator,；
C, quickly errorless that arbitrary instruction sequence is issued to flash memory component.
In conclusion the present invention configures flash memory command sequence generator controller, needing main control end to flash memory component
When the arbitrary instructions such as sending reading or write-in, it is only necessary to after giving register by a small number of information of processor read-write, by directly tune
It is quickly errorless that arbitrary instruction is issued to flash memory component with any flash memory command sequence prestored in advance in sequence generator
Sequence uses the task performance for effectively promoting flash memory main control module.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (4)
1. a kind of method for quickly generating flash interface signal sequence automatically for flash memory master control hardware, including main control chip (1),
It is characterized by: setting flash memory store controller (2) and flash memory control physical layer (3), the flash memory in the main control chip (1)
Flash control register (4) and flash interface controller (5), the flash control register (4) are equipped in store controller (2)
It connects flash interface controller (5), flash interface controller (5) connection flash memory control physical layer (3), the flash memory control
Physical layer (3) is also connected with external multiple flash memory storage assemblies.
2. the method according to claim 1 for quickly generating flash interface signal sequence automatically for flash memory master control hardware,
It is characterized by: multiple flash memory storage assemblies include the first flash memory storage assembly (6), the second flash memory storage assembly (7), third sudden strain of a muscle
Storage assembly (8), N flash memory storage assembly are deposited, N is the integer greater than 3.
3. the method according to claim 1 for quickly generating flash interface signal sequence automatically for flash memory master control hardware,
It is characterized by: being additionally provided with flash memory command sequence generator (9) in the flash memory store controller (2), the flash memory command sequence
Column generator (9) is separately connected flash control register (4) and flash interface controller (5).
4. the method according to claim 1 for quickly generating flash interface signal sequence automatically for flash memory master control hardware,
It is characterized by comprising following steps:
A, flash memory command sequence generator controller is configured,；
B, make main control end when needing to issue the arbitrary instructions such as reading or write-in to flash memory component, it is only necessary to be read and write by processor
After a small number of information give register, by calling directly any flash memory command sequence prestored in advance in sequence generator,；
C, quickly errorless that arbitrary instruction sequence is issued to flash memory component.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811499865.1A CN109558336A (en) | 2018-12-09 | 2018-12-09 | Quickly generate the method for flash interface signal sequence automatically for flash memory master control hardware |
| PCT/CN2019/078231 WO2020118941A1 (en) | 2018-12-09 | 2019-03-15 | Method used for main flash memory hardware automatically and quickly generating flash memory interface signal sequence |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811499865.1A CN109558336A (en) | 2018-12-09 | 2018-12-09 | Quickly generate the method for flash interface signal sequence automatically for flash memory master control hardware |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109558336A true CN109558336A (en) | 2019-04-02 |
Family
ID=65869482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811499865.1A Withdrawn CN109558336A (en) | 2018-12-09 | 2018-12-09 | Quickly generate the method for flash interface signal sequence automatically for flash memory master control hardware |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109558336A (en) |
| WO (1) | WO2020118941A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110209352A (en) * | 2019-05-14 | 2019-09-06 | 西安艾可萨科技有限公司 | A kind of control method of memory, Memory Controller, electronic equipment and storage medium |
| CN110515559A (en) * | 2019-08-27 | 2019-11-29 | 江苏华存电子科技有限公司 | High-effect instruction sequence controller based on synchronizing channel operational architecture flash memory master control |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103389963B (en) * | 2012-05-09 | 2016-08-31 | 北京兆易创新科技股份有限公司 | A kind of embedded system controller |
| US20130318285A1 (en) * | 2012-05-23 | 2013-11-28 | Violin Memory Inc | Flash memory controller |
| US10209904B2 (en) * | 2013-04-09 | 2019-02-19 | EMC IP Holding Company LLC | Multiprocessor system with independent direct access to bulk solid state memory resources |
| CN108595124A (en) * | 2018-04-27 | 2018-09-28 | 江苏华存电子科技有限公司 | A kind of management method promoting the parallel write-in school energy of more flash memories |
| CN108762974A (en) * | 2018-04-27 | 2018-11-06 | 江苏华存电子科技有限公司 | A kind of blank page checking system for flash memory correlation main control end control device |
-
2018
- 2018-12-09 CN CN201811499865.1A patent/CN109558336A/en not_active Withdrawn
-
2019
- 2019-03-15 WO PCT/CN2019/078231 patent/WO2020118941A1/en active Application Filing
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110209352A (en) * | 2019-05-14 | 2019-09-06 | 西安艾可萨科技有限公司 | A kind of control method of memory, Memory Controller, electronic equipment and storage medium |
| CN110209352B (en) * | 2019-05-14 | 2023-03-14 | 西安艾可萨科技有限公司 | Memory control method, memory controller, electronic device and storage medium |
| CN110515559A (en) * | 2019-08-27 | 2019-11-29 | 江苏华存电子科技有限公司 | High-effect instruction sequence controller based on synchronizing channel operational architecture flash memory master control |
| WO2021035800A1 (en) * | 2019-08-27 | 2021-03-04 | 江苏华存电子科技有限公司 | High-performance instruction sequence control module based on synchronous channel operation architecture flash master control |
| CN110515559B (en) * | 2019-08-27 | 2022-08-30 | 江苏华存电子科技有限公司 | High performance command sequence controller based on synchronous channel operation architecture flash memory master control |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020118941A1 (en) | 2020-06-18 |
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Application publication date: 20190402 |