CN108932961A - It is a kind of to promote reaction rate method using flash memory pin - Google Patents
It is a kind of to promote reaction rate method using flash memory pin Download PDFInfo
- Publication number
- CN108932961A CN108932961A CN201810806777.5A CN201810806777A CN108932961A CN 108932961 A CN108932961 A CN 108932961A CN 201810806777 A CN201810806777 A CN 201810806777A CN 108932961 A CN108932961 A CN 108932961A
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- pin
- chip
- flash memory
- ready
- flash
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- 230000015654 memory Effects 0.000 title claims abstract description 52
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 208000033748 Device issues Diseases 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
Abstract
Promote reaction rate method using flash memory pin the invention discloses a kind of, comprising the following steps: step 1: switching multidiameter option switch to chip enables pin；Step 2: reading, write-in/programming or erasing instruction are issued to flash chip by the flash memory command control device in memory control chip；Step 3: switching multidiameter option switch to ready/busy pin；Step 4: whether inquiry ready/busy pin signal is high level, if, return is completed, switching multidiameter option switch is that chip enables pin, if not, continue to inquire whether ready/busy pin signal is high level, which saves a ready/busy pin using a multidiameter option switch and reach high efficiency, greatly promotes compared with traditional approach reaction rate.
Description
Technical field
The present invention relates to flash disk operation technical fields, specially a kind of to promote reaction rate method using flash memory pin.
Background technique
Flash memory is the memory device of non-deorienting, there is a three-level unit (TLC) of three bits of storage, two bits it is more
Grade unit (MLC) flash memory and single stage unit (SLC) flash memory require to control core through memory regardless of flash memory
Piece controls flash chip, and memory control chip issues flash memory command and (such as reads instruction, write-in/programming instruction and erasing and refer to
Enable) after, flash chip makes corresponding behavior and reads or be written data, and flash memory has formed address latch by more pins and enabled to draw
Foot ALE, instruction latch enabled pin CLE, data transmission pin DQS, read enabled pin RE, enabled pin WE, chip is written
Enabled pin CE, ready/busy pin RB.Flash chip is controlled through these pins,
Since memory control chip can not learn the operation conditions of flash chip, after giving reading or write instruction, storage
Chip can cause it is busy make corresponding movement, need to issue flash chip the instruction of one readings flash state, read correctly
Flash state (success or failure), judge flash memory act success or not.Traditional approach is usually there are two types of mode it has been confirmed that the
It is for second the state through the ready/busy pin on flash chip one is being instructed to read flash memory with flash state.The former
The time is spent, the latter can have more a pin.It has more the area that a pin will lead to chip to become larger, increased production cost.
Traditional approach is after issuing the instruction of flash memory reading state, if flash memory is replied just busy, continues to send and reads shape
State instruction, until completing to read.Since each channel can connect more flash memories, a channel information width is shared, it is frequent to send
Reading state instruction can occupy channel information width, lead to performance degradation, it would therefore be highly desirable to which a kind of improved technology is existing to solve
This problem in the presence of technology.
Summary of the invention
Reaction rate method is promoted using flash memory pin the purpose of the present invention is to provide a kind of, utilizes a multi-path choice
Switch saves a ready/busy pin and reaches high efficiency, greatly promotes compared with traditional approach reaction rate, above-mentioned to solve
The problem of being proposed in background technique.
To achieve the above object, the invention provides the following technical scheme: a kind of promote reaction rate side using flash memory pin
Method, comprising the following steps:
Step 1: switching multidiameter option switch to chip enables pin；
Step 2: by memory control chip in flash memory command control device to flash chip issue read, write-in/programming or
Erasing instruction；
Step 3: switching multidiameter option switch to ready/busy pin；
Step 4: whether inquiry ready/busy pin signal is high level, if so, return is completed, switching multidiameter option switch is
Chip enables pin, if it is not, continuing to inquire whether ready/busy pin signal is high level.
Preferably, memory control chip passes through the enabled pin ALE of address latch, the enabled pin of instruction latch in step 1
CLE, data transmission pin DQS, the enabled pin RE of reading, the enabled pin WE of write-in, chip enable pin CE, ready/busy pin
RB controls flash chip.
Preferably, a flash memory command control device is equipped in memory control chip in step 2 and pass through flash memory command
Control device issues instruction control flash chip.
Preferably, it is additionally provided with a multidiameter option switch in memory control chip in step 2, multidiameter option switch is
The device of multiple one output of input.
Compared with prior art, the beneficial effects of the present invention are:
A ready/busy pin is saved using a multidiameter option switch and reaches high efficiency, compared with traditional approach reaction rate
It greatly promotes.
Detailed description of the invention
Fig. 1 is the flow diagram of the method for the present invention.
Fig. 2 be memory control chip structure and with flash memory attachment structure schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, the present invention provides a kind of technical solution: a kind of to promote reaction rate method, packet using flash memory pin
Include following steps:
Step 1: switching multidiameter option switch to chip enables pin；
Step 2: by memory control chip in flash memory command control device to flash chip issue read, write-in/programming or
Erasing instruction；
Step 3: switching multidiameter option switch to ready/busy pin；
Step 4: whether inquiry ready/busy pin signal is high level, if so, return is completed, switching multidiameter option switch is
Chip enables pin, if it is not, continuing to inquire whether ready/busy pin signal is high level.
As shown in Fig. 2, memory control chip enables pin ALE by address latch, enabled pin CLE is latched in instruction,
Data transmit pin DQS, the enabled pin RE of reading, the enabled pin WE of write-in, chip and enable pin CE, ready/busy pin RB and control
Flash chip processed, memory, which controls in chip, a flash memory command control device, can issue instruction control through this device
Flash chip processed, such as read, be written, erasing with reading state instruction, more pins are controlled, such as issue flash memory reading order
When, instruction can be made to latch enabled pin and maintain high level, address latch enables pin and maintains low level, and enabled pin is written
For rising edge, flash memory can receive flash memory and read instruction, have a multidiameter option switch, multi-path choice in memory control chip
Switch is multiple inputs, and the device of an output selects switch to switch to signal appropriate, blocks non-selected signal, such as
One four tunnels selection switch, there are four input signal, an output signals, it is assumed that the signal for selection signal three selects multichannel
It selects switching device and is cut into signal three, three signals of signal is only allowed to be transferred to delivery outlet, disabling signal one, signal two and signal four
Signal, chip enables pin and ready/busy pin and connects on this multidiameter option switch simultaneously, through this multi-path choice
Switching device, switching to be used is that chip enables pin or ready/busy pin.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (4)
1. a kind of promote reaction rate method using flash memory pin, it is characterised in that: the following steps are included:
Step 1: switching multidiameter option switch to chip enables pin；
Step 2: by memory control chip in flash memory command control device to flash chip issue read, write-in/programming or
Erasing instruction；
Step 3: switching multidiameter option switch to ready/busy pin；
Step 4: whether inquiry ready/busy pin signal is high level, if so, return is completed, switching multidiameter option switch is
Chip enables pin, if it is not, continuing to inquire whether ready/busy pin signal is high level.
2. a kind of utilization flash memory pin according to claim 1 promotes reaction rate method, it is characterised in that: the step
Memory control chip enables pin ALE, the enabled pin CLE of instruction latch, data by address latch and transmits pin in one
DQS, the enabled pin RE of reading, enabled pin CE, ready/busy pin RB the control flash chip of enabled pin WE, chip is written.
3. a kind of utilization flash memory pin according to claim 1 promotes reaction rate method, it is characterised in that: the step
A flash memory command control device is equipped in memory control chip in two and instruction control is issued by flash memory command control device
Flash chip processed.
4. a kind of utilization flash memory pin according to claim 1 promotes reaction rate method, it is characterised in that: the step
A multidiameter option switch is additionally provided in two in memory control chip, the multidiameter option switch is one output of multiple inputs
Device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810806777.5A CN108932961A (en) | 2018-07-20 | 2018-07-20 | It is a kind of to promote reaction rate method using flash memory pin |
| PCT/CN2018/105895 WO2020015136A1 (en) | 2018-07-20 | 2018-09-15 | Method for increasing reaction rate employing flash memory pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810806777.5A CN108932961A (en) | 2018-07-20 | 2018-07-20 | It is a kind of to promote reaction rate method using flash memory pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108932961A true CN108932961A (en) | 2018-12-04 |
Family
ID=64444275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810806777.5A Pending CN108932961A (en) | 2018-07-20 | 2018-07-20 | It is a kind of to promote reaction rate method using flash memory pin |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108932961A (en) |
| WO (1) | WO2020015136A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078261A (en) * | 2019-11-13 | 2020-04-28 | 汉纳森（厦门）数据股份有限公司 | Flash memory upgrading device and vehicle |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930798A (en) * | 2009-06-25 | 2010-12-29 | 联发科技股份有限公司 | The method of flash memory device, storage arrangement and control flash memory device |
| CN104681072A (en) * | 2006-12-29 | 2015-06-03 | 三星电子株式会社 | NAND flash memory having C/A pin and flash memory system including the same |
| US20170212849A1 (en) * | 2013-12-31 | 2017-07-27 | Sandisk Technologies Llc | Pulse mechanism for memory circuit interruption |
| CN107767913A (en) * | 2016-08-16 | 2018-03-06 | 三星电子株式会社 | Export the device of the internal state of storage device and use its storage system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7428603B2 (en) * | 2005-06-30 | 2008-09-23 | Sigmatel, Inc. | System and method for communicating with memory devices via plurality of state machines and a DMA controller |
| CN101539895B (en) * | 2009-05-07 | 2011-11-30 | 成都市华为赛门铁克科技有限公司 | Method, device and system for inquiring state based on Flash |
| CN102609242B (en) * | 2011-01-24 | 2015-09-30 | 晨星软件研发(深圳)有限公司 | Electronic installation and internal memory control method thereof and related computer readable get Storage Media |
| CN102279823B (en) * | 2011-06-13 | 2013-09-18 | 杭州华三通信技术有限公司 | Device and method for detecting status of Nand Flash |
| CN206331414U (en) * | 2016-06-29 | 2017-07-14 | 湖南国科微电子股份有限公司 | A kind of solid state hard disc |
-
2018
- 2018-07-20 CN CN201810806777.5A patent/CN108932961A/en active Pending
- 2018-09-15 WO PCT/CN2018/105895 patent/WO2020015136A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681072A (en) * | 2006-12-29 | 2015-06-03 | 三星电子株式会社 | NAND flash memory having C/A pin and flash memory system including the same |
| CN101930798A (en) * | 2009-06-25 | 2010-12-29 | 联发科技股份有限公司 | The method of flash memory device, storage arrangement and control flash memory device |
| US20170212849A1 (en) * | 2013-12-31 | 2017-07-27 | Sandisk Technologies Llc | Pulse mechanism for memory circuit interruption |
| CN107767913A (en) * | 2016-08-16 | 2018-03-06 | 三星电子株式会社 | Export the device of the internal state of storage device and use its storage system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078261A (en) * | 2019-11-13 | 2020-04-28 | 汉纳森（厦门）数据股份有限公司 | Flash memory upgrading device and vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020015136A1 (en) | 2020-01-23 |
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