WO2020002560A3 - Vorrichtung mit elektrischer kontaktstruktur - Google Patents
Vorrichtung mit elektrischer kontaktstruktur Download PDFInfo
- Publication number
- WO2020002560A3 WO2020002560A3 PCT/EP2019/067258 EP2019067258W WO2020002560A3 WO 2020002560 A3 WO2020002560 A3 WO 2020002560A3 EP 2019067258 W EP2019067258 W EP 2019067258W WO 2020002560 A3 WO2020002560 A3 WO 2020002560A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrically conductive
- contact structure
- contact holes
- electrical contact
- conductive material
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/42—Printed circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
- B23K26/382—Removing material by boring or cutting by boring
- B23K26/386—Removing material by boring or cutting by boring of blind holes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Multi-Conductor Connections (AREA)
Abstract
Eine Vorrichtung weist eine Schichtanordnung und eine Kontaktstruktur auf. Die Schichtanordnung weist eine elektrisch leitende Schicht und eine Vielzahl von Kontaktlöchern auf. Die Kontaktstruktur weist ein elektrisch leitendes Material auf, wobei die Kontaktlöcher mindestens teilweise mit dem elektrisch leitenden Material gefüllt sind, um die elektrisch leitende Schicht elektrisch zu kontaktieren und wobei das elektrisch leitende Material in einem der Kontaktlöcher mit dem elektrisch leitenden Material in den übrigen Kontaktlöchern der Vielzahl von Kontaktlöchern elektrisch leitend verbunden ist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112019003306.9T DE112019003306A5 (de) | 2018-06-29 | 2019-06-27 | Vorrichtung mit elektrischer kontaktstruktur |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE202018103749.8 | 2018-06-29 | ||
DE202018103749.8U DE202018103749U1 (de) | 2018-06-29 | 2018-06-29 | Vorrichtung mit elektrischer Kontaktstruktur |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2020002560A2 WO2020002560A2 (de) | 2020-01-02 |
WO2020002560A3 true WO2020002560A3 (de) | 2020-02-20 |
Family
ID=62983027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2019/067258 WO2020002560A2 (de) | 2018-06-29 | 2019-06-27 | Vorrichtung mit elektrischer kontaktstruktur |
Country Status (2)
Country | Link |
---|---|
DE (2) | DE202018103749U1 (de) |
WO (1) | WO2020002560A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220369455A1 (en) * | 2019-07-22 | 2022-11-17 | Technische Hochschule Aschaffenburg | Electrical connection pad with enhanced solderability and corresponding method for laser treating an electrical connection pad |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005062932A1 (de) * | 2005-12-29 | 2007-07-12 | Infineon Technologies Ag | Chip-Träger mit reduzierter Störsignalempfindlichkeit |
DE102006049562A1 (de) * | 2006-10-20 | 2008-04-24 | Qimonda Ag | Substrat mit Durchführung und Verfahren zur Herstellung desselben |
US20180074118A1 (en) * | 2016-09-15 | 2018-03-15 | Texas Instruments Incorporated | Heatable interposer for temperature-controlled testing of semiconductor devices |
-
2018
- 2018-06-29 DE DE202018103749.8U patent/DE202018103749U1/de active Active
-
2019
- 2019-06-27 WO PCT/EP2019/067258 patent/WO2020002560A2/de active Application Filing
- 2019-06-27 DE DE112019003306.9T patent/DE112019003306A5/de active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005062932A1 (de) * | 2005-12-29 | 2007-07-12 | Infineon Technologies Ag | Chip-Träger mit reduzierter Störsignalempfindlichkeit |
DE102006049562A1 (de) * | 2006-10-20 | 2008-04-24 | Qimonda Ag | Substrat mit Durchführung und Verfahren zur Herstellung desselben |
US20180074118A1 (en) * | 2016-09-15 | 2018-03-15 | Texas Instruments Incorporated | Heatable interposer for temperature-controlled testing of semiconductor devices |
Non-Patent Citations (1)
Title |
---|
TOBIAS DYCK: "Functional Surfaces by Laser Interference", LASER TECHNIK JOURNAL, 1 April 2017 (2017-04-01), pages 16 - 19, XP055653050, Retrieved from the Internet <URL:https://onlinelibrary.wiley.com/doi/pdf/10.1002/latj.201700007> [retrieved on 20191216], DOI: 10.1002/latj.201700007 * |
Also Published As
Publication number | Publication date |
---|---|
DE112019003306A5 (de) | 2021-03-18 |
DE202018103749U1 (de) | 2018-07-06 |
WO2020002560A2 (de) | 2020-01-02 |
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