WO2020000475A1 - 单端转差分放大器和射频接收机 - Google Patents

单端转差分放大器和射频接收机 Download PDF

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Publication number
WO2020000475A1
WO2020000475A1 PCT/CN2018/093885 CN2018093885W WO2020000475A1 WO 2020000475 A1 WO2020000475 A1 WO 2020000475A1 CN 2018093885 W CN2018093885 W CN 2018093885W WO 2020000475 A1 WO2020000475 A1 WO 2020000475A1
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Prior art keywords
inverting amplifier
coupled
amplifier
drain
ended
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PCT/CN2018/093885
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English (en)
French (fr)
Inventor
应文荣
麦凯恩·特瑞
罗克内尔·威廉姆
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/093885 priority Critical patent/WO2020000475A1/zh
Priority to EP18924683.8A priority patent/EP3790189A4/en
Priority to CN201880091785.4A priority patent/CN111903054B/zh
Publication of WO2020000475A1 publication Critical patent/WO2020000475A1/zh
Priority to US17/100,502 priority patent/US11606069B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H03F3/265—Push-pull amplifiers; Phase-splitters therefor with field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a single-ended to differential amplifier and a radio frequency receiver.
  • a Low Noise Amplifier In the front-end design of the RF receiver, a Low Noise Amplifier (LNA) is an essential component, which determines the receiving sensitivity of the entire receiver.
  • LNA Low Noise Amplifier
  • the low-noise amplifier often use a passive inductor Balun to implement the functions of single-ended input and differential output.
  • the low-noise amplifier includes: a resistor, two metal oxide semiconductor (MOS) tubes, a passive inductor balun, and a capacitor. After the radio frequency signal is input to the low noise amplifier, it is input to the passive inductor balun through the two MOS tubes, and then the passive inductor balun and the capacitor are converted into a differential signal for output.
  • MOS metal oxide semiconductor
  • the area of the low-noise amplifier is large.
  • the low-noise amplifier uses inductors and capacitors as loads, the low-noise amplifier has a narrow-band structure, that is, the frequency range of the low-noise amplifier is small. At this time, multiple low-noise amplifiers need to be used simultaneously to achieve wide-band coverage. , which further leads to an increase in the area of the RF receiver.
  • This application provides a single-ended-to-differential amplifier and a radio frequency receiver, which can implement single-ended-to-differential based on signal amplification without significantly increasing the area of the single-ended-to-differential amplifier.
  • the technical solution is as follows:
  • a single-ended to differential amplifier includes: a first inverting amplifier, a second inverting amplifier, and a third inverting amplifier; and an input of the first inverting amplifier.
  • the input of the second inverting amplifier are both coupled to the input of the single-ended to differential amplifier, and the output of the first inverting amplifier is coupled to the input of the third inverting amplifier, so
  • the output of the second inverting amplifier is coupled to the first output of the single-ended to differential amplifier, and the output of the third inverting amplifier is coupled to the second output of the single-ended to differential amplifier;
  • An impedance element is coupled between an input terminal of the first inverting amplifier and an output terminal of the first inverting amplifier.
  • the single-ended-to-differential amplifier has a small area and a large frequency range, and can achieve broadband matching. In this way, only a small number of the single-ended to differential amplifiers can cover a wide frequency range, so that the area of the single-ended to differential amplifiers can be reduced.
  • the single-ended-to-differential amplifier when the single-ended-to-differential amplifier is in operation, after a radio frequency signal is input to the input end of the single-ended-to-differential amplifier, it is input to a first inverting amplifier and a third inverting amplifier. After the radio frequency signal is input to the first inverting amplifier, the first inverting amplifier outputs a first signal having a phase opposite to that of the radio frequency signal. After the first signal is input to the third inverting amplifier, the third inverting amplifier outputs the first signal. The opposite phase of the second signal. After the radio frequency signal is input to the second inverting amplifier, the second inverting amplifier outputs a third signal having a phase opposite to that of the radio frequency signal.
  • the second output terminal of the single-ended-to-differential amplifier outputs a second signal
  • the first output terminal of the single-ended-to-differential amplifier outputs a third signal
  • the phase of the second signal is opposite to that of the third signal, thereby realizing In order to convert the radio frequency signal into a differential signal formed by the second signal and the third signal.
  • the first inverting amplifier, the second inverting amplifier, and the third inverting amplifier in the single-ended-to-differential amplifier can be amplifiers implemented in MOS technology, there is no need for an inductor, so the area of the single-ended-to-differential amplifier is It is small and has a large frequency range, which can achieve broadband matching. In this way, using only a small number of the single-ended to differential amplifiers can cover a wide frequency range, so that the number of RF ports can be further reduced, and the area of the single-ended to differential amplifiers is further reduced.
  • the first inverting amplifier may be a unity gain inverting amplifier, and the gain of the second inverting amplifier may be the same as that of the third inverting amplifier.
  • the first inverting amplifier may be a non-unity gain inverting amplifier, and the product of the gain of the first inverting amplifier and the gain of the third inverting amplifier may be an inverse number of the gain of the second inverting amplifier.
  • the first inverting amplifier includes: a first P-type metal-oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS) tube and a first N-type metal-oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS)
  • PMOS P-type metal-oxide semiconductor
  • NMOS N-Metal-Oxide-Semiconductor
  • a source of the first PMOS tube is coupled to a first power source
  • a drain of the first PMOS tube is coupled to a drain of the first NMOS tube, and a source of the first NMOS tube is grounded
  • the drain of the first PMOS transistor is coupled to the output terminal of the first inverting amplifier
  • the drain of the first NMOS transistor is coupled to the output terminal of the first inverting amplifier.
  • the drain of the first PMOS tube and the drain of the first NMOS tube are both coupled to the input terminal of the first inverting amplifier through the impedance element; the gate of the first PMOS tube and the first The gates of the NMOS transistors are all coupled to the input terminal of the first inverting amplifier.
  • the first PMOS transistor and the first NMOS transistor are formed to The feedback path at the input of the first inverting amplifier.
  • the inverse of the sum of the transconductance value of the first PMOS transistor and the transconductance value of the first NMOS transistor is the input impedance of the first inverting amplifier.
  • the noise of the first PMOS transistor and the noise of the first NMOS transistor are output to the second output terminal of the single-ended-to-differential amplifier through a third inverting amplifier, and to the single output terminal through the feedback path and the second inverting amplifier.
  • the first output terminal of the end-to-differential amplifier At this time, the noise contributed by the first PMOS tube and the first NMOS tube at the second output end of the single-ended differential amplifier and the first output of the single-ended differential amplifier.
  • the noise is equal in magnitude and phase, so they can cancel each other, so that the first PMOS tube and the first NMOS tube will not contribute noise to the differential signal output by the single-ended to differential amplifier, which can greatly improve the single-ended conversion. Noise performance of a differential amplifier.
  • the impedance element may include at least one of a first resistor and a sixth capacitor. That is, at least one of the first resistor and the sixth capacitor may be connected in series with the drain of the first PMOS transistor and the drain of the first NMOS transistor and the first inverting amplifier. Between the inputs.
  • the first inverting amplifier may further include: a second PMOS tube and a second NMOS tube; a drain of the first PMOS tube is coupled to a source of the second PMOS tube, and the second PMOS The drain of the tube is coupled to the drain of the second NMOS tube, the source of the second NMOS tube is coupled to the drain of the first NMOS tube; the gate of the second PMOS tube is coupled to the first The bias voltage, the gate of the second NMOS transistor is coupled to the second bias voltage; the drain of the second PMOS transistor and the drain of the second NMOS transistor both pass through the impedance element and the first An input terminal of an inverting amplifier is coupled; a drain of the first PMOS tube is coupled to a third output terminal of the output terminals of the first inverting amplifier, and a drain of the first NMOS tube is coupled to all A fourth output terminal of the output terminals of the first inverting amplifier is coupled.
  • the signal swing of the coupling point of the impedance element with the drain of the second PMOS transistor and the drain of the second NMOS transistor depends on the impedance of the impedance element, so By designing the impedance of the impedance element, the signal swing of the feedback point can be adjusted, and the linearity performance of the single-ended to differential amplifier can be improved.
  • the path formed by the first PMOS tube, the second PMOS tube, the first NMOS tube, and the second NMOS tube is in a high-impedance state, it is difficult for the noise of the impedance element to be output to the second output terminal of the single-ended to differential amplifier. That is, the impedance element does not introduce significant noise.
  • the first inverting amplifier further includes: a first capacitor coupled between the third output terminal and the fourth output terminal.
  • the load of the first PMOS tube and the load of the first NMOS tube are both a parallel structure of the second PMOS tube and the second NMOS tube. Therefore, even when the signal swing is large, the second At least one of the PMOS tube and the second NMOS tube is turned on to ensure the normal output of the first inverting amplifier. At this time, the load of the first PMOS tube and the load of the first NMOS tube are more linear, which can effectively improve the unit. Linearity performance of an end-to-differential amplifier.
  • the first PMOS tube and the second PMOS tube and the first NMOS tube and the second NMOS tube have complementary input structures. Therefore, even when the signal swing is large, the The output path can always be turned on, thereby ensuring the performance of the 1-dB compression point of the single-ended to differential amplifier.
  • the first inverting amplifier further includes: a second capacitor; at least one of a gate of the first PMOS transistor and a gate of the first NMOS transistor is connected to the first inverting capacitor through the second capacitor.
  • the input of the phase amplifier is coupled.
  • the second capacitor has a DC blocking effect, which can prevent the DC signal at the input end of the first inverting amplifier from affecting the DC operating point of at least one of the first PMOS tube and the first NMOS tube.
  • the third inverting amplifier includes: a third PMOS tube and a third NMOS tube; a source of the third PMOS tube is coupled to a second power source, and a drain of the third PMOS tube is connected to the third The drain of the NMOS tube is coupled, and the source of the third NMOS tube is grounded; both the drain of the third PMOS tube and the drain of the third NMOS tube are coupled to the output of the third inverting amplifier A gate of the third PMOS transistor is coupled to the third output terminal, and a gate of the third NMOS transistor is coupled to the fourth output terminal.
  • the third PMOS tube and the third NMOS tube constitute an inverter structure, so that the output signal of the third inverting amplifier can have a large swing space, which can effectively improve the single-ended to differential Dynamic range of the amplifier.
  • the third inverting amplifier further includes: a third capacitor; the drain of the third PMOS transistor and the drain of the third NMOS transistor are both inverted with the third through the third capacitor.
  • the output of the amplifier is coupled.
  • the third capacitor has a DC blocking effect, which can prevent the DC signal in the single-ended-to-differential amplifier from affecting the DC operating point of the next-stage circuit, thereby ensuring the normal operation of the next-stage circuit.
  • the third inverting amplifier further includes: a fourth capacitor and a fifth capacitor; a gate of the third PMOS transistor is coupled to the third output terminal through the fourth capacitor, and the third NMOS The gate of the tube is coupled to the fourth output terminal through the fifth capacitor.
  • the fourth capacitor has a DC blocking effect, which can prevent the DC signal at the third output terminal of the first inverting amplifier from affecting the DC operating point of the third PMOS tube
  • the fifth capacitor also has a DC blocking effect, which can avoid the first inverting amplifier.
  • the DC signals at the four output terminals affect the DC operating point of the third NMOS tube.
  • the second inverting amplifier includes: a fourth PMOS tube and a fourth NMOS tube; a source of the fourth PMOS tube is coupled to a second power source, and a drain of the fourth PMOS tube is connected to the fourth The drain of the NMOS transistor is coupled, and the source of the fourth NMOS transistor is grounded; the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both coupled to the output of the second inverting amplifier A gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are both coupled to an input terminal of the second inverting amplifier.
  • the fourth PMOS transistor and the fourth NMOS transistor constitute an inverter structure, so that the output signal of the second inverting amplifier can have a large swing space, which can effectively improve the single-ended to differential Dynamic range of the amplifier.
  • the second inverting amplifier further includes: a seventh capacitor; the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both inverted with the second through the seventh capacitor.
  • the output of the amplifier is coupled.
  • the seventh capacitor has a DC blocking effect, which can prevent the DC signal in the single-ended-to-differential amplifier from affecting the DC operating point of the next-stage circuit, thereby ensuring the normal operation of the next-stage circuit.
  • the second inverting amplifier further includes: an eighth capacitor; the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are both inverted with the second through the eighth capacitor.
  • the input of the amplifier is coupled.
  • the eighth capacitor has a DC blocking effect, which can prevent the direct current signal at the input end of the second inverting amplifier from affecting the direct current operating point of the fourth PMOS transistor.
  • a radio frequency receiver in a second aspect, includes the single-ended to differential amplifier described in the first aspect.
  • the single-ended-to-differential amplifier may be a single-ended-to-differential low-noise amplifier.
  • the radio frequency receiver may further include a mixer, and the mixer may be connected to the first of the low-noise amplifier.
  • the output terminal is coupled to the second output terminal.
  • a radio frequency chip including the single-ended to differential amplifier according to the first aspect or the radio frequency receiver according to the second aspect.
  • a communication device including the radio frequency chip described in the third aspect.
  • the communication device is a wireless terminal.
  • FIG. 1 is a schematic structural diagram of a low-noise amplifier provided in the related art
  • FIG. 2 is a schematic structural diagram of a radio frequency receiver according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a first low-noise amplifier according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a second low-noise amplifier according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a third low-noise amplifier according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a fourth low-noise amplifier according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a fifth low-noise amplifier according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a sixth low-noise amplifier according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a seventh low-noise amplifier according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an eighth low-noise amplifier according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a ninth low-noise amplifier according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a tenth low-noise amplifier according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of an eleventh low-noise amplifier according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a twelfth low-noise amplifier provided by an embodiment of the present application.
  • La input end of the low noise amplifier
  • Lb first output end of the low noise amplifier
  • Lc second output end of the low noise amplifier
  • first inverting amplifier 1a: input of first inverting amplifier, 1b: output of first inverting amplifier, 1c: third output of first inverting amplifier, 1d: first inverting amplifier Fourth output terminal, 2: second inverting amplifier, 2a: input of second inverting amplifier, 2b: output of second inverting amplifier, 3: third inverting amplifier, 3a: third inverting Input terminal of the amplifier, 3b: output terminal of the third inverting amplifier;
  • Z impedance element
  • R1 first resistor
  • R2 second resistor
  • C1 first capacitor
  • C2 second capacitor
  • C3 third capacitor
  • C4 fourth capacitor
  • C5 fifth capacitor
  • C6 first Six capacitors
  • C7 seventh capacitor
  • C8 eighth capacitor.
  • the single-ended-to-differential amplifier provided in the embodiment of the present application is applied to a radio frequency receiver.
  • the following description uses a single-ended-to-differential low-noise amplifier as an example.
  • FIG. 2 is a schematic structural diagram of a radio frequency receiver according to an embodiment of the present application.
  • the radio frequency receiver may be located in a radio frequency chip.
  • the radio frequency port of the radio frequency receiver is the radio frequency input port of the radio frequency chip and is used to input radio frequency signals.
  • the radio frequency receiver may include at least one radio frequency path, each radio frequency path is coupled with one radio frequency port, and each radio frequency path may include a low noise amplifier (LNA), a mixer (MIXER), and a transimpedance Amplifiers (trans-impedance amplifiers, TIAs), low-noise amplifiers, mixers, and transimpedance amplifiers are connected in series, and the output signals are processed by a back-end device.
  • LNA low noise amplifier
  • MIXER mixer
  • TIAs transimpedance Amplifiers
  • the back-end devices may include analog-to-digital converters (ADCs). Wait.
  • the radio frequency chip is located in a communication device, and the communication device may be a base station, a relay station, a repeater, a repeater station, a radio remote head (RRH), a wireless terminal, user equipment, a personal computer, a laptop computer, Various wireless communication devices such as a tablet computer or an Internet of Things device are not limited in this embodiment.
  • the above-mentioned radio frequency chip is an integrated semiconductor chip and can be generated by a semiconductor manufacturing process.
  • the radio frequency receiver can be included in a radio frequency chip, or it can be used as part of a discrete system, that is, the multiple components present in the system are not integrated circuits in an integrated chip, but discrete individual component. Therefore, each part of the radio frequency receiver can also be composed of discrete components.
  • the following embodiments do not limit whether a specific circuit structure adopts an integrated circuit process or forms part of an integrated circuit of a chip.
  • the low-noise amplifier can be any of the low-noise amplifiers shown in Figures 3 to 14 below.
  • the input end La of the low-noise amplifier can be coupled to the RF port of the RF receiver.
  • the second output terminal Lc of the low-noise amplifier can be coupled with the mixer, the low-noise amplifier can convert the radio frequency signal input through the radio frequency port into a differential signal, and input the differential signal to the mixer, the mixer
  • the differential signal can be mixed with the local oscillator signal (LO) to obtain an intermediate frequency signal, and the intermediate frequency signal is input to a transimpedance amplifier.
  • the transimpedance amplifier can convert the intermediate frequency signal into a voltage signal and output the voltage signal to Back-end device for processing.
  • the radio frequency signal received and processed by the radio frequency receiver may be a service data signal, a radio control signal, a radio scheduling signal, a pilot signal, a radio broadcast signal, a physical layer or higher-layer communication protocol signal, or one of them Or a combination of multiple.
  • the radio frequency receiver and the communication device in which the radio frequency receiver is located can implement communication operations with another communication device that transmits the radio frequency signal.
  • FIG. 3 is a schematic structural diagram of a low-noise amplifier according to an embodiment of the present application.
  • the low-noise amplifier may include a first inverting amplifier 1, a second inverting amplifier 2, and a third inverting amplifier 3.
  • the input terminal 1a of the first inverting amplifier 1 and the input terminal 2a of the second inverting amplifier 2 are coupled to the input terminal La of the low-noise amplifier, and the output terminal 1b of the first inverting amplifier 1 and the third inverting amplifier 3
  • the input terminal 3a of the second inverting amplifier 2 is coupled to the first output terminal Lb of the low noise amplifier
  • the output terminal 3b of the third inverting amplifier 3 is coupled to the second output terminal Lc of the low noise amplifier.
  • an impedance element Z is coupled between the input terminal 1a of the first inverting amplifier 1 and the output terminal 1b of the first inverting amplifier 1.
  • the first inverting amplifier 1, the second inverting amplifier 2, and the third inverting amplifier 3 can all implement the inverting function, that is, the signal output from the output terminal 1b of the first inverting amplifier 1
  • the phase is opposite to the phase of the signal input from the input terminal 1a of the first inverting amplifier 1
  • the phase of the signal output from the output terminal 2b of the second inverting amplifier 2 is the same as that of the signal input from the input 2a of the second inverting amplifier 2.
  • the phase of the signal output from the output terminal 3b of the third inverting amplifier 3 is opposite to that of the signal input from the input terminal 3a of the third inverting amplifier 3.
  • the first inverting amplifier 1 can be a unity-gain inverting amplifier, and the gain of the second inverting amplifier 2 can be the same as that of the third inverting amplifier 3.
  • the output impedance of the second inverting amplifier 2 and the output impedance of the third inverting amplifier 3 Equal, of course, the first inverting amplifier 1 can also be a non-unitary gain inverting amplifier.
  • the product of the gain of the first inverting amplifier 1 and the gain of the third inverting amplifier 3 can be the second inverting amplifier.
  • the gain of each inverting amplifier in this embodiment can be set according to actual application requirements, so that the gain of the low-noise amplifier can be set to a required value, that is, the value is set by the first
  • the gains of the inverting amplifier 1, the second inverting amplifier 2, and the third inverting amplifier 3 are jointly determined.
  • the gain of the low-noise amplifier can be set to be adjustable, that is, to adjust between multiple different values. At this time, the gain of each corresponding inverting amplifier is adjustable.
  • the product of the gain of the first inverting amplifier 1 and the gain of the third inverting amplifier 3 is approximately equal to the inverse of the gain of the second inverting amplifier 2, a differential output can be achieved. Therefore, those skilled in the art can set the gains of the three inverting amplifiers according to the actual application requirements during the design of the circuit, and only need to ensure the gains of the first inverting amplifier 1 and the third inverting amplifier 3 during the setting process.
  • the product of the gain is approximately equal to the inverse number of the gain of the second inverting amplifier 2, which ensures that the two signals of the differential output of the entire low-noise amplifier are the same amplitude of the input signal but have opposite phases.
  • the low-noise amplifier when the low-noise amplifier is in operation, after the radio frequency signal is input to the input terminal La of the low-noise amplifier, it is input to the first inverting amplifier 1 and the third inverting amplifier 3.
  • the first inverting amplifier 1 After the radio frequency signal is input to the first inverting amplifier 1, the first inverting amplifier 1 outputs a first signal having a phase opposite to that of the radio frequency signal.
  • the third inverting amplifier 3 outputs A second signal having a phase opposite to that of the first signal.
  • the radio frequency signal is input to the second inverting amplifier 2
  • the second inverting amplifier 2 outputs a third signal having a phase opposite to that of the radio frequency signal.
  • the second output terminal Lc of the low-noise amplifier outputs a second signal
  • the first output terminal Lb of the low-noise amplifier outputs a third signal.
  • the phase of the second signal is opposite to that of the third signal.
  • the radio frequency signal is converted into a differential signal formed by the second signal and the third signal.
  • the low-noise amplifier uses a single-ended-to-differential circuit structure.
  • the input end La of the low-noise amplifier is coupled to a radio frequency port. After a radio frequency signal is input to the input end La of the low noise amplifier through the radio frequency port, the low The first output terminal Lb and the second output terminal Lc of the noise amplifier can output differential signals, thereby realizing the functions of single-ended input and differential output.
  • embodiments of the present application are used.
  • the low-noise amplifier in can greatly reduce the number of RF ports.
  • the first inverting amplifier 1, the second inverting amplifier 2, and the third inverting amplifier 3 in the low noise amplifier may be amplifiers implemented by MOS technology, there is no need for an inductor, so The area can be made smaller, and the frequency range is larger, enabling broadband matching. In this way, only a small number of the low noise amplifiers can be used to cover a wide frequency range, so that the number of radio frequency ports can be further reduced, thereby reducing the area of the radio frequency receiver where the low noise amplifiers are located. For example, using this low-noise amplifier, no other low-noise amplifier is needed below 3 GHz (GHz), and only a same low-noise amplifier is needed at 3GHz-6GHz. At this time, a single low-noise amplifier can achieve a wide frequency band. cover.
  • GHz 3 GHz
  • the first inverting amplifier 1 includes: a first PMOS transistor Q11 and a first NMOS transistor Q12; a source s11 of the first PMOS transistor Q11 is coupled to a first power source vdd1, and a drain d11 of the first PMOS transistor Q11 and The drain d12 of the first NMOS transistor Q12 is coupled, and the source s12 of the first NMOS transistor Q12 is grounded.
  • the drain d11 of the first PMOS transistor Q11 is coupled to the output terminal 1b of the first inverting amplifier 1.
  • the drain d12 is coupled to the output terminal 1b of the first inverting amplifier 1.
  • the drain d11 of the first PMOS transistor Q11 and the drain d12 of the first NMOS transistor Q12 are both connected to the input terminal of the first inverting amplifier 1 through the impedance element Z. 1a coupling; the gate g11 of the first PMOS transistor Q11 and the gate g12 of the first NMOS transistor Q12 are both coupled to the input terminal 1a of the first inverting amplifier 1.
  • drain d11 of the first PMOS transistor Q11 and the drain d12 of the first NMOS transistor Q12 are both coupled to the input terminal 1a of the first inverting amplifier 1 through the impedance element Z to form the first PMOS transistor Q11. And the feedback path from the first NMOS transistor Q12 to the input terminal 1a of the first inverting amplifier 1.
  • the inverse of the sum of the transconductance value of the first PMOS transistor Q11 and the transconductance value of the first NMOS transistor Q12 is Is the input impedance of the first inverting amplifier 1, so by designing the transconductance value of the first PMOS transistor Q11 and the transconductance value of the first NMOS transistor Q12, the impedance matching of the input terminal La of the low noise amplifier can be achieved.
  • the sum of the transconductance value of the first PMOS transistor Q11 and the transconductance value of the first NMOS transistor Q12 can be designed to be 0.02 Siemens (S).
  • the noise of the first PMOS transistor Q11 and the noise of the first NMOS transistor Q12 are output to the second output terminal Lc of the low-noise amplifier through the third inverting amplifier 3, and output through the feedback path and the second inverting amplifier 2 described above.
  • the noise contributed by the first PMOS tube Q11 and the first NMOS tube Q12 at the second output terminal Lc of the low noise amplifier and at the first output terminal of the low noise amplifier is equal in magnitude and phase, so they can cancel each other out.
  • the noise cancellation mechanism introduced in the embodiment of the present application prevents the first PMOS transistor Q11 and the first NMOS transistor Q12 from contributing noise to the differential signal output by the low noise amplifier, thereby greatly improving the noise of the low noise amplifier. performance.
  • the impedance element Z may include at least one of a first resistor R1 and a sixth capacitor C6.
  • the drain d11 of the first PMOS transistor Q11 and the drain d12 of the first NMOS transistor Q12 are both coupled to the input terminal 1a of the first inverting amplifier 1 through at least one of the first resistor R1 and the sixth capacitor C6. That is, at least one of the first resistor R1 and the sixth capacitor C6 may be connected in series with the drain d11 of the first PMOS transistor Q11 and the drain d12 of the first NMOS transistor Q12 and the input terminal of the first inverting amplifier 1. Between 1a.
  • the first inverting amplifier 1 may further include a second PMOS transistor Q21 and a second NMOS transistor Q22, configured to connect the drain d11 of the first PMOS transistor Q11 and the drain of the first NMOS transistor Q12. d12 coupling.
  • the drain d11 of the first PMOS transistor Q11 is coupled to the source s21 of the second PMOS transistor Q21
  • the drain d21 of the second PMOS transistor Q21 is coupled to the drain d22 of the second NMOS transistor Q22
  • the second NMOS transistor Q22 The source s22 is coupled to the drain d12 of the first NMOS transistor Q12
  • the gate g21 of the second PMOS transistor Q21 is coupled to the first bias voltage
  • the gate g22 of the second NMOS transistor Q22 is coupled to the second bias voltage
  • the drain d21 of the second PMOS transistor Q21 and the drain d22 of the second NMOS transistor Q22 are both coupled to the input terminal 1 a of the first inverting amplifier 1 through the impedance element Z.
  • the values of the first bias voltage and the second bias voltage can be set by those skilled in the art according to actual application requirements or experience.
  • the output terminal 1b of the first inverting amplifier 1 coupled to the drain d11 of the first PMOS transistor Q11 and the output of the first inverting amplifier 1 coupled to the drain d12 of the first NMOS transistor Q12.
  • the terminal 1b includes two different output terminals, namely a third output terminal 1c and a fourth output terminal 1d. That is, the drain d11 of the first PMOS transistor Q11 may be coupled to the third output terminal 1c of the output terminal 1b of the first inverting amplifier 1, and the drain d12 of the first NMOS transistor Q12 may be coupled to the first inverting amplifier. A fourth output terminal 1d of the output terminal 1b of 1 is coupled.
  • the signals generated by the two output terminals 1b are different. Specifically, the generated two signals include small signals with the same phase but different large signal voltage offsets.
  • the signal swing of the coupling point of the impedance element Z with the drain d21 of the second PMOS transistor Q21 and the drain d22 of the second NMOS transistor Q22 depends on the impedance of the impedance element Z, so By designing the impedance of the impedance element Z, the signal swing of the feedback point can be adjusted, and the linearity performance of the low noise amplifier can be improved.
  • the path formed by the first PMOS tube Q11, the second PMOS tube Q21, the first NMOS tube Q12, and the second NMOS tube Q22 is a high-impedance state, it is difficult for the noise of the impedance element Z to be output to the second of the low-noise amplifier.
  • the output terminal Lc, that is, the impedance element Z does not introduce significant noise.
  • the first inverting amplifier 1 may further include a first capacitor C1 coupled between the third output terminal 1c and the fourth output terminal 1d of the first inverting amplifier 1.
  • the load of the first PMOS tube Q11 and the load of the first NMOS tube Q12 are both a parallel structure of the second PMOS tube Q21 and the second NMOS tube Q22. Therefore, even when the signal swing is large, It can ensure that at least one of the second PMOS transistor Q21 and the second NMOS transistor Q22 is turned on, and the normal output of the first inverting amplifier 1 is guaranteed. At this time, the load of the first PMOS transistor Q11 and the load of the first NMOS transistor Q12 More linear, which can effectively improve the linearity performance of the low noise amplifier.
  • first PMOS transistor Q11 and the second PMOS transistor Q21 and the first NMOS transistor Q12 and the second NMOS transistor Q22 are complementary input structures, so even in the case of a large signal swing, the first inversion The output path of the amplifier 1 can always be turned on, thereby ensuring the performance of the 1 decibel (dB) compression point of the low noise amplifier.
  • the second inverting amplifier 2 may include: a fourth PMOS transistor Q41 and a fourth NMOS transistor Q42; a source s41 of the fourth PMOS transistor Q41 is coupled to a second power source vdd2, and a drain d41 of the fourth PMOS transistor Q41 Is coupled to the drain d42 of the fourth NMOS transistor Q42, and the source s42 of the fourth NMOS transistor Q42 is grounded; the drain d41 of the fourth PMOS transistor Q41 and the drain d42 of the fourth NMOS transistor Q42 are both connected to the second inverting amplifier 2
  • the output terminal 2b is coupled; the gate g41 of the fourth PMOS transistor Q41 and the gate g42 of the fourth NMOS transistor Q42 are both coupled to the input terminal 2a of the second inverting amplifier 2.
  • the fourth PMOS transistor Q41 and the fourth NMOS transistor Q42 constitute an inverter structure, so that the output signal of the second inverting amplifier 2 can have a large swing space, which can effectively improve the low noise amplifier. Dynamic range.
  • the second power source vdd2 may be the same as or different from the first power source vdd1, both of which are constant voltages and are used to supply power to respective inverting amplifiers, which is not limited in the embodiment of the present application.
  • the second inverting amplifier 2 may further include: a seventh capacitor C7; the drain d41 of the fourth PMOS transistor Q41 and the drain d42 of the fourth NMOS transistor Q42 both pass the seventh capacitor C7 and the second The output terminal 2b of the inverting amplifier 2 is coupled.
  • the seventh capacitor C7 has a DC blocking effect, which can prevent the DC signal in the low-noise amplifier from affecting the DC operating point of the next-stage circuit, thereby ensuring the normal operation of the next-stage circuit.
  • the third inverting amplifier 3 may include: a third PMOS transistor Q31 and a third NMOS transistor Q32; a source s31 of the third PMOS transistor Q31 is coupled to a second power source vdd2, and a drain d31 of the third PMOS transistor Q31 Is coupled to the drain d32 of the third NMOS transistor Q32, and the source s32 of the third NMOS transistor Q32 is grounded; the drain d31 of the third PMOS transistor Q31 and the drain d32 of the third NMOS transistor Q32 are both connected to the third inverting amplifier 3
  • the gate g31 of the third PMOS transistor Q31 is coupled to the third output terminal 1c of the first inverting amplifier 1, and the gate g32 of the third NMOS transistor Q32 is coupled to the fourth output of the first inverting amplifier 1.
  • Terminal 1d is coupled.
  • the third PMOS transistor Q31 and the third NMOS transistor Q32 form an inverter structure, so that the output signal of the third inverting amplifier 3 can have a large swing space, which can effectively improve the low noise amplifier. Dynamic range.
  • the third inverting amplifier 3 may further include a third capacitor C3; the drain d31 of the third PMOS transistor Q31 and the drain d32 of the third NMOS transistor Q32 both pass through the third capacitor C3 and the third The output terminal 3b of the inverting amplifier 3 is coupled.
  • the third capacitor C3 has a DC blocking effect, which can prevent the DC signal in the low-noise amplifier from affecting the DC operating point of the next-stage circuit, thereby ensuring the normal operation of the next-stage circuit.
  • the conductance value is equal to the transconductance value of the fourth PMOS transistor Q41, and the transconductance value of the third NMOS transistor Q32 is equal to the transconductance value of the fourth NMOS transistor Q42.
  • Each gate can be coupled to a bias voltage bias for providing a DC operating point.
  • the gate of any one of the six MOS transistors can be connected to the corresponding bias voltage bias through the second resistor R2, and the value of the bias voltage bias corresponding to each MOS transistor can be set to be the same or different.
  • Each bias voltage bias can provide a direct current operating point for a corresponding MOS transistor through a corresponding second resistor R2 to ensure that the MOS tube can work normally.
  • the gates of the first PMOS transistor Q11, the first NMOS transistor Q12, the third PMOS transistor Q31, the third NMOS transistor Q32, the fourth PMOS transistor Q41, and the fourth NMOS transistor Q42 can be coupled to each other through a capacitor.
  • the capacitor of the corresponding inverting amplifier input has a DC blocking function, which can prevent the DC signal at the input of each inverting amplifier from affecting the DC operating point of the corresponding MOS tube.
  • the first inverting amplifier 1 may further include one or more second capacitors C2. At least one of the gate g12 of the first PMOS transistor Q11 and the gate g12 of the first NMOS transistor Q12 is connected to the first capacitor C2 through the second capacitor C2. An input terminal 1a of an inverting amplifier 1 is coupled.
  • the third inverting amplifier 3 may further include a fourth capacitor C4 and a fifth capacitor C5.
  • the gate g31 of the third PMOS transistor Q31 is coupled to the third output terminal 1c of the first inverting amplifier 1 through the fourth capacitor C4.
  • the gate g32 of the NMOS transistor Q32 is coupled to the fourth output terminal 1d of the first inverting amplifier 1 through a fifth capacitor C5.
  • the second inverting amplifier 2 may further include an eighth capacitor C8.
  • the gate g41 of the fourth PMOS transistor Q41 and the gate g42 of the fourth NMOS transistor Q42 both pass the eighth capacitor C8 and the input terminal 2a of the second inverting amplifier 2. coupling.
  • the area of the low-noise amplifier is small, and the frequency range is large, which can achieve broadband matching.
  • only a small number of the low-noise amplifiers can be used to cover a wide frequency range, so that the area of the RF receiver where the low-noise amplifiers are located can be reduced.
  • the "at least one" mentioned in the embodiments of the present application may be one or more; the mentioned “including” means non-exclusive inclusion, that is, it may include other elements in addition to the mentioned elements ; “A and / or B” refers to one or all of A or B; “Coupling” refers to electrical connection or coupling, which includes direct connection through a wire or connection through other elements.
  • the above-mentioned embodiments provided by this application are not intended to limit this application. Any modification, equivalent replacement, or improvement made within the spirit and principle of this application shall be included in the protection scope of this application.
  • this embodiment uses a low-noise amplifier as an example to describe its technical solution and beneficial effects
  • the single-ended to differential amplifier to which the above structure is applied may be applicable to other application scenarios, such as a variable gain amplifier, etc.
  • the technical effect of realizing the single-ended to differential function without using an inductor and reducing the number of input terminals is realized.
  • the amplifier structure in the specific embodiment may exist as an integrated circuit in a chip, may also exist as a discrete device, or may be a combination of the two.
  • capacitors and resistors may be integrated circuits as part of a radio frequency chip or other chips, and the capacitors and resistors are discrete devices.
  • one or more resistors may also exist in an integrated circuit and be located in the chip.
  • one or more capacitors may also exist in an integrated circuit manner and are located in the chip.
  • the one or more capacitors may be MOS tube capacitors. This embodiment does not limit the specific implementation manner.

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Abstract

本申请公开了一种单端转差分放大器和射频接收机。单端转差分放大器包括：第一反相放大器、第二反相放大器和第三反相放大器；第一反相放大器的输入端和第二反相放大器的输入端均与单端转差分放大器的输入端耦合，第一反相放大器的输出端与第三反相放大器的输入端耦合，第二反相放大器的输出端与单端转差分放大器的第一输出端耦合，第三反相放大器的输出端与单端转差分放大器的第二输出端耦合，第一反相放大器的输入端与第一反相放大器的输出端之间耦合有阻抗元件。本申请中的单端转差分放大器的面积较小，且频率范围较大，可以实现宽带匹配，从而仅使用较少数量的单端转差分放大器就可以覆盖宽频率范围，进而可以减小射频接收机的面积。

Description

单端转差分放大器和射频接收机 技术领域
本申请涉及电子技术领域，特别涉及一种单端转差分放大器和射频接收机。
背景技术
在射频接收机的前端设计中，低噪声放大器(Low Noise Amplifier，LNA)是必不可少的组成部分，其决定了整个接收机的接收灵敏度。为了减少射频接收机的面积，需要减少射频端口的使用，为此，低噪声放大器通常使用采用单端转差分的电路结构，即低噪声放大器与射频接收机的射频端口耦合后，射频信号通过射频端口输入低噪声放大器，低噪声放大器可以输出差分信号，从而可以减少射频接收机的射频端口数量。
目前，低噪声放大器往往采用无源电感巴伦(Balun)来实现单端输入、差分输出的功能。具体地，如图1所示，低噪声放大器包括：电阻、两个金属氧化物半导体(metal oxide semiconductor，MOS)管、无源电感巴伦和电容。射频信号输入该低噪声放大器后，通过这两个MOS管输入到无源电感巴伦，然后通过无源电感巴伦和该电容转换为差分信号进行输出。
然而，由于上述低噪声放大器中采用了电感，所以导致该低噪声放大器的面积较大。另外，由于该低噪声放大器中使用电感和电容作为负载，所以该低噪声放大器为窄带结构，即该低噪声放大器的频率范围较小，此时需要同时使用多个低噪声放大器才能实现宽频带覆盖，从而进一步导致射频接收机的面积增大。
发明内容
本申请提供了一种单端转差分放大器和射频接收机，可以在信号放大基础上实现单端转差分，并且不会显著增加单端转差分放大器的面积。所述技术方案如下：
第一方面，提供了一种单端转差分放大器，所述单端转差分放大器包括：第一反相放大器、第二反相放大器和第三反相放大器；所述第一反相放大器的输入端和所述第二反相放大器的输入端均与所述单端转差分放大器的输入端耦合，所述第一反相放大器的输出端与所述第三反相放大器的输入端耦合，所述第二反相放大器的输出端与所述单端转差分放大器的第一输出端耦合，所述第三反相放大器的输出端与所述单端转差分放大器的第二输出端耦合；所述第一反相放大器的输入端与所述第一反相放大器的输出端之间耦合有阻抗元件。
在本申请实施例中，该单端转差分放大器中可以不存在电感，因而该单端转差分放大器的面积较小，且频率范围较大，可以实现宽带匹配。如此，仅使用较少数量的该单端转差分放大器就可以覆盖宽频率范围，从而可以减小该单端转差分放大器的面积。
具体地，该单端转差分放大器工作时，射频信号输入该单端转差分放大器的输入端后，会输入第一反相放大器和第三反相放大器。该射频信号输入第一反相放大器后，第一反相放大器输出与该射频信号的相位相反的第一信号，第一信号输入第三反相放大器后，第三反相放大器输出与第一信号的相位相反的第二信号。该射频信号输入第二反相放大器后， 第二反相放大器输出与该射频信号的相位相反的第三信号。此时，该单端转差分放大器的第二输出端输出第二信号，该单端转差分放大器的第一输出端输出第三信号，第二信号的相位与第三信号的相位相反，从而实现了将该射频信号转换为由第二信号和第三信号形成的差分信号。
由于该单端转差分放大器中的第一反相放大器、第二反相放大器和第三反相放大器可以是以MOS技术实现的放大器，因此，不必存在电感，所以该单端转差分放大器的面积较小，且频率范围较大，可以实现宽带匹配。如此，仅使用较少数量的该单端转差分放大器就可以覆盖宽频率范围，从而可以进一步减少射频端口数量，进而减小该单端转差分放大器的面积。
需要说明的是，第一反相放大器可以为单位增益的反相放大器，第二反相放大器的增益可以与第三反相放大器的增益相同。或者，第一反相放大器可以为非单位增益的反相放大器，第一反相放大器的增益与第三反相放大器的增益之积可以为第二反相放大器的增益的相反数。
其中，所述第一反相放大器包括：第一P型金属氧化物半导体(P-Metal-Oxide-Semiconductor，PMOS)管和第一N型金属氧化物半导体(N-Metal-Oxide-Semiconductor，NMOS)管；所述第一PMOS管的源极与第一电源耦合，所述第一PMOS管的漏极与所述第一NMOS管的漏极耦合，所述第一NMOS管的源极接地；所述第一PMOS管的漏极与所述第一反相放大器的所述输出端耦合，所述第一NMOS管的漏极与所述第一反相放大器的所述输出端耦合，所述第一PMOS管的漏极和所述第一NMOS管的漏极均通过所述阻抗元件与所述第一反相放大器的输入端耦合；所述第一PMOS管的栅极和所述第一NMOS管的栅极均与所述第一反相放大器的输入端耦合。
在本申请实施例中，第一PMOS管的漏极和第一NMOS管的漏极均通过阻抗元件与第一反相放大器的输入端耦合后，构成了第一PMOS管和第一NMOS管到第一反相放大器的输入端的反馈通路，这种情况下，第一PMOS管的跨导值与第一NMOS管的跨导值之和的倒数即为第一反相放大器的输入阻抗，因而通过设计第一PMOS管的跨导值和第一NMOS管的跨导值，即可实现对该单端转差分放大器的输入端的阻抗匹配。
另外，第一PMOS管的噪声和第一NMOS管的噪声通过第三反相放大器输出到该单端转差分放大器的第二输出端，并且通过上述反馈通路和第二反相放大器输出到该单端转差分放大器的第一输出端，此时第一PMOS管和第一NMOS管在该单端转差分放大器的第二输出端贡献的噪声和在该单端转差分放大器的第一输出端贡献的噪声大小相等、相位相同，因而可以相互抵消，从而使得第一PMOS管和第一NMOS管不会贡献噪声到该单端转差分放大器输出的差分信号中，进而可以极大地提高该单端转差分放大器的噪声性能。
其中，所述阻抗元件可以包括第一电阻和第六电容中的至少一个。也即是说，所述第一电阻和所述第六电容中的至少一个可以串联在所述第一PMOS管的漏极和所述第一NMOS管的漏极与所述第一反相放大器的输入端之间。
进一步地，所述第一反相放大器还可以包括：第二PMOS管和第二NMOS管；所述第一PMOS管的漏极与所述第二PMOS管的源极耦合，所述第二PMOS管的漏极与所述第二NMOS管的漏极耦合，所述第二NMOS管的源极与所述第一NMOS管的漏极耦合；所述第二PMOS管的栅极耦合于第一偏置电压，所述第二NMOS管的栅极耦合于第二偏置电压； 所述第二PMOS管的漏极和所述第二NMOS管的漏极均通过所述阻抗元件与所述第一反相放大器的输入端耦合；所述第一PMOS管的漏极与所述第一反相放大器的所述输出端中的第三输出端耦合，所述第一NMOS管的漏极与所述第一反相放大器的所述输出端中的第四输出端耦合。
在本申请实施例中，阻抗元件与第二PMOS管的漏极和第二NMOS管的漏极的耦合点(即上述反馈通路的反馈点)的信号摆幅取决于阻抗元件的阻抗，因而通过设计阻抗元件的阻抗，即可调节该反馈点的信号摆幅，提升该单端转差分放大器的线性度性能。并且，由于第一PMOS管、第二PMOS管、第一NMOS管和第二NMOS管构成的通路为高阻态，所以阻抗元件的噪声难以输出到该单端转差分放大器的第二输出端，即阻抗元件不会引入显著噪声。
更进一步地，所述第一反相放大器还包括：第一电容，耦合在所述第三输出端与所述第四输出端之间。这种情况下，第一PMOS管的负载和第一NMOS管的负载均为第二PMOS管和第二NMOS管的并联结构，因而即使在信号摆幅较大的情况下，也能够保证第二PMOS管和第二NMOS管中至少有一个是导通的，保证第一反相放大器的正常输出，此时第一PMOS管的负载和第一NMOS管的负载更加线性，从而可以有效提升该单端转差分放大器的线性度性能。
在本申请实施例中，第一PMOS管和第二PMOS管与第一NMOS管和第二NMOS管是互补的输入结构，因而即使在信号摆幅较大的情况下，第一反相放大器的输出通路也总能导通，从而保障了该单端转差分放大器的1分贝压缩点的性能。
进一步地，所述第一反相放大器还包括：第二电容；第一PMOS管的栅极和所述第一NMOS管的栅极中的至少一个通过所述第二电容与所述第一反相放大器的输入端耦合。第二电容具有隔直作用，可以避免第一反相放大器的输入端的直流信号影响第一PMOS管和第一NMOS管中的至少一个的直流工作点。
其中，所述第三反相放大器包括：第三PMOS管和第三NMOS管；所述第三PMOS管的源极与第二电源耦合，所述第三PMOS管的漏极与所述第三NMOS管的漏极耦合，所述第三NMOS管的源极接地；所述第三PMOS管的漏极和所述第三NMOS管的漏极均与所述第三反相放大器的输出端耦合；所述第三PMOS管的栅极与所述第三输出端耦合，所述第三NMOS管的栅极与所述第四输出端耦合。
在本申请实施例中，第三PMOS管和第三NMOS管构成反相器结构，从而使得第三反相放大器的输出信号可以具有很大的摆幅空间，进而可以有效提升该单端转差分放大器的动态范围。
进一步地，所述第三反相放大器还包括：第三电容；所述第三PMOS管的漏极和所述第三NMOS管的漏极均通过所述第三电容与所述第三反相放大器的输出端耦合。第三电容具有隔直作用，可以避免该单端转差分放大器中的直流信号影响其下一级电路的直流工作点，从而可以保证其下一级电路的正常工作。
进一步地，所述第三反相放大器还包括：第四电容和第五电容；所述第三PMOS管的栅极通过所述第四电容与所述第三输出端耦合，所述第三NMOS管的栅极通过所述第五电容与所述第四输出端耦合。第四电容具有隔直作用，可以避免第一反相放大器的第三输出端的直流信号影响第三PMOS管的直流工作点，第五电容也具有隔直作用，可以避免第一 反相放大器的第四输出端的直流信号影响第三NMOS管的直流工作点。
其中，所述第二反相放大器包括：第四PMOS管和第四NMOS管；所述第四PMOS管的源极与第二电源耦合，所述第四PMOS管的漏极与所述第四NMOS管的漏极耦合，所述第四NMOS管的源极接地；所述第四PMOS管的漏极和所述第四NMOS管的漏极均与所述第二反相放大器的输出端耦合；所述第四PMOS管的栅极和所述第四NMOS管的栅极均与所述第二反相放大器的输入端耦合。
在本申请实施例中，第四PMOS管和第四NMOS管构成反相器结构，从而使得第二反相放大器的输出信号可以具有很大的摆幅空间，进而可以有效提升该单端转差分放大器的动态范围。
进一步地，所述第二反相放大器还包括：第七电容；所述第四PMOS管的漏极和所述第四NMOS管的漏极均通过所述第七电容与所述第二反相放大器的输出端耦合。第七电容具有隔直作用，可以避免该单端转差分放大器中的直流信号影响其下一级电路的直流工作点，从而可以保证其下一级电路的正常工作。
进一步地，所述第二反相放大器还包括：第八电容；所述第四PMOS管的栅极和所述第四NMOS管的栅极均通过所述第八电容与所述第二反相放大器的输入端耦合。第八电容具有隔直作用，可以避免第二反相放大器的输入端的直流信号影响第四PMOS管的直流工作点。
第二方面，提供了一种射频接收机，所述射频接收机包括上述第一方面所述的单端转差分放大器。
在一种可能的实现方式中，该单端转差分放大器可以为单端转差分的低噪声放大器，该射频接收机还可以包括混频器，该混频器可以与该低噪声放大器的第一输出端和第二输出端耦合。
第三方面，提供了一种射频芯片，包括述第一方面所述的单端转差分放大器或第二方面所述的射频接收机。
第四方面，提供了一种通信装置，包括述第三方面所述的射频芯片。可选地，该通信装置是无线终端。
上述第二方面、第三方面或第四方面所获得的技术效果与上述第一方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
附图说明
图1是相关现有技术提供的一种低噪声放大器的结构示意图；
图2是本申请实施例提供的一种射频接收机的结构示意图；
图3是本申请实施例提供的第一种低噪声放大器的结构示意图；
图4是本申请实施例提供的第二种低噪声放大器的结构示意图；
图5是本申请实施例提供的第三种低噪声放大器的结构示意图；
图6是本申请实施例提供的第四种低噪声放大器的结构示意图；
图7是本申请实施例提供的第五种低噪声放大器的结构示意图；
图8是本申请实施例提供的第六种低噪声放大器的结构示意图；
图9是本申请实施例提供的第七种低噪声放大器的结构示意图；
图10是本申请实施例提供的第八种低噪声放大器的结构示意图；
图11是本申请实施例提供的第九种低噪声放大器的结构示意图；
图12是本申请实施例提供的第十种低噪声放大器的结构示意图；
图13是本申请实施例提供的第十一种低噪声放大器的结构示意图；
图14是本申请实施例提供的第十二种低噪声放大器的结构示意图。
附图标记：
La：低噪声放大器的输入端，Lb：低噪声放大器的第一输出端，Lc：低噪声放大器的第二输出端；
1：第一反相放大器，1a：第一反相放大器的输入端，1b：第一反相放大器的输出端，1c：第一反相放大器的第三输出端，1d：第一反相放大器的第四输出端，2：第二反相放大器，2a：第二反相放大器的输入端，2b：第二反相放大器的输出端，3：第三反相放大器，3a：第三反相放大器的输入端，3b：第三反相放大器的输出端；
Q11：第一PMOS管，s11：第一PMOS管的源极，d11：第一PMOS管的漏极，g11：第一PMOS管的栅极，Q12：第一NMOS管，s12：第一NMOS管的源极，d12：第一NMOS管的漏极，g12：第一NMOS管的栅极，Q21：第二PMOS管，s21：第二PMOS管的源极，d21：第二PMOS管的漏极，g21：第二PMOS管的栅极，Q22：第二NMOS管，s22：第二NMOS管的源极，d22：第二NMOS管的漏极，g22：第二NMOS管的栅极，Q31：第三PMOS管，s31：第三PMOS管的源极，d31：第三PMOS管的漏极，g31：第三PMOS管的栅极，Q32：第三NMOS管，s32：第三NMOS管的源极，d32：第三NMOS管的漏极，g32：第三NMOS管的栅极，Q41：第四PMOS管，s41：第四PMOS管的源极，d41：第四PMOS管的漏极，g41：第四PMOS管的栅极，Q42：第四NMOS管，s42：第四NMOS管的源极，d42：第四NMOS管的漏极，g42：第四NMOS管的栅极；
Z：阻抗元件，R1：第一电阻，R2：第二电阻，C1：第一电容，C2：第二电容，C3：第三电容，C4：第四电容，C5：第五电容，C6：第六电容，C7：第七电容，C8：第八电容。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的实施方式作进一步地详细描述。
在对本申请实施例进行详细地解释说明之前，先对本申请实施例涉及的应用场景予以说明。
随着射频接收机的广泛应用，降低射频接收机的成本的需求越来越迫切，为此，往往在射频接收机中使用具有单转双的电路结构的低噪声放大器来减少射频端口的使用。本申请实施例提供的单端转差分放大器即应用于射频接收机中，为了便于理解，下面以该单端转差分放大器为单端转差分的低噪声放大器为例来进行说明。
图2是本申请实施例提供的一种射频接收机的结构示意图，该射频接收机可以位于射 频芯片中，该射频接收机的射频端口为该射频芯片的射频输入端口，且用于输入射频信号。参见图2，该射频接收机可以包括至少一条射频通路，每条射频通路均与一个射频端口耦合，且每条射频通路中可以包括低噪声放大器(LNA)、混频器(MIXER)和跨阻放大器(trans-impedance amplifier，TIA)，低噪声放大器、混频器与跨阻放大器串联连接，输出的信号至后端器件处理，该后端器件可包括模数转换器(Analog to Digital，ADC)等。进一步地，所述射频芯片位于一个通信装置中，该通信装置可以是基站、中继站、直放站、转发站、射频拉远头(RRH)、无线终端、用户设备、个人电脑、膝上电脑、平板电脑、或物联网设备等各类无线通信装置，本实施例对此不限定。
可以理解，以上提到的射频芯片是一个集成的半导体芯片，可以由半导体制造工艺生成。此外，该射频接收机除了可以包括在射频芯片中，也可以作为分立式系统的一部分，即在该系统中存在的多个部件不是一个集成的芯片中的集成电路，而是采用分立的各个部件。因此，该射频接收机中的各个部分也可以由分立器件组成。以下实施例对于具体的电路结构是否采用集成电路工艺或构成芯片的一部分集成电路不做限定。
该低噪声放大器可以为下图3-图14任一所示的低噪声放大器，该低噪声放大器的输入端La可以与该射频接收机的射频端口耦合，该低噪声放大器的第一输出端Lb和该低噪声放大器的第二输出端Lc可以与混频器耦合，该低噪声放大器可以将通过射频端口输入的射频信号转换为差分信号，并将该差分信号输入到混频器，混频器可以将该差分信号与本振信号(LO)进行混频得到中频信号，并将该中频信号输入到跨阻放大器，跨阻放大器可以将该中频信号转换为电压信号，并将该电压信号输出至后端器件进行处理。
在以上实施例中，射频接收机接收和处理的射频信号可以是业务数据信号、无线控制信号、无线调度信号、导频信号、无线广播信号、物理层或更高层的通信协议信号或其一种或多种的组合。通过接收和处理的射频信号，该射频接收机及其所处于的通信装置可以与发送射频信号的另一通信装置实现通信操作。
图3是本申请实施例提供的一种低噪声放大器的结构示意图。参见图3，该低噪声放大器可以包括：第一反相放大器1、第二反相放大器2和第三反相放大器3。第一反相放大器1的输入端1a和第二反相放大器2的输入端2a均与该低噪声放大器的输入端La耦合，第一反相放大器1的输出端1b与第三反相放大器3的输入端3a耦合，第二反相放大器2的输出端2b与该低噪声放大器的第一输出端Lb耦合，第三反相放大器3的输出端3b与该低噪声放大器的第二输出端Lc耦合，第一反相放大器1的输入端1a与第一反相放大器1的输出端1b之间耦合有阻抗元件Z。
需要说明的是，第一反相放大器1、第二反相放大器2和第三反相放大器3均可以实现反相功能，也即是，第一反相放大器1的输出端1b输出的信号的相位与第一反相放大器1的输入端1a输入的信号的相位相反，第二反相放大器2的输出端2b输出的信号的相位与第二反相放大器2的输入端2a输入的信号的相位相反，第三反相放大器3的输出端3b输出的信号的相位与第三反相放大器3的输入端3a输入的信号的相位相反。
另外，为了保证该低噪声放大器输出的信号为差分信号，即为了保证第二反相放大器2输出的信号与第三反相放大器3输出的信号的幅度相等、相位相反，第一反相放大器1可以为单位增益的反相放大器，第二反相放大器2的增益可以与第三反相放大器3的增益相同，此时第二反相放大器2的输出阻抗与第三反相放大器3的输出阻抗相等，当然，第一 反相放大器1也可以为非单位增益的反相放大器，这种情况下，第一反相放大器1的增益与第三反相放大器3的增益之积可以为第二反相放大器2的增益的相反数。本领域技术人员可以理解，本实施例的每个反相放大器的增益是可以根据实际应用需求设置的，从而使得所述低噪声放大器的增益可设置为所需要的值，即该值由第一反相放大器1、第二反相放大器2和第三反相放大器3三者的增益共同决定。可选地，低噪声放大器的增益可设置为可调，即可在多个不同的值之间做调整，此时对应的每个反相放大器的增益都是可调的。无论整个低噪声放大器如何调整，只要保证第一反相放大器1的增益与第三反相放大器3的增益之积大致等于第二反相放大器2的增益的相反数，即可实现差分输出。因此，本领域技术人员可以在设计电路的过程中根据实际应用需求设置三个反相放大器的增益，并在设置过程中只需要保证第一反相放大器1的增益与第三反相放大器3的增益之积大致等于第二反相放大器2的增益的相反数，保证整个低噪声放大器的差分输出的两路信号是输入信号被放大相同的幅值但具有相反相位。
具体地，该低噪声放大器工作时，射频信号输入该低噪声放大器的输入端La后，会输入第一反相放大器1和第三反相放大器3。该射频信号输入第一反相放大器1后，第一反相放大器1输出与该射频信号的相位相反的第一信号，第一信号输入第三反相放大器3后，第三反相放大器3输出与第一信号的相位相反的第二信号。该射频信号输入第二反相放大器2后，第二反相放大器2输出与该射频信号的相位相反的第三信号。此时，该低噪声放大器的第二输出端Lc输出第二信号，该低噪声放大器的第一输出端Lb输出第三信号，第二信号的相位与第三信号的相位相反，从而实现了将该射频信号转换为由第二信号和第三信号形成的差分信号。
值得说明的是，该低噪声放大器采用单端转差分的电路结构，该低噪声放大器的输入端La与射频端口耦合，射频信号通过该射频端口输入该低噪声放大器的输入端La后，该低噪声放大器的第一输出端Lb和第二输出端Lc可以输出差分信号，从而实现单端输入、差分输出的功能，相比于相关技术中需要进行差分输入的低噪声放大器，使用本申请实施例中的低噪声放大器可以大大减少射频端口数量。
另外，由于该低噪声放大器中的第一反相放大器1、第二反相放大器2和第三反相放大器3可以是以MOS技术实现的放大器，因此，不必存在电感，所以该低噪声放大器的面积可以被实现的较小，且频率范围较大，可以实现宽带匹配。如此，仅使用较少数量的该低噪声放大器就可以覆盖宽频率范围，从而可以进一步减少射频端口数量，进而减小该低噪声放大器所在的射频接收机的面积。例如，使用该低噪声放大器，在3吉赫(GHz)以下无需再使用其它低噪声放大器，在3GHz-6GHz只需再使用一个同样的低噪声放大器，此时单个低噪声放大器即可实现宽频带覆盖。
下面对第一反相放大器1的结构进行说明。参见图4，第一反相放大器1包括：第一PMOS管Q11和第一NMOS管Q12；第一PMOS管Q11的源极s11与第一电源vdd1耦合，第一PMOS管Q11的漏极d11与第一NMOS管Q12的漏极d12耦合，第一NMOS管Q12的源极s12接地；第一PMOS管Q11的漏极d11与第一反相放大器1的输出端1b耦合，第一NMOS管Q12的漏极d12与第一反相放大器1的输出端1b耦合，第一PMOS管Q11的漏极d11和第一NMOS管Q12的漏极d12均通过阻抗元件Z与第一反相放大器1的输入端1a耦合；第一PMOS管Q11的栅极g11和第一NMOS管Q12的栅极g12均与第一反相放 大器1的输入端1a耦合。
需要说明的是，第一PMOS管Q11的漏极d11和第一NMOS管Q12的漏极d12均通过阻抗元件Z与第一反相放大器1的输入端1a耦合后，构成了第一PMOS管Q11和第一NMOS管Q12到第一反相放大器1的输入端1a的反馈通路，这种情况下，第一PMOS管Q11的跨导值与第一NMOS管Q12的跨导值之和的倒数即为第一反相放大器1的输入阻抗，因而通过设计第一PMOS管Q11的跨导值和第一NMOS管Q12的跨导值，即可实现对该低噪声放大器的输入端La的阻抗匹配。例如，可以设计第一PMOS管Q11的跨导值与第一NMOS管Q12的跨导值之和为0.02西门子(S)，此时第一反相放大器1的输入阻抗为1/0.02＝50欧姆，从而可以实现对该低噪声放大器的输入端La的阻抗匹配。
另外，第一PMOS管Q11的噪声和第一NMOS管Q12的噪声通过第三反相放大器3输出到该低噪声放大器的第二输出端Lc，并且通过上述反馈通路和第二反相放大器2输出到该低噪声放大器的第一输出端Lb，此时第一PMOS管Q11和第一NMOS管Q12在该低噪声放大器的第二输出端Lc贡献的噪声和在该低噪声放大器的第一输出端Lb贡献的噪声大小相等、相位相同，因而可以相互抵消。本申请实施例引入的这种噪声抵消机制，使得第一PMOS管Q11和第一NMOS管Q12不会贡献噪声到该低噪声放大器输出的差分信号中，从而可以极大地提高该低噪声放大器的噪声性能。
进一步地，参见图5、图6和图7，阻抗元件Z可以包括第一电阻R1和第六电容C6中的至少一个。第一PMOS管Q11的漏极d11和第一NMOS管Q12的漏极d12均通过第一电阻R1和第六电容C6中的至少一个与第一反相放大器1的输入端1a耦合。也即是说，第一电阻R1和第六电容C6中的至少一个可以串联在第一PMOS管Q11的漏极d11和第一NMOS管Q12的漏极d12与第一反相放大器1的输入端1a之间。
进一步地，参见图8，第一反相放大器1还可以包括：第二PMOS管Q21和第二NMOS管Q22，用于将第一PMOS管Q11的漏极d11与第一NMOS管Q12的漏极d12耦合。具体地，第一PMOS管Q11的漏极d11与第二PMOS管Q21的源极s21耦合，第二PMOS管Q21的漏极d21与第二NMOS管Q22的漏极d22耦合，第二NMOS管Q22的源极s22与第一NMOS管Q12的漏极d12耦合；第二PMOS管Q21的栅极g21耦合于第一偏置电压，第二NMOS管Q22的栅极g22耦合于第二偏置电压；第二PMOS管Q21的漏极d21和第二NMOS管Q22的漏极d22均通过阻抗元件Z与第一反相放大器1的输入端1a耦合。所述第一偏置电压和第二偏置电压的值可以由本领域技术人员依照实际应用需求或经验设置。
在此结构下，与第一PMOS管Q11的漏极d11相耦合的第一反相放大器1的输出端1b和与第一NMOS管Q12的漏极d12相耦合的第一反相放大器1的输出端1b包括两个不同输出端，即第三输出端1c和第四输出端1d。也即是，第一PMOS管Q11的漏极d11可以与第一反相放大器1的输出端1b中的第三输出端1c耦合，第一NMOS管Q12的漏极d12可以与第一反相放大器1的输出端1b中的第四输出端1d耦合。两个输出端1b产生的信号不同，具体地，产生的两个信号中包含相位相同的小信号，但具有不同的大信号电压偏置。
另外，阻抗元件Z与第二PMOS管Q21的漏极d21和第二NMOS管Q22的漏极d22的耦合点(即上述反馈通路的反馈点)的信号摆幅取决于阻抗元件Z的阻抗，因而通过设计阻抗元件Z的阻抗，即可调节该反馈点的信号摆幅，提升该低噪声放大器的线性度性能。 并且，由于第一PMOS管Q11、第二PMOS管Q21、第一NMOS管Q12和第二NMOS管Q22构成的通路为高阻态，所以阻抗元件Z的噪声难以输出到该低噪声放大器的第二输出端Lc，即阻抗元件Z不会引入显著噪声。
更进一步地，参见图9，第一反相放大器1还可以包括：第一电容C1，耦合在第一反相放大器1的第三输出端1c与第四输出端1d之间。这种情况下，第一PMOS管Q11的负载和第一NMOS管Q12的负载均为第二PMOS管Q21和第二NMOS管Q22的并联结构，因而即使在信号摆幅较大的情况下，也能够保证第二PMOS管Q21和第二NMOS管Q22中至少有一个是导通的，保证第一反相放大器1的正常输出，此时第一PMOS管Q11的负载和第一NMOS管Q12的负载更加线性，从而可以有效提升该低噪声放大器的线性度性能。
值得注意的是，第一PMOS管Q11和第二PMOS管Q21与第一NMOS管Q12和第二NMOS管Q22是互补的输入结构，因而即使在信号摆幅较大的情况下，第一反相放大器1的输出通路也总能导通，从而保障了该低噪声放大器的1分贝(dB)压缩点的性能。
下面对第二反相放大器2的结构进行说明。参见图10，第二反相放大器2可以包括：第四PMOS管Q41和第四NMOS管Q42；第四PMOS管Q41的源极s41与第二电源vdd2耦合，第四PMOS管Q41的漏极d41与第四NMOS管Q42的漏极d42耦合，第四NMOS管Q42的源极s42接地；第四PMOS管Q41的漏极d41和第四NMOS管Q42的漏极d42均与第二反相放大器2的输出端2b耦合；第四PMOS管Q41的栅极g41和第四NMOS管Q42的栅极g42均与第二反相放大器2的输入端2a耦合。这种情况下，第四PMOS管Q41和第四NMOS管Q42构成反相器结构，从而使得第二反相放大器2的输出信号可以具有很大的摆幅空间，进而可以有效提升该低噪声放大器的动态范围。第二电源vdd2可以与第一电源vdd1相同或不同，二者均是恒定电压，并用于为各自的反相放大器供电，本申请实施例对此不作限定。
进一步地，参见图11，第二反相放大器2还可以包括：第七电容C7；第四PMOS管Q41的漏极d41和第四NMOS管Q42的漏极d42均通过第七电容C7与第二反相放大器2的输出端2b耦合。需要说明的是，第七电容C7具有隔直作用，可以避免该低噪声放大器中的直流信号影响其下一级电路的直流工作点，从而可以保证其下一级电路的正常工作。
下面对第三反相放大器3的结构进行说明。参见图12，第三反相放大器3可以包括：第三PMOS管Q31和第三NMOS管Q32；第三PMOS管Q31的源极s31与第二电源vdd2耦合，第三PMOS管Q31的漏极d31与第三NMOS管Q32的漏极d32耦合，第三NMOS管Q32的源极s32接地；第三PMOS管Q31的漏极d31和第三NMOS管Q32的漏极d32均与第三反相放大器3的输出端3b耦合；第三PMOS管Q31的栅极g31与第一反相放大器1的第三输出端1c耦合，第三NMOS管Q32的栅极g32与第一反相放大器1的第四输出端1d耦合。这种情况下，第三PMOS管Q31和第三NMOS管Q32构成反相器结构，从而使得第三反相放大器3的输出信号可以具有很大的摆幅空间，进而可以有效提升该低噪声放大器的动态范围。
进一步地，参见图13，第三反相放大器3还可以包括：第三电容C3；第三PMOS管Q31的漏极d31和第三NMOS管Q32的漏极d32均通过第三电容C3与第三反相放大器3的输出端3b耦合。需要说明的是，第三电容C3具有隔直作用，可以避免该低噪声放大器中的直流信号影响其下一级电路的直流工作点，从而可以保证其下一级电路的正常工作。
上述结构中，为了保证第一PMOS管Q11和第一NMOS管Q12在该低噪声放大器的第一输出端Lb贡献的噪声和在该低噪声放大器的第二输出端Lc贡献的噪声大小相等，可以设计第一PMOS管Q11的跨导值和第二PMOS管Q21的跨导值相等、第一NMOS管Q12的跨导值和第二NMOS管Q22的跨导值相等、第三PMOS管Q31的跨导值和第四PMOS管Q41的跨导值相等、第三NMOS管Q32的跨导值和第四NMOS管Q42的跨导值相等。
进一步地，为了保证MOS管可以正常工作，参见图14，第一PMOS管Q11、第一NMOS管Q12、第三PMOS管Q31、第三NMOS管Q32、第四PMOS管Q41和第四NMOS管Q42的栅极均可以耦合至用于提供直流工作点的偏置电压bias。例如，这六个MOS管中的任意一个MOS管的栅极可以通过第二电阻R2连接至对应的偏置电压bias，每个MOS管对应的偏置电压bias的值可以设置为相同或不同。每个偏置电压bias可以通过对应的第二电阻R2为对应的MOS管提供直流工作点，保证这个MOS管可以正常工作。
此外，参见图14，第一PMOS管Q11、第一NMOS管Q12、第三PMOS管Q31、第三NMOS管Q32、第四PMOS管Q41和第四NMOS管Q42的栅极均可以通过电容耦合至对应的反相放大器的输入端，该电容具有隔直作用，可以避免每个反相放大器的输入端的直流信号影响对应的MOS管的直流工作点。
例如，第一反相放大器1还可以包括一个或多个第二电容C2，第一PMOS管Q11的栅极g12和第一NMOS管Q12的栅极g12中的至少一个通过第二电容C2与第一反相放大器1的输入端1a耦合。第三反相放大器3还可以包括第四电容C4和第五电容C5，第三PMOS管Q31的栅极g31通过第四电容C4与第一反相放大器1的第三输出端1c耦合，第三NMOS管Q32的栅极g32通过第五电容C5与第一反相放大器1的第四输出端1d耦合。第二反相放大器2还可以包括第八电容C8，第四PMOS管Q41的栅极g41和第四NMOS管Q42的栅极g42均通过第八电容C8与第二反相放大器2的输入端2a耦合。
在本申请实施例中，低噪声放大器可以不存在电感，因而该低噪声放大器的面积较小，且频率范围较大，可以实现宽带匹配。如此，仅使用较少数量的该低噪声放大器就可以覆盖宽频率范围，从而可以减小该低噪声放大器所在的射频接收机的面积。
需理解，本申请实施例中提到的“至少一个”可以是一个或多个；所提到的“包括”是指不排他的包含，即除了包含所提到的元素，还可能包含其他元素；所提到的“A和/或B”表示A或B中的一个或全部；所提到的“耦合”表示电连接或电耦合，其包括通过导线直接相连或通过其他元件相连。
以上所述为本申请提供的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。例如，虽然本实施例以低噪声放大器为例作说明，描述了其技术方案和有益效果，但应用以上结构的单端转差分放大器可以适用于其他应用场景，如可变增益放大器等，同样可实现无需使用电感即可实现单端转差分功能，减少输入端数量的技术效果。此外，具体实施例中的放大器结构可以以芯片中集成电路的方式存在，也可以以分立器件方式存在，或者可以是两者的结合。例如，以上实施例中除了电容和电阻外的其他器件，如每个MOS管都可以是集成电路，作为射频芯片或其他芯片的一部分，而电容和电阻采用分立器件。或者，可选地，一个或多个电阻也可以集成电路方式存在而位于所述芯片内。或者，可选地，一个或多个 电容也可以集成电路方式存在而位于所述芯片内，此时的一个或多个电容可以是MOS管电容，本实施例不限制具体实现方式。

Claims (15)

  1. 一种单端转差分放大器，其特征在于，包括：第一反相放大器、第二反相放大器和第三反相放大器；
    所述第一反相放大器的输入端和所述第二反相放大器的输入端均与所述单端转差分放大器的输入端耦合，所述第一反相放大器的输出端与所述第三反相放大器的输入端耦合，所述第二反相放大器的输出端与所述单端转差分放大器的第一输出端耦合，所述第三反相放大器的输出端与所述单端转差分放大器的第二输出端耦合；
    所述第一反相放大器的输入端与所述第一反相放大器的输出端之间耦合有阻抗元件。
  2. 如权利要求1所述的单端转差分放大器，其特征在于，所述第一反相放大器为单位增益的反相放大器。
  3. 如权利要求1或2所述的单端转差分放大器，其特征在于，所述第一反相放大器包括：第一P型金属氧化物半导体PMOS管和第一N型金属氧化物半导体NMOS管；
    所述第一PMOS管的源极与第一电源耦合，所述第一PMOS管的漏极与所述第一NMOS管的漏极耦合，所述第一NMOS管的源极接地；
    所述第一PMOS管的漏极与所述第一反相放大器的所述输出端耦合，所述第一NMOS管的漏极与所述第一反相放大器的所述输出端耦合，所述第一PMOS管的漏极和所述第一NMOS管的漏极均通过所述阻抗元件与所述第一反相放大器的输入端耦合；
    所述第一PMOS管的栅极和所述第一NMOS管的栅极均与所述第一反相放大器的输入端耦合。
  4. 如权利要求3所述的单端转差分放大器，其特征在于，所述第一反相放大器还包括：第二PMOS管和第二NMOS管；
    所述第一PMOS管的漏极与所述第二PMOS管的源极耦合，所述第二PMOS管的漏极与所述第二NMOS管的漏极耦合，所述第二NMOS管的源极与所述第一NMOS管的漏极耦合；
    所述第二PMOS管的栅极耦合于第一偏置电压，所述第二NMOS管的栅极耦合于第二偏置电压；
    所述第二PMOS管的漏极和所述第二NMOS管的漏极均通过所述阻抗元件与所述第一反相放大器的输入端耦合；
    所述第一PMOS管的漏极与所述第一反相放大器的所述输出端中的第三输出端耦合，所述第一NMOS管的漏极与所述第一反相放大器的所述输出端中的第四输出端耦合。
  5. 如权利要求4所述的单端转差分放大器，其特征在于，所述第一反相放大器还包括：第一电容，耦合在所述第三输出端与所述第四输出端之间。
  6. 如权利要求3至5中任一项所述的单端转差分放大器，其特征在于，所述第一反相放 大器还包括：第二电容；
    第一PMOS管的栅极和所述第一NMOS管的栅极中的至少一个通过所述第二电容与所述第一反相放大器的输入端耦合。
  7. 如权利要求4或5所述的单端转差分放大器，其特征在于，所述第三反相放大器包括：第三PMOS管和第三NMOS管；
    所述第三PMOS管的源极与第二电源耦合，所述第三PMOS管的漏极与所述第三NMOS管的漏极耦合，所述第三NMOS管的源极接地；
    所述第三PMOS管的漏极和所述第三NMOS管的漏极均与所述第三反相放大器的输出端耦合；
    所述第三PMOS管的栅极与所述第三输出端耦合，所述第三NMOS管的栅极与所述第四输出端耦合。
  8. 如权利要求7所述的单端转差分放大器，其特征在于，所述第三反相放大器还包括：第三电容；
    所述第三PMOS管的漏极和所述第三NMOS管的漏极均通过所述第三电容与所述第三反相放大器的输出端耦合。
  9. 如权利要求7或8所述的单端转差分低噪声放大器，其特征在于，所述第三反相放大器还包括：第四电容和第五电容；
    所述第三PMOS管的栅极通过所述第四电容与所述第三输出端耦合，所述第三NMOS管的栅极通过所述第五电容与所述第四输出端耦合。
  10. 如权利要求1至9中任一项所述的单端转差分放大器，其特征在于，所述阻抗元件包括第一电阻和第六电容中的至少一个。
  11. 如权利要求1至10中任一项所述的单端转差分放大器，其特征在于，所述第二反相放大器包括：第四PMOS管和第四NMOS管；
    所述第四PMOS管的源极与第二电源耦合，所述第四PMOS管的漏极与所述第四NMOS管的漏极耦合，所述第四NMOS管的源极接地；
    所述第四PMOS管的漏极和所述第四NMOS管的漏极均与所述第二反相放大器的输出端耦合；
    所述第四PMOS管的栅极和所述第四NMOS管的栅极均与所述第二反相放大器的输入端耦合。
  12. 如权利要求11所述的单端转差分放大器，其特征在于，所述第二反相放大器还包括：第七电容；
    所述第四PMOS管的漏极和所述第四NMOS管的漏极均通过所述第七电容与所述第二反相放大器的输出端耦合。
  13. 如权利要求11或12所述的单端转差分放大器，其特征在于，所述第二反相放大器还包括：第八电容；
    所述第四PMOS管的栅极和所述第四NMOS管的栅极均通过所述第八电容与所述第二反相放大器的输入端耦合。
  14. 一种射频接收机，其特征在于，所述射频接收机包括上述权利要求1至13任一项所述的单端转差分放大器。
  15. 如权利要求14所述的射频接收机，其特征在于，所述单端转差分放大器是单端转差分的低噪声放大器；
    所述射频接收机还包括：混频器，与所述第一输出端和所述第二输出端耦合。
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US20210075379A1 (en) 2021-03-11
US11606069B2 (en) 2023-03-14

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