WO2019234923A1 - Appareil de transmission, appareil de réception et procédé d'encodage - Google Patents

Appareil de transmission, appareil de réception et procédé d'encodage Download PDF

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Publication number
WO2019234923A1
WO2019234923A1 PCT/JP2018/022070 JP2018022070W WO2019234923A1 WO 2019234923 A1 WO2019234923 A1 WO 2019234923A1 JP 2018022070 W JP2018022070 W JP 2018022070W WO 2019234923 A1 WO2019234923 A1 WO 2019234923A1
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Prior art keywords
fixed value
bit
bits
sequence
unit
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PCT/JP2018/022070
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English (en)
Japanese (ja)
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中村　隆彦
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三菱電機株式会社
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Priority to PCT/JP2018/022070 priority Critical patent/WO2019234923A1/fr
Priority to JP2018556945A priority patent/JPWO2019234923A1/ja
Publication of WO2019234923A1 publication Critical patent/WO2019234923A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Definitions

  • the present invention relates to a transmission apparatus, a reception apparatus, and an encoding method that perform encoding processing.
  • LDPC Low Density Parity Check
  • the radio communication apparatus on the transmission side encodes the transmission bit string using a check matrix, and obtains an LDPC encoded sequence composed of systematic bits and parity bits, which are information bit portions.
  • the receiving-side wireless communication apparatus repeatedly receives the likelihood of each bit in the row direction of the check matrix and the column direction of the check matrix, thereby decoding the received data and obtaining a received bit string.
  • the parity check matrix can be represented by a Tanner graph that is a bipartite graph composed of rows and columns.
  • each row of the parity check matrix is referred to as a check node
  • each column of the parity check matrix is referred to as a variable node.
  • Each variable node and each check node of the Tanner graph are connected in accordance with the arrangement of “1” in the check matrix, and the wireless communication device on the receiving side repeatedly performs the delivery of likelihood between the connected nodes.
  • the received data is decoded to obtain a received bit string.
  • the Shortened method is a technique for performing encoding by inserting a fixed bit, which is known between a transmission-side wireless communication device and a reception-side wireless communication device, into a transmission bit string, and deleting the fixed bit from the obtained codeword. It is. Thereby, a coding rate lower than the coding rate of the LDPC code can be set.
  • a wireless communication device inserts a fixed bit at a position equal to a systematic bit position corresponding to a variable node having the largest number of connections with a check node in a Tanner graph of a check matrix.
  • the wireless communication device described in Patent Literature 1 includes a plurality of variable nodes for each variable node belonging to a combination having the largest number of connections with a plurality of different check nodes. Insert a fixed bit at a position equal to the systematic bit position. Accordingly, the wireless communication device described in Patent Literature 1 can improve decoding performance in the wireless communication device on the reception side.
  • the wireless communication device described in Patent Document 1 When inserting a plurality of fixed bits, the wireless communication device described in Patent Document 1 inserts a fixed bit into a combination having the largest number of connections with a plurality of different check nodes among a plurality of combinations of variable nodes. . Therefore, the wireless communication device described in Patent Document 1 has a problem that the processing load for confirming the number of connections for all combinations of variable nodes increases as the code length increases.
  • the present invention has been made in view of the above, and an object of the present invention is to obtain a transmission apparatus that generates a transmission sequence capable of improving the decoding performance of the reception apparatus while suppressing the processing load.
  • the transmission apparatus of the present invention uses K, L, M, N, and P as positive integers, and includes an L-bit information bit sequence and a K-bit fixed value.
  • an L + K-by-N parity check matrix for encoding a configured L + K-bit encoding target bit sequence using a pseudo cyclic low-density parity check code having a code length N can be divided into sub-matrices of M rows and M columns
  • a block having a small column weight of the corresponding check matrix preferentially includes a fixed value of K bits.
  • a fixed value insertion unit that generates a bit sequence to be encoded by inserting a fixed value into the information bit sequence.
  • the transmission apparatus performs coding processing on the coding target bit sequence by using the check matrix and coding processing by the pseudo cyclic low density parity check code, and coding processing by the coding unit.
  • a transmission sequence generation unit that preferentially deletes data corresponding to a bit position in which a fixed value is inserted from a bit sequence in which a check bit is added to a processing target bit sequence, and generates a transmission sequence.
  • the transmission apparatus according to the present invention has an effect that it is possible to generate a transmission sequence that can improve the decoding performance of the reception apparatus while suppressing the processing load.
  • FIG. Flowchart showing transmission processing of transmission apparatus according to Embodiment 1
  • FIG. The figure which shows the example which the fixed value insertion part which concerns on Embodiment 1 divides
  • FIG. 1 Flowchart showing reception processing of receiving apparatus according to embodiment 1
  • the figure which shows the example in the case of comprising the processing circuit with which the transmission apparatus which concerns on Embodiment 1 is provided with a processor and memory
  • FIG. The figure which shows the 1st example of insertion of the fixed value of K bits in the case of M ⁇ K ⁇ 2M in the fixed value insertion part which concerns on Embodiment 3.
  • FIG. 1 The figure which shows the 2nd example of insertion of the fixed value of K bits in the case of M ⁇ K ⁇ 2M in the fixed value insertion part which concerns on Embodiment 3.
  • FIG. 1 The figure which shows the example of insertion of the fixed value of K bit in the case of 2M ⁇ K ⁇ 3M in the fixed value insertion part which concerns on Embodiment 4.
  • FIG. 1 The figure which shows the 2nd example of insertion of the fixed value of K bits in the case of M ⁇ K ⁇ 2M in the fixed value insertion part which concerns on Embodiment 3.
  • FIG. 4 The figure which shows the example of insertion of the fixed value of K bit in the case of 2M ⁇ K ⁇ 3M in the fixed value insertion part which concerns on Embodiment 4.
  • FIG. 1 is a diagram illustrating a configuration example of a radio communication system 40 according to Embodiment 1 of the present invention.
  • the wireless communication system 40 includes a transmission device 10 and a reception device 30.
  • the wireless communication system 40 is a system in which the transmission device 10 transmits a transmission sequence to the reception device 30 via the communication path 20.
  • the transmission device 10 includes a fixed value insertion unit 11, an encoding unit 12, a transmission sequence generation unit 13, and a modulation unit 14.
  • the fixed value insertion unit 11 inserts a fixed value for the bit length of the information bit sequence to be encoded by the LDPC in the encoding unit 12 with respect to the input information bit sequence, and the encoding processing target bit Generate a series.
  • a fixed pattern whose values are all “0” is set as a fixed value.
  • the encoding unit 12 is a systematic LDPC encoding unit that performs an encoding process on the encoding target bit sequence generated by the fixed value insertion unit 11.
  • the encoding unit 12 uses a QC-LDPC (Quasi Cyclic-Low Density Parity Check) code that is a pseudo cyclic low density parity check code as an LDPC encoding process that is a low density parity check encoding process.
  • the encoding unit 12 adds a check bit that is a result of performing the encoding process to the bit sequence to be encoded.
  • the encoding unit 12 outputs the part of the encoding processing target bit sequence as it is.
  • the transmission sequence generation unit 13 inserts a fixed value from a bit sequence that is encoded by the encoding unit 12 and a check bit is added to the bit sequence to be encoded in order to generate a transmission sequence having a predetermined bit length.
  • This is a fixed value deleting unit that preferentially deletes data corresponding to the bit position where the fixed value is inserted in the unit 11.
  • the transmission sequence generation unit 13 deletes data from the bit sequence in which the check bit is added to the encoding processing target bit sequence, and generates a transmission sequence.
  • the modulation unit 14 performs modulation processing on the transmission sequence generated by the transmission sequence generation unit 13.
  • the modulation unit 14 transmits the transmission sequence after the modulation processing to the reception device 30 via the communication path 20.
  • FIG. 2 is a flowchart showing a transmission process of the transmission apparatus 10 according to the first embodiment.
  • FIG. 3 is a diagram illustrating processing contents in each component of the transmission device 10 according to the first embodiment.
  • the fixed value insertion unit 11 fixes a K bit with respect to an L-bit information bit sequence when an information bit sequence having a predetermined bit length and an L-bit length is input.
  • a value is inserted (step S11).
  • the fixed value insertion unit 11 generates an encoding process target bit sequence of L + K bits that is an object of the encoding process.
  • the encoding target bit sequence of L + K bits is composed of an L-bit information bit sequence and a K-bit fixed value.
  • FIG. 3A is an L-bit information bit sequence input to the fixed value insertion unit 11
  • FIG. 3B is an L + K-bit encoding process target generated by the fixed value insertion unit 11. It is a bit series.
  • “Fixed value insertion” between FIG. 3A and FIG. 3B indicates the processing content of the fixed value insertion unit 11.
  • the bit length of the information bit sequence input to the fixed value insertion unit 11 is L bits
  • the bit length of the encoding target bit sequence to be error-correction encoded by the code length N QC-LDPC code is L + K bits.
  • a check matrix of L + K rows and N columns used in the QC-LDPC code can be divided into sub-matrices of M rows and M columns.
  • the small matrix is represented by any one of a zero matrix, a unit matrix, or a matrix obtained by adding a plurality of rows obtained by cyclically shifting the number of rows defined in advance at one position of the unit matrix.
  • the L + K bit encoding target bit sequence can be divided into P blocks for each M bits.
  • the fixed value insertion unit 11 compares the column weights of each column of the parity check matrix corresponding to each block of the L + K bit encoding target bit sequence.
  • the fixed value insertion unit 11 fixes the information bit sequence so that a K bit fixed value is preferentially included in a block with a small column weight of the corresponding check matrix among the P blocks obtained by the division.
  • a bit sequence to be encoded is generated by inserting a value.
  • inserting a K-bit fixed value into an L-bit information bit sequence and including a K-bit fixed value in an L + K-bit encoding target bit sequence are the same. is there. In FIG.
  • the fixed value insertion unit 11 divides an L + K bit encoding target bit sequence into P blocks every M bits in order from the top, and inserts a fixed value of K bits. It is a figure which shows an example.
  • the column weight of the parity check matrix corresponding to each block has a fixed value, specifically, a value based on the number of '1's included in each column of the parity check matrix corresponding to each block. become.
  • the column weights of the parity check matrix corresponding to each of the P blocks are W1, W2,... WP in order from the top, and the column weights are W1 ⁇ W2 ⁇ . WP.
  • the fixed value insertion unit 11 inserts a K-bit fixed value into the first M-bit block # 1 having the smallest column weight of the parity check matrix.
  • the column weight of the parity check matrix corresponding to each block may be simply referred to as the column weight of each block.
  • the encoding unit 12 performs an encoding process by QC-LDPC on the L + K bit encoding target bit sequence generated by the fixed value insertion unit 11 using the L + K rows and N columns check matrix described above. (Step S12).
  • the encoding unit 12 outputs the L + K bit encoding target bit sequence input from the fixed value insertion unit 11 as it is, adds the calculated check bit to the end of the L + K bit encoding target bit sequence, and outputs it.
  • FIG. 3C illustrates a bit sequence that is encoded by the encoding process by the encoding unit 12 and a check bit is added to the encoding processing target bit sequence. “Encoding process” between FIG. 3B and FIG. 3C indicates the processing content of the encoding unit 12.
  • the transmission sequence generation unit 13 When the length of the transmission sequence transmitted to the communication path 20, that is, the number of bits is defined in advance, the transmission sequence generation unit 13 is fixed among the bit sequences in which the check bit is added to the encoding processing target bit sequence. Data corresponding to the bit position into which the value has been inserted is deleted preferentially (step S13). The transmission sequence generation unit 13 generates a transmission sequence having a specified length.
  • FIG. 3D shows a transmission sequence generated by data deletion by the transmission sequence generation unit 13. “Data deletion (transmission sequence generation)” between FIG. 3C and FIG. 3D indicates the processing content of the transmission sequence generation unit 13.
  • the transmission sequence generation unit 13 deletes all the inserted fixed values, and further, some bits of the information bit sequence, Alternatively, some bits of the check bit are deleted.
  • the modulation unit 14 performs modulation processing on the transmission sequence generated by the transmission sequence generation unit 13 (step S14). Specifically, the modulation unit 14 performs mapping processing on the transmission sequence in accordance with a modulation method defined in advance. Examples of the modulation method include, but are not limited to, BPSK (Binary Phase Shift Keying) and QPSK (Quadrature Phase Shift Keying).
  • the modulation unit 14 transmits the transmission sequence after the modulation processing to the reception device 30 via the communication path 20.
  • the receiving device 30 includes a demodulator 31, a frame generator 32, a decoder 33, and a puncture unit 34.
  • the demodulator 31 performs a demodulation process corresponding to the modulation process of the modulator 14 of the transmission device 10 on the received signal, and generates soft decision information.
  • the received signal is a signal that the demodulator 31 receives the transmission sequence transmitted from the transmission device 10 through the communication path 20.
  • the frame generation unit 32 inserts a fixed value into the bit position from which data has been deleted by the transmission sequence generation unit 13 of the transmission apparatus 10 with respect to the soft decision information generated by the demodulation unit 31.
  • the decoding unit 33 performs a decoding process corresponding to the encoding process of the encoding unit 12 of the transmission device 10 on the soft decision information in which the fixed value is inserted by the frame generation unit 32, and generates a hard decision decoding result. .
  • the puncture unit 34 deletes the data corresponding to the bit position where the fixed value is inserted by the fixed value insertion unit 11 of the transmission device 10 from the hard decision decoding result generated by the decoding unit 33, and generates a decoding result.
  • FIG. 5 is a flowchart showing a reception process of the reception device 30 according to the first embodiment.
  • the demodulator 31 performs a demodulation process on the received signal (step S21). Specifically, the demodulator 31 obtains the distance between the position of the received signal point and each signal point defined by the modulation method for the received signal, and the hard decision value is 0 for each bit of the received signal. A certain likelihood and a likelihood with a hard decision value of 1 are calculated, and soft decision information for each bit is generated from the likelihood ratio.
  • the frame generation unit 32 inserts a fixed value into the bit position from which data has been deleted by the transmission sequence generation unit 13 of the transmission device 10 with respect to the soft decision information generated by the demodulation unit 31 (step S22).
  • the frame generation unit 32 sets the reliability, that is, the likelihood of the portion where the fixed value is inserted to the maximum value.
  • the frame generation unit 32 converts the reception signal demodulated by the demodulation unit 31 using soft decision information to generate a reception frame. Specifically, the frame generation unit 32 converts the portion of the received signal whose likelihood is calculated by the demodulation unit 31 into soft decision information having the largest likelihood.
  • the received frame corresponds to an L + K-bit encoding process target bit sequence that is an encoding process target in the encoding unit 12 of the transmission apparatus 10.
  • the decoding unit 33 uses the same check matrix as the check matrix used by the encoding unit 12 of the transmission apparatus 10 for the reception frame generated by the frame generation unit 32, and performs a repeated decoding process a predetermined number of times. Is performed (step S23).
  • the decoding unit 33 is an information bit sequence in which a fixed value is inserted, that is, an L + K bit encoding target bit sequence generated by the fixed value insertion unit 11 of the transmission device 10 illustrated in FIG. A hard decision decoding result corresponding to is generated.
  • the puncturing unit 34 deletes data corresponding to the bit position where the fixed value is inserted by the fixed value insertion unit 11 of the transmission device 10 from the hard decision decoding result generated by the decoding unit 33 (step S24).
  • the puncturing unit 34 generates and outputs a result obtained by deleting data from the hard decision decoding result as a decoding result.
  • the transmission apparatus 10 inserts a fixed value into a portion with a small column weight of the check matrix of the QC-LDPC code for the input information bit sequence.
  • the transmission apparatus 10 can reduce the possibility of overflow by inserting a fixed value as described above. Since the receiving device 30 can reduce the possibility of overflow, that is, the possibility of performance deterioration, the decoding performance can be improved as a result.
  • the fixed value insertion unit 11 the encoding unit 12, the transmission sequence generation unit 13, and the modulation unit 14 are realized by a processing circuit.
  • the processing circuit may be dedicated hardware, or the processor may execute a program stored in the memory.
  • FIG. 6 is a diagram illustrating an example when the processing circuit included in the transmission device 10 according to the first embodiment is configured with dedicated hardware.
  • the processing circuit 91 shown in FIG. 6 includes, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), An FPGA (Field Programmable Gate Array) or a combination of these is applicable.
  • the function of each component of the transmission apparatus 10 may be realized by the processing circuit 91 for each function, or the function of each component may be realized by the processing circuit 91 collectively.
  • FIG. 7 is a diagram illustrating an example in which the processing circuit included in the transmission device 10 according to the first embodiment is configured with a processor and a memory.
  • the processing circuit includes the processor 92 and the memory 93
  • each function of the processing circuit of the transmission device 10 is realized by software, firmware, or a combination of software and firmware.
  • Software or firmware is described as a program and stored in the memory 93.
  • each function is realized by the processor 92 reading and executing the program stored in the memory 93. That is, the processing circuit includes a memory 93 for storing a program that results in the processing of the transmission device 10 being executed.
  • these programs are what makes a computer perform the procedure and method of the transmitter 10.
  • the processor 92 may be a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, a DSP (Digital Signal Processor), or the like.
  • the memory 93 is a non-volatile or volatile memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM).
  • RAM Random Access Memory
  • ROM Read Only Memory
  • flash memory EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM).
  • Semiconductor memory magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disc), etc. are applicable.
  • each function of the transmission device 10 may be realized by dedicated hardware, and a part may be realized by software or firmware.
  • the processing circuit can realize the above-described functions by dedicated hardware, software, firmware, or a combination thereof.
  • the hardware configuration of the transmission device 10 has been described, the hardware configuration of the reception device 30 is the same. That is, in the receiving device 30, the demodulation unit 31, the frame generation unit 32, the decoding unit 33, and the puncture unit 34 are realized by a processing circuit.
  • the processing circuit may be dedicated hardware as shown in FIG. 6, or the processor may execute a program stored in the memory as shown in FIG.
  • transmission apparatus 10 has a bit length of a bit sequence to be encoded by QC-LDPC having an input information bit sequence of L bits and a code length of N.
  • L + K bits a check matrix of L + K rows and N columns can be divided into sub-matrices of M rows and M columns, and an encoding target bit sequence of L + K bits can be divided into P blocks for each M bits
  • Encoding processing is performed by preferentially inserting a fixed value of K bits from an encoding processing target bit sequence block corresponding to a block having a small column weight of a parity check matrix with respect to an input L-bit information bit sequence.
  • the transmission apparatus 10 generates a transmission sequence by preferentially deleting data corresponding to the bit position where the fixed value is inserted from the bit sequence in which the check bit is added to the encoding processing target bit sequence, and transmits the transmission sequence. It was decided. Thereby, the transmitter 10 can generate a transmission sequence that can improve the decoding performance of the receiver 30 while suppressing the processing load.
  • Embodiment 2 FIG. In the first embodiment, the case has been described where the number of fixed-value bits K to be inserted by the transmission apparatus 10 is smaller than M of the number of rows and the number of columns of the small matrix obtained by dividing the check matrix. In the second embodiment, a case will be described in which the number of fixed-value bits K inserted by transmitting apparatus 10 is larger than the number of rows and the number of columns of the sub-matrix of the parity check matrix.
  • the configuration of the wireless communication system 40 is the same as that of the wireless communication system 40 of the first embodiment shown in FIG.
  • the second embodiment is different from the first embodiment in the content of step S11 in which a K-bit fixed value is inserted into an L-bit information bit sequence in the transmission processing of the transmission apparatus 10 shown in FIG.
  • FIG. 8 is a diagram illustrating an example of inserting a K-bit fixed value when M ⁇ K ⁇ 2M in the fixed value insertion unit 11 according to the second embodiment.
  • the fixed value insertion unit 11 when M ⁇ K ⁇ 2M, the fixed value insertion unit 11 inserts an M-bit fixed value into all the bits of the first M-bit block # 1 having the smallest column weight. . Also, the fixed value insertion unit 11 inserts the remaining KM bits of fixed values into the second M bit block # 2 that has the next smallest column weight.
  • K> M the fixed value insertion unit 11 inserts an M-bit fixed value into the block having the smallest column weight when the number of blocks having the smallest column weight is one, and then the column weight. A fixed value of KM bits is inserted into a small block.
  • transmission apparatus 10 preferentially assigns a fixed value to a block with a small column weight even when M ⁇ K ⁇ 2M. Similarly, it is possible to reduce the possibility of overflow in the decoding process of the receiving device 30 and generate a transmission sequence that can improve the decoding performance of the receiving device 30.
  • Embodiment 3 FIG. In the second embodiment, the case has been described where the number of fixed-value bits K inserted by the transmission apparatus 10 is larger than the number of rows and the number of columns of the sub-matrix of the parity check matrix. In Embodiment 3, the number of fixed-value bits K inserted by transmitting apparatus 10 is larger than M of the number of rows and columns of the sub-matrix of the parity check matrix, and M bits that have the smallest column weights. A case where there are a plurality of blocks will be described.
  • the configuration of the wireless communication system 40 is the same as that of the wireless communication system 40 of the first embodiment shown in FIG. Embodiment 3 differs from Embodiments 1 and 2 in the content of step S11 for inserting a fixed value of K bits into an L-bit information bit sequence in the transmission processing of transmitting apparatus 10 shown in FIG.
  • FIG. 9 is a diagram illustrating a first insertion example of a fixed value of K bits when M ⁇ K ⁇ 2M in the fixed value insertion unit 11 according to the third embodiment.
  • the first M-bit block # 1 and the second M-bit block # 2 are the blocks having the smallest column weight values.
  • the fixed value insertion unit 11 applies to each of the first M-bit block # 1 and the second M-bit block # 2 having the smallest column weight.
  • K is an even number.
  • FIG. 10 is a diagram illustrating a second insertion example of a fixed value of K bits when M ⁇ K ⁇ 2M in the fixed value insertion unit 11 according to the third embodiment.
  • the column weight of each block is the same as the condition of FIG. 9, and M ⁇ K ⁇ 2M.
  • the fixed value insertion unit 11 inserts an M-bit fixed value into all the bits of the first M-bit block # 1 having the smallest column weight as in the second embodiment. Further, the fixed value insertion unit 11 inserts the remaining KM bits of fixed values into the second M bit block # 2 which is another block having the smallest column weight.
  • the fixed value insertion unit 11 selects K bits from the 2M bits of the block # 1 and the block # 2 having the smallest column weight, and inserts a fixed value at the position of the selected K bits. Similar effects can be obtained.
  • K> M the fixed value insertion unit 11 has R blocks having the smallest column weight, and when M ⁇ R ⁇ K, the M ⁇ R bits of the R blocks having the smallest column weight are K bits from the M ⁇ R bits. And a fixed value is inserted into the selected K bits.
  • R is a positive integer.
  • transmission apparatus 10 gives priority to a fixed value for a block with a small column weight even when there are a plurality of blocks with the smallest column weight and M ⁇ K ⁇ 2M.
  • it is possible to reduce the possibility of overflow in the decoding process of the receiving device 30, and to generate a transmission sequence that can improve the decoding performance of the receiving device 30.
  • Embodiment 4 FIG.
  • the case has been described in which the smallest number of column weights is two and the number of fixed value bits K inserted by the transmission apparatus 10 is M ⁇ K ⁇ 2M.
  • the fourth embodiment a case will be described in which the smallest number of column weights is two and the number of fixed value bits K inserted by the transmission apparatus 10 is 2M ⁇ K.
  • the configuration of the wireless communication system 40 is the same as that of the wireless communication system 40 of the first embodiment shown in FIG.
  • FIG. 11 is a diagram illustrating an example of inserting a K-bit fixed value in the case of 2M ⁇ K ⁇ 3M in the fixed value insertion unit 11 according to the fourth embodiment.
  • the first M-bit block # 1 and the second M-bit block # 2 are the blocks having the smallest column weight value.
  • the fixed value insertion unit 11 applies to each of the first M-bit block # 1 and the second M-bit block # 2 having the smallest column weight.
  • a fixed value of M bits is inserted.
  • the fixed value insertion unit 11 inserts the remaining fixed value of K-2M bits into the third block # 3 that has the next smallest column weight.
  • the fixed value insertion unit 11 has R blocks with the smallest column weight, and when M ⁇ R ⁇ K, each of the R blocks with the smallest column weight has an M-bit fixed value. Then, a fixed value of KM ⁇ R bits is inserted into a block having a small column weight. Note that R is a positive integer.
  • transmission apparatus 10 gives priority to a fixed value for a block having a small column weight even when there are a plurality of blocks having the smallest column weight and 2M ⁇ K ⁇ 3M.
  • it is possible to reduce the possibility of overflow in the decoding process of the receiving device 30, and to generate a transmission sequence that can improve the decoding performance of the receiving device 30.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
  • 10 transmission device 11 fixed value insertion unit, 12 encoding unit, 13 transmission sequence generation unit, 14 modulation unit, 20 communication path, 30 reception device, 31 demodulation unit, 32 frame generation unit, 33 decoding unit, 34 puncture unit, 40 Wireless communication system.

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Abstract

Selon l'invention, un appareil de transmission comprend : une unité d'insertion de valeur fixe (11) qui, lorsqu'une matrice de contrôle à L + K lignes et N colonnes permettant d'encoder une séquence de bits à encoder constituée d'une séquence de bits d'information de L bits et d'une valeur fixe de K bits peut être divisée en sous-matrices à M lignes et M colonnes, insère la valeur fixe dans la séquence de bits d'information et produit la séquence de bits à encoder de sorte que la valeur fixe de K bits soit comprise préférentiellement dans un bloc, parmi des blocs obtenus par division de la séquence de bits à encoder en P blocs de M bits chacun, dans lequel la pondération de colonne de la matrice de contrôle correspondante est faible ; une unité d'encodage (12) qui soumet la séquence de bits à encoder à un processus d'encodage grâce à un code de contrôle de parité de faible densité pseudocyclique utilisant la matrice de contrôle ; et une unité de production de séquence de transmission (13) qui produit une séquence de transmission en effaçant préférentiellement, de la séquence de bits qui a été obtenue grâce au processus d'encodage dans l'unité d'encodage (12) et par l'ajout d'un bit de contrôle à la séquence de bits à encoder, des données correspondant à une position de bit à laquelle la valeur fixe a été insérée.
PCT/JP2018/022070 2018-06-08 2018-06-08 Appareil de transmission, appareil de réception et procédé d'encodage WO2019234923A1 (fr)

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JP2018556945A JPWO2019234923A1 (ja) 2018-06-08 2018-06-08 送信装置、受信装置および符号化方法

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