WO2019233217A1 - 一种可重构的低功耗低成本支持多频多模的接收机前端 - Google Patents

一种可重构的低功耗低成本支持多频多模的接收机前端 Download PDF

Info

Publication number
WO2019233217A1
WO2019233217A1 PCT/CN2019/084659 CN2019084659W WO2019233217A1 WO 2019233217 A1 WO2019233217 A1 WO 2019233217A1 CN 2019084659 W CN2019084659 W CN 2019084659W WO 2019233217 A1 WO2019233217 A1 WO 2019233217A1
Authority
WO
WIPO (PCT)
Prior art keywords
resonance
cascode
circuit
low
tube
Prior art date
Application number
PCT/CN2019/084659
Other languages
English (en)
French (fr)
Inventor
冯海刚
曹鹏益
幸新鹏
Original Assignee
清华大学深圳研究生院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 清华大学深圳研究生院 filed Critical 清华大学深圳研究生院
Publication of WO2019233217A1 publication Critical patent/WO2019233217A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Definitions

  • the present invention relates to wireless communication technology, and in particular to a reconfigurable low-power-consumption low-cost receiver front-end that supports multi-frequency and multi-mode.
  • Receiver chips that implement multi-standard, multi-frequency and multi-mode receivers on a single chip can be divided into two categories: one is a wideband receiver, as shown in Figure 1, reference J. Kim and J. Silva-Martinez, "Low -Power, Low-Cost, CMOS, Direct-Conversion, Receiver, Multi-standard Applications, "in IEEE Journal of Solid-State Circuits, vol. 48, no. 9, pp. 2090-2103, Sep. 2013. This 2013 JSSC introduced a wideband receiver front-end architecture with a frequency band of 1.4G-5.2G.
  • the RF input signal is amplified by a broadband low-noise amplifier and mixed with the local oscillator signal to convert the RF signal into a baseband signal. Then, the current signal is converted into a current-voltage amplifier (TIA) with a filter function. Voltage signals and filter out high frequency interference signals.
  • TIA current-voltage amplifier
  • This circuit can process signals in a very wide frequency band, but there are disadvantages that the circuit is not reconfigurable and can not meet multiple applications at the same time; at the same time, in order to ensure the performance of the entire frequency band, more power is often consumed and the overall performance index is not as good as that of a single frequency Receiver.
  • the other type is a multi-link receiver, as shown in Figure 2.
  • This 2016 ISCAS proposes a low-power receiver that can process both 2.4GHz and 5.2GHz signals. From the block diagram of our structure, we It can be seen that the RF signal is sent to the low-noise amplifier (LNA) through the antenna, and then the signal is processed separately.
  • the low-noise amplifier (LNA) can amplify 2.4G and 5.2G signals at the same time.
  • the LNA schematic diagram contains 6 inductors, occupying a large area. At the same time, multiple inductors are easily interfered with each other and coupled, which increases the system. Design complexity. This circuit can process signals in two frequency bands at the same time; however, a large amount of inductance is used in the LNA design, which wastes chip area; it cannot be reconfigured, causing some modules to be repeatedly configured.
  • FIG. 3 One of the prior art low-noise amplifier circuit (LNA) structure diagrams is shown in FIG. 3, which includes a primary coil S11 and a secondary coil S12. A resonant capacitor C1 is connected in parallel at both ends of the secondary coil S12 to form a resonant circuit.
  • the value of the stage coil S12 and the resonance capacitor C1 determine the first resonance frequency, and thus determine which frequency band the low-noise amplifier circuit (LNA) can receive, and one end of the resonance circuit is connected to the first common source of the first common source cascode amplifier circuit.
  • the other end of the gate of the transistor M1 is connected to the gate of the second common source tube M3 of the second cascode amplifier circuit.
  • the source of the first common source tube M1 is connected to one end of the source negative feedback inductor L1.
  • the drain of the source tube M1 is connected to the source of the first cascode tube M2, the drain of the first cascode tube M2 is connected to one end of the drain load inductor L2, the gate of the first cascode tube M2 is connected to the power source VDD, and the second The source of the common source tube M3 is connected to the other end of the source negative feedback inductor L1, the drain of the second common source tube M3 is connected to the source of the second common gate tube M4, and the drain of the second common source tube M4 is connected to the drain The other end of the load inductor L2, the gate of the second common-gate transistor M4 is connected to the power source VDD, the source The center tap in the middle of the negative feedback inductor L1 is connected to the ground terminal, the center tap in the middle of the drain load inductor L2 is connected to the power supply VDD, the two ends of the drain load inductor L2 are connected in parallel with
  • This kind of inductor negative feedback common source structure low noise amplifier has lower noise figure lower limit than common gate amplifier.
  • Using inductor and capacitor parallel resonance as the load of the amplifier can make the circuit work at higher frequency.
  • the DC voltage drop is smaller than the resistance.
  • Such a topology can still work when the power supply voltage is very low.
  • By adjusting the input inductance and capacitance you can achieve good matching at a specific frequency.
  • the disadvantage of this circuit is that it can only amplify RF signals in one frequency band.
  • FIG. 4 The second schematic diagram of the structure of a low-noise amplifier circuit (LNA) in the prior art is shown in FIG. 4.
  • a plurality of resonance capacitors C1, C2, and C3 are connected in parallel at both ends of the secondary coil S12, and each resonance The capacitor is connected in series with the strobe switch.
  • the low-noise amplifier circuit (LNA) is matched with RF signals in multiple frequency bands.
  • it is suitable for multi-band RF signals, but in fact, for different frequency bands, such as 900MHz, 1800MHz, and 2400MHz signals, the same secondary coil is used to resonate at 900MHz.
  • the capacitance value is resonant at 2400MHz.
  • the capacitance value is 7 times. Due to the parasitic effect of the capacitor, a small-sized switch is required to make this large capacitor have the smallest possible impact on the circuit. This means that the on-resistance of the switch is relatively large, which directly leads to the circuit. Noise performance deteriorates. If the switch size becomes larger when the circuit resonates at 900MHz, the circuit cannot resonate at 2.4GHz. In summary, if the circuit structure shown in FIG. 4 is used, the performance indicators of the three frequency bands cannot be satisfied at the same time.
  • the purpose of the present invention is to solve the problem that the front end of a receiver in the prior art is not reconfigurable and cannot implement multi-frequency multi-mode.
  • the present application provides a reconfigurable low-power-consumption receiver that supports multi-frequency multi-mode. front end.
  • a reconfigurable low-power low-cost receiver front end supporting multi-frequency and multi-mode includes a multi-band low-noise amplifier circuit; the input end of the multi-band low-noise amplifier circuit includes a primary coil and at least two secondary coils , Used to correspondingly convert single-ended radio frequency signals of at least three frequency bands into double-ended differential voltage signals.
  • the multi-band low-noise amplifier circuit includes a control unit, a selection unit, a resonance unit, and an amplification unit, the control unit is configured to issue a control signal, and the selection unit includes a plurality of selection channels to be used according to the control. The signal is conducted through different selection channels.
  • the resonance unit includes at least two secondary coils, and each secondary coil and a resonance capacitor form a resonance circuit. The resonance circuit is used to generate resonance for a specific frequency band radio frequency signal. For amplifying and outputting a resonance signal output from the resonance circuit.
  • the resonance unit further includes a primary coil for receiving single-ended radio frequency signals of multiple frequency bands, the secondary coil has a control end, and the control unit is connected to the control end of the secondary coil for controlling The secondary coil.
  • the resonance capacitor and the selection channel are connected in series to form a capacitance selection channel for gating different resonance capacitances in different frequency bands, and two ends of the secondary coil are connected in parallel with at least one of the capacitance selection channels.
  • the amplifying unit includes an amplifying circuit having a cascode structure, and two ends of the secondary coil are respectively connected to different common source tubes, and at least two common source tubes at the same end of the secondary coil are connected to A common grid tube.
  • the amplifying unit includes an amplifying circuit with a cascode structure.
  • the first cascode tube and the first cascode tube, the second cascode tube and the second cascode tube respectively form the first and second cascode devices.
  • Gate amplifier circuit; the two ends of the first resonance circuit are respectively connected to the gates of the first and second common source tubes of the first and second common source cascode amplifier circuits, and the source of the first and second common source tubes are connected
  • the first and second cascode amplifier circuits of the first and second cascode amplifier circuits are connected to the two ends of the drain load inductor, and a capacitor composed of the output resonance capacitor and the selection channel in series.
  • the two ends of the channel are selected; the source negative feedback inductance and the drain load inductance have center taps, the center tap of the source negative feedback inductance is grounded, and the center tap of the drain load is connected to the power terminal.
  • the amplifying unit further includes third and fourth common source tubes, the third common source tube and the first common grid tube, the fourth common source tube and the second common grid tube forming the third and fourth common source, respectively.
  • Common-gate amplifier circuit the two ends of the second resonance circuit are respectively connected to the gates of the third and fourth common-source tubes of the third and fourth common-source cascode circuits, and the sources of the third and fourth common-source tubes Connect the two ends of the source negative feedback inductor; the first and second cascode drains of the third and fourth cascode amplifier circuits are connected to the drain load inductor, the output resonant capacitor and the selection channel of the capacitor selection channel in series
  • the source negative feedback inductor and the drain load inductor have a center tap, the center tap of the source negative feedback inductor is grounded, and the center tap of the drain load inductor is connected to the power supply terminal.
  • both ends of the drain load inductor are connected in parallel with at least one capacitor selection channel.
  • the plurality of resonance frequencies formed by the drain load inductance and the parallel capacitor are matched with the resonance frequencies of the first and second resonance circuits, respectively.
  • the second resonance circuit has at least two resonance frequencies.
  • the reconfigurable, multi-frequency and multi-mode receiver front end adopts a primary coil and multiple secondary coils.
  • Each secondary coil is controlled by a different control signal, and multiple resonances are connected in parallel at both ends of each secondary coil.
  • Capacitance, each resonance capacitor is controlled by a control signal.
  • the front end of the reconfigurable receiver supporting multi-frequency and multi-mode of the present invention realizes multi-frequency by a plurality of coils and capacitors, which reduces the cost.
  • the multi-frequency low-noise amplifier of the present invention adopts a cascode structure and improves the gain of the front end of the receiver.
  • the transformer structure of the multi-secondary coil of the present invention can eliminate the adverse effect of the capacitance parasitic effect on the circuit in the resonance circuit. At the same time, it also solves the problem that the same inductor cannot maintain a high Q value in a wide frequency band, so that the circuit can have better performance in multiple frequency bands.
  • FIG. 1 is a schematic diagram of the overall structure of a wideband receiver
  • FIG. 2 is a schematic diagram of an overall structure of a multi-link receiver
  • FIG. 3 is a schematic diagram of a prior art low noise amplifier circuit structure
  • FIG. 4 is a schematic structural diagram of a conventional multi-band low-noise amplifier circuit
  • FIG. 5 is a schematic diagram of the overall structure of a receiver of the present invention.
  • FIG. 6 is a schematic structural diagram of a transformer at the front end of the receiver of the present invention.
  • FIG. 7 is a schematic structural diagram of a multi-band low-noise amplifier at the front end of a receiver according to the present invention.
  • FIG. 8 is a schematic structural diagram of a multi-band low-noise amplifier circuit at the front end of a receiver according to the present invention.
  • FIG. 9 is a schematic structural diagram of a state of a multi-band low-noise amplifier circuit at the front end of a receiver according to the present invention.
  • FIG. 10 is a schematic structural diagram of a state of a multi-band low-noise amplifier circuit at the front end of a receiver of the present invention.
  • FIG. 5 A schematic diagram of the overall structure of the receiver of the present invention is shown in FIG. 5 and includes a multi-band low noise amplifier (LNA), a buffer circuit, a mixer circuit (Mixer), a TIA circuit, and an LPF circuit.
  • the signal is converted into a double-ended differential voltage signal with high gain and low noise.
  • the buffer circuit is used to convert the differential voltage signal into a differential current signal and is divided into two outputs.
  • the Mixer circuit is used to convert the duty cycle to 25% of the local oscillator.
  • the signal is mixed with the double-ended differential current signal to obtain a highly linear current signal.
  • the TIA circuit is used to convert the current signal into a voltage signal, and the voltage signal is amplified and filtered.
  • the LPF circuit is used to configure the bandwidth and filter. Out-of-band signals and output IF signals.
  • the multi-band low-noise amplifier circuit of the present invention includes a control unit 10, a selection unit 30, a resonance unit 20, and an amplification unit 40.
  • the control unit 10 is configured to issue a control signal.
  • the selection unit 30 includes Multiple selection channels are used to conduct different selection channels according to the control signal.
  • the resonance unit 20 includes at least two secondary coils, and each secondary coil and a resonance capacitor form a resonance circuit.
  • the radio frequency signal in a specific frequency band generates resonance; the amplifying unit 40 is configured to amplify and output a resonance signal output from the resonance circuit.
  • the resonance unit 20 is connected to the control unit 10, the selection unit 30, and the amplification unit 40.
  • the control unit 10 is also connected to the selection unit 30 at the same time.
  • Multi-band radio frequency signals are input to the resonance unit 20.
  • the control unit 10 controls the selection unit 30 to select the corresponding resonance capacitor.
  • the control resonance unit 20 selects a corresponding secondary coil, and the selected secondary coil and the resonance capacitor generate resonance in the radio frequency signal of the input frequency band, and amplify the signal in this frequency band through the amplification unit 40 to output a double-ended differential voltage signal.
  • the transformer structure diagram of the resonance unit 20 of the present invention includes a primary coil S1, two secondary coils S2, S3, a control terminal Vb1 in the middle of the secondary coil S2, and a control terminal in the middle of the secondary coil S3. Vb2.
  • the control terminals Vb1 and Vb2 are used to receive a control signal from the control unit 10, and decide to select the secondary coil S2 or the secondary coil S3 for resonance according to the control signal.
  • the multi-band low-noise amplifier circuit structure diagram of the present invention includes a primary coil S1, two secondary coils S2 and S3, and one end of the primary coil S1 receives a radio frequency signal and the other end is grounded.
  • the resonance capacitor C2 and the selection switch SW1 are connected in series to form a first capacitance selection channel.
  • the resonance capacitor C3 and the selection switch SW2 are connected in series to form a second capacitance selection channel.
  • the resonance capacitor C4 and the selection switch SW3 are connected in series to form a third capacitance selection channel.
  • the resonance capacitor C5 is connected to the selection.
  • the switch SW4 forms a fourth capacitor selection channel in series, and the resonance capacitor C6 and the selection switch SW5 form a fifth capacitor selection channel in series.
  • the selection unit 30 includes a plurality of selection switches SW1, SW2, SW3, SW4, and SW5.
  • the control unit 10 controls ON or OFF of the selection switches SW1, SW2, SW3, SW4, and SW5.
  • the resonance unit 20 includes a primary coil S1, two secondary coils S2, S3, a first capacitor selection channel connected in parallel with the secondary coil S2, and second and third capacitor selection channels connected in parallel with the secondary coil S3.
  • the secondary coil The control terminal Vb1 of S2 is connected to a control circuit (not shown), and the control terminal Vb2 of the secondary coil S3 is connected to a control circuit (not shown)
  • a first resonance circuit is formed, one end of which is connected to the gate of the first cascode tube M1 of the first cascode amplifier circuit, and the other end is connected.
  • the gate of the second cascode amplifier M3 of the second cascode amplifier circuit, the source of the first cascode M1, and the source of the second cascode M3 are connected to both ends of the source negative feedback inductance L1.
  • the negative terminal of the negative feedback inductor L1 is grounded, the drain of the first cascode M1 is connected to the source of the first cascode M2 of the first cascode amplifier circuit, and the drain of the second cascode M3 is connected to the first
  • the source of the second cascode tube M4 of the two cascode amplifier circuit, the drain of the first cascode tube M2 and the drain of the second cascode tube M4 are connected to both ends of the drain load inductor L2, and the drain load
  • the inductor L2, the third capacitor selection channel, the fourth capacitor selection channel, and the fifth capacitor selection channel are connected in parallel, and a differential voltage signal is derived from the two ends of the parallel connection.
  • the control circuit controls the operation of one of the at least two secondary coils, and controls the second capacitor selection channel and the third capacitor selection channel to be turned on at the same time or separately, so that the resonance frequency generated by the secondary coil and the resonance capacitor It matches the frequency of the input radio frequency signal; and the combination of at least two secondary coils and the resonance capacitor can resonate radio frequency signals in at least three frequency bands, thereby achieving the matching of multi-band and multi-mode radio frequency signals.
  • the control circuit controls at least one of the third capacitor selection channel, the fourth capacitor selection channel, and the fifth capacitor selection channel to be turned on, so that the resonance frequency generated by the drain load inductance L2 and the resonance capacitor matches the frequency generated by the resonance circuit, and further Achieve low-noise amplification of multi-band RF signals.
  • the gate of the fourth common source tube M6, the source of the third common source tube M5, and the source of the fourth common source tube M6 are connected to both ends of the source negative feedback inductance L1, and the source negative feedback inductance L1
  • the middle lead-out terminal is grounded, the drain of the third common source transistor M5 is connected to the source of the first common source transistor M2 of the first common source cascode amplifier circuit, and the drain of the fourth common source transistor M6 is connected to the second common source transistor.
  • the source of the second cascode transistor M4 of the gate amplifier circuit, the drain of the first cascode transistor M2, and the drain of the second cascode transistor M4 are connected to both ends of the drain load inductance L2, the drain load inductance L2, the first The three capacitor selection channel, the fourth capacitor selection channel, and the fifth capacitor selection channel are connected in parallel, and a double-ended differential voltage signal is derived from the two ends of the parallel connection.
  • the grid terminal of the first cascode transistor M2, the grid of the second cascode transistor M4, and the middle lead-out terminal of the drain load inductance L2 are connected to the power supply terminal.
  • At least two common source tubes on the same side of the secondary pole coil are connected to the source of the same common grid tube, which reduces the number of common grid tubes and reduces the cost.
  • the control circuit controls Vb1 to a fixed voltage value and Vb2 is grounded.
  • Vb1 the first common source tube M1 connected to it Electrode
  • the gate of the second common source tube M3 is grounded, the first common source tube M1, the second common source tube M3 is in an off state, and the gate of the third common source tube M5 and the The grids of the four common source tubes M6 are connected to a fixed voltage value.
  • the third common source tube M5 and the fourth common source tube M6 are in an on state.
  • the second resonant circuit works and the circuit resonates in the first frequency band. Accordingly, the amplifier circuit The frequency band matches the frequency band of the second resonance circuit to increase the output impedance.
  • the fifth capacitor selection channel is turned on, and the third and fourth capacitor selection channels are turned off. Its working mode is shown in Figure 9.
  • the control circuit controls Vb2 to a fixed voltage value, Vb1 is grounded, and the secondary coil S2 is connected to the third common source tube M5 because the control terminal is grounded.
  • the grid of the fourth common source tube M6 is grounded, the third common source tube M5 and the fourth common source tube M6 are in the off state, and the grid of the first common source tube M1 connected to the two ends of the secondary coil S3.
  • the gate of the second common source tube M3 is connected to a fixed voltage value.
  • the first common source tube M1 and the second common source tube M3 are in an on state. At this time, there are two working modes:
  • the first mode the control circuit controls the second capacitor selection channel to be turned on, the third capacitor selection channel is turned off, and the first resonance circuit works in the second frequency band. Accordingly, the frequency band of the amplifier circuit is matched with the second frequency band to increase Large output impedance, the fourth capacitor selection channel is on, and the third and fifth capacitor selection channels are off. Its working mode is shown in Figure 10.
  • the second mode the control circuit controls the third capacitor selection channel to be turned on, the second capacitor selection channel is turned off, and the first resonance circuit works in the third frequency band. Accordingly, the frequency band of the amplification circuit is matched with the third frequency band to increase Large output impedance, the third capacitor selection channel is on, and the fourth and fifth capacitor selection channels are off.
  • two or more capacitor selection channels can be in a conducting state at the same time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

本发明公开了一种可重构的低功耗低成本支持多频多模的接收机前端，包括多频段低噪声放大电路；所述多频段低噪声放大电路输入端包括一个初级线圈和至少二个次级线圈，对于不同频段的射频信号，选择不同的次级线圈及谐振电容进行匹配，从而对不同频段的射频信号产生谐振放大，将至少三个频段的单端射频信号对应转化为差分信号，从而抑制共模噪声，一个初级线圈和两个次级线圈的变压器结构，可以很好的实现多频段输入端的匹配和低噪声性能。

Description

一种可重构的低功耗低成本支持多频多模的接收机前端 技术领域
本发明涉及无线通信技术，尤其涉及一种可重构的低功耗低成本支持多频多模的接收机前端。
背景技术
随着移动通信技术的发展，低功耗、低成本、支持多模多频的单芯片设计成为主流。在单颗芯片上实现多标准的多频多模的接收机芯片可以分为两类：一类为宽带接收机，如图1所示，参考文献J.Kim and J.Silva-Martinez,"Low-Power,Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications,"in IEEE Journal of Solid-State Circuits,vol.48,no.9,pp.2090-2103,Sept.2013.这篇2013年的JSSC介绍了一种频带范围为1.4G-5.2G的宽带接收机前端架构。射频输入信号经过宽带低噪声放大器放大之后与本振信号相混频，将射频信号转化为基带信号，然后再通过具有带滤波功能的将电流转换为电压的放大器(TIA)，将电流信号转换为电压信号并滤掉高频干扰信号。该电路可以处理很宽频带的信号，但存在电路不可重构，不能同时满足多种应用的缺点；同时为了保证整个频带的性能，往往需要消耗更多的功耗而且整体性能指标不如单个频率的接收机。
另一类为多链路接收机，如图2所示，参考文献H.S.Hsu,Q.Y.Duan and Y.T.Liao,"A low power 2.4/5.2GHz concurrent receiver using current-reused architecture,"2016IEEE International Symposium on Circuits and Systems(ISCAS),Montreal,QC,2016,pp.1398-1401.这篇2016年的ISCAS中提出了一种可以同时处理2.4GHz和5.2GHz信号的低功耗接收机，从其结构框图中我们可以看到射频信号经过天线送入低噪声放大器(LNA)，之后信号被分别两路，分别进行处理。其中低噪声放大器(LNA)可以同时放大2.4G和5.2G信号，LNA原理图中包含了6个电感，占用了较大的面积，与此同时多电感之间很容易相互干扰耦合，增加了系统设计的复杂性。该电路可以同时处理两个频段的信号；但是LNA设计中使用了大量电感，浪费芯片面积；不可重构，造成一些模块重复配置。
现有技术的低噪声放大器电路(LNA)结构示意图之一如图3所示，包括一个初级线圈S11和一个次级线圈S12，在次级线圈S12的两端并联谐振电容C1组成谐振电路，次级线圈S12与谐振电容C1的数值决定了第一谐振频率，从而决定低噪声放大器电路(LNA)能接收那个频段的射频信号，谐振电路一端连接第一共源共栅放大电路的第一共源管M1的栅极，另一端连接第二共源共栅放大电路的第二共源管M3的栅极，第一共源管M1的源极连接源极负反馈电感L1的一端，第一共源管M1的漏极连接第一共栅管M2的源极，第一共栅管M2的漏极连接漏极负载电感L2的一端，第一共栅管M2的栅极连接电源VDD，第二共源管M3的源极连接源极负反馈电感L1的另一端，第二共源管M3的漏极连接第二共栅管M4的源极，第二共栅管M4的漏极连接漏极负载电感L2的另一端，第二共栅管M4的栅极连接电源VDD，源极负反馈电感L1中间的中心抽头接地端，漏极负载电感L2中间的中心抽头接电源VDD，漏极负载电感L2的两端并联谐振电容C2，漏极负载电感L2与谐振电容C2的数值决定了第二谐振频率，第二谐振频率与第一谐振频率匹配。此种电感负反馈共源级结构低噪声放大器比共栅级放大器具有更低的噪声系数下限，使用电感和电容并联谐振作为放大器的负载可以使电路工作在更高的频率，同时由于加在电感上的直流压降比电阻更小，这样的拓扑结构在电源电压非常低时仍可工作。通过调节输入端电感、电容可以实现在某个特定频率的良好匹配。此电路的缺点是只能对一个频段的射频信号进行放大。
现有技术的低噪声放大器电路(LNA)结构示意图之二如图4所示，与图3不同的是，在次级线圈S12的两端并联多个谐振电容C1、C2、C3，每一谐振电容与选通开关串联连接，通过选择不同的谐振电容与次级线圈S12组合，从而组成多个谐振电路，使低噪声放大器电路(LNA)与多个频段的射频信号匹配，从而此种电路结构原理上适用于多频段的射频信号，但实际上对于不同的频段，如对于900MHz、1800MHz、2400MHz三个频段的信号进行处理，使用相同的次级线圈则谐振在900MHz的电容值是谐振在2400MHz电容值的7倍，由于电容存在寄生效应，要想使这个大电容对电路产生尽可能小的影响就需要一个很小尺寸的开关，这就意味着开关导通电阻比较大，这样直接导致电路噪声性能恶化。如果电路谐振在900MHz时的开关尺寸变大则会导致电路不能谐振在2.4GHz。综上 所述，如采用图4所示的电路结构则不能同时满足3个频段的性能指标。
发明内容
本发明的目的是为了解决现有技术的接收机前端不可重构、无法实现多频多模的问题，本申请提供了一种可重构的低功耗低成本支持多频多模的接收机前端。
为了解决上述技术问题，本申请采用如下技术方案：
一种可重构的低功耗低成本支持多频多模的接收机前端，包括多频段低噪声放大电路；所述多频段低噪声放大电路输入端包括一个初级线圈和至少二个次级线圈，用于将至少三个频段的单端射频信号对应转化为双端差分电压信号。
优选地，所述多频段低噪声放大电路包括控制单元、选择单元、谐振单元、放大单元，所述控制单元用于发出控制信号，所述选择单元包括多路选择通道，用于根据所述控制信号导通不同的选择通道，所述谐振单元包括至少二个次级线圈，每一次级线圈与谐振电容组成谐振电路，所述谐振电路用于对特定频段射频信号产生谐振；所述放大单元用于对所述谐振电路的输出的谐振信号进行放大输出。
优选地，所述谐振单元还包括一个初级线圈，用于接收多频段的单端射频信号，所述次级线圈具有控制端，所述控制单元连接所述次级线圈的控制端，用于控制所述次级线圈。
优选地，所述谐振电容与所述选择通道串联组成电容选择通道，用于在不同频段选通不同的谐振电容，所述次级线圈的两端与至少一个所述电容选择通道并联。
优选地，所述放大单元包括共源共栅结构的放大电路，所述次级线圈的两端分别连接不同的共源管，至少二个所述次级线圈同一侧端点的共源管连接同一个共栅管。
优选地，所述放大单元包括共源共栅结构的放大电路，第一共源管与第一共栅管、第二共源管与第二共栅管分别组成第一、第二共源共栅放大电路；第一所述谐振电路的两端分别连接第一、第二共源共栅放大电路的第一、第二共源管栅极，第一、第二共源管的源极连接源极负反馈电感的两端；第一、第二共源共栅 放大电路的第一、第二共栅管漏极连接漏极负载电感的两端、输出谐振电容与选择通道串联组成的电容选择通道的两端；所述源极负反馈电感、漏极负载电感具有中心抽头，所述源极负反馈电感的中心抽头接地，所述漏极负载的中心抽头接电源端。
优选地，所述放大单元还包括第三、第四共源管，第三共源管与第一共栅管、第四共源管与第二共栅管分别组成第三、第四共源共栅放大电路；第二所述谐振电路的两端分别连接第三、第四共源共栅放大电路的第三、第四共源管栅极，第三、第四共源管的源极连接源极负反馈电感的两端；第三、第四共源共栅放大电路的第一、第二共栅管漏极连接漏极负载电感、输出谐振电容与选择通道串联组成的电容选择通道的两端；所述源极负反馈电感、漏极负载电感具有中心抽头，所述源极负反馈电感的中心抽头接地，所述漏极负载电感的中心抽头接电源端。
优选地，所述漏极负载电感的两端与至少一路电容选择通道并联。
优选地，所述漏极负载电感与并联电容形成的多个谐振频率与分别与第一、第二所述谐振电路的谐振频率匹配。
优选地，第二所述谐振电路具有至少二个谐振频率。
与现有技术相比，本发明的有益效果为：
本发明的可重构、支持多频多模的接收机前端，采用一个初级线圈与多个次级线圈，各次级线圈由不同的控制信号进行控制，各次级线圈两端并联多个谐振电容，每个谐振电容由控制信号控制，当不同的线圈工作时，选择不同大小的谐振电容，使接收机前端谐振在不同的频段，实现多频多模重构。
进一步地，本发明的可重构、支持多频多模的接收机前端，由多个线圈与电容实现多频，降低了成本。
进一步地，本发明的多频低噪声放大器，采用共源共栅结构，提高了接收机前端的增益。
进一步地，本发明的多次级线圈的变压器结构，可以消除谐振电路中电容寄生效应对电路产生的不良影响。同时也解决了同一电感无法在很宽的频带范围内保持较高Q值的问题，使电路能在多个频段上都具有较好的性能。
附图说明
图1是宽带接收机的整体结构示意图；
图2是多链路接收机的整体结构示意图；
图3是现有技术的低噪声放大器电路结构示意图；
图4是现有技术的多频段低噪声放大器电路结构示意图；
图5是本发明接收机的整体结构示意图；
图6是本发明接收机前端的变压器结构示意图；
图7是本发明接收机前端的多频段低噪声放大器结构示意图；
图8是本发明接收机前端的多频段低噪声放大器电路结构示意图；
图9是本发明接收机前端的多频段低噪声放大器电路状态一结构示意图；
图10是本发明接收机前端的多频段低噪声放大器电路状态一结构示意图。
具体实施方式
下面结合具体实施方式并对照附图对本发明做进一步详细说明。其中相同的附图标记表示相同的部件，除非另外特别说明。应该强调的是，下述说明仅仅是示例性的，而不是为了限制本发明的范围及其应用。
本发明的接收机的整体结构示意图如图5所示，包括多频段低噪声放大器(LNA),buffer电路、混频电路(Mixer)、TIA电路、LPF电路，其中LNA电路用于将单端射频信号转化为高增益低噪声的双端差分电压信号，buffer电路用于把所述的差分电压信号转化为差分电流信号，并分为两路输出，Mixer电路用于将占空比25％本振信号与双端差分电流信号进行混频处理，得到线性度高的电流信号，TIA电路用于将电流信号转化为电压信号，并对电压信号进行放大及滤波，LPF电路用于配置带宽，滤除带外信号并输出中频信号。
本发明的多频段低噪声放大器电路，如图6所示，包括控制单元10、选择单元30、谐振单元20、放大单元40，所述控制单元10用于发出控制信号，所述选择单元30包括多路选择通道，用于根据所述控制信号导通不同的选择通道，所述谐振单元20包括至少二个次级线圈，每一次级线圈与谐振电容组成谐振电路，所述谐振电路用于对特定频段射频信号产生谐振；所述放大单元40用于对所述谐振电路的输出的谐振信号进行放大输出。
谐振单元20与控制单元10、选择单元30、放大单元40连接，控制单元10同时与选择单元30连接，多频段射频信号输入到谐振单元20，控制单元10控制选择单元30选择对应的谐振电容，控制谐振单元20选择对应的次级线圈，被选中的次级线圈和谐振电容对输入频段的射频信号产生谐振，经过放大单元40对此频段信号的放大，输出双端差分电压信号。
如图7所示为本发明的谐振单元20中变压器结构图，包括一个初级线圈S1，二个次级线圈S2、S3，次级线圈S2中间的控制端Vb1，次级线圈S3中间的控制端Vb2，控制端Vb1、Vb2用于接收控制单元10的控制信号，根据控制信号决定选择次级线圈S2或次级线圈S3进行谐振。
如图8所示为本发明的多频段低噪声放大器电路结构图，包括一个初级线圈S1，二个次级线圈S2、S3，初级线圈S1一端接收射频信号另一端接地。
谐振电容C2与选择开关SW1串联组成第一电容选择通道，谐振电容C3与选择开关SW2串联组成第二电容选择通道，谐振电容C4与选择开关SW3串联组成第三电容选择通道，谐振电容C5与选择开关SW4串联组成第四电容选择通道，谐振电容C6与选择开关SW5串联组成第五电容选择通道。
选择单元30包括多个选择开关SW1、SW2、SW3、SW4、SW5。
控制单元10控制选择开关SW1、SW2、SW3、SW4、SW5的导通或断开。
谐振单元20包括一个初级线圈S1，二个次级线圈S2、S3，与次级线圈S2并联的第一电容选择通道，与次级线圈S3并联的第二、第三电容选择通道，次级线圈S2的控制端Vb1连接控制电路(图中未示出)、次级线圈S3的控制端Vb2连接控制电路(图中未示出)
次级线圈S3、第二电容选择通道、第三电容选择通道并联后，组成第一谐振电路，其一端连接第一共源共栅放大电路的第一共源管M1的栅极，另一端连接第二共源共栅放大电路的第二共源管M3的栅极，第一共源管M1的源极、第二共源管M3的源极连接源极负反馈电感L1的两端，源极负反馈电感L1中间引出端接地，第一共源管M1的漏极连接第一共源共栅放大电路的第一共栅管M2的源极，第二共源管M3的漏极连接第二共源共栅放大电路的第二共栅管M4的源极，第一共栅管M2的漏极、第二共栅管M4的漏极连接漏极负载电感L2的两端，漏极负载电感L2、第三电容选择通道、第四电容选择通道、第五电 容选择通道并联连接，由其并联的两端引出差分电压信号。
控制电路控制至少二个次级线圈中的一个工作，并控制第二电容选择通道、第三电容选择通道可以同时导通，也可以单独导通，从而使次级线圈与谐振电容产生的谐振频率与输入射频信号的频率匹配；并且至少二个次级线圈与谐振电容的组合，可对至少三个频段的射频信号进行谐振，实现了对多频段、多模式的射频信号的匹配。
控制电路控制第三电容选择通道、第四电容选择通道、第五电容选择通道中至少一个导通，从而使漏极负载电感L2与谐振电容产生的谐振频率与谐振电路产生的频率相匹配，进而实现对多频段射频信号的低噪声放大。次级线圈S2的两端与谐振电容C1并联后，组成第二谐振电路，其一端连接第三共源共栅放大电路的第三共源管M5的栅极，另一端连接第四共源共栅放大电路的第四共源管M6的栅极，第三共源管M5的源极、第四共源管M6的源极连接源极负反馈电感L1的两端，源极负反馈电感L1的中间引出端接地，第三共源管M5的漏极连接第一共源共栅放大电路的第一共栅管M2的源极，第四共源管M6的漏极连接第二共源共栅放大电路的第二共栅管M4的源极，第一共栅管M2的漏极、第二共栅管M4的漏极连接漏极负载电感L2的两端，漏极负载电感L2、第三电容选择通道、第四电容选择通道、第五电容选择通道并联连接，由其并联的两端引出双端差分电压信号。
第一共栅管M2的栅极、第二共栅管M4的栅极、漏极负载电感L2的中间引出端连接电源端。
至少二个次极线圈同一侧的共源管连接同一个共栅管的源极，减小了共栅管的数量，降低了成本。
因电感在集成电路中的面积很大，多个谐振电路共用放大电路中的漏极负载电感L2、源极负反馈电感L1，在减小了电感数量的同时减小了电路的体积，降低了成本。
如图8所示的多频段低噪声放大器电路，其工作模式分别如图9、10所示：
当电路需要工作在第一频段，如900MHz频段时，控制电路控制Vb1为一固定电压值，Vb2接地，此时，次级线圈S3因为控制端接地，与其连接的第一共源管M1的栅极、第二共源管M3的栅极接地，第一共源管M1、第二共源管 M3处于截止状态，与次级线圈S2两端连接的第三共源管M5的栅极、第四共源管M6的栅极接固定电压值，第三共源管M5、第四共源管M6处于导通状态，第二谐振电路工作，电路谐振在第一频段，相应地，放大电路的频段与第二谐振电路的频段相匹配，以增大输出阻抗，第五电容选择通道导通，第三、第四电容选择通道断开。其工作模式如图9所示。
当电路需要工作在第二、第三频段，如1800MHz、2400MHz频段时，控制电路控制Vb2为一固定电压值，Vb1接地，次级线圈S2因为控制端接地，与其连接的第三共源管M5的栅极、第四共源管M6的栅极接地，第三共源管M5、第四共源管M6处于截止状态，与次级线圈S3两端连接的第一共源管M1的栅极、第二共源管M3的栅极接固定电压值，第一共源管M1、第二共源管M3处于导通状态，此时分以下两种工作模式：
第一种模式：控制电路控制第二电容选择通道导通，第三电容选择通道断开，第一谐振电路工作在第二频段，相应地，放大电路的频段与第二频段相匹配，以增大输出阻抗，第四电容选择通道导通，第三、第五电容选择通道断开。其工作模式如图10所示。
第二种模式：控制电路控制第三电容选择通道导通，第二电容选择通道断开，第一谐振电路工作在第三频段，相应地，放大电路的频段与第三频段相匹配，以增大输出阻抗，第三电容选择通道导通，第四、第五电容选择通道断开。
更进一步的，电容选择通道可同时有二个或二个以上的处于导通状态。
以上内容是结合具体的优选实施方式对本实用新型所作的进一步详细说明，不能认定本实用新型的具体实施只局限于这些说明。对于本实用新型所属技术领域的技术人员来说，在不脱离本实用新型构思的前提下，还可以做出若干等同替代或明显变型，而且性能或用途相同，都应当视为属于本实用新型的保护范围。

Claims (10)

  1. 一种可重构的低功耗低成本支持多频多模的接收机前端，其特征在于，包括多频段低噪声放大电路；所述多频段低噪声放大电路输入端包括一个初级线圈和至少二个次级线圈，用于将至少三个频段的单端射频信号对应转化为双端差分电压信号。
  2. 根据权利要求1所述的接收机前端，其特征在于，所述多频段低噪声放大电路包括控制单元、选择单元、谐振单元、放大单元，所述控制单元用于发出控制信号，所述选择单元包括多路选择通道，用于根据所述控制信号导通不同的选择通道，所述谐振单元包括至少二个次级线圈，每一次级线圈与谐振电容组成谐振电路，所述谐振电路用于对特定频段射频信号产生谐振；所述放大单元用于对所述谐振电路的输出的谐振信号进行放大输出。
  3. 根据权利要求2所述的接收机前端，其特征在于，所述谐振单元还包括一个初级线圈，用于接收多频段的单端射频信号，所述次级线圈具有控制端，所述控制单元连接所述次级线圈的控制端，用于控制所述次级线圈。
  4. 根据权利要求3所述的接收机前端，其特征在于，所述谐振电容与所述选择通道串联组成电容选择通道，用于在不同频段选通不同的谐振电容，所述次级线圈的两端与至少一个所述电容选择通道并联。
  5. 根据权利要求1所述的接收机前端，其特征在于，所述放大单元包括共源共栅结构的放大电路，所述次级线圈的两端分别连接不同的共源管，至少二个所述次级线圈同一侧端点的共源管连接同一个共栅管。
  6. 根据权利要求5所述的接收机前端，其特征在于，所述放大单元包括共源共栅结构的放大电路，第一共源管与第一共栅管、第二共源管与第二共栅管分别组成第一、第二共源共栅放大电路；第一所述谐振电路的两端分别连接第一、第二共源共栅放大电路的第一、第二共源管栅极，第一、第二共源管的源极连接源极负反馈电感的两端；第一、第二共源共栅放大电路的第一、第二共栅管漏极连接漏极负载电感的两端、输出谐振电容与选择通道串联组成的电容选择通道的两端；所述源极负反馈电感、漏极负载电感具有中心抽头，所述源极负反馈电感的中心抽头接地， 所述漏极负载电感的中心抽头接电源端。
  7. 根据权利要求6所述的接收机前端，其特征在于，所述放大单元还包括第三、第四共源管，第三共源管与第一共栅管、第四共源管与第二共栅管分别组成第三、第四共源共栅放大电路；第二所述谐振电路的两端分别连接第三、第四共源共栅放大电路的第三、第四共源管栅极，第三、第四共源管的源极连接源极负反馈电感L1的两端；第三、第四共源共栅放大电路的第一、第二共栅管漏极连接漏极负载电感的两端、输出谐振电容与选择通道串联组成的电容选择通道的两端；所述源极负反馈电感、漏极负载电感具有中心抽头，所述源极负反馈电感的中心抽头接地，所述负载电感的中心抽头接电源端。
  8. 根据权利要求6或7所述的接收机前端，其特征在于，所述漏极负载电感的两端与至少一路电容选择通道并联。
  9. 根据权利要求8所述的接收机前端，其特征在于，所述漏极负载电感与并联电容形成的多个谐振频率与分别与第一、第二所述谐振电路的谐振频率匹配。
  10. 根据权利要求7所述的接收机前端，其特征在于，第二所述谐振电路具有至少二个谐振频率。
PCT/CN2019/084659 2018-06-07 2019-04-26 一种可重构的低功耗低成本支持多频多模的接收机前端 WO2019233217A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810580698.7 2018-06-07
CN201810580698.7A CN108809262B (zh) 2018-06-07 2018-06-07 一种可重构的低功耗低成本支持多频多模的接收机前端

Publications (1)

Publication Number Publication Date
WO2019233217A1 true WO2019233217A1 (zh) 2019-12-12

Family

ID=64087691

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/084659 WO2019233217A1 (zh) 2018-06-07 2019-04-26 一种可重构的低功耗低成本支持多频多模的接收机前端

Country Status (2)

Country Link
CN (1) CN108809262B (zh)
WO (1) WO2019233217A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108809262B (zh) * 2018-06-07 2020-09-22 清华大学深圳研究生院 一种可重构的低功耗低成本支持多频多模的接收机前端
CN112019228B (zh) * 2019-05-30 2021-11-23 格兰康希通信科技(上海)有限公司 多模多频收发电路
CN112671350B (zh) * 2020-12-28 2022-01-04 北京力通通信有限公司 低噪声大带宽放大器
CN112865713B (zh) * 2021-01-22 2022-06-07 成都市凌巨通科技有限公司 一种多频段信号放大器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103891134A (zh) * 2011-10-28 2014-06-25 高通股份有限公司 单差分变压器核
US20160276098A1 (en) * 2013-12-19 2016-09-22 Zte Corporation Transformer, method for manufacturing transformer and chip
CN107645300A (zh) * 2017-10-16 2018-01-30 中国科学院上海高等研究院 一种电流复用低功耗射频接收机
CN108809262A (zh) * 2018-06-07 2018-11-13 清华大学深圳研究生院 一种可重构的低功耗低成本支持多频多模的接收机前端

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882228B2 (en) * 2003-09-08 2005-04-19 Broadcom Corp. Radio frequency integrated circuit having an antenna diversity structure
US8655299B2 (en) * 2010-06-03 2014-02-18 Broadcom Corporation Saw-less receiver with RF frequency translated BPF
CN103684518A (zh) * 2012-09-18 2014-03-26 北京中电华大电子设计有限责任公司 一种基于片上变压器的收发匹配网络共用的射频电路
US9543995B1 (en) * 2013-02-05 2017-01-10 Marvell International Ltd. Analog front end receivers with resonant mixer configured to reject local oscillator harmonics
CN105591625B (zh) * 2014-10-20 2018-11-20 联芯科技有限公司 一种lna及该lna对信号进行放大的方法
CN204832524U (zh) * 2015-01-26 2015-12-02 武汉大学苏州研究院 一种双模可重构的gnss射频前端接收系统
CN105141263A (zh) * 2015-09-29 2015-12-09 株洲宏达天成微波有限公司 一种多频段低噪声放大方法及多频段低噪声放大器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103891134A (zh) * 2011-10-28 2014-06-25 高通股份有限公司 单差分变压器核
US20160276098A1 (en) * 2013-12-19 2016-09-22 Zte Corporation Transformer, method for manufacturing transformer and chip
CN107645300A (zh) * 2017-10-16 2018-01-30 中国科学院上海高等研究院 一种电流复用低功耗射频接收机
CN108809262A (zh) * 2018-06-07 2018-11-13 清华大学深圳研究生院 一种可重构的低功耗低成本支持多频多模的接收机前端

Also Published As

Publication number Publication date
CN108809262A (zh) 2018-11-13
CN108809262B (zh) 2020-09-22

Similar Documents

Publication Publication Date Title
WO2019233217A1 (zh) 一种可重构的低功耗低成本支持多频多模的接收机前端
CN101282110B (zh) 一种低功耗单端输入差分输出低噪声放大器
CN101167245B (zh) 基于差分电感器的低噪声放大器
CN101951230B (zh) 一种宽带低噪声放大器
CN108736835B (zh) 一种多频带低功耗低噪声放大器
CN110138351B (zh) 一种cmos宽带巴伦射频接收前端电路
CN101895265A (zh) 一种全差分cmos多模低噪声放大器
CN101867347A (zh) 多频段无线移动通信系统中频带可重构的功率放大器电路
CN101834576A (zh) 多模可调谐cmos差分低噪声放大器
CN103746665A (zh) 一种0.1～3GHz CMOS增益可调驱动功率放大器
Geis et al. A 0.045 mm 2 0.1–6GHz reconfigurable multi-band, multi-gain LNA for SDR
CN103532497A (zh) 一种采用电感补偿技术的超宽带低噪声放大器
CN101924524A (zh) 一种带有片上有源Balun的差分CMOS多模低噪声放大器
CN216390924U (zh) 超宽带通信标准的低噪声放大器和射频芯片
Wang et al. A multi-band multi-standard RF front-end IEEE 802.16 a for IEEE 802.16 a and IEEE 802.11 a/b/g applications
CN111525894A (zh) 一种宽带、高干扰消除能力的射频低噪声放大器
CN102332877A (zh) 一种带有片上有源Balun的差分CMOS多模低噪声放大器
Nguyen et al. A RF CMOS amplifier with optimized gain, noise, linearity and return losses for UWB applications
WO2023160431A1 (zh) 低噪声放大电路及射频前端模组
Dehqan et al. An ultra low voltage ultra low power CMOS UWB LNA using forward body biasing
CN109004905B (zh) 一种带有巴伦的上变频混频器
CN107276547B (zh) 一种单片集成的毫米波开关模式功率放大器电路
WO2020000614A1 (zh) 混频器电路
CN113746431A (zh) 一种带镜像抑制功能的超宽带高线性度混频器
Xing et al. A 0.9/1.8/2.4 GHz-reconfigurable LNA with Inductor and Capacitor Tuning for IoT Application in 65nm CMOS

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19815339

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19815339

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.04.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19815339

Country of ref document: EP

Kind code of ref document: A1