WO2019233176A1 - 低噪声放大器芯片及前端放大模块、射频接收装置 - Google Patents

低噪声放大器芯片及前端放大模块、射频接收装置 Download PDF

Info

Publication number
WO2019233176A1
WO2019233176A1 PCT/CN2019/082179 CN2019082179W WO2019233176A1 WO 2019233176 A1 WO2019233176 A1 WO 2019233176A1 CN 2019082179 W CN2019082179 W CN 2019082179W WO 2019233176 A1 WO2019233176 A1 WO 2019233176A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
stage
port
low
amplifier circuit
Prior art date
Application number
PCT/CN2019/082179
Other languages
English (en)
French (fr)
Inventor
江少涛
吴光胜
李晓丛
Original Assignee
深圳市华讯方舟微电子科技有限公司
华讯方舟科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华讯方舟微电子科技有限公司, 华讯方舟科技有限公司 filed Critical 深圳市华讯方舟微电子科技有限公司
Publication of WO2019233176A1 publication Critical patent/WO2019233176A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback

Definitions

  • the invention relates to the technical field of electronic circuits, in particular to a low-noise amplifier chip, a front-end amplification module, and a radio frequency receiving device.
  • the low noise amplifier is a very important part of modern wireless communication, radar, electronic countermeasure system and other applications. It is often used in the front-end amplification module of the RF receiving system to suppress noise interference and improve the sensitivity of the system while amplifying the signal. If a high-performance low-noise amplifier is connected to the front end of the receiving system, and the noise of the subsequent stage can be suppressed if the amplifier gain is sufficiently large, the noise figure of the entire receiving system mainly depends on the noise of the amplifier. If the noise figure of the low-noise amplifier is reduced, the noise figure of the receiving system will be reduced, the signal-to-noise ratio will be improved, and the sensitivity will be greatly improved.
  • the performance of the low noise amplifier restricts the performance of the entire receiving system, and also plays a decisive role in improving the technical level of the entire receiving system.
  • Traditional low-noise amplifiers need to use a lot of external ports, which makes them vulnerable to external interference.
  • a low-noise amplifier chip includes a first port, a first-stage amplifier circuit, an inter-stage matching circuit, a second-stage amplifier circuit, a voltage bias circuit, a power bias circuit, and a second port.
  • the input terminal of the first-stage amplifier circuit is connected; the output terminal of the first-stage amplifier circuit is connected to the input terminal of the second-stage amplifier circuit through the inter-stage matching circuit; the output of the second-stage amplifier circuit
  • One end of the voltage bias circuit is connected to the ground terminal of the second-stage amplifier circuit; the other end of the voltage bias circuit is connected to the input terminal of the first-stage amplifier circuit Connection; one end of the power bias circuit is connected to the second port; the other end of the power bias circuit is connected to the output terminal of the first-stage amplifier circuit;
  • the first port is used as a signal input terminal;
  • the second port is used as a signal output terminal and a power supply terminal at the same time.
  • the above-mentioned low-noise amplifier chip uses the signal input terminal and the power supply terminal to share the second port, and uses the voltage bias circuit to take the output of the second-stage amplifier circuit as the bias voltage of the first-stage amplifier circuit, and passes the power supply bias circuit.
  • the power input from the second port is used as the power of the first-stage amplifier circuit, so that the power of the first-stage amplifier circuit and the second-stage amplifier circuit are shared. Therefore, the above-mentioned low-noise amplifier chip only needs to adopt a two-port design, which is not susceptible to external interference, and simplifies subsequent debugging circuit design and facilitates testing and debugging.
  • the power bias circuit includes a first resistor; one end of the first resistor is connected to the second port; the other end of the first resistor is connected to the first-stage amplifier circuit. Output connection.
  • the voltage bias circuit includes a second resistor, a third resistor, and a fourth resistor; a ground terminal of the second-stage amplifier circuit is connected in series with the third resistor and the fourth resistor and grounded.
  • One end of the second resistor is connected to the input terminal of the first-stage amplifier circuit; the other end of the second resistor is connected to a common terminal of the third resistor and the fourth resistor.
  • the first-stage amplifier circuit adopts a common-source cascade inductor negative feedback circuit structure; and the second-stage amplifier circuit adopts a common-source amplifier circuit structure.
  • the first-stage amplifier circuit includes a first transistor and a first inductor; a gate of the first transistor serves as an input terminal of the first-stage amplifier circuit; and a source of the first transistor.
  • the first inductor is grounded in series; the ground terminal of the first inductor is used as the ground terminal of the first-stage amplifier circuit; the drain of the first transistor is used as the output terminal of the first-stage amplifier circuit;
  • the second-stage amplifier circuit includes a second transistor; a gate of the second transistor serves as an input terminal of the second-stage amplifier circuit; and a drain of the second transistor serves as an output of the second-stage amplifier circuit.
  • the source of the second transistor is used as the ground terminal of the second-stage amplifier circuit.
  • a bypass unit is further included; one end of the bypass unit is connected to the source of the second transistor; and the other end of the bypass unit is grounded.
  • the first transistor and the second transistor are both GaAs pseudocrystal high electron mobility transistors.
  • it further includes an input matching unit and an output matching unit; one end of the input matching unit is connected to the first port, and the other end of the input matching unit is also connected to the first-stage amplifier circuit.
  • the input end is connected; one end of the output matching unit is connected to the output end of the second-stage amplifier circuit; the other end of the output matching unit is connected to the second port.
  • a front-end amplifier module includes an input matching circuit, a low noise amplifier chip, and an output matching circuit; the input matching circuit is connected to a first port of the low noise amplifier chip; the output matching circuit is connected to the low noise amplifier chip The second port is connected; the low-noise amplifier chip is the low-noise amplifier chip according to any one of the preceding embodiments.
  • a radio frequency receiving device includes a radio frequency signal receiving module and a front-end amplification module; the radio frequency signal receiving module is connected to the front-end amplification module; the front-end amplification module is the front-end amplification module according to the foregoing embodiment.
  • FIG. 1 is a structural block diagram of a low-noise amplifier chip according to an embodiment
  • FIG. 2 is a structural block diagram of a low-noise amplifier chip in another embodiment
  • FIG. 3 is a circuit schematic diagram of a low-noise amplifier chip in an embodiment
  • FIG. 4 is a graph of an input matching coefficient S11 of the low-noise amplifier chip in the embodiment shown in FIG. 3;
  • FIG. 5 is a graph of an output matching coefficient S22 of the low-noise amplifier chip in the embodiment shown in FIG. 3;
  • FIG. 6 is a graph of the isolation S12 of the low-noise amplifier chip in FIG. 3;
  • FIG. 7 is a graph of a gain S21 of the low-noise amplifier chip in FIG. 3;
  • FIG. 8 is a simulation result diagram of the minimum noise figure NFmin and the actual noise figure nf (2) of the low noise amplifier chip in FIG. 3;
  • FIG. 9 is a stability simulation result diagram of the low-noise amplifier chip in FIG. 3; FIG.
  • FIG. 10 is a circuit block diagram of a front-end amplification module in an embodiment
  • FIG. 11 is a circuit schematic diagram of a front-end amplification module in an embodiment.
  • FIG. 1 is a structural block diagram of a low-noise amplifier chip according to an embodiment.
  • the low-noise amplifier chip can be used in a front-end amplification module of a radio frequency receiving system to implement amplification processing of a radio frequency signal received by the front end.
  • the above-mentioned low-noise amplifier chip works in the Ku frequency band, so it can also be called a Ku-band low noise amplifier chip.
  • the frequency of the Ku band is protected by relevant international laws.
  • the Ku band has a downlink from 10.7GHz to 12.75GHz and an uplink from 12.75GHz to 18.1GHz.
  • the low-noise amplifier chip includes a first port P1, a first-stage amplifier circuit 110, an inter-stage matching circuit 120, a second-stage amplifier circuit 130, a voltage bias circuit 140, a power bias circuit 150, and a second port P2.
  • the first port P1 is connected to the input terminal of the first-stage amplifier circuit 110.
  • the output terminal of the first-stage amplifier circuit 110 is connected to the input terminal of the second-stage amplifier circuit 130 through the inter-stage matching circuit 120.
  • the ground terminal of the first-stage amplifier circuit 110 is grounded.
  • An output terminal of the second-stage amplification circuit 130 is connected to the second port P2.
  • the ground terminal of the second-stage amplifier circuit 130 is connected to the voltage bias circuit 140 and is grounded through the voltage bias circuit 140.
  • the voltage bias circuit 140 is also connected to an input terminal of the first-stage amplifier circuit 110.
  • One end of the power bias circuit 150 is connected to the second port P2, that is, the output end of the second-stage amplification circuit 130, and the other end is connected to the output end of the first-stage amplification circuit 110.
  • the first port P1 is used as a signal input terminal
  • the second port P2 is used as a signal output terminal and a power supply terminal at the same time.
  • the above-mentioned low-noise amplifier chip uses the signal input terminal and the power supply terminal to share the second port P2, and the output of the second-stage amplifier circuit 130 is used as the bias voltage of the first-stage amplifier circuit 110 through the voltage bias circuit 140.
  • the power bias circuit 150 uses the power input from the second port P2 as the power of the first-stage amplifier circuit 110, so that the power of the first-stage amplifier circuit 110 and the second-stage amplifier circuit 130 are shared. Therefore, the above-mentioned low-noise amplifier chip only needs to adopt a two-port (P1, P2) design, and is not easily susceptible to external interference. Moreover, the chip adopts a two-port design, which can simplify subsequent packaging design and PCB application design, shorten subsequent debugging cycles, simplify subsequent debugging circuit design, and facilitate testing and debugging.
  • the low-noise amplifier chip further includes an input matching unit 160 and an output matching unit 170, as shown in FIG. 2.
  • the input matching unit 160 is connected between the first port P1 and the input terminal of the first-stage amplifier circuit 110.
  • the output matching unit 170 is connected between the second port P2 and the output terminal of the second-stage amplifier circuit 130.
  • the input matching unit 160 and the output matching unit 170 are used to achieve impedance matching between input and output, so as to optimize the performance of the entire amplifier chip.
  • FIG. 3 is a circuit schematic diagram of a low-noise amplifier chip in an embodiment.
  • the power bias circuit includes a first resistor R1. One end of the first resistor R1 is connected to the second port P2, and the other end is connected to the output terminal of the first-stage amplifier circuit. It can be understood that, in other embodiments, the power bias circuit may further include other resistors or other impedance elements.
  • the power supply bias circuit can divide the power supply voltage at the second port P2 and output it to the output end of the first-stage amplifier circuit, so that the power supply of the two-stage amplifier circuit is shared, and there is no need to separately set corresponding power ports. Through the internal power sharing, the power routing in the chip can be reduced, and the stability is better.
  • the voltage bias circuit includes a second resistor R2, a third resistor R3, and a fourth resistor R4.
  • the ground terminal of the second-stage amplifier circuit is connected to the third resistor R3 and the fourth resistor R4 in series.
  • One end of the second resistor R2 is connected to the input end of the first-stage amplification circuit through an input matching circuit.
  • the input matching circuit includes a second inductor L2. The second inductor L2 is connected in series to the first port P1 and the input terminal of the first-stage amplifier circuit.
  • the first-stage amplifier circuit adopts a common-source cascade inductor negative feedback circuit structure.
  • the first-stage amplifier circuit includes a first transistor T1 and a first inductor L1, as shown in FIG. 3.
  • the gate of the first transistor T1 is used as the input terminal of the first-stage amplifier circuit
  • the drain of the first transistor T1 is used as the output terminal of the first-stage amplifier circuit
  • the source of the first transistor T1 is connected in series with the first inductor L1 and grounded.
  • the ground terminal of the first inductor L1 is used as the ground terminal of the first-stage amplifier circuit.
  • the first inductor L1 is used as a source negative feedback inductor.
  • the first transistor T1 is a gallium arsenide pseudo-crystal high electron mobility transistor (GaAs PHEMT).
  • the inter-stage matching circuit includes a third inductor L3.
  • the third inductor L3 is connected to the drain of the first transistor T1 and is connected to the input terminal of the second-stage amplifier circuit.
  • the second-stage amplifier circuit has a common-source amplifier circuit structure and includes a second transistor T2.
  • the gate of the second transistor T2 is used as an input terminal of the second-stage amplifier circuit.
  • the source of the second transistor T2 is used as the ground terminal of the second-stage amplifier circuit, that is, the third transistor R3 and the fourth resistor R4 are connected in series to the ground.
  • the drain of the second transistor T2 is used as the output terminal of the second-stage amplifier circuit.
  • a bypass unit is further included.
  • the bypass unit includes a first capacitor C1. One end of the first capacitor C1 is connected to the source of the second transistor T2, and the other end is grounded.
  • the first capacitor C1 acts as a bypass capacitor.
  • the second transistor T2 also uses a GaAs pseudo-crystal high electron mobility transistor (GaAs PHEMT). Both the first transistor T1 and the second transistor T2 in this embodiment can be prepared by using a 0.25 micrometer GaAs process.
  • GaAs PHEMT GaAs pseudo-crystal high electron mobility transistor
  • the output matching circuit includes a fourth inductor L4 and a second capacitor C2.
  • One end of the fourth inductor L4 is connected to the drain of the second transistor T2, and the other end of the fourth inductor L4 is connected to the second port P2.
  • One end of the fourth inductor L4 connected to the second port P2 is also connected to the second capacitor C2 in series and grounded.
  • the layout of the low-noise amplifier chip is 600 micrometers long, 426 micrometers wide, and 100 micrometers thick.
  • the working frequency band of the low-noise amplifier chip in the embodiment shown in FIG. 3 is 10 GHz to 13 GHz, and its stability is good.
  • the stability coefficient can be greater than 1, and the circuit satisfies unconditional stability.
  • the second-stage amplifier circuit can provide a larger gain.
  • FIG. 4 is a graph of an input matching coefficient S11 of the low-noise amplifier chip in the embodiment shown in FIG. 3. It can be seen from the figure that S11 is lower than -10dB in the operating frequency range of the low noise amplifier chip, that is, its input matching can meet the requirements.
  • FIG. 5 is a graph of the output matching coefficient S22 of the low-noise amplifier chip in the embodiment shown in FIG. 3. It can be seen from the figure that S22 is lower than -9dB in the operating frequency range of the low noise amplifier chip, that is, its output matching can meet the requirements, so that the noise of the entire low noise amplifier chip is less than or equal to 1.5dB.
  • FIG. 4 is a graph of an input matching coefficient S11 of the low-noise amplifier chip in the embodiment shown in FIG. 3. It can be seen from the figure that S11 is lower than -10dB in the operating frequency range of the low noise amplifier chip, that is, its input matching can meet the requirements.
  • FIG. 5 is a graph of the output matching coefficient S22
  • FIG. 6 is a graph of the isolation S12 of the low-noise amplifier chip in FIG. 3. As can be seen from Figure 6, the S12 are all less than -31dB, which can also meet the device requirements.
  • FIG. 7 is a graph of the gain S21 of the low-noise amplifier chip in FIG. 3. As can be seen from Figure 7, it has a higher gain in the frequency range, which can reach more than 20dB.
  • FIG. 8 is a simulation result diagram of the minimum noise figure NFmin and the actual noise figure nf (2) of the low-noise amplifier chip in FIG. 3. It can be seen from FIG.
  • FIG. 9 is a simulation result diagram of the stability of the low-noise amplifier chip in FIG. 3. As can be seen from Figure 9, the stability coefficients are all greater than 1, that is, the circuit satisfies unconditional stability.
  • a front-end amplification module includes an input matching circuit 210, a low-noise amplifier chip 220, and an output matching circuit 230, as shown in FIG.
  • the low-noise amplifier chip 220 may be the low-noise amplifier chip in any of the foregoing embodiments.
  • the input matching circuit 210 is connected to a first port of the low noise amplifier chip 220, and the output matching circuit 230 is connected to a second port of the low noise amplifier chip 220.
  • the output matching circuit 210 and the output matching circuit 230 are both used for input and output matching outside the chip.
  • the input matching circuit 210 and the output matching circuit 230 may use a commonly used matching circuit composed of a capacitor and an inductor.
  • the aforementioned front-end amplification module further includes an input DC blocking capacitor Cin and an output DC blocking capacitor Cout, as shown in FIG. 11.
  • Cin can prevent the DC signal from entering the transistor and cause damage, which is equivalent to a short circuit when the RF signal is input
  • CL can prevent the DC signal from entering the load and cause damage, which is equivalent to a short circuit when the RF signal is input.
  • the power source VCC supplies power to the second transistor T2 in the second-stage amplifier circuit through the second port P2, and passes the resistor R1 in the power supply bias circuit and R2 in the voltage bias circuit.
  • ⁇ R3 realizes the sharing of the power of the two-stage amplifier circuit. Therefore, the low-noise amplifier chip 220 only needs to have a two-port design to meet the usage requirements, is not easily affected by external interference, and simplifies subsequent debugging circuit design and facilitates testing and debugging.
  • An embodiment of the present invention further provides a radio frequency receiving device, which includes a radio frequency signal receiving module and a front-end amplification module.
  • the front-end amplification module may use the front-end amplification module in the foregoing embodiment.

Abstract

一种低噪声放大器芯片(220)及前端放大模块、射频接收装置，其中，低噪声放大器芯片(220)包括第一端口(P1)、第一级放大电路(110)、级间匹配电路(120)、第二级放大电路(130)、电压偏置电路(140)、电源偏置电路(150)以及第二端口(P2)；第一端口(P1)与第一级放大电路(110)的输入端连接；第一级放大电路(110)的输出端通过级间匹配电路(120)与第二级放大电路(130)的输入端连接，输出端与第二端口(P2)连接；电压偏置电路(140)的一端与第二级放大电路(130)的接地端连接，另一端与第一级放大电路(110)的输入端连接；电源偏置电路(150)的一端与第二端口(P2)连接，另一端与第一级放大电路(110)的输出端连接；第一端口(P1)作为信号输入端；第二端口(P2)同时作为信号输出端和电源供应端。上述低噪声放大器芯片(220)只需要采用两端口设计即可，不容易受到外界干扰。

Description

低噪声放大器芯片及前端放大模块、射频接收装置 技术领域
本发明涉及电子电路技术领域，特别是涉及一种低噪声放大器芯片及前端放大模块、射频接收装置。
背景技术
低噪声放大器是现代无线通信、雷达、电子对抗系统等应用中一个非常重要的部分，常用于射频接收系统的前端放大模块，在放大信号的同时抑制噪声干扰，提高系统的灵敏度。如果在接收系统的前端连接高性能的低噪声放大器，在放大器增益足够大的情况下，就能抑制后级电路的噪声，则整个接收系统的噪声系数主要取决于放大器的噪声。如果低噪声放大器的噪声系数降低，接收系统的噪声系数也会变小，信噪比则得以改善，灵敏度大大提高。由此可见低噪声放大器的性能制约了整个接收系统的性能，对于整个接收系统的技术水平的提高也起了决定性的作用。传统的低噪声放大器需要使用较多的外接端口，从而容易受到外界干扰。
发明内容
基于此，有必要针对传统的低噪声放大器芯片需要使用较多的外接端口，容易受到外界干扰的问题，提供一种低噪声放大器芯片及前端放大模块、射频接收装置。
一种低噪声放大器芯片，包括第一端口、第一级放大电路、级间匹配电路、 第二级放大电路、电压偏置电路、电源偏置电路以及第二端口；所述第一端口与所述第一级放大电路的输入端连接；所述第一级放大电路的输出端通过所述级间匹配电路与所述第二级放大电路的输入端连接；所述第二级放大电路的输出端与所述第二端口连接；所述电压偏置电路的一端与所述第二级放大电路的接地端连接；所述电压偏置电路的另一端与所述第一级放大电路的输入端连接；所述电源偏置电路的一端与所述第二端口连接；所述电源偏置电路的另一端与所述第一级放大电路的输出端连接；所述第一端口作为信号输入端；所述第二端口同时作为信号输出端和电源供应端。
上述低噪声放大器芯片，通过将信号输入端和电源供应端共用第二端口，并且通过电压偏置电路将第二级放大电路的输出作为第一级放大电路的偏置电压，通过电源偏置电路将第二端口输入的电源作为第一级放大电路的电源，实现第一级放大电路和第二级放大电路的电源共用。因此，上述低噪声放大器芯片只需要采用两端口设计即可，不容易受到外界干扰，且简化了后续调试电路设计及方便测试调试工作。
在其中一个实施例中，所述电源偏置电路包括第一电阻；所述第一电阻的一端与所述第二端口连接；所述第一电阻的另一端与所述第一级放大电路的输出端连接。
在其中一个实施例中，所述电压偏置电路包括第二电阻、第三电阻和第四电阻；所述第二级放大电路的接地端串联所述第三电阻和所述第四电阻后接地；所述第二电阻的一端与所述第一级放大电路的输入端连接；所述第二电阻的另一端连接于所述第三电阻和第四电阻的公共端。
在其中一个实施例中，所述第一级放大电路采用共源极级联电感负反馈电路结构；所述第二级放大电路采用共源极放大电路结构。
在其中一个实施例中，所述第一级放大电路包括第一晶体管和第一电感；所述第一晶体管的栅极作为所述第一级放大电路的输入端；所述第一晶体管的源极串联所述第一电感后接地；所述第一电感的接地端作为所述第一级放大电路的接地端；所述第一晶体管的漏极作为所述第一级放大电路的输出端；
所述第二级放大电路包括第二晶体管；所述第二晶体管的栅极作为所述第二级放大电路的输入端；所述第二晶体管的漏极作为所述第二级放大电路的输出端；所述第二晶体管的源极作为所述第二级放大电路的接地端。
在其中一个实施例中，还包括旁路单元；所述旁路单元的一端与所述第二晶体管的源极连接；所述旁路单元的另一端接地。
在其中一个实施例中，所述第一晶体管和所述第二晶体管均为砷化镓假晶形高电子迁移率晶体管。
在其中一个实施例中，还包括输入匹配单元和输出匹配单元；所述输入匹配单元的一端与所述第一端口连接，所述输入匹配单元的另一端还与所述第一级放大电路的输入端连接；所述输出匹配单元的一端与所述第二级放大电路的输出端连接；所述输出匹配单元的另一端与所述第二端口连接。
一种前端放大模块，包括输入匹配电路、低噪声放大器芯片以及输出匹配电路；所述输入匹配电路与所述低噪声放大器芯片的第一端口连接；所述输出匹配电路与所述低噪声放大器芯片的第二端口连接；所述低噪声放大器芯片为如前述任一实施例所述的低噪声放大器芯片。
一种射频接收装置，包括射频信号接收模块和前端放大模块；所述射频信号接收模块与所述前端放大模块连接；所述前端放大模块为如前述实施例所述的前端放大模块。
附图说明
图1为一实施例中的低噪声放大器芯片的结构框图；
图2为另一实施例中的低噪声放大器芯片的结构框图；
图3为一实施例中的低噪声放大器芯片的电路原理图；
图4为图3所示实施例中的低噪声放大器芯片的输入匹配系数S11的曲线图；
图5为图3所示实施例中的低噪声放大器芯片的输出匹配系数S22的曲线图；
图6为图3中的低噪声放大器芯片的隔离度S12的曲线图；
图7为图3中的低噪声放大器芯片的增益S21的曲线图；
图8为图3中的低噪声放大器芯片的最小噪声系数NFmin和实际噪声系数nf(2)的仿真结果图；
图9为图3中的低噪声放大器芯片的稳定性仿真结果图；
图10为一实施例中的前端放大模块的电路框图；
图11为一实施例中的前端放大模块的电路原理图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
图1为一实施例中的低噪声放大器芯片的结构框图，该低噪声放大器芯片可以用于射频接收系统的前端放大模块中，以实现对前端接收到的射频信号的放大处理。在本实施例中，上述低噪声放大器芯片工作在Ku频段，因此也可以 称之为Ku频段低噪声放大器芯片。Ku频段的频率受到国际有关法律保护，Ku频段下行从10.7GHz到12.75GHz，上行从12.75GHz到18.1GHz。
参见图1，该低噪声放大器芯片包括第一端口P1、第一级放大电路110、级间匹配电路120、第二级放大电路130、电压偏置电路140、电源偏置电路150以及第二端口P2。其中，第一端口P1与第一级放大电路110的输入端连接。第一级放大电路110的输出端通过级间匹配电路120与第二级放大电路130的输入端连接。第一级放大电路110的接地端接地。第二级放大电路130的输出端与第二端口P2连接。第二级放大电路130的接地端与电压偏置电路140连接，并通过电压偏置电路140接地。电压偏置电路140还与第一级放大电路110的输入端连接。电源偏置电路150的一端与第二端口P2，也即与第二级放大电路130的输出端连接，另一端则与第一级放大电路110的输出端连接。在本实施例中，第一端口P1作为信号输入端，第二端口P2同时作为信号输出端和电源供应端。
上述低噪声放大器芯片，通过将信号输入端和电源供应端共用第二端口P2，并且通过电压偏置电路140将第二级放大电路130的输出作为第一级放大电路110的偏置电压，通过电源偏置电路150将第二端口P2输入的电源作为第一级放大电路110的电源，从而实现第一级放大电路110和第二级放大电路130的电源共用。因此，上述低噪声放大器芯片只需要采用两端口(P1、P2)设计即可，不容易受到外界干扰。并且芯片采用两端口设计后，可以简化后续封装设计和PCB应用设计，可缩短后续的调试周期，并简化后续调试电路设计及方便测试调试工作。
在一实施例中，上述低噪声放大器芯片还包括输入匹配单元160和输出匹配单元170，如图2所示。其中，输入匹配单元160连接于第一端口P1和第一 级放大电路110的输入端之间。输出匹配单元170则连接于第二端口P2和第二级放大电路130的输出端之间。输入匹配单元160和输出匹配单元170用于实现输入和输出的阻抗匹配，以优化整个放大器芯片的性能。
图3为一实施例中的低噪声放大器芯片的电路原理图。参见图3，在本实施例中，电源偏置电路包括第一电阻R1。第一电阻R1的一端与第二端口P2连接，另一端则与第一级放大电路的输出端连接。可以理解，在其他的实施例中，电源偏置电路中还可以包括其他的电阻，或者其他阻抗元件。通过电源偏置电路可以将第二端口P2处的供电电压进行分压后输出至第一级放大电路的输出端，实现两级放大电路的电源共用，无需分别设置相应的电源端口。通过内部电源共用，可以减少芯片内的电源走线，稳定性较好。
在一实施例中，电压偏置电路包括第二电阻R2、第三电阻R3和第四电阻R4。其中，第二级放大电路的接地端串联第三电阻R3和第四电阻R4后接地。第二电阻R2的一端通过输入匹配电路与第一级放大电路的输入端连接。在一实施例中，输入匹配电路包括第二电感L2。第二电感L2串联在第一端口P1和第一级放大电路的输入端。
在一实施例中，第一级放大电路采用共源极级联电感负反馈电路结构。具体地，第一级放大电路包括第一晶体管T1和第一电感L1，参见图3。第一晶体管T1的栅极作为第一级放大电路的输入端，第一晶体管T1的漏极作为第一级放大电路的输出端，第一晶体管T1的源极串联第一电感L1后接地。第一电感L1的接地端作为第一级放大电路的接地端。第一电感L1作为源极负反馈电感。在一实施例中，第一晶体管T1为砷化镓假晶形高电子迁移率晶体管(GaAs PHEMT)。
在一实施例中，级间匹配电路包括第三电感L3。第三电感L3连接于第一晶 体管T1的漏极，并与第二级放大电路的输入端连接。
第二级放大电路为共源放大电路结构，其包括第二晶体管T2。第二晶体管T2的栅极作为第二级放大电路的输入端。第二晶体管T2的源极作为第二级放大电路的接地端，也即其串联第三电阻R3和第四电阻R4后接地。第二晶体管T2的漏极作为第二级放大电路的输出端。在一实施例中，还包括旁路单元。旁路单元包括第一电容C1。第一电容C1的一端连接于第二晶体管T2的源极，另一端接地。第一电容C1作为旁路电容。其中，第二晶体管T2同样采用砷化镓假晶形高电子迁移率晶体管(GaAs PHEMT)。本实施例中的第一晶体管T1和第二晶体管T2均可以采用0.25微米GaAs工艺制备得到。
在一实施例中，输出匹配电路包括第四电感L4和第二电容C2。其中，第四电感L4的一端与第二晶体管T2的漏极连接，第四电感L4的另一端则与第二端口P2连接。第四电感L4与第二端口P2连接的一端还串联第二电容C2后接地。
在一实施例中，上述低噪声放大器芯片的版图长为600微米，宽为426微米，厚为100微米。
图3所示实施例中的低噪声放大器芯片的工作频带为10GHz～13GHz，其稳定性较好，稳定系数可以大于1，电路满足无条件稳定。并且，通过采用共源极级联电感负反馈电路结构作为第一级放大电路，可以实现较小的噪声系数，第二级放大电路则可以提供较大的增益。
下面结合效果图对上述实施例中的低噪声放大器芯片的优点做进一步说明。图4为图3所示实施例中的低噪声放大器芯片的输入匹配系数S11的曲线图。从图中可以看出，S11在低噪声放大器芯片的工作频率范围内均低于-10dB，也即其输入匹配能够满足要求。图5为图3所示实施例中的低噪声放大器芯片的输出匹配系数S22的曲线图。从图中可以看出，S22在低噪声放大器芯片的工 作频率范围内均低于-9dB，也即其输出匹配能够满足要求，使得整个低噪声放大器芯片的噪声小于等于1.5dB。图6为图3中的低噪声放大器芯片的隔离度S12的曲线图。从图6中可以看到，其S12均小于-31dB，同样能够满足器件要求。图7为图3中的低噪声放大器芯片的增益S21的曲线图。从图7中可以看出，其在频率范围内具有较高的增益，能够达到20dB以上。图8为图3中的低噪声放大器芯片的最小噪声系数NFmin和实际噪声系数nf(2)的仿真结果图。从图8中可以看出，其实际噪声系数nf(2)比较接近最小噪声系数NFmin，也就说明通过匹配电路以及匹配单元的调节，噪声基本已经达到最小。图9为图3中的低噪声放大器芯片的稳定性仿真结果图。从图9中可以看出，其稳定系数均大于1，即电路满足无条件稳定。
在本发明一实施例还提供一种前端放大模块。该前端放大模块包括输入匹配电路210、低噪声放大器芯片220以及输出匹配电路230，如图10所示。其中，低噪声放大器芯片220可以采用前述任一实施例中的低噪声放大器芯片。输入匹配电路210与低噪声放大器芯片220的第一端口连接，输出匹配电路230与低噪声放大器芯片220的第二端口连接。在本实施例中，输出匹配电路210和输出匹配电路230均用于芯片外部的输入、输出匹配。输入匹配电路210和输出匹配电路230可以采用常用的由电容电感构成的匹配电路。
在一实施例中，上述前端放大模块还包括输入隔直电容Cin和输出隔直电容Cout，如图11所示。Cin可以阻止直流信号进入晶体管造成损伤，其在射频信号输入时相当于短路，CL可以阻止直流信号进入负载造成损伤，其在射频信号输入时相当于短路。
参见图11，在本实施例中，电源VCC通过第二端口P2向第二级放大电路中的第二晶体管T2进行供电，并通过电源偏置电路中的电阻R1以及电压偏置电 路中的R2～R3实现两级放大电路电源共用。因此，低噪声放大器芯片220只需要做两端口设计即可满足使用需求，不容易受到外界干扰，且简化了后续调试电路设计及方便测试调试工作。
本发明一实施例还提供一种射频接收装置，其包括射频信号接收模块和前端放大模块。其中，该前端放大模块可以采用前述实施例中的前端放大模块。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种低噪声放大器芯片，其特征在于，包括第一端口、第一级放大电路、级间匹配电路、第二级放大电路、电压偏置电路、电源偏置电路以及第二端口；所述第一端口与所述第一级放大电路的输入端连接；所述第一级放大电路的输出端通过所述级间匹配电路与所述第二级放大电路的输入端连接；所述第二级放大电路的输出端与所述第二端口连接；所述电压偏置电路的一端与所述第二级放大电路的接地端连接；所述电压偏置电路的另一端与所述第一级放大电路的输入端连接；所述电源偏置电路的一端与所述第二端口连接；所述电源偏置电路的另一端与所述第一级放大电路的输出端连接；所述第一端口作为信号输入端；所述第二端口同时作为信号输出端和电源供应端。
  2. 根据权利要求1所述的低噪声放大器芯片，其特征在于，所述电源偏置电路包括第一电阻；所述第一电阻的一端与所述第二端口连接；所述第一电阻的另一端与所述第一级放大电路的输出端连接。
  3. 根据权利要求1所述的低噪声放大器芯片，其特征在于，所述电压偏置电路包括第二电阻、第三电阻和第四电阻；所述第二级放大电路的接地端串联所述第三电阻和所述第四电阻后接地；所述第二电阻的一端与所述第一级放大电路的输入端连接；所述第二电阻的另一端连接于所述第三电阻和第四电阻的公共端。
  4. 根据权利要求1所述的低噪声放大器芯片，其特征在于，所述第一级放大电路采用共源极级联电感负反馈电路结构；所述第二级放大电路采用共源极放大电路结构。
  5. 根据权利要求4所述的低噪声放大器芯片，其特征在于，所述第一级放大电路包括第一晶体管和第一电感；所述第一晶体管的栅极作为所述第一级放 大电路的输入端；所述第一晶体管的源极串联所述第一电感后接地；所述第一电感的接地端作为所述第一级放大电路的接地端；所述第一晶体管的漏极作为所述第一级放大电路的输出端；
    所述第二级放大电路包括第二晶体管；所述第二晶体管的栅极作为所述第二级放大电路的输入端；所述第二晶体管的漏极作为所述第二级放大电路的输出端；所述第二晶体管的源极作为所述第二级放大电路的接地端。
  6. 根据权利要5所述的低噪声放大器芯片，其特征在于，还包括旁路单元；所述旁路单元的一端与所述第二晶体管的源极连接；所述旁路单元的另一端接地。
  7. 根据权利要5所述的低噪声放大器芯片，其特征在于，所述第一晶体管和所述第二晶体管均为砷化镓假晶形高电子迁移率晶体管。
  8. 根据权利要求1所述的低噪声放大器芯片，其特征在于，还包括输入匹配单元和输出匹配单元；所述输入匹配单元的一端与所述第一端口连接，所述输入匹配单元的另一端还与所述第一级放大电路的输入端连接；所述输出匹配单元的一端与所述第二级放大电路的输出端连接；所述输出匹配单元的另一端与所述第二端口连接。
  9. 一种前端放大模块，其特征在于，包括输入匹配电路、低噪声放大器芯片以及输出匹配电路；所述输入匹配电路与所述低噪声放大器芯片的第一端口连接；所述输出匹配电路与所述低噪声放大器芯片的第二端口连接；所述低噪声放大器芯片为如权利要求1～8任一所述的低噪声放大器芯片。
  10. 一种射频接收装置，其特征在于，包括射频信号接收模块和前端放大模块；所述射频信号接收模块与所述前端放大模块连接；所述前端放大模块为如权利要求9所述的前端放大模块。
PCT/CN2019/082179 2018-06-08 2019-04-11 低噪声放大器芯片及前端放大模块、射频接收装置 WO2019233176A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810589748.8A CN108832903A (zh) 2018-06-08 2018-06-08 低噪声放大器芯片及前端放大模块、射频接收装置
CN201810589748.8 2018-06-08

Publications (1)

Publication Number Publication Date
WO2019233176A1 true WO2019233176A1 (zh) 2019-12-12

Family

ID=64143627

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/082179 WO2019233176A1 (zh) 2018-06-08 2019-04-11 低噪声放大器芯片及前端放大模块、射频接收装置

Country Status (2)

Country Link
CN (1) CN108832903A (zh)
WO (1) WO2019233176A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108832903A (zh) * 2018-06-08 2018-11-16 深圳市华讯方舟微电子科技有限公司 低噪声放大器芯片及前端放大模块、射频接收装置
CN111130465B (zh) * 2019-11-19 2023-02-28 中国兵器装备集团上海电控研究所 适用于北斗二代频段的低噪放射频前端电路
CN112350673B (zh) * 2020-11-09 2023-06-27 中国电子科技集团公司第三十八研究所 一种星载甚低频前置放大器
CN116073774A (zh) * 2022-12-12 2023-05-05 苏州科技大学 一种基于GaN HEMT的高线性微波功率放大器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102983817A (zh) * 2012-11-22 2013-03-20 东南大学 一种高增益的宽带低噪声放大器
CN103117711A (zh) * 2013-01-29 2013-05-22 天津大学 一种单片集成的射频高增益低噪声放大器
CN107332517A (zh) * 2017-06-21 2017-11-07 成都嘉纳海威科技有限责任公司 一种基于增益补偿技术的高线性宽带堆叠低噪声放大器
CN108832903A (zh) * 2018-06-08 2018-11-16 深圳市华讯方舟微电子科技有限公司 低噪声放大器芯片及前端放大模块、射频接收装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201869166U (zh) * 2010-12-07 2011-06-15 广州特信网络技术有限公司 超低温低噪声放大器
EP2501035B1 (en) * 2011-03-15 2020-09-30 Nxp B.V. Amplifier
CN103066925B (zh) * 2012-12-04 2015-10-28 江苏指南针导航通信技术有限公司 低噪声功率放大方法、放大装置及卫星导航接收设备
CN205265631U (zh) * 2015-12-29 2016-05-25 成都创吉科技有限责任公司 一种带射频输出端馈电的放大电路
CN107846195A (zh) * 2017-10-19 2018-03-27 中国科学技术大学 一种带有源多路反馈的超宽带微波低噪声放大器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102983817A (zh) * 2012-11-22 2013-03-20 东南大学 一种高增益的宽带低噪声放大器
CN103117711A (zh) * 2013-01-29 2013-05-22 天津大学 一种单片集成的射频高增益低噪声放大器
CN107332517A (zh) * 2017-06-21 2017-11-07 成都嘉纳海威科技有限责任公司 一种基于增益补偿技术的高线性宽带堆叠低噪声放大器
CN108832903A (zh) * 2018-06-08 2018-11-16 深圳市华讯方舟微电子科技有限公司 低噪声放大器芯片及前端放大模块、射频接收装置

Also Published As

Publication number Publication date
CN108832903A (zh) 2018-11-16

Similar Documents

Publication Publication Date Title
WO2019233176A1 (zh) 低噪声放大器芯片及前端放大模块、射频接收装置
KR102287445B1 (ko) 저잡음 증폭기를 바이패스하는 시스템 및 방법
US8271028B2 (en) Dual band amplifier
CN106788278B (zh) Ku波段低噪声放大器
CN110138345B (zh) 一种宽带放大电路
JP2005520372A (ja) 高性能ＢｉＦＥＴ低雑音増幅器
US7603091B2 (en) Hybrid balun apparatus and receiver comprising the same
US6930546B2 (en) Bypass switch topology for low-noise amplifiers
KR102163047B1 (ko) 저잡음 증폭 회로
US4841253A (en) Multiple spiral inductors for DC biasing of an amplifier
JPH01254013A (ja) ガリウム・ひ素・モノリシック・マイクロ波集積回路前置増幅器
KR20110017639A (ko) 공핍 모드 고전자 이동도 트랜지스터를 포함하는 전력 증폭기
Mohebi et al. Highly linear wide band low noise amplifiers: A literature review (2010–2018)
US10979007B2 (en) Amplification device with isolation characteristics
Vimalan et al. Performance analysis of various topologies of common source low noise amplifier (cs-lna) at 90nm technology
JP2008103889A (ja) 低雑音増幅器
EP1961124B1 (en) Low noise amplifier
CN115118229A (zh) 一种高线性度低噪声放大器芯片
CN113131875B (zh) 一种高可靠性低噪声放大器
CN114285383A (zh) 一种电流复用结构的增益放大模块
JP2010213141A (ja) 利得可変増幅器およびそれを用いた通信機器
US9543902B2 (en) Power amplifier
US20040029535A1 (en) Radio-frequency power amplification circuit having stabilization circuit
US7064611B2 (en) IDSS RF amplifier
Xia et al. Design of a 6–18 GHz low noise amplifier using 0.25-um GaAs pHEMT D-mode technology

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19814525

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19814525

Country of ref document: EP

Kind code of ref document: A1