WO2019227773A1 - Coa substrate, manufacturing method, and display device - Google Patents

Coa substrate, manufacturing method, and display device Download PDF

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Publication number
WO2019227773A1
WO2019227773A1 PCT/CN2018/105771 CN2018105771W WO2019227773A1 WO 2019227773 A1 WO2019227773 A1 WO 2019227773A1 CN 2018105771 W CN2018105771 W CN 2018105771W WO 2019227773 A1 WO2019227773 A1 WO 2019227773A1
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WO
WIPO (PCT)
Prior art keywords
color filter
ito
connection line
pattern
array substrate
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PCT/CN2018/105771
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French (fr)
Chinese (zh)
Inventor
曹武
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2019227773A1 publication Critical patent/WO2019227773A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present application relates to the field of display technology, and in particular, to a COA array substrate, a preparation method and a display device.
  • the COA array substrate, the preparation method and the display device are used to solve the problem of ITO residuals and reduce the on-resistance of the DBS common electrode traces.
  • a COA array substrate includes: a TFT structure provided on the substrate; a color filter layer pattern provided above the TFT structure; the color filter layer pattern is excavated in a gate line region and connected to each other in a data line region; Overlay the DBS common electrode traces in parallel above the data lines; at least one ITO connection line extending in the direction of the gate line and connecting two adjacent DBS common electrode traces to each other, at least one of which is described above
  • the ITO connecting line is an ITO connecting line extending along the bottom of the slope of the pattern boundary of the color filter layer.
  • an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
  • the ITO connection line extending along the bottom of the color filter layer pattern boundary slope surface is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure and is connected to DBS common electrode traces.
  • the boundary of the ITO connection line extending along the bottom of the slope of the color filter layer pattern border near the color filter layer pattern is at least equal to the color filter layer pattern boundary.
  • the bottom edge of the slope is aligned, or there is an overlap of less than 3 microns; the boundary on one side far from the color filter pattern is at least 1.5 microns from the bottom edge of the color filter pattern.
  • the gate line region is provided with a black spacer.
  • a display device includes a COA array substrate.
  • the COA array substrate includes:
  • a color filter layer pattern, the color filter layer pattern is dug in a gate line region, and is connected and overlapped with each other in a data line region 4;
  • the ITO conductive electrode pattern includes:
  • DBS common electrode traces which are arranged in parallel on the data lines
  • At least one ITO connection line is connected in the gate line area and extends in the direction of the gate line to route two adjacent DBS common electrodes, and at least one of the ITO connection lines is along the color filter layer pattern The boundary of the slope extends at the bottom.
  • an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
  • the ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure connection Route to DBS common electrode.
  • the boundary of the ITO connection line extending along the bottom of the slope of the color filter layer pattern border near the color filter layer pattern is at least equal to the color filter layer pattern boundary.
  • the bottom edge of the slope is aligned, or there is an overlap of less than 3 microns; the boundary on one side far from the color filter pattern is at least 1.5 microns from the bottom edge of the color filter pattern.
  • the gate line region is provided with a black spacer.
  • a method for preparing a COA array substrate includes:
  • the color filter layer pattern is dug in a gate line area, and is connected and overlapped with each other in a data line area;
  • the ITO conductive electrode pattern includes a DBS common electrode trace arranged in parallel above the data line; and at least one ITO connection extending in the gate line direction and extending in the direction of the gate line to connect two adjacent DBS common electrode traces to each other.
  • Line, at least one of said ITO connecting lines is an ITO connecting line extending along the bottom of the slope of the boundary of the color filter layer pattern.
  • only one ITO connection line extending along the bottom of the slope of the boundary of the color filter layer pattern is provided in the gate line region.
  • an ITO connection line is provided in a gate line region, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
  • the ITO connection line extending along the bottom of the color filter layer pattern boundary slope surface is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT.
  • the structure is connected to the DBS common electrode trace.
  • the boundary of the ITO connection line extending along the bottom of the slope of the border of the color filter layer pattern close to the side of the color filter layer pattern is at least equal to the color filter layer.
  • the bottom edge of the slope of the graphic boundary is aligned, or there is an overlap of less than 3 microns; the boundary far from the side of the color filter pattern is at least 1.5 microns from the bottom edge of the slope of the color filter pattern boundary.
  • a black spacer is provided in the gate line region.
  • the beneficial effects of the COA array substrate, the preparation method and the display device provided by the present application are: the COA array substrate, the preparation method and the display device of the present application are provided with an ITO connection line at the bottom end of the slope boundary of the color filter pattern, and the ITO It is easy to form a residual boundary terrain, stabilize the film formation, and reduce the on-resistance; at the same time, avoid the intersection of the ITO connection line and the metal trace, and reduce the risk of disconnection.
  • FIG. 1 is a schematic diagram of a first embodiment of a COA array substrate provided by the present application.
  • FIG. 2 is a schematic diagram of a second embodiment of a COA array substrate provided in the present application.
  • FIG. 3 is a schematic diagram of a third embodiment of a COA array substrate provided by the present application.
  • FIG. 4 is a schematic diagram of a fourth embodiment of a COA array substrate provided by the present application.
  • 5A and 5B are schematic cross-sectional views of the ITO connection line of the COA array substrate provided along the bottom of the slope of the boundary of the color filter layer pattern provided in the present application.
  • M1 / M2 / ITO metal layer 1 / metal layer 2 / indium tin oxide
  • ITO indium tin oxide
  • the safe distance between different electrodes of the material depends on dimensional resolution, etc., generally about 5um with ITO as an example) to prevent short circuit or crosstalk.
  • the ITO inorganic film is in the COA process, the underlying terrain is uneven.
  • the photoresist PR is easy to deposit thick films in areas with low terrain, narrow, and large step changes after exposure. Complete, which causes the remaining ITO to remain during etching, and finally causes a short circuit.
  • RGB are color-resistance strips
  • CF island architectures which are characterized by digging out color resistance in areas such as gate lines and are commonly used in BPS 1Tone architecture application.
  • FIG. 1 is a schematic diagram of a first embodiment of a COA array substrate provided by the present application.
  • the color resistance formed by the color filter layer 1 is dug and discontinued in the lateral gate line region 2 to form an island-like structure, and the data line region 4 is connected and overlapped with each other; the gate line region 2 corresponds to the BPS region, and is subsequently This area is coated with BPS material, leveled and developed by exposure to form a long-striped BPS pattern, and the final spacer structure is obtained.
  • the gate line area 2 is dug, the number of graphic boundaries 26 of the color filter layer 1 increases sharply, resulting in poor topographical conditions during subsequent deposition of ITO; secondly, except for the data line 28, above the data line 102 It is also provided with an ITO line—DBS common electrode (DBS Com) trace 24, which uses DBS (Data BM Less) technology to control the liquid crystal potential to achieve light shielding.
  • DBS Data BM Less
  • FIG. 2 is a schematic diagram of a second embodiment of a COA array substrate provided by the present application.
  • the COA array substrate 100 mainly includes: a TFT structure 31 provided on the substrate 5, including a gate line 29 and a data line 102, and the entire surface is covered with a first insulating protection layer 32; and a color filter provided above the TFT structure 31
  • the layer pattern 22 is the RGB color resistance; the color filter layer pattern 22 is cut out in the gate line region 2.
  • the gate line region 2 is also provided with a drain electrode or a storage capacitor for the TFT structure 31
  • Source and drain metal block pattern 21 a black spacer 36 can be made subsequently, and a color filter layer pattern 22 is connected and overlapped with each other in the data line region 4; a second insulating protection layer 33 is subsequently deposited, and an ITO conductive electrode pattern is prepared 103.
  • the ITO conductive electrode pattern 103 mainly includes: a pixel electrode 23 provided on the color filter layer pattern 22; a DBS common electrode trace 24 arranged in parallel above the data line 102 for light shielding in a liquid crystal display; and a gate line region 2
  • the ITO connection line 28 extends along the bottom of the slope of the boundary 26 of the color filter layer pattern 22;
  • the electrode line region 2 is provided with a source-drain metal block pattern 21 for a TFT drain electrode or a storage capacitor.
  • FIG. 3 is a schematic diagram of a third embodiment of a COA array substrate provided by the present application.
  • the ITO conductive electrode pattern 103 mainly includes: a pixel electrode 23 provided on the color filter layer pattern 22; a DBS common electrode trace 24 arranged in parallel above the data line 102 for light shielding in a liquid crystal display; and a gate line region 2
  • ITO connecting lines 25 and 27 extending along the gate line 29 and connecting two adjacent DBS common electrode traces 24 to each other.
  • At least one ITO connecting line 27 extends along the bottom of the slope of the boundary 26 of the color filter layer pattern 22 , Solve the residual problem, and avoid crossing with metal traces.
  • the ITO connection line 25 extends substantially parallel to the gate line 29 and turns at the TFT structure 31 to bypass the TFT structure 31.
  • This application utilizes the characteristics of ITO residues to form a complete ITO connection line, provides multiple conduction paths, further reduces impedance, improves stability, and avoids ITO breakage on metal lines.
  • An ITO connection line 25 is provided between adjacent common electrode traces 24 in the area where the gate line 29 is located to reduce impedance.
  • this application proposes a ITO connection line at the bottom of the CF pattern slope boundary 26 for the CF island + DBS common electrode routing technology.
  • the residual boundary is easily formed by using ITO 26 terrain, stable film formation, reducing on-resistance. At the same time, the intersection of the ITO connection line and the metal trace is avoided, and the risk of disconnection is reduced.
  • FIG. 4 is a schematic diagram of a fourth embodiment of a COA array substrate provided by the present application.
  • the ITO conductive electrode pattern 103 mainly includes: a pixel electrode 23 provided on the color filter layer pattern 22; a DBS common electrode trace 24 arranged in parallel above the data line 102 for light shielding in a liquid crystal display; and a gate line region 2 It is provided with an ITO connection line 27 extending along the gate line 29 and connecting two adjacent DBS common electrode traces 24 to each other.
  • the ITO connection line 27 extends along the bottom of the slope of the boundary 26 of the color filter layer pattern 22; the gate line In addition to the gate line 29, the region 2 is provided with a source-drain metal block pattern 21 for a drain electrode or a storage capacitor of the TFT structure 31.
  • the ITO connection line 27 is provided with a branch connection line 30 adjacent to the TFT structure 31, and the branch connection line 30 bypasses the TFT structure 31 and is connected to the DBS common electrode trace 24, which is beneficial to forming a symmetrical and uniform external electric field effect on the TFT.
  • FIG. 5A and 5B are schematic cross-sectional views of the ITO connection line of the COA array substrate of the present application extending along the bottom of the slope of the boundary of the color filter layer pattern, showing two possible slope cross-sectional structures.
  • the ITO connecting line 41 extending along the bottom of the slope of the boundary 26 of the color filter pattern 40 is close to the boundary 26 on the side of the color filter pattern 40 at least with the bottom of the slope of the boundary 26 of the color filter pattern 40, or There is an overlap of less than 3 micrometers, preferably 2 to 3 micrometers; the boundary 26 on the side far from the color filter layer pattern is at least 1.5 micrometers from the bottom edge of the slope of the color filter layer pattern boundary 26.
  • This application uses a new ITO connection line to connect the DBS common electrode traces.
  • the new ITO connection line is provided on the slope of the CF island-like boundary (the non-pixel electrode climbing side).
  • the ITO connection line can be formed entirely on the low end of the CF slope, or it can be partially formed on the CF slope.
  • the present application also provides a corresponding display device, including the above-mentioned COA array substrate.
  • This application also provides a method for preparing the COA array substrate, which mainly includes:
  • Preparing a TFT structure on a substrate including a gate line and a data line;
  • a color filter layer pattern is prepared, the color filter layer pattern is dug in the gate line area, and is connected and overlapped with each other in the data line area; the RGB color resistance is dug out and discontinuous in the gate line area, and connected to each other in the data line area. overlap;
  • the ITO conductive electrode pattern includes a DBS common electrode trace arranged in parallel above the data line; and at least one ITO connection extending in the gate line direction and extending in the direction of the gate line to connect two adjacent DBS common electrode traces to each other.
  • at least one of the ITO connection lines is an ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer.
  • ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer can be provided in the gate line region, and the structure is simple.
  • the ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer can be provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure and connects to the DBS common electrode traces, which is conducive to forming a symmetrical and uniform TFT External electric field effects.
  • the COA array substrate, the preparation method and the display device of the present application are provided with an ITO connection line at the bottom end of the slope boundary of the color filter film pattern.
  • the residual boundary terrain is easily formed by using ITO to stabilize the film formation and reduce the on-resistance; At the same time, the intersection of the ITO connection line and the metal trace is avoided, and the risk of disconnection is reduced.

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Abstract

A COA substrate, a manufacturing method, and a display device. In the COA substrate, the manufacturing method, and the display device, an ITO connection line (27) is provided at and extends along a bottom end of a sloped boundary (26) of a color filter pattern (22). The invention employs a boundary contour that facilitates formation and retention of an ITO material, thereby stably forming a film and reducing conduction impedance. The invention also prevents crossing of the ITO connection line (27) and a metal wire, thereby reducing risks of circuit interruption.

Description

COA阵列基板、制备方法及显示装置COA array substrate, preparation method and display device 技术领域Technical field
本申请涉及显示技术领域，尤其涉及一种COA阵列基板、制备方法及显示装置。The present application relates to the field of display technology, and in particular, to a COA array substrate, a preparation method and a display device.
背景技术Background technique
在液晶显示（liquid crystal display，LCD）制造中，经常会发生某一层电极图形化残留的问题，在某些非设定区域产生导电材料残留，根据程度不同会对面板显示质量产生影响。在实际生产经验中，该风险常见于在形成氧化铟锡（indium tin oxide，ITO）层时，尤其是当ITO层下的基板表面的平整度差时,在黄光图形化时，光刻胶（photoresistor，PR）涂敷后易在地势低，狭窄，段差变化大的区域沉积厚膜，曝光显影不完全，导致ITO层在蚀刻时形成残留，最后导致短路发生。In the manufacture of liquid crystal displays (LCDs), the problem of residual patterning of a certain layer of electrodes often occurs. Residual conductive materials are generated in certain non-set areas, and the display quality of the panel may be affected according to the degree. In actual production experience, this risk is common in the formation of indium tin oxide. tin oxide (ITO) layer, especially when the flatness of the substrate surface under the ITO layer is poor, when yellow light is patterned, the photoresistor (PR) is easy to be low in the terrain, narrow and the step changes after coating. Thick film is deposited in a large area, and the exposure and development are not complete, which leads to the formation of residues in the ITO layer during etching, and finally causes a short circuit.
技术问题technical problem
COA阵列基板、制备方法及显示装置，以解决ITO残留问题的同时降低DBS公共电极走线的导通电阻。The COA array substrate, the preparation method and the display device are used to solve the problem of ITO residuals and reduce the on-resistance of the DBS common electrode traces.
技术解决方案Technical solutions
一种COA阵列基板，包括：设于基板上的TFT结构；设于TFT结构上方的彩色滤光层图形；所述彩色滤光层图形在栅极线区域挖开，在数据线区域互相连接交叠；在数据线上方平行设有DBS公共电极走线；在栅极线区域设有沿栅极线方向延伸将相邻两DBS公共电极走线互相连接的至少一条ITO连接线，至少一条所述ITO连接线为沿彩色滤光层图形边界的坡面底部延伸的ITO连接线。A COA array substrate includes: a TFT structure provided on the substrate; a color filter layer pattern provided above the TFT structure; the color filter layer pattern is excavated in a gate line region and connected to each other in a data line region; Overlay the DBS common electrode traces in parallel above the data lines; at least one ITO connection line extending in the direction of the gate line and connecting two adjacent DBS common electrode traces to each other, at least one of which is described above The ITO connecting line is an ITO connecting line extending along the bottom of the slope of the pattern boundary of the color filter layer.
在本申请实施例所提供的COA阵列基板中，在栅极线区域仅设有一条沿彩色滤光层图形边界坡面底部延伸的ITO连接线。In the COA array substrate provided in the embodiment of the present application, there is only one ITO connection line extending along the bottom of the slope of the boundary of the color filter layer pattern in the gate line area.
在本申请实施例所提供的COA阵列基板中，在栅极线区域设有一条ITO连接线，所述ITO连接线临近栅极线平行延伸并在TFT结构处转折以绕过TFT结构。In the COA array substrate provided in the embodiment of the present application, an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
在本申请实施例所提供的COA阵列基板中，所述沿彩色滤光层图形边界坡面底部延伸的ITO连接线临近TFT结构设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线。In the COA array substrate provided in the embodiment of the present application, the ITO connection line extending along the bottom of the color filter layer pattern boundary slope surface is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure and is connected to DBS common electrode traces.
在本申请实施例所提供的COA阵列基板中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线靠近彩色滤光层图形一侧的边界至少与彩色滤光层图形边界的坡面底边对齐，或者有3微米以下的交叠；远离彩色滤光层图形一侧的边界至少距离彩色滤光层图形边界的坡面底边1.5微米。In the COA array substrate provided in the embodiment of the present application, the boundary of the ITO connection line extending along the bottom of the slope of the color filter layer pattern border near the color filter layer pattern is at least equal to the color filter layer pattern boundary. The bottom edge of the slope is aligned, or there is an overlap of less than 3 microns; the boundary on one side far from the color filter pattern is at least 1.5 microns from the bottom edge of the color filter pattern.
在本申请实施例所提供的COA阵列基板中，所述栅极线区域设有黑色隔垫物。In the COA array substrate provided in the embodiment of the present application, the gate line region is provided with a black spacer.
一种显示装置包括一COA阵列基板，所述COA阵列基板包括：A display device includes a COA array substrate. The COA array substrate includes:
彩色滤光层图形，所述彩色滤光层图形在栅极线区域挖开，在数据线区域4互相连接交叠；A color filter layer pattern, the color filter layer pattern is dug in a gate line region, and is connected and overlapped with each other in a data line region 4;
ITO导电电极图形，所述ITO导电电极图形包括：ITO conductive electrode pattern, the ITO conductive electrode pattern includes:
DBS公共电极走线，所述DBS公共电极走线平行设置于在数据线上；以及DBS common electrode traces, which are arranged in parallel on the data lines; and
至少一条ITO连接线，所述至少一条ITO连接线连接在栅极线区域设置的沿栅极线方向延伸将相邻两DBS公共电极走线，至少一条所述ITO连接线沿彩色滤光层图形的边界的坡面底部延伸。At least one ITO connection line, the at least one ITO connection line is connected in the gate line area and extends in the direction of the gate line to route two adjacent DBS common electrodes, and at least one of the ITO connection lines is along the color filter layer pattern The boundary of the slope extends at the bottom.
在本申请实施例所提供的COA阵列基板中，在栅极线区域仅设有一条沿彩色滤光层图形边界的坡面底部延伸的ITO连接线。In the COA array substrate provided in the embodiment of the present application, there is only one ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer in the gate line area.
在本申请实施例所提供的COA阵列基板中，在栅极线区域设有一条ITO连接线，所述ITO连接线临近栅极线平行延伸并在TFT结构处转折以绕过TFT结构。In the COA array substrate provided in the embodiment of the present application, an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
在本申请实施例所提供的COA阵列基板中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线临近TFT结构设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线。In the COA array substrate provided in the embodiment of the present application, the ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure connection Route to DBS common electrode.
在本申请实施例所提供的COA阵列基板中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线靠近彩色滤光层图形一侧的边界至少与彩色滤光层图形边界的坡面底边对齐，或者有3微米以下的交叠；远离彩色滤光层图形一侧的边界至少距离彩色滤光层图形边界的坡面底边1.5微米。In the COA array substrate provided in the embodiment of the present application, the boundary of the ITO connection line extending along the bottom of the slope of the color filter layer pattern border near the color filter layer pattern is at least equal to the color filter layer pattern boundary. The bottom edge of the slope is aligned, or there is an overlap of less than 3 microns; the boundary on one side far from the color filter pattern is at least 1.5 microns from the bottom edge of the color filter pattern.
在本申请实施例所提供的COA阵列基板中，所述栅极线区域设有黑色隔垫物。In the COA array substrate provided in the embodiment of the present application, the gate line region is provided with a black spacer.
一种COA阵列基板的制备方法，包括：A method for preparing a COA array substrate includes:
在基板上制备TFT阵列；Preparing a TFT array on a substrate;
沉积第一绝缘保护层；Depositing a first insulating protective layer;
制备图形化彩色滤光层图形，所述彩色滤光层图形在栅极线区域挖开，在数据线区域互相连接交叠；Preparing a patterned color filter layer pattern, the color filter layer pattern is dug in a gate line area, and is connected and overlapped with each other in a data line area;
沉积第二绝缘保护层；Depositing a second insulating protective layer;
制备ITO导电电极图形；Preparing ITO conductive electrode patterns;
所述ITO导电电极图形包括在数据线上方平行设置的DBS公共电极走线；以及在栅极线区域设置的沿栅极线方向延伸将相邻两DBS公共电极走线互相连接的至少一条ITO连接线，至少一条所述ITO连接线为沿彩色滤光层图形边界坡面底部延伸的ITO连接线。The ITO conductive electrode pattern includes a DBS common electrode trace arranged in parallel above the data line; and at least one ITO connection extending in the gate line direction and extending in the direction of the gate line to connect two adjacent DBS common electrode traces to each other. Line, at least one of said ITO connecting lines is an ITO connecting line extending along the bottom of the slope of the boundary of the color filter layer pattern.
在本申请实施例所提供的COA阵列基板的制备方法中，在栅极线区域仅设置一条沿彩色滤光层图形边界坡面底部延伸的ITO连接线。In the method for preparing a COA array substrate provided in the embodiments of the present application, only one ITO connection line extending along the bottom of the slope of the boundary of the color filter layer pattern is provided in the gate line region.
在本申请实施例所提供的COA阵列基板的制备方法中，在栅极线区域设有一条ITO连接线，所述ITO连接线临近栅极线平行延伸并在TFT结构处转折以绕过TFT结构。In the method for preparing a COA array substrate provided in the embodiments of the present application, an ITO connection line is provided in a gate line region, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure. .
在本申请实施例所提供的COA阵列基板的制备方法中，所述沿彩色滤光层图形边界坡面底部延伸的ITO连接线临近TFT结构设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线。In the method for preparing a COA array substrate provided in the embodiment of the present application, the ITO connection line extending along the bottom of the color filter layer pattern boundary slope surface is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT. The structure is connected to the DBS common electrode trace.
在本申请实施例所提供的COA阵列基板的制备方法中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线靠近彩色滤光层图形一侧的边界至少与彩色滤光层图形边界的坡面底边对齐，或者有3微米以下的交叠；远离彩色滤光层图形一侧的边界至少距离彩色滤光层图形边界的坡面底边1.5微米。In the method for preparing a COA array substrate provided in the embodiment of the present application, the boundary of the ITO connection line extending along the bottom of the slope of the border of the color filter layer pattern close to the side of the color filter layer pattern is at least equal to the color filter layer. The bottom edge of the slope of the graphic boundary is aligned, or there is an overlap of less than 3 microns; the boundary far from the side of the color filter pattern is at least 1.5 microns from the bottom edge of the slope of the color filter pattern boundary.
在本申请实施例所提供的COA阵列基板的制备方法中，在所述栅极线区域设置黑色隔垫物。。In the method for manufacturing a COA array substrate provided in the embodiments of the present application, a black spacer is provided in the gate line region. .
有益效果Beneficial effect
本申请所提供的COA阵列基板、制备方法及显示装置的有益效果是：本申请的COA阵列基板、制备方法及显示装置设置一条在彩色滤光膜图形坡面边界底端的ITO连接线，利用ITO易形成残留的边界地势，稳定成膜，降低导通阻抗；同时还避免ITO连接线与金属走线的交叉，降低断路风险。The beneficial effects of the COA array substrate, the preparation method and the display device provided by the present application are: the COA array substrate, the preparation method and the display device of the present application are provided with an ITO connection line at the bottom end of the slope boundary of the color filter pattern, and the ITO It is easy to form a residual boundary terrain, stabilize the film formation, and reduce the on-resistance; at the same time, avoid the intersection of the ITO connection line and the metal trace, and reduce the risk of disconnection.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to explain the technical solutions in the embodiments of the present application more clearly, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are just some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative labor.
图1是本申请所提供的COA阵列基板的第一种实施方式的示意图。FIG. 1 is a schematic diagram of a first embodiment of a COA array substrate provided by the present application.
图2是本申请所提供的COA阵列基板的第二种实施方式的示意图。FIG. 2 is a schematic diagram of a second embodiment of a COA array substrate provided in the present application.
图3是本申请所提供的COA阵列基板的第三种实施方式的示意图。FIG. 3 is a schematic diagram of a third embodiment of a COA array substrate provided by the present application.
图4是本申请所提供的COA阵列基板的第四种实施方式的示意图。FIG. 4 is a schematic diagram of a fourth embodiment of a COA array substrate provided by the present application.
图5A及5B为本申请所提供的COA阵列基板的ITO连接线沿彩色滤光层图形的边界的坡面底部延伸的剖面示意图。5A and 5B are schematic cross-sectional views of the ITO connection line of the COA array substrate provided along the bottom of the slope of the boundary of the color filter layer pattern provided in the present application.
本发明的实施方式Embodiments of the invention
在LCD制造中，主要有M1/M2/ITO（金属层1/金属层2/氧化铟锡）用作图形化电极层，在设计和制程中均需要保证成膜图形的间距，尤其是同层材料不同电极之间的安全距离(视尺寸分辨率等而定，以ITO为例一般5um左右) ，以防止短接或串扰。In LCD manufacturing, M1 / M2 / ITO (metal layer 1 / metal layer 2 / indium tin oxide) is mainly used as a patterned electrode layer. In the design and manufacturing process, it is necessary to ensure the spacing of film formation patterns, especially the same layer. The safe distance between different electrodes of the material (depending on dimensional resolution, etc., generally about 5um with ITO as an example) to prevent short circuit or crosstalk.
同时除了设计和工艺上可以预期的结果外，制程中也常会发生某一层电极图形化残留的问题，在某些非设定区域产生导电材料残留，根据程度不同会对面板显示质量产生影响。于生产经验中，该风险常见于ITO道次，尤其是当ITO下层基板地形平整度差时，，例如COA(Color Filter On Array)阵列基板，更具体的例如CF（彩色滤光层）材料过孔周围或者图形区块四周易发生ITO残留。At the same time, in addition to the results that can be expected in design and process, the problem of residual patterning of a certain layer of electrode often occurs in the process. Residual conductive materials are generated in certain non-set areas, which will affect the display quality of the panel according to the degree. In production experience, this risk is common in ITO passes, especially when the topography of the underlying ITO substrate is poor, such as COA (Color Filter On Array) array substrates, such as CF (color filter layer) material via holes or around graphic blocks, are more prone to ITO residues.
由于ITO无机薄膜在COA制程中，因其下层地形凹凸不平，黄光图形化时，光刻胶（PR）涂敷后易在地势低，狭窄，段差变化大的区域沉积厚膜，曝光显影不完全，导致下方ITO在蚀刻时残留，最后导致短路发生。Because the ITO inorganic film is in the COA process, the underlying terrain is uneven. When yellow light is patterned, the photoresist (PR) is easy to deposit thick films in areas with low terrain, narrow, and large step changes after exposure. Complete, which causes the remaining ITO to remain during etching, and finally causes a short circuit.
目前COA架构常用设计是RGB分别为色阻条状，但也有新的架构采用CF 岛状架构，特征是在栅极线等区域中挖开色阻，且常见于BPS 1Tone架构应用中。At present, the common design of the COA architecture is that RGB are color-resistance strips, but there are also new architectures using CF island architectures, which are characterized by digging out color resistance in areas such as gate lines and are commonly used in BPS 1Tone architecture application.
请参阅图1，图1是本申请所提供的COA阵列基板的第一种实施方式的示意图。彩色滤光层1所形成的色阻在横向栅极线区域2挖开而不连续，形成岛状架构，在数据线区域4互相连接交叠；栅极线区域2对应于BPS区域，后续在此区域涂敷BPS材料，流平后经曝光显影，形成长条纹型BPS图案，并得到最终隔垫物结构。由于栅极线区域2挖开，因此彩色滤光层1的图形边界26数骤增，导致ITO后续沉积时的地形状况不佳；其次竖向除了数据（Data）线28外，数据线102上方还设置有ITO线条——DBS公共电极（DBS Com）走线24，利用DBS（Data BM Less）技术控制液晶电位而实现遮光。Please refer to FIG. 1, which is a schematic diagram of a first embodiment of a COA array substrate provided by the present application. The color resistance formed by the color filter layer 1 is dug and discontinued in the lateral gate line region 2 to form an island-like structure, and the data line region 4 is connected and overlapped with each other; the gate line region 2 corresponds to the BPS region, and is subsequently This area is coated with BPS material, leveled and developed by exposure to form a long-striped BPS pattern, and the final spacer structure is obtained. Because the gate line area 2 is dug, the number of graphic boundaries 26 of the color filter layer 1 increases sharply, resulting in poor topographical conditions during subsequent deposition of ITO; secondly, except for the data line 28, above the data line 102 It is also provided with an ITO line—DBS common electrode (DBS Com) trace 24, which uses DBS (Data BM Less) technology to control the liquid crystal potential to achieve light shielding.
请参阅图2，图2是本申请所提供的COA阵列基板的第二种实施方式的示意图。所述COA阵列基板100主要包括：设于基板5上的TFT结构31，含栅极线29和数据线102，整面覆盖有第一绝缘保护层32；设于TFT结构31上方的彩色滤光层图形22，即RGB色阻；彩色滤光层图形22在栅极线区域2挖开，栅极线区域2除设有栅极线29外，还设有用于TFT结构31漏电极或者存储电容的源漏极金属块状图案21，后续可制作黑色隔垫物36，彩色滤光层图形22在数据线区域4互相连接交叠；后续沉积第二绝缘保护层33，再制备ITO导电电极图形103。Please refer to FIG. 2, which is a schematic diagram of a second embodiment of a COA array substrate provided by the present application. The COA array substrate 100 mainly includes: a TFT structure 31 provided on the substrate 5, including a gate line 29 and a data line 102, and the entire surface is covered with a first insulating protection layer 32; and a color filter provided above the TFT structure 31 The layer pattern 22 is the RGB color resistance; the color filter layer pattern 22 is cut out in the gate line region 2. In addition to the gate line 29, the gate line region 2 is also provided with a drain electrode or a storage capacitor for the TFT structure 31 Source and drain metal block pattern 21, a black spacer 36 can be made subsequently, and a color filter layer pattern 22 is connected and overlapped with each other in the data line region 4; a second insulating protection layer 33 is subsequently deposited, and an ITO conductive electrode pattern is prepared 103.
ITO导电电极图形103主要包括：设置于彩色滤光层图形22上的像素电极23；在数据线102上方平行设置的DBS公共电极走线24，用于液晶显示中实现遮光；在栅极线区域2仅设有一条沿栅极线29方向延伸将相邻两DBS公共电极走线24互相连接的ITO连接线28，ITO连接线28沿彩色滤光层图形22边界26的坡面底部延伸；栅极线区域2除设有栅极线29外，还设有用于TFT漏电极或者存储电容的源漏极金属块状图案21。The ITO conductive electrode pattern 103 mainly includes: a pixel electrode 23 provided on the color filter layer pattern 22; a DBS common electrode trace 24 arranged in parallel above the data line 102 for light shielding in a liquid crystal display; and a gate line region 2 There is only one ITO connection line 28 extending along the gate line 29 and connecting two adjacent DBS common electrode traces 24 to each other. The ITO connection line 28 extends along the bottom of the slope of the boundary 26 of the color filter layer pattern 22; In addition to the gate line 29, the electrode line region 2 is provided with a source-drain metal block pattern 21 for a TFT drain electrode or a storage capacitor.
请参阅图3，图3是本申请所提供的COA阵列基板的第三种实施方式的示意图。Please refer to FIG. 3, which is a schematic diagram of a third embodiment of a COA array substrate provided by the present application.
ITO导电电极图形103主要包括：设置于彩色滤光层图形22上的像素电极23；在数据线102上方平行设置的DBS公共电极走线24，用于液晶显示中实现遮光；在栅极线区域2设有沿栅极线29方向延伸将相邻两DBS公共电极走线24互相连接的ITO连接线25和27，至少一条ITO连接线27沿彩色滤光层图形22边界26的坡面底部延伸，解决残留问题，同时避免与金属走线的交叉。ITO连接线25大体上临近栅极线29平行延伸并在TFT结构31处转折以绕过TFT结构31。本申请利用ITO残留的特点形成完整的ITO连接线，提供多的导通路径，进一步降低阻抗，提高稳定性；避免ITO在金属线上的断裂。相邻公共电极走线 24之间在栅极线29所在区域设有ITO连接线25进行连接，以降低阻抗。The ITO conductive electrode pattern 103 mainly includes: a pixel electrode 23 provided on the color filter layer pattern 22; a DBS common electrode trace 24 arranged in parallel above the data line 102 for light shielding in a liquid crystal display; and a gate line region 2 There are ITO connecting lines 25 and 27 extending along the gate line 29 and connecting two adjacent DBS common electrode traces 24 to each other. At least one ITO connecting line 27 extends along the bottom of the slope of the boundary 26 of the color filter layer pattern 22 , Solve the residual problem, and avoid crossing with metal traces. The ITO connection line 25 extends substantially parallel to the gate line 29 and turns at the TFT structure 31 to bypass the TFT structure 31. This application utilizes the characteristics of ITO residues to form a complete ITO connection line, provides multiple conduction paths, further reduces impedance, improves stability, and avoids ITO breakage on metal lines. An ITO connection line 25 is provided between adjacent common electrode traces 24 in the area where the gate line 29 is located to reduce impedance.
因BPS技术开发中的新架构和新的风险，本申请提出针对CF岛状+DBS公共电极走线技术，设置一条在CF图形坡面边界26底端的ITO连接线，利用ITO易形成残留的边界26地势，稳定成膜，降低导通阻抗。同时还避免ITO连接线与金属走线的交叉，降低断路风险。Due to the new architecture and new risks in the development of BPS technology, this application proposes a ITO connection line at the bottom of the CF pattern slope boundary 26 for the CF island + DBS common electrode routing technology. The residual boundary is easily formed by using ITO 26 terrain, stable film formation, reducing on-resistance. At the same time, the intersection of the ITO connection line and the metal trace is avoided, and the risk of disconnection is reduced.
请参阅图4，图4是本申请所提供的COA阵列基板的第四种实施方式的示意图。Please refer to FIG. 4, which is a schematic diagram of a fourth embodiment of a COA array substrate provided by the present application.
ITO导电电极图形103主要包括：设置于彩色滤光层图形22上的像素电极23；在数据线102上方平行设置的DBS公共电极走线24，用于液晶显示中实现遮光；在栅极线区域2设有沿栅极线29方向延伸将相邻两DBS公共电极走线24互相连接的ITO连接线27，ITO连接线27沿彩色滤光层图形22边界26的坡面底部延伸；栅极线区域2除设有栅极线29外，还设有用于TFT结构31漏电极或者存储电容的源漏极金属块状图案21。ITO连接线27临近TFT结构31设有分支连接线30，所述分支连接线30绕过TFT结构31连接至DBS公共电极走线24，有利于给TFT形成对称均匀的外部电场影响。The ITO conductive electrode pattern 103 mainly includes: a pixel electrode 23 provided on the color filter layer pattern 22; a DBS common electrode trace 24 arranged in parallel above the data line 102 for light shielding in a liquid crystal display; and a gate line region 2 It is provided with an ITO connection line 27 extending along the gate line 29 and connecting two adjacent DBS common electrode traces 24 to each other. The ITO connection line 27 extends along the bottom of the slope of the boundary 26 of the color filter layer pattern 22; the gate line In addition to the gate line 29, the region 2 is provided with a source-drain metal block pattern 21 for a drain electrode or a storage capacitor of the TFT structure 31. The ITO connection line 27 is provided with a branch connection line 30 adjacent to the TFT structure 31, and the branch connection line 30 bypasses the TFT structure 31 and is connected to the DBS common electrode trace 24, which is beneficial to forming a symmetrical and uniform external electric field effect on the TFT.
图5A及5B为本申请COA阵列基板的ITO连接线沿彩色滤光层图形的边界的坡面底部延伸的剖面示意图，绘示了两种可能的坡面剖面结构。沿彩色滤光层图形40的边界26的坡面底部延伸的ITO连接线41靠近彩色滤光层图形40一侧的边界26至少与彩色滤光层图形40边界26的坡面底边对齐，或者有3微米以下优选为2~3微米的交叠；远离彩色滤光层图形一侧的边界26至少距离彩色滤光层图形边界26的坡面底边1.5微米。5A and 5B are schematic cross-sectional views of the ITO connection line of the COA array substrate of the present application extending along the bottom of the slope of the boundary of the color filter layer pattern, showing two possible slope cross-sectional structures. The ITO connecting line 41 extending along the bottom of the slope of the boundary 26 of the color filter pattern 40 is close to the boundary 26 on the side of the color filter pattern 40 at least with the bottom of the slope of the boundary 26 of the color filter pattern 40, or There is an overlap of less than 3 micrometers, preferably 2 to 3 micrometers; the boundary 26 on the side far from the color filter layer pattern is at least 1.5 micrometers from the bottom edge of the slope of the color filter layer pattern boundary 26.
本申请使用新的ITO连接线用以连接DBS公共电极走线，新的ITO连接线设置于CF岛状的边界的坡面上(为非像素电极爬坡侧)。ITO连接线可以全部形成于CF坡面地形的低端，也可以部分形成在CF的坡面斜坡上。ITO连接线可以不止一条，但至少含有本申请所提出的新的连接线。利用不平整特殊地形所致的ITO残留，定义并形成图形化的ITO连接线，解决残留问题的同时，降低其他主要ITO公共电极走线的导通电阻。This application uses a new ITO connection line to connect the DBS common electrode traces. The new ITO connection line is provided on the slope of the CF island-like boundary (the non-pixel electrode climbing side). The ITO connection line can be formed entirely on the low end of the CF slope, or it can be partially formed on the CF slope. There can be more than one ITO connection line, but at least the new connection line proposed in this application. Use the ITO residue caused by uneven special terrain to define and form a patterned ITO connection line, while solving the residue problem, reduce the on-resistance of other main ITO common electrode traces.
本申请还提供了相应的显示装置，包括上述的COA阵列基板。The present application also provides a corresponding display device, including the above-mentioned COA array substrate.
本申请还提供了上述COA阵列基板的制备方法，主要包括：This application also provides a method for preparing the COA array substrate, which mainly includes:
在基板上制备TFT结构，含栅极线和数据线；Preparing a TFT structure on a substrate, including a gate line and a data line;
沉积第一绝缘保护层；Depositing a first insulating protective layer;
制备彩色滤光层图形，所述彩色滤光层图形在栅极线区域挖开，在数据线区域互相连接交叠；RGB色阻在栅极线区域挖开不连续，在数据线区域互相连接交叠；A color filter layer pattern is prepared, the color filter layer pattern is dug in the gate line area, and is connected and overlapped with each other in the data line area; the RGB color resistance is dug out and discontinuous in the gate line area, and connected to each other in the data line area. overlap;
沉积第二绝缘保护层；Depositing a second insulating protective layer;
制备ITO导电电极图形；Preparing ITO conductive electrode patterns;
所述ITO导电电极图形包括在数据线上方平行设置的DBS公共电极走线；以及在栅极线区域设置的沿栅极线方向延伸将相邻两DBS公共电极走线互相连接的至少一条ITO连接线，至少一条所述ITO连接线为沿彩色滤光层图形边界的坡面底部延伸的ITO连接线。The ITO conductive electrode pattern includes a DBS common electrode trace arranged in parallel above the data line; and at least one ITO connection extending in the gate line direction and extending in the direction of the gate line to connect two adjacent DBS common electrode traces to each other. Line, at least one of the ITO connection lines is an ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer.
后续形成黑色隔垫物，组装对侧基板等步骤在此不再赘述。The subsequent steps of forming a black spacer and assembling the opposite substrate are not repeated here.
本申请在栅极线区域可以仅设置一条沿彩色滤光层图形边界的坡面底部延伸的ITO连接线，结构简单。沿彩色滤光层图形边界的坡面底部延伸的ITO连接线临近TFT结构可以设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线，有利于给TFT形成对称均匀的外部电场影响。In the present application, only one ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer can be provided in the gate line region, and the structure is simple. The ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer can be provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure and connects to the DBS common electrode traces, which is conducive to forming a symmetrical and uniform TFT External electric field effects.
综上，本申请的COA阵列基板、制备方法及显示装置设置一条在彩色滤光膜图形坡面边界底端的ITO连接线，利用ITO易形成残留的边界地势，稳定成膜，降低导通阻抗；同时还避免ITO连接线与金属走线的交叉，降低断路风险。In summary, the COA array substrate, the preparation method and the display device of the present application are provided with an ITO connection line at the bottom end of the slope boundary of the color filter film pattern. The residual boundary terrain is easily formed by using ITO to stabilize the film formation and reduce the on-resistance; At the same time, the intersection of the ITO connection line and the metal trace is avoided, and the risk of disconnection is reduced.
以上所述，对于本领域的普通技术人员来说，可以根据本申请的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本申请后附的权利要求的保护范围。。As mentioned above, for a person of ordinary skill in the art, various other corresponding changes and modifications can be made according to the technical solutions and technical concepts of this application, and all these changes and modifications should belong to the claims appended to this application. Scope of protection. .

Claims (18)

  1. 一种COA阵列基板，其中，包括：设于基板上的TFT结构；设于TFT结构上方的彩色滤光层图形；所述彩色滤光层图形在栅极线区域挖开，在数据线区域互相连接交叠；在数据线上方平行设有DBS公共电极走线；在栅极线区域设有沿栅极线方向延伸将相邻两DBS公共电极走线互相连接的至少一条ITO连接线，至少一条所述ITO连接线为沿彩色滤光层图形边界的坡面底部延伸的ITO连接线。A COA array substrate includes: a TFT structure provided on the substrate; a color filter layer pattern provided above the TFT structure; the color filter layer pattern is cut out in a gate line region and mutually in a data line region; Overlapping connections; DBS common electrode traces are arranged in parallel above the data lines; at least one ITO connection line extending in the direction of the gate line to connect two adjacent DBS common electrode traces to each other, at least one The ITO connection line is an ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer.
  2. 如权利要求1所述的COA阵列基板，其中，在栅极线区域仅设有一条沿彩色滤光层图形边界坡面底部延伸的ITO连接线。The COA array substrate according to claim 1, wherein only one ITO connection line extending along a bottom of a boundary slope of a color filter layer pattern is provided in the gate line region.
  3. 如权利要求1所述的COA阵列基板，其中，在栅极线区域设有一条ITO连接线，所述ITO连接线临近栅极线平行延伸并在TFT结构处转折以绕过TFT结构。The COA array substrate according to claim 1, wherein an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
  4. 如权利要求1所述的COA阵列基板，其中，所述沿彩色滤光层图形边界坡面底部延伸的ITO连接线临近TFT结构设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线。The COA array substrate according to claim 1, wherein the ITO connection line extending along the bottom of the color filter layer pattern boundary slope surface is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure and is connected to DBS common electrode traces.
  5. 如权利要求1所述的COA阵列基板，其中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线靠近彩色滤光层图形一侧的边界至少与彩色滤光层图形边界的坡面底边对齐，或者有3微米以下的交叠；远离彩色滤光层图形一侧的边界至少距离彩色滤光层图形边界的坡面底边1.5微米。The COA array substrate according to claim 1, wherein the boundary of the ITO connection line extending along the bottom of the slope of the color filter pattern boundary near the color filter pattern side is at least equal to that of the color filter layer pattern. The bottom edge of the slope is aligned, or there is an overlap of less than 3 microns; the boundary on one side far from the color filter pattern is at least 1.5 microns from the bottom edge of the color filter pattern.
  6. 如权利要求1所述的COA阵列基板，其中，所述栅极线区域设有黑色隔垫物。The COA array substrate according to claim 1, wherein a black spacer is provided in the gate line region.
  7. 一种显示装置包括一COA阵列基板，其中，所述COA阵列基板包括：A display device includes a COA array substrate, wherein the COA array substrate includes:
    彩色滤光层图形，所述彩色滤光层图形在栅极线区域挖开，在数据线区域4互相连接交叠；A color filter layer pattern, the color filter layer pattern is dug in a gate line region, and is connected and overlapped with each other in a data line region 4;
    ITO导电电极图形，所述ITO导电电极图形包括：ITO conductive electrode pattern, the ITO conductive electrode pattern includes:
    DBS公共电极走线，所述DBS公共电极走线平行设置于在数据线上；以及DBS common electrode traces, which are arranged in parallel on the data lines; and
    至少一条ITO连接线，所述至少一条ITO连接线连接在栅极线区域设置的沿栅极线方向延伸将相邻两DBS公共电极走线，至少一条所述ITO连接线沿彩色滤光层图形的边界的坡面底部延伸。At least one ITO connection line, the at least one ITO connection line is connected in the gate line area and extends in the direction of the gate line to route two adjacent DBS common electrodes, and at least one of the ITO connection lines is along the color filter layer pattern The boundary of the slope extends at the bottom.
  8. 如权利要求7所述的COA阵列基板，其中，在栅极线区域仅设有一条沿彩色滤光层图形边界的坡面底部延伸的ITO连接线。The COA array substrate according to claim 7, wherein only one ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer is provided in the gate line region.
  9. 如权利要求7所述的COA阵列基板，其中，在栅极线区域设有一条ITO连接线，所述ITO连接线临近栅极线平行延伸并在TFT结构处转折以绕过TFT结构。The COA array substrate according to claim 7, wherein an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure.
  10. 如权利要求7所述的COA阵列基板，其中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线临近TFT结构设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线。The COA array substrate according to claim 7, wherein the ITO connection line extending along the bottom of the slope of the pattern boundary of the color filter layer is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT structure and is connected Route to DBS common electrode.
  11. 如权利要求7所述的COA阵列基板，其中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线靠近彩色滤光层图形一侧的边界至少与彩色滤光层图形边界的坡面底边对齐，或者有3微米以下的交叠；远离彩色滤光层图形一侧的边界至少距离彩色滤光层图形边界的坡面底边1.5微米。The COA array substrate according to claim 7, wherein the boundary of the ITO connection line extending along the bottom of the slope of the border of the color filter pattern near the color filter pattern is at least equal to the border of the color filter pattern. The bottom edge of the slope is aligned, or there is an overlap of less than 3 microns; the boundary on one side far from the color filter pattern is at least 1.5 microns from the bottom edge of the color filter pattern.
  12. 如权利要求7所述的COA阵列基板，其中，所述栅极线区域设有黑色隔垫物。The COA array substrate according to claim 7, wherein a black spacer is provided in the gate line region.
  13. 一种COA阵列基板的制备方法，其中，包括：A method for preparing a COA array substrate, including:
    在基板上制备TFT阵列；Preparing a TFT array on a substrate;
    沉积第一绝缘保护层；Depositing a first insulating protective layer;
    制备图形化彩色滤光层图形，所述彩色滤光层图形在栅极线区域挖开，在数据线区域互相连接交叠；Preparing a patterned color filter layer pattern, the color filter layer pattern is dug in a gate line area, and is connected and overlapped with each other in a data line area;
    沉积第二绝缘保护层；Depositing a second insulating protective layer;
    制备ITO导电电极图形；Preparing ITO conductive electrode patterns;
    所述ITO导电电极图形包括在数据线上方平行设置的DBS公共电极走线；以及在栅极线区域设置的沿栅极线方向延伸将相邻两DBS公共电极走线互相连接的至少一条ITO连接线，至少一条所述ITO连接线为沿彩色滤光层图形边界坡面底部延伸的ITO连接线。The ITO conductive electrode pattern includes a DBS common electrode trace arranged in parallel above the data line; and at least one ITO connection extending in the gate line direction and extending in the direction of the gate line to connect two adjacent DBS common electrode traces to each other. Line, at least one of said ITO connecting lines is an ITO connecting line extending along the bottom of the slope of the boundary of the color filter layer pattern.
  14. 如权利要求13所述的COA阵列基板的制备方法，其中，在栅极线区域仅设置一条沿彩色滤光层图形边界坡面底部延伸的ITO连接线。The method for manufacturing a COA array substrate according to claim 13, wherein only one ITO connection line extending along a bottom of a slope surface of a border of the color filter layer pattern is provided in the gate line region.
  15. 如权利要求13所述的COA阵列基板的制备方法，其中，在栅极线区域设有一条ITO连接线，所述ITO连接线临近栅极线平行延伸并在TFT结构处转折以绕过TFT结构。The method for preparing a COA array substrate according to claim 13, wherein an ITO connection line is provided in the gate line area, and the ITO connection line extends parallel to the gate line and turns at the TFT structure to bypass the TFT structure. .
  16. 如权利要求13所述的COA阵列基板的制备方法，其中，所述沿彩色滤光层图形边界坡面底部延伸的ITO连接线临近TFT结构设有分支连接线，所述分支连接线绕过TFT结构连接至DBS公共电极走线。The method for preparing a COA array substrate according to claim 13, wherein the ITO connection line extending along the bottom of the color filter layer pattern boundary slope surface is provided with a branch connection line adjacent to the TFT structure, and the branch connection line bypasses the TFT The structure is connected to the DBS common electrode trace.
  17. 如权利要求13所述的COA阵列基板的制备方法，其中，所述沿彩色滤光层图形边界的坡面底部延伸的ITO连接线靠近彩色滤光层图形一侧的边界至少与彩色滤光层图形边界的坡面底边对齐，或者有3微米以下的交叠；远离彩色滤光层图形一侧的边界至少距离彩色滤光层图形边界的坡面底边1.5微米。The method for preparing a COA array substrate according to claim 13, wherein the boundary of the ITO connection line extending along the bottom of the slope of the border of the color filter layer pattern close to the side of the color filter layer pattern is at least equal to the color filter layer The bottom edge of the slope of the graphic boundary is aligned, or there is an overlap of less than 3 microns; the boundary far from the side of the color filter pattern is at least 1.5 microns from the bottom edge of the slope of the color filter pattern boundary.
  18. 如权利要求13所述的COA阵列基板的制备方法，其中，在所述栅极线区域设置黑色隔垫物。。The method for manufacturing a COA array substrate according to claim 13, wherein a black spacer is provided in the gate line region. .
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