CN110967883B

CN110967883B - Liquid crystal display panel and preparation method thereof

Info

Publication number: CN110967883B
Application number: CN201911172429.8A
Authority: CN
Inventors: 张银峰
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2019-11-26
Filing date: 2019-11-26
Publication date: 2022-04-05
Anticipated expiration: 2039-11-26
Also published as: CN110967883A

Abstract

The invention discloses a liquid crystal display panel and a preparation method thereof.A shared electrode of three rows of adjacent pixels is connected by an ITO lead through an opening, so that the sub-area partial pressure design among the pixels is realized; and only the black matrix in the TFT area is reserved to shield the shared electrode, DBS common electrode wiring is adopted in the area where the black matrix is removed, a winding special-shaped DBS design is adopted at an ITO wire adopted due to the shared design of the shared electrode, and the DBS common electrode wiring at the disconnected position is connected to the adjacent direct-connected DBS common electrode wiring in a cross-wiring mode to form the function of effectively conducting to realize DBS.

Description

Liquid crystal display panel and preparation method thereof

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to a liquid crystal display panel and a preparation method thereof.

Background

A conventional liquid crystal display panel generally includes a TFT (thin film transistor) array substrate, a CF (color filter) substrate attached to the TFT array substrate, and a liquid crystal layer disposed between the TFT array substrate and the CF substrate. In the manufacture of liquid crystal display panels, M1/M2/ITO (first metal layer/second metal layer/ITO) is mainly used as a patterned electrode layer. With the gradual popularization of high-specification displays, large panel manufacturers strive for key display technologies such as high layout resolution, low color shift and the like, 3T/3T + and 8domain designs gain wide attention by virtue of excellent color shift performance, and meanwhile, a 4mask process is widely adopted for reducing production cost.

Because the 4mask process integrates a-Si (amorphous silicon active layer) and M2 as a mask, the a-Si layer is slightly wider than the M2 layer due to the limitation of the process, thereby limiting the influence of the layout of the M2 layer on the aperture ratio. Meanwhile, Share bar (shared electrode) in the M2 layer is in direct contact with the a-Si layer, and photogenerated carriers are generated under the condition of illumination, so that the stability of Share bar is influenced, and the normal display of pixels (pixels) is adversely influenced. Under the existing design condition, the M1 slightly wider than the share bar and the a-Si layer is reserved for shading, so that the generation of photogenerated carriers is avoided, and the share bar stability is improved. Although the optical stability can be improved by retaining the design of the M1 layer under the share bar, the physical light-shielding property of the M1 layer also causes a further reduction in the aperture ratio, thereby severely limiting the transmittance.

Referring to fig. 1, a schematic top view of a conventional lcd panel structure is shown, which is a top view from a substrate side of a TFT array substrate, for convenience of display and description, the substrate is omitted in fig. 1, and mainly shows a portion of the lcd panel structure related to the share bar design, and the portions that are not related are not repeated herein. As shown in fig. 1, the liquid crystal display panel mainly includes: a plurality of pixel regions 11 and a plurality of TFT regions 12 defined by intersections of gate lines and data lines (not shown) on the TFT array substrate side, and a BM (black matrix) 13 on the CF substrate side. A pixel electrode 110 is disposed in the pixel region 11, and the pixel region 11 includes a main (main) region 111 and a sub (sub) region 112. The TFT region 12 is disposed between the main region 111 and the sub region 112, and a TFT structure and a share bar (not shown) are disposed in the TFT region 12; the pixel electrodes of the main region 111 and the sub region 112 are respectively connected with corresponding TFT structures through first openings 121, and share bars of three adjacent rows of pixels are connected through second openings 122 by using ITO wires 123, so that share of share bars among pixels is realized, and sub-area voltage division design among pixels is realized; for example, the share bar of the R/G pixel in the adjacent R/G/B pixels is connected to the share bar of the B pixel by an ITO wire through the opening design, so as to realize the sub-differential design of RGB. The BM13 is disposed on the CF substrate and corresponds to the data lines and the TFT regions 12, that is, the projection of the BM13 (for convenience of displaying other structures, the BM13 of the TFT region 12 is shown by a dotted line in the figure) on the TFT array substrate covers the data lines and the share bars between the pixel regions 11, thereby achieving the light shielding effect.

However, since the BM is located on the CF substrate, it is easy to shift when the TFT array substrate and the CF substrate are paired, which affects the light-shielding effect, especially the light-shielding effect for the data line; meanwhile, in the design of the curved panel, the BM on the CF substrate is more likely to shift relatively when the panel is distorted, so that the actual shading effect is deteriorated, and important indexes such as contrast and color shift are deteriorated.

Therefore, it is highly desirable to perform a proper light shielding design on the basis of maintaining the existing share bar sharing design to reduce the risk of group pair offset, so as to implement the wide application of the liquid crystal display panel in high-specification display products, especially curved panel products.

Disclosure of Invention

The invention aims to provide a liquid crystal display panel and a preparation method thereof, aiming at the problems in the prior art, so that share of share bars among pixels can be realized, and the risk of group offset is reduced while shading is realized.

To achieve the above object, the present invention provides a liquid crystal display panel including: the pixel area is defined by the intersection of a gate line and a data line, and comprises a main area and a sub area, and pixel electrodes are arranged in the main area and the sub area; the TFT area is arranged between the main area and the sub area, a TFT structure and a shared electrode are arranged in the TFT area, the pixel electrode of the main area and the pixel electrode of the sub area are respectively connected with the corresponding TFT structure through a first opening, and three adjacent shared electrodes in the same row are connected through a second opening by adopting an ITO lead; the DBS common electrode routing is arranged on the side of the array substrate of the liquid crystal display panel and is parallel to the data line, the projection of the data line on the DBS common electrode routing falls into the DBS common electrode routing, and the DBS common electrode routing is turned at the first opening and/or the second opening to bypass the first opening and/or the second opening; and a black matrix for shielding the TFT region.

In order to achieve the above object, the present invention further provides a method for manufacturing a liquid crystal display panel, including the steps of: providing a substrate, wherein the substrate comprises a pixel region and a TFT region, the pixel region comprises a main region and a sub region, and the TFT region is positioned between the main region and the sub region; preparing a data line and a gate line on the substrate, and preparing a TFT structure and a shared electrode in a region corresponding to the TFT; depositing an insulating protective layer; preparing pixel electrodes on the insulating protection layer corresponding to the pixel regions, wherein the pixel electrodes of the main region and the sub region are respectively connected with the corresponding TFT structures through first openings; preparing an ITO lead on the insulating protective layer corresponding to the TFT area, and connecting three adjacent shared electrodes in the same row through a second opening by adopting the ITO lead; preparing a DBS common electrode wire on the insulating protective layer, wherein the DBS common electrode wire is arranged in parallel with the data wire, the projection of the data wire on the DBS common electrode wire falls into the DBS common electrode wire, and the DBS common electrode wire is turned at the first opening and/or the second opening to bypass the first opening and/or the second opening; and preparing a black matrix corresponding to the TFT area to shield the TFT area.

The invention has the advantages that: according to the invention, the sharing electrodes of three rows of adjacent pixels are connected by the ITO leads through the holes, so that sharing of the sharing electrodes among the pixels is realized, and further, the sub-area partial pressure design among the pixels is realized; black matrixes between main areas and sub areas of the pixel are removed, only the black matrix of the TFT area is reserved to shield the shared electrode, and generation of photo-generated carriers is avoided to improve stability of the shared electrode; DBS common electrode wiring is adopted in the areas where the black matrixes are removed, a winding special-shaped DBS design is adopted at the position of an ITO wire adopted due to the sharing design of the shared electrode, and the DBS common electrode wiring at the disconnected position is connected to the adjacent direct-connected DBS common electrode wiring in a cross-line mode, so that the function of effectively conducting and achieving DBS is formed. According to the invention, the DBS common electrode wiring is integrated on the TFT array substrate side, so that the light leakage phenomenon caused by the group alignment error of the TFT array substrate and the CF substrate can be avoided, the excellent shading performance is realized, and the DBS common electrode wiring can be widely applied to high-specification display products, particularly curved-surface screen products.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic top view of a conventional LCD panel;

FIG. 2 is a schematic top view of a liquid crystal display panel according to the present invention;

FIG. 3 is a schematic flow chart of a method for manufacturing a liquid crystal display panel according to the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The directional phrases used in this disclosure include, for example: up, down, left, right, front, rear, inner, outer, lateral, etc., are simply directions with reference to the drawings. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, it being understood that such described elements may be interchanged under appropriate circumstances. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which have been repeated for purposes of brevity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

According to the liquid crystal display panel, the share bars of three adjacent rows of pixels are connected through the holes by using the ITO leads, so that share bar sharing among the pixels is realized, and sub-area differential design among the pixels is further realized; BM between main areas and sub areas of pixels are removed, BM of a TFT area is reserved, DBS (data BM less) design of an ITO (indium tin oxide) layer is adopted in the BM removing area, a winding special-shaped DBS design is adopted at a disconnected position where DBS cannot be directly connected up and down due to share bar sharing design, and DBS at the disconnected position is connected to adjacent directly connected DBS in an overline mode, so that the function of effectively conducting and realizing DBS is formed. The special DBS design is integrated on the TFT array substrate side, so that the light leakage phenomenon caused by the group alignment error of the TFT array substrate and the CF substrate can be avoided, the excellent shading performance is realized, and the special DBS design can be widely applied to high-specification display products, particularly curved screen products.

Referring to fig. 2, a schematic top view of the liquid crystal display panel structure of the present invention is shown, wherein the top view is performed from one side of the substrate of the TFT array substrate, and for convenience of display and description, the substrate is omitted in fig. 2, and mainly shows portions related to the share bar and DBS design in the liquid crystal display panel structure, and the portions that are not related are not repeated herein. As shown in fig. 2, the liquid crystal display panel mainly includes: a plurality of pixel regions 21, a plurality of TFT regions 22, a DBS common electrode trace 23, and a Black Matrix (BM) 24. The black matrix 24 is used to shield the TFT area 22, and is shown by a dotted line for convenience of displaying other structures.

The pixel region 21 is defined by gate lines and data lines (not shown) crossing each other, and the pixel region 21 includes a main region 211 and a sub region 212, and a pixel electrode 210 is disposed in each of the main region 211 and the sub region 212.

The TFT region 22 is disposed between the main region 211 and the sub-region 212, and a TFT structure and a common electrode (not shown) are disposed in the TFT region 22. The pixel electrode of the main region 211 and the pixel electrode of the sub region 212 are connected to the corresponding TFT structures through first openings 221, respectively. Three adjacent shared electrodes in the same row are connected through a second opening 222 by an ITO lead 223; the shared electrodes of three rows of adjacent pixels are connected by ITO wires through the holes, so that sharing of the shared electrodes among the pixels is realized, and sub-area differential design among the pixels is further realized; for example, the sharing electrode of the R/G pixel in the adjacent R/G/B pixels is connected to the sharing electrode of the B pixel by an ITO (indium tin oxide) conducting wire through the opening design, so that the sub-area voltage dividing design of RGB (red, green and blue) is realized. The shared electrode is used for carrying out sub-area voltage division so as to improve the 8domain visual angle performance.

The DBS common electrode trace 23 is disposed on the array substrate side of the lcd panel and parallel to the data line, and the projection of the data line on the DBS common electrode trace 23 falls into the DBS common electrode trace 23, and the DBS common electrode trace 23 turns around the first opening 221 and the second opening 222 to bypass the first opening 221 and the second opening 222; that is, the DBS common electrode trace 23 completely shields the data line, and a winding special-shaped DBS design is adopted at a disconnected position where the shared area DBS cannot be directly connected up and down due to the shared design of the shared electrode, so that a function of effectively conducting and realizing DBS is formed.

The principle of utilizing DBS (data BM less) technology to control liquid crystal potential to realize shading is as follows: since the potential of the DBS common electrode line 23 and the potential of the CF com (common electrode) of the opposite substrate are both the same common potential, the liquid crystal sandwiched between the DBS common electrode line 23 and the CF com does not rotate regardless of the signal given to the pixel electrode. The liquid crystal does not rotate, which means that the phase of the polarized light is not changed, the polarized light passing through the first layer of polarizer cannot pass through the second layer of polarizer if the phase is not changed in the liquid crystal display in the normally black mode, and the liquid crystal display plays a role of being equivalent to a BM and plays a role in shading light.

In a further embodiment, the DBS common electrode trace 23, the ITO wire 223 and the pixel electrode 210 are made of the same ITO layer.

In a further embodiment, the DBS common electrode trace 23 includes: a first sub-DBS common electrode trace 231, which is disposed in parallel with the first data line and is disconnected at the TFT region 22; a second sub-DBS common electrode trace 232 disposed parallel to the second data line and penetrating the TFT region 22; a DBS connection line 233 is disposed in the TFT region 22, and the DBS connection line 233 turns around the first opening 221 and/or the second opening 222 to bypass the first opening 221 and/or the second opening 222 and connect the first sub-DBS common electrode trace 231 and the second sub-DBS common electrode trace 232 which are adjacent to each other. That is, the DBS common electrode trace 23 adopts a winding-based heterotype DBS design at the disconnected position where the shared area DBS cannot be directly connected up and down due to the shared design of the shared electrode, and connects the DBS at the disconnected position to the adjacent directly connected DBS across wires, thereby forming a function of effectively turning on and realizing DBS.

In a further embodiment, the DBS connection line 233 is led out from the second sub-DBS common electrode trace 232, turns around the first opening 221 near the first opening 221, and is connected to the first sub-DBS common electrode trace 231 on the sub-area 212 side (or the main area 211 side). In other embodiments, the DBS connection line 233 may be led out from the second sub-DBS common electrode line 232, turn near the second opening 222 to bypass the second opening 222, and be connected to the first sub-DBS common electrode line 231 on the main region 211 side (or the sub-region 212 side).

In a further embodiment, the DBS connection line 233 is led out from the second sub-DBS common electrode line 232 and is divided into two

branch connection lines

2331 and 2332 adjacent to the second opening 222, one branch connection line 2331 is connected to the first sub-DBS common electrode line 231 on the main area 211 side by bypassing the second opening 222, and the other branch connection line 2332 is connected to the first sub-DBS common electrode line 231 on the sub-area 212 side by bypassing the first opening 221.

In a further embodiment, the DBS connection line 233 and the ITO wire 223 have a predetermined distance therebetween. When the DBS common electrode trace 23, the ITO wire 223 and the pixel electrode 210 are made of the same ITO layer, the distance between film-forming patterns, especially the safety distance between different electrodes of the same layer of material, needs to be ensured in the manufacturing process to prevent short circuit or crosstalk. The DBS connecting line has the advantages that the DBS connecting line has the function of connecting the DBS overline at the disconnected position to the adjacent direct-connected DBS, the DBS connecting line is effectively conducted, and the DBS connecting line is realized.

As an alternative embodiment, the black matrix 13 may be disposed on one side of the array substrate of the liquid crystal display panel, or may be disposed on one side of the CF substrate corresponding to the array substrate. The black matrix is used for shielding the TFT area, particularly a shared electrode of the TFT area, so that generation of photo-generated carriers is avoided, and stability of the shared electrode is improved.

According to the liquid crystal display panel, the sharing electrodes of three rows of adjacent pixels are connected through the holes by using the ITO leads, so that sharing of the sharing electrodes among the pixels is realized, and further, the sub-area partial pressure design among the pixels is realized; black matrixes between main areas and sub areas of the pixel are removed, only the black matrix of the TFT area is reserved to shield the shared electrode, and generation of photo-generated carriers is avoided to improve stability of the shared electrode; DBS common electrode wiring is adopted in the areas where the black matrixes are removed, a winding special-shaped DBS design is adopted at the position of an ITO wire adopted due to the sharing design of the shared electrode, and the DBS common electrode wiring at the disconnected position is connected to the adjacent direct-connected DBS common electrode wiring in a cross-line mode, so that the function of effectively conducting and achieving DBS is formed. According to the invention, the DBS common electrode wiring is integrated on the TFT array substrate side, so that the light leakage phenomenon caused by the group alignment error of the TFT array substrate and the CF substrate can be avoided, the excellent shading performance is realized, and the DBS common electrode wiring can be widely applied to high-specification display products, particularly curved-surface screen products.

Based on the same inventive concept, the invention also provides a preparation method of the liquid crystal display panel. Referring to fig. 3, a flow chart of a method for manufacturing a liquid crystal display panel according to the present invention is shown. The preparation method of the liquid crystal display panel specifically comprises the following steps: s31: providing a substrate, wherein the substrate comprises a pixel region and a TFT region, the pixel region comprises a main region and a sub region, and the TFT region is positioned between the main region and the sub region; s32: preparing a data line and a gate line on the substrate, and preparing a TFT structure and a shared electrode in a region corresponding to the TFT; s33: depositing an insulating protective layer; s34: preparing pixel electrodes on the insulating protection layer corresponding to the pixel regions, wherein the pixel electrodes of the main region and the sub region are respectively connected with the corresponding TFT structures through first openings; s35: preparing an ITO lead on the insulating protective layer corresponding to the TFT area, and connecting three adjacent shared electrodes in the same row through a second opening by adopting the ITO lead; s36: preparing a DBS common electrode wire on the insulating protective layer, wherein the DBS common electrode wire is arranged in parallel with the data wire, the projection of the data wire on the DBS common electrode wire falls into the DBS common electrode wire, and the DBS common electrode wire is turned at the first opening and/or the second opening to bypass the first opening and/or the second opening; and S37: and preparing a black matrix corresponding to the TFT area so as to shield the TFT area. The TFT structure, the common electrode, the pixel electrode, and the black matrix may be prepared by a conventional process, which is not described herein again.

As an alternative embodiment, the black matrix may be disposed on one side of the array substrate of the liquid crystal display panel, or may be disposed on one side of the CF substrate corresponding to the array substrate. The black matrix is used for shielding the TFT area, particularly a shared electrode of the TFT area, so that generation of photo-generated carriers is avoided, and stability of the shared electrode is improved.

In a further embodiment, the shared electrode and the active layer in the TFT structure are made of the same mask plate, so that the production cost is effectively reduced.

In a further embodiment, the DBS common electrode trace, the ITO wire, and the pixel electrode are made of the same ITO layer, thereby saving the process and effectively reducing the production cost.

In a further embodiment, referring to fig. 2, the DBS common electrode trace 23 includes: a first sub-DBS common electrode trace 231, which is disposed in parallel with the first data line and is disconnected at the TFT region 22; a second sub-DBS common electrode trace 232 disposed parallel to the second data line and penetrating the TFT region 22; a DBS connection line 233 is disposed in the TFT region 22, and the DBS connection line 233 turns around the first opening 221 and/or the second opening 222 to bypass the first opening 221 and/or the second opening 222 and connect the first sub-DBS common electrode trace 231 and the second sub-DBS common electrode trace 232 which are adjacent to each other. That is, the DBS common electrode trace 23 adopts a winding-based heterotype DBS design at the disconnected position where the shared area DBS cannot be directly connected up and down due to the shared design of the shared electrode, and connects the DBS at the disconnected position to the adjacent directly connected DBS across wires, thereby forming a function of effectively turning on and realizing DBS.

In a further embodiment, referring to fig. 2, the DBS connection line 233 is led out from the second sub-DBS common electrode trace 232, turns around the first opening 221 near the first opening 221, and is connected to the first sub-DBS common electrode trace 231 on the sub-area 212 side (or the main area 211 side). In other embodiments, the DBS connection line 233 may be led out from the second sub-DBS common electrode line 232, turn near the second opening 222 to bypass the second opening 222, and be connected to the first sub-DBS common electrode line 231 on the main region 211 side (or the sub-region 212 side).

In a further embodiment, referring to fig. 2, the DBS connection line 233 is led out from the second sub-DBS common electrode line 232 and is divided into two

branch connection lines

2331 and 2332 at a position adjacent to the second opening 222, one branch connection line 2331 is connected to the first sub-DBS common electrode line 231 on the main area 211 side by bypassing the second opening 222, and the other branch connection line 2332 is connected to the first sub-DBS common electrode line 231 on the sub-area 212 side by bypassing the first opening 221.

In a further embodiment, referring to fig. 2, the DBS connection lines 233 and the ITO wires 223 have a predetermined distance therebetween. When the DBS common electrode trace 23, the ITO wire 223 and the pixel electrode 210 are made of the same ITO layer, the distance between film-forming patterns, especially the safety distance between different electrodes of the same layer of material, needs to be ensured in the manufacturing process to prevent short circuit or crosstalk. The DBS connecting line has the advantages that the DBS connecting line has the function of connecting the DBS overline at the disconnected position to the adjacent direct-connected DBS, the DBS connecting line is effectively conducted, and the DBS connecting line is realized.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A liquid crystal display panel, comprising:

the pixel area is defined by the intersection of a gate line and a data line, and comprises a main area and a sub area, and pixel electrodes are arranged in the main area and the sub area;

the TFT area is arranged between the main area and the sub area, a TFT structure and a shared electrode are arranged in the TFT area, the pixel electrode of the main area and the pixel electrode of the sub area are respectively connected with the corresponding TFT structure through a first opening, and three adjacent shared electrodes in the same row are connected through a second opening by adopting an ITO lead;

the DBS common electrode routing is arranged on the side of the array substrate of the liquid crystal display panel and is parallel to the data line, the projection of the data line on the DBS common electrode routing falls into the DBS common electrode routing, and the DBS common electrode routing is turned at the first opening and/or the second opening to bypass the first opening and/or the second opening; and

a black matrix for shielding the TFT region;

wherein the DBS common electrode routing comprises:

a first sub DBS common electrode routing wire which is arranged in parallel with the first data wire and is disconnected at the TFT area;

a second sub DBS common electrode routing wire which is arranged in parallel with the second data line and penetrates through the TFT area;

and the DBS connecting line is arranged in the TFT area, turns at the first opening and/or the second opening to bypass the first opening and/or the second opening, and is connected with the first sub DBS common electrode wiring and the second sub DBS common electrode wiring which are adjacent.

2. The liquid crystal display panel of claim 1, wherein the DBS common electrode trace, the ITO wire, and the pixel electrode are made of a same ITO layer.

3. The liquid crystal display panel according to claim 1, wherein the DBS connection line is led out from the second sub DBS common electrode line, and is divided into two branch connection lines adjacent to the second opening, one of the branch connection lines being connected to the first sub DBS common electrode line on the main region side by bypassing the first opening/the second opening, and the other of the branch connection lines being connected to the first sub DBS common electrode line on the sub region side by bypassing the second opening/the first opening.

4. The liquid crystal display panel according to claim 1, wherein the black matrix is disposed on a side of an array substrate of the liquid crystal display panel or on a side of a CF substrate corresponding to the array substrate.

5. The preparation method of the liquid crystal display panel is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises a pixel region and a TFT region, the pixel region comprises a main region and a sub region, and the TFT region is positioned between the main region and the sub region;

preparing a data line and a gate line on the substrate, and preparing a TFT structure and a shared electrode in a region corresponding to the TFT;

depositing an insulating protective layer;

preparing pixel electrodes on the insulating protection layer corresponding to the pixel regions, wherein the pixel electrodes of the main region and the sub region are respectively connected with the corresponding TFT structures through first openings;

preparing an ITO lead on the insulating protective layer corresponding to the TFT area, and connecting three adjacent shared electrodes in the same row through a second opening by adopting the ITO lead;

preparing a DBS common electrode wire on the insulating protective layer, wherein the DBS common electrode wire is arranged in parallel with the data wire, the projection of the data wire on the DBS common electrode wire falls into the DBS common electrode wire, and the DBS common electrode wire is turned at the first opening and/or the second opening to bypass the first opening and/or the second opening; and

preparing a black matrix corresponding to the TFT area to shield the TFT area;

wherein the DBS common electrode routing comprises:

6. The method according to claim 5, wherein the common electrode and the active layer in the TFT structure are formed by using the same mask.

7. The method of claim 5, wherein the DBS common electrode trace, the ITO conductive line and the pixel electrode are fabricated from the same ITO layer.

8. The manufacturing method according to claim 6, wherein the DBS connection line is led out from the second sub-DBS common electrode wiring, and is divided into two branch connection lines adjacent to the second opening, one of the branch connection lines is connected to the first sub-DBS common electrode wiring on the main area side by bypassing the first opening/the second opening, and the other of the branch connection lines is connected to the first sub-DBS common electrode wiring on the sub-area side by bypassing the second opening/the first opening.