Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
  • H03M13/1148—Structural properties of the code parity-check or generator matrix
  • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
  • H03M13/1148—Structural properties of the code parity-check or generator matrix
  • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/63—Joint error correction and other techniques
  • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/63—Joint error correction and other techniques
  • H03M13/635—Error control coding in combination with rate matching
  • H03M13/6362—Error control coding in combination with rate matching by puncturing
  • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
  • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0041—Arrangements at the transmitter end
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0057—Block codes

Definitions

• the present invention relates to forward error correction, in particular to channel coding for telecommunication systems or parity check for storage devices.
• the present invention in particular provides a variable-length rate-adaptive quasi cyclic (QC) low density parity check (LDPC) code with linear time encoding and low error floor.
• QC quasi cyclic
• LDPC low density parity check
• QC codes are an important class of error-correcting codes having a rich algebraic structure and are widely used in applications.
• a linear (N, K)-code is said to be a QC code of index n, n
• QC LDPC codes are used in many modern communications standards and are adopted for 5G eMBB.
• Message passing decoding algorithms for QC LDPC codes such as BP, Min-Sum, and their modifications (NMSA, OMSA, 7) naturally support a high level of parallelism. Thus they can be used in very high throughput applications with moderate complexity, which is very important for 5G where the throughput is expected to be up to 20Gb/s.
• Fig. 9 A general dataflow of a modern wireless communication system is shown in Fig. 9.
• HARQ hybrid automatic repeat request
• a multi-edge type (MET) QC LDPC code with a raptor-like extension is a very powerful class of forward error correcting codes that can naturally support a length and rate adaptation.
• MET QC LDPC codes can be considered as the standard QC LDPC, where:
• a rate-adaptive MET QC LDPC matrix is usually divided into a core part and a raptor extension part used for HARQ retransmissions.
• This class of matrices is already adopted in the 5G eMBB standard and is considered as a strong candidate for the upcoming 5G URLLC standard.
• the target block error rate for the 5G URLLC standard is expected to be much smaller than for the 5G eMBB standard (from IE-5 down to IE-9).
• a nested family of codes with PCMs obtained from one or several base matrices can be used.
• a family of codes of different rates and lengths can be obtained from mother PCMs using a combination of lifting, shortening and puncturing.
• QC LDPC as well as MET QC LDPC codes are usually decoded by a message passing decoder such as such as BP, Min-Sum, and their modifications (NMSA, OMSA, ). Performance of the concrete codes depend on multiple factors like the base graph (typically optimized using density evolution methods), amount of short cycles and trapping sets, code distance in the lifted graph and etc.
• c (u, p) be a codeword, where it is the vector of information (user) bits and p is the vector of parity bits.
• the first step can be implemented with small complexity since the matrix H and hence its submatrix H u are sparse.
• the second step in the general case is much more complex since the inverse matrix H r t may not be sparse. That is why in the LDPC codes used in practice the submatrix H p is usually a subject to some additional constraints in order to ensure low complexity of the second step of the described two-step encoding algorithm.
• any additional constrains to the parity-check matrix may lead to its performance degradation. For example a large number of small weight columns may lead to error floor, i.e., a poor performance in the region of high SNR.
• an irregular repeat-accumulate (IRA) family of QC LDPC codes are used.
• the exponent matrices of their parity-check matrices have a block dual-diagonal structure as shown in Fig. 13.
• the left part of the matrix corresponds to the columns of the information part of the matrix and there are no restrictions on this part.
• the right part should have three non-negative elements (where the exponent a can be arbitrary) in the first row and all other columns have exactly two zero exponents.
• Such codes are already used in many modern communication standards.
• the complexity of their encoding is linear with the codeword length. An example is shown in Fig.
• the present invention aims to improve the conventional versioning management systems.
• the present invention has the object to provide an encoding method, which allows for low complexity encoding and does not have problems with error floor.
• F 2 be a Galois field of two elements and F 2 M a ring of polynomials with coefficients from F 2 .
• Such matrices are considered matrices over the field F 2 .
• the weight of the circulant is the number of non-zero elements in the first row.
• a set of all such polynomials of degree less than Z from the ring F 2 [x] is identified with the quotient polynomial ring F 2 [ ]/(x z — 1), where addition and multiplication operations are the standard polynomial addition and multiplication modulo the polynomial x z — 1.
• a binary mZ x nZ matrix is called a quasi-cyclic (QC) matrix with circulant size Z if it can be represented as a block matrix: where each Z x Z block A ⁇ ; ⁇ is a circulant of size Z.
• Any binary QC mZ x nZ matrix can be represented by the m x n matrix with entries from the ring F 2 [x]/(x z — 1), where each entry is the polynomial that represents the corresponding circulant.
• the weight of a QC matrix is the sum of weights for all its circulants. Because of the way the ring F 2 [x]/(x z — 1) is introduced, its elements are also elements of the ring F 2 [x]. Thus, matrices over the ring F 2 [x]/(x z — 1) are sometimes considered as matrices over the ring F 2 [x] . Below a 6x9 QC matrix with Z— 3 and weight 8 is shown:
• the complexity of multiplication by a QC matrix with circulant size Z and weight w is O(wZ).
• Type-I QC LDPC codes are the QC LDPC codes with QC parity-check matrices, where each circulant is either of weight one, i.e., a circulant permutation matrix (CPM) or of weight zero, i.e., the zero matrix (ZM).
• CPM circulant permutation matrix
• ZM zero matrix
• Not Type-I QC LDPC codes (where some circulants have weight > 1) are usually called Type-II QC LDPC codes.
• Type-I QC LDPC codes are considered, and the Type- I prefix is omitted in the following.
• a code with mZxnZ parity-check matrix is considered, and the Type- I prefix is omitted in the following.
• the base matrix for H is the binary m x n matrix B
• H is the lifted matrix obtained from the base matrix B with the lifting factor Z.
• the number of non-negative elements in a row (column) of the exponent matrix E ( H ) is called the row (column) weight.
• the distribution of row and column weights in this matrix is an important parameter that has a great influence to the error correction performance of the QC LDPC code under the standard message passing algorithms.
• a QC matrix H is the lifted matrix obtained from the base matrix with the lifting size Z then the Tanner graph T(H) is called the lifted graph obtained from the base graph T(B) (also called the protograph) with the lifting size Z.
• the process of obtaining the lifted matrix (graph) from the base matrix (graph) is called lifting.
• Fig. 8 shows an example of a parity check matrix H and the corresponding Tanner graph with girth 4 (for example, it has 4-cycle v 4 , c v v 8 , c 6 ).
• the present invention provides a class of Multi-Edge Type QC LDPC codes that have the core part with a minimum column weight equal to 3.
• the class of matrices according to the present invention avoids low weight columns (with weight 1 and 2). This is very important since the QC LDPC codes with a large number of low weight columns tend to have worse error floor than the QC LDPC codes without such columns.
• class of matrices of the present invention doesn't use circulants of weight more than 1 and also can be used with standard modular lifting already adopted in the eMBB standard which makes them compatible with corresponding hardware implementations.
• the method also has much smaller complexity and a corresponding hardware encoder can be implemented using only barrel shifters and vector XOR operations.
• a size of ROM needed to store an inverse of the parity submatrix is very small. This allows to use the proposed method to construct multi-rate LDPC codes for wireless data storage applications that are described by several QC LDPC matrices with the same block submatrix A.
• H u is an information part of H
• H p is a parity part of H.
• the method further comprises the step of reordering mZ rows and nZ columns of the parity-check matrix H when determining the parity bits vector p.
• the at least one bit in the codeword c is shortened or punctured, and each punctured bit is an information bit or a parity bit.
• the parity-check matrix H comprises a raptor-like extension
• the codeword comprises at least one additional parity bit, wherein a total number of additional parity bits relates to a number of additional rows in the parity-check matrix H resulting from the raptor-like extension.
• the d rows and d columns are added to H obtained according to H ® wherein 0 is a zero matrix, / is an d x d identity
• H R is a sparse matrix
• the submatrix A is a 4Z x 4Z submatrix, wherein A has a 4 x 4 exponent matrix of:
• the data encoder of the second aspect can have implementation forms according to the implementation forms of the method of the first aspect. Accordingly, it includes the same advantages as the method according to the first aspect and its implementation forms.
• a third aspect of the present invention provides a communication device comprising a memory and a processor, wherein the memory stores program code for controlling the processor according to the method of the first aspect or any of its implementation forms.
• a fourth aspect of the present invention provides a storage device comprising a memory and a processor, wherein the memory stores program code for controlling the processor according to the method of the first aspect or any of its implementation forms.
• the storage device of the fourth aspect includes the same advantages as the method according to the first aspect and its implementation forms.
• a fifth aspect of the present invention provides a computer program product comprising program code for performing, when running on a computer, the method of the first aspect or any of its implementation forms.
• the computer program product of the fifth aspect includes the same advantages as the method according to the first aspect and its implementation forms.
• FIG. 1 shows a schematic view of a method according to an embodiment of the present invention.
• FIG. 2 shows a schematic view of a parity-check matrix according to an embodiment of the present invention.
• FIG. 3 shows a schematic view of a parity-check matrix according to an embodiment of the present invention in more detail.
• FIG. 4 shows a schematic view of a parity-check matrix according to an embodiment of the present invention in more detail.
• FIG. 5 shows a schematic view of an encoding algorithm according to an embodiment of the present invention.
• FIG. 6 shows a schematic view of a parity-check matrix according to an embodiment of the present invention in more detail.
• FIG. 7 shows a schematic view of a performance comparison of codes.
• FIG. 8 shows a schematic view of graphs and matrices.
• FIG. 9 shows a schematic view of data flow in a communication system according to the prior art.
• FIG. 10 shows a schematic view of a parity-check matrix according to the prior art.
• FIG. 1 1 shows a schematic view of another parity-check matrix according to the prior art.
• FIG. 12 shows a schematic view of another parity-check matrix according to the prior art.
• FIG. 13 shows a schematic view of another parity-check matrix according to the prior art.
• FIG. 14 shows a schematic view of another parity-check matrix according to the prior art.
• FIG. 15 shows a schematic view of another parity-check matrix according to the prior art.
• FIG. 16 shows a schematic view of another parity-check matrix according to the prior art.
• FIG. 1 shows a schematic view of a data encoding method 100.
• the method is for parity checking and can be used in any field of data encoding, e.g. for parity check in wireless transmission, or data storage.
• the method 100 comprises a first step of receiving 101 a user bits vector it.
• the present invention discloses a family of Type-I LDPC parity-check matrices that can be used in the method 100. As it is e.g. shown in Fig. 2, a matrix from this family can be obtained from an m x n base matrix that consists of two parts: an information part H u and a parity part H p . There are no restrictions to the information part H u .
• the first m— r circulant columns of H p have zero circulants above the main diagonal, the remaining r circulant columns have zero circulants in the first m— r circulant rows, and the last r circulant rows and columns forms an rZ x rZ square quasi-cyclic submatrix A such that in the polynomial representation over the ring F 2 [x] its determinant is equal to a monomial x 1 , where 0 £ i ⁇ Z, l ⁇ r £ m.
• the constructed matrix A has girth 6 if the circulant size Z > 2 and its inverse A -1 has low weight, which allows a low complexity encoding.
• modular lifting can be used to construct several child PCMs from a mother PCM with the described above structure in the parity part. All constructed child PCMs also have girth 6 and allow easy encoding.
• a codeword can be further punctured or shortened in order to support different rates and codeword sizes.
• the general structure of the parity-check matrix with the proposed structure is shown in Fig. 2. If the appropriate lower triangular matrix is used the minimal column weight in the core can be equal to 3.
• the parity-check matrix may also have an optional raptor extension 301 , 302.
• steps SI , S2, S3 and S4 correspond to steps SI , S2, S3 and S4 as shown in Fig. 5.
• the matrix A In order to achieve low-complexity encoding the matrix A must have the following property:
• the inverse B A -1 has small weight or the multiplication by B can be implemented with small number of XOR operations.
• the following 4 Z x 4 Z QC matrix A with the circulant size Z shown in the exponent representation is used to achieve said low-complexity encoding and avoid problems with low error floor:
• the inverse of the matrix A has the following polynomial representation:
• the determinant of the inventive 4 Z X 4 Z QC matrix A in the polynomial representation over the ring F 2 [x] is equal to 1. This implies that the determinant of the matrix A in the polynomial representation over the quotient ring F 2 [X]/(X Z — 1) is also equal to 1 for any circulant size Z.
• any m X m matrix A that in polynomial representation over the ring F 2 [x] has the determinant equal to a monomial x i 3 0, can also be easily inverted for any circulant size Z by using the formula:
• A-i x -i mod Z . ad j( !
• adj(A) is the adjugate of the polynomial matrix A over the the quotient ring F 2 [X]/(X Z — 1) , i.e. adj(A) i ⁇ is the (j, i)-cofactor of A.
• any m x m matrix A with the above properties is compatible with the modular lifting.
• the present invention also allows to use arbitrary matrices A with this property.
• simulation results of an example 12 x 21 QC LDPC matrix with an easy invertible submatrix according to the present invention are shown. Its PCM is shown in Fig. 6.
• This matrix can be used to describe a variable-length rate-adaptive family of MET QC LDPC codes. Since main parameters of this matrix such as the size of the core graph, the maximal lifting size, the number punctured information nodes are identical with the BG2 matrix from the 5G eMBB standard they are compared in terms of error correcting performance.
• the used model of noise is the additive white Gaussian noise (AWGN) and the decoding algorithm is standard BP with flooding schedule and 50 iterations.
• AWGN additive white Gaussian noise
• the performance of these two matrices are similar if the word error rate (WER) is in the range 10 -1 - 10 -3 .
• WER word error rate
• the performance of the matrix according to the present invention is much better if the range of WER is 10 4 - 10 ⁇ s .

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• 2018
  • 2018-05-22 WO PCT/RU2018/000318 patent/WO2019226064A1/en active Application Filing
  • 2018-05-22 CN CN201880093668.1A patent/CN112204888A/zh active Pending

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