WO2019225135A1

WO2019225135A1 - Pll circuit

Info

Publication number: WO2019225135A1
Application number: PCT/JP2019/012160
Authority: WO
Inventors: 康裕井手
Original assignee: 株式会社デンソー
Priority date: 2018-05-21
Filing date: 2019-03-22
Publication date: 2019-11-28
Also published as: JP2019204998A

Abstract

A PLL circuit according to the present disclosure comprises: a divider (5) that divides a reference clock signal and outputs a divided clock signal; a phase comparator (2, 22) that compares the phases of the reference clock signal and the divided clock signal and outputs an error signal corresponding to the phase difference between the two signals; an oscillator (4, 24) that outputs a clock signal having a frequency corresponding to the error signal to the divider; first variation calculators (12R to 14R) that obtain a first variation per unit time in a count value in a first counter (6) that counts the number of clocks of the reference clock signal; second variation calculators (12D to 14D) that obtain a second variation per unit time in a count value in a second counter (7) that counts the number of clocks of the divided clock signal; a subtractor (16) that obtains a difference between the first variation and the second variation; a third counter (16) that adds the subtraction results of the subtractor; and an abnormality detection unit (17) that detects an unlock state of a phase synchronizing operation when the value of the third counter exceeds a predetermined value range.

Description

PLL circuit

Cross-reference of related applications

This application is based on Japanese Application No. 2018-97073 filed on May 21, 2018, the contents of which are incorporated herein by reference.

This disclosure relates to a PLL (Phase Locked Loop) circuit.

As a technique for detecting an abnormality in the PLL circuit, for example, Patent Document 1 monitors the input voltage of the VCO, and Patent Document 2 counts the number of clocks output from the frequency divider.

JP-A-9-246962 Japanese Patent Laying-Open No. 2015-133560

However, the technique of Patent Document 1 cannot be applied to a case where the range of the voltage input to the VCO is wide, such as when the PLL circuit performs a chirp operation, or a usage pattern in which the voltage fluctuates. The technique of Patent Document 2 is applied only to a PLL circuit of a type that controls so that the phase difference becomes zero because there is a difference in the count value if there is a phase difference between the reference clock and the divided clock. Can not.

The present disclosure has been made in view of the above circumstances, and the purpose of the present disclosure is to control so that a predetermined phase difference is applied between the reference clock and the divided clock when the voltage input to the oscillator fluctuates. Another object of the present invention is to provide a PLL circuit capable of detecting an abnormality for the type to be used.

According to the PLL circuit of the present disclosure, the first counter counts the number of clocks of the reference clock signal, and the first change amount calculator obtains the first change amount per unit time of the count value in the first counter. Further, the second counter counts the number of clocks of the divided clock signal, and the second change amount calculator obtains a second change amount per unit time of the count value in the second counter. The subtracter obtains the difference between the first change amount and the second change amount, and the third counter adds the subtraction result of the subtractor. Then, when the value of the third counter exceeds a predetermined value range, the abnormality detection unit detects the unlocked state of the phase synchronization operation.

That is, the abnormality detection unit detects that the phase synchronization operation is unlocked when the change amount of the difference between the count values of the reference clock and the frequency-divided clock exceeds a predetermined range. Therefore, abnormality detection can be performed even when the voltage input to the oscillator fluctuates or for a type of PLL circuit that is controlled to give a predetermined phase difference between the reference clock and the divided clock.

Further, according to the PLL circuit of the present disclosure, the first and second change amount calculators are configured by the first and second shift registers, respectively. Then, the selector selects the number of clock shifts in each shift register to obtain the first and second variation amounts. With this configuration, for example, by setting the difference to be large, even if the difference between the count values of the reference clock signal and the divided clock is small, the unlocked state of the phase synchronization operation can be detected early. Can do. In this case, when the frequency of the divided clock signal is largely changed by the chirp operation, the frequency change can be masked so as not to be detected as an unlocked state.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a functional block diagram showing the configuration of the PLL circuit in the first embodiment. FIG. 2 is a diagram showing a start sequence of the PLL circuit, FIG. 3 is a flowchart showing the circuit operation in the chirp setup. FIG. 4 is a timing chart showing normal operation. FIG. 5 is a timing chart showing the operation at the time of abnormality, FIG. 6 is a flowchart showing circuit operation during chirping. FIG. 7 is a timing chart showing the normal operation. FIG. 8 is a timing chart showing the operation at the time of abnormality, FIG. 9 is a timing chart showing the operation at the time of abnormality when the clock shift number for obtaining the change amount is set large. FIG. 10 is a diagram showing the setting of the output frequency for detecting the abnormality of the VCO in the second embodiment. FIG. 11 is a flowchart showing the circuit operation. FIG. 12 is a functional block diagram showing the configuration of the PLL circuit in the third embodiment.

(First embodiment)
As shown in FIG. 1, the PLL circuit 1 of this embodiment includes a phase comparator (PFD) 2, a low-pass filter (LPF) 3, a voltage controlled oscillator (VCO) 4, and a frequency divider (/ multiplier) 5. A known configuration to be formed includes a REF counter 6, a DIV counter 7, and an arithmetic unit 8. A reference clock signal REF is input to the phase comparison unit 2 and the REF counter 6. The divided clock signal DIV output from the frequency divider 5 is input to the phase comparison unit 2 and the DIV counter 7. The frequency divider 5 can also output a substantially multiplied clock signal by setting the frequency dividing ratio to an inverse number.

The REF counter 6 and the DIV counter 7 count the number of pulses of the reference clock signal REF and the divided clock signal DIV, respectively. These

counters

6 and 7 are both up / down counters. The count values of the REF counter 6 and the DIV counter 7 are input to the calculator 8. The REF counter 6 and the DIV counter 7 correspond to first and second counters, respectively.

The arithmetic unit 8 includes a shift register 11, two

selectors

12 and 13, and a subtractor 14 for each of the reference clock side and the divided clock side, and “R” and “D” are added to the signs of the respective sides. Attached is shown. The shift register 11 is configured by connecting, for example, n registers 15 in series, and sequentially shifts data input in synchronization with the reference clock signal REF. The

selectors

12 and 13 receive the count data of the

counter

6 or 7 and the output data of each register 15. Then, the subtracter 14 takes the difference between the data value selected by the selector 13 and the data value selected by the selector 12 and outputs the difference to the difference adder 16.

The subtraction result of the subtracter 14R is a data difference d_ref obtained by shifting the count value of the REF counter 6 by a predetermined number of clocks in the shift register 11R. The subtraction result of the subtracter 14D is a data difference d_div in which the count value of the DIV counter 7 is shifted by a predetermined number of clocks in the shift register 11D. The same number of shifts is selected on each of the reference clock side and the divided clock side. The shift register 11R, the

selectors

12R and 13R, and the subtractor 14R correspond to a first change amount calculator. The shift register 11D, the

selectors

12D and 13D, and the subtractor 14D correspond to a second change amount calculator.

The difference adder 16 takes the difference between the difference data d_ref and the difference data d_div, and outputs a value s_diff obtained by adding the difference values. The difference adder 16 corresponds to a subtracter and a third counter. The addition data s_diff is input to the comparator 17. If the difference data s_diff is larger than the threshold value UNLOCK_VAL, the comparator 17 changes the lock error detection signal lock_error to high that is an active level. The comparator 17 corresponds to an abnormality detection unit.

The PLL circuit 1 also includes a control unit (not shown) that performs processing such as setting frequency division ratio data in the frequency divider 5 and outputting a selection control signal to the

selectors

12 and 13. The PLL circuit 1 is used, for example, in a radar or the like, and the frequency range to be changed in the chirp operation is, for example, about 76 GHz to 77 GHz.

Next, the operation of this embodiment will be described. As shown in FIG. 2, when the PLL circuit 1 is activated, the control unit first performs calibration and raises the output frequency to an initial value of 76 GHz. When the calibration is completed, the control unit resets the

counters

6 and 7 and the calculator 8 and sets how many clock shifts the

selectors

12 and 13 take. Then, the output frequency is maintained at an initial value of 76 GHz, and the process shown in FIG. 3 is performed in the inter-chirp setup period.

As shown in FIG. 4, the cycle ratio of the divided clock signal DIV to the reference clock signal REF is “1”. The frequency division ratio is determined by the reference clock signal REF and the oscillation frequency of the voltage controlled oscillator 4, and the ratio between the normal reference clock signal REF and the frequency divided clock signal DIV is 1: 1. The threshold value UNLOCK_VAL set in the comparator 17 is 4-bit binary and is set to “1000” = “8”. The REF counter 6 and the DIV counter 7 respectively count the number of clock pulses of the reference clock signal REF and the divided clock signal DIV (S1), and the count values are sequentially shifted in the shift registers 11R and 11D.

The

selectors

12 and 13 are set so as to take a difference between the input / output data of each register 15 (1). Accordingly, the values of the output data d_ref and d_div of the

subtracters

14R and 14D are “1” (S2). Then, the value of the output data s_diff of the difference adder 17 becomes “0”, and this state continues if the operation of the PLL circuit 1 is normal (S3; NO). The

counters

6 and 7 are switched to the down-counting operation from the time when the count value reaches “103”. Accordingly, the values of the subsequent data d_ref and d_div are “−1”.

The processes in steps S2 and S3 are continued until the inter-chirp setup period ends or a reset is applied (S4; NO). When the above period ends or a reset is applied (S4; YES), the process proceeds to step S1.

On the other hand, as shown in FIG. 5, it is assumed that the period of the divided clock signal is twice that of the reference clock signal regardless of the period ratio of “1”. At this time, the count value cnt_div of the DIV counter 7 is incremented every other clock. Thereby, the value of the output data d_div of the subtractor 14D repeats “1” / “0” alternately. Then, the value of the addition data s_diff is incremented every other clock, and when the value reaches “8” (S3; YES), the comparator 17 changes the lock error detection signal lock_error to the high level. An unlocked state is detected.

When the setup period ends and the PLL circuit 1 starts the chirp operation (FIG. 6, S6; YES), steps S1 to S3 are executed in the same manner as in the setup period. In step S7 instead of step S4, it is determined whether the chirping operation is completed or reset is applied. When the chirp operation is completed (YES), the operation shifts to a steady frequency operation that maintains the output frequency at the initial value (S5). Thereafter, the chirp operation and the steady frequency operation are alternately performed.

7 and 8 are diagrams corresponding to FIGS. 4 and 5 during the chirp operation. During the chirp operation, the frequency of the frequency-divided clock signal changes, but for the sake of illustration, the frequency in these figures is constant. During the chirp operation, the signal chirp_on indicating that the operation is in progress is at a high level. When the chirp operation ends and the signal chirp_on becomes low level, the reset is applied. As shown in FIG. 8, the error detection signal output during the chirp operation is chirp_error.

In FIG. 9, the output data d_ref and d_div of the

subtractors

14R and 14D are the differences between the data r10_cnt_ref and r10_cnt_div whose shift numbers are 9th stage and the input data cnt_ref and cnt_div of the register 15 (1), respectively. The case where the

selectors

12 and 13 are set as described above is shown.

After the

counters

6 and 7 are switched to the down-count operation, the values of the output data d_ref and d_div of the

subtracters

14R and 14D are both decreased by “2”. The difference between them (d_ref−d_div) remains “0”. In this state, when only one pulse of the divided clock signal DIV is lost, the value of the output data d_div changes from “3” to “2” as the count value “100” continues. As a result, the difference (d_ref−d_div) changes to “−1”, and the value of the addition data s_diff is incremented. When the value reaches “8”, the error detection signal chirp_error output from the comparator 17 becomes high level, and the unlocked state is detected.

As described above, according to the present embodiment, the number of clocks of the reference clock signal REF is counted by the REF counter 6, and the subtractor 14R obtains the change amount d_ref per unit time of the count value cnt_ref of the REF counter 6. Further, the DIV counter 7 counts the number of clocks of the divided clock signal DIV, and the subtractor 14D obtains a change amount d_div per unit time of the count value cnt_div of the DIV counter 7. The difference adder 16 calculates a difference between the change amounts d_ref and d_div and adds the difference. Then, the comparator 17 detects the unlocked state of the phase synchronization operation when the value s_diff output from the difference adder 16 exceeds a predetermined value range by becoming larger than UNLOCK_VAL.

As a result, even when the voltage input to the voltage controlled oscillator 4 fluctuates, or when the PLL circuit 1 is controlled to give a predetermined phase difference between the reference clock and the divided clock, the abnormality detection is performed. It can be carried out. In the present embodiment, for convenience of illustration, a locked waveform is shown in a state where there is no phase difference between the reference clock and the divided clock. However, even when there is a phase difference, the unlocked state can be similarly detected. .

In addition, the shift register 11 and the

selectors

12 and 13 can select how many clock shift numbers the change amounts d_ref and d_div are to be obtained. As a result, by setting a large difference in the number of shifts, even if the difference between the count values d_ref and d_div of the reference clock signal REF and the divided clock signal DIV is slight, the phase synchronization operation is unlocked early. It becomes possible to detect. In this case, when the frequency of the divided clock signal DIV is greatly changed by the chirp operation, the frequency change can be masked so as not to be detected as an unlocked state.

In addition, since the

counters

6 and 7 are up / down counters, when the count value overflows and changes to zero, it is not necessary to mask the change in the count value. it can.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts are described. In the second embodiment, whether or not the function of the voltage controlled oscillator 4 is normal is confirmed using the abnormality detection function described in the first embodiment. Therefore, as shown in FIG. 10, it is determined whether or not the unlocked state is detected for each of the case where the output frequency of the PLL circuit 1 is lowered and the case where the output frequency is raised. The process for confirming this function is performed by switching the PLL circuit 1 to the test mode.

As shown in FIG. 11, from the state in which the PLL circuit 1 is operating at a steady frequency (S5), the frequency dividing ratio is set in the frequency divider 5 so that the output frequency of the voltage controlled oscillator 4 is lowered (S11). . Then, Steps S1 to S3 are executed, and if “NO” is determined in Step S3, the

counters

6 and 7 and the arithmetic unit 8 are reset after elapse of a predetermined time, and then the output frequency of the voltage controlled oscillator 4 is increased. A frequency division ratio is set in the frequency divider 5 (S12). Then, the same processes as in steps S1 to S3 are performed (steps S13 to S15), and if no abnormality is detected (S15; NO), the

counters

6 and 7 and the arithmetic unit 8 are reset after the lapse of a predetermined time. Exit.

As described above, according to the second embodiment, the control unit changes the frequency division ratio of the frequency divider 5 in two stages, and determines whether or not an unlocked state is detected at each frequency division ratio. It was made to judge with. Thereby, it can be confirmed whether or not the function of the voltage controlled oscillator 4 is normal.

(Third embodiment)
A PLL circuit 21 according to the third embodiment shown in FIG. 12 has a PLL unit configured by a digital circuit. Instead of the phase comparison unit 2, the LPF 3 and the voltage controlled oscillator 4, a TDC (Time To Digital Converter) 22, digital An arithmetic unit 23 for performing a filter operation and a DCO (Digital Control Oscillator) 24 are provided. Even in this case, the abnormality detection process performed by the calculator 8 is the same.

(Other embodiments)
A charge pump circuit may be provided between the phase comparison unit 2 and the LPF 3.
The

counters

6 and 7 may be constituted by up counters or down counters.
You may apply to products other than a radar.
In the second embodiment, the output frequency may be changed in three stages or more.
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

A frequency divider (5) for dividing the reference clock signal and outputting the divided clock signal;
A phase comparator (2, 22) for comparing the phases of the reference clock signal and the divided clock signal and outputting an error signal corresponding to the phase difference between the two;
An oscillator for outputting a clock signal having a frequency according to the error signal to the frequency divider (4, 24);
A first counter (6) for counting the number of clocks of the reference clock signal;
A first change amount calculator (12R to 14R) for obtaining a first change amount per unit time of the count value in the first counter;
A second counter (7) for counting the number of clocks of the divided clock signal;
A second change amount calculator (12D to 14D) for obtaining a second change amount per unit time of the count value in the second counter;
A subtractor (16) for obtaining a difference between the first change amount and the second change amount;
A third counter (16) for adding the subtraction results of the subtractor;
A PLL circuit comprising: an abnormality detection unit (17) for detecting an unlocked state of the phase synchronization operation when the value of the third counter exceeds a predetermined value range.
The first change amount calculator and the second change amount calculator each include a first shift register (11R) and a second shift register (11D),
The PLL circuit according to claim 1, further comprising: a selector that selects how many clock shifts in each shift register to obtain the first change amount and the second change amount.
The frequency divider can set a frequency division ratio,
3. The PLL circuit according to claim 1, further comprising a control unit that changes the frequency division ratio in two or more stages and causes the abnormality detection unit to determine whether or not the unlocked state is detected at each frequency division ratio.
The PLL circuit according to any one of claims 1 to 3, wherein an up / down counter is used for the first and second counters.