WO2019223673A1 - 一种编码方法及相关设备 - Google Patents

一种编码方法及相关设备 Download PDF

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Publication number
WO2019223673A1
WO2019223673A1 PCT/CN2019/087728 CN2019087728W WO2019223673A1 WO 2019223673 A1 WO2019223673 A1 WO 2019223673A1 CN 2019087728 W CN2019087728 W CN 2019087728W WO 2019223673 A1 WO2019223673 A1 WO 2019223673A1
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code
block
code block
source
encoded
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PCT/CN2019/087728
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English (en)
French (fr)
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陆玉春
马林
李亮
李永耀
沈胜宇
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华为技术有限公司
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Priority to EP19806958.5A priority Critical patent/EP3817253A4/en
Publication of WO2019223673A1 publication Critical patent/WO2019223673A1/zh
Priority to US17/100,394 priority patent/US11539461B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER

Definitions

  • the present application relates to the field of network technologies, and in particular, to a coding method and related equipment.
  • PCIE Peripheral Component Interconnect Express
  • the interface rate has started from the PCIE 1.0 era, and has experienced 2.5GT / s, 5GT / s, 8GT / s, and then 16GT / s of the newly released PCIE4.0.
  • PCIE will also evolve to 32GT / s and 56GT / s. The transmission rate is getting higher and higher, and the link loss is getting larger and larger.
  • the embodiments of the present application provide a coding method and related equipment.
  • the FEC codeword obtained by FEC coding can meet the requirements of low delay and high gain.
  • an embodiment of the present application provides an encoding method, including:
  • a short code with low overhead can be obtained by encoding, which can meet the requirements of low delay
  • a long code with strong error correction capability can also be obtained by encoding, which meets the requirements of high gain. Therefore, the FEC codeword obtained by FEC coding can meet the requirements of low delay and high gain.
  • the source code block after the source code block is encoded based on the 128B / 130B encoding method, it can be transmitted downward through two paths: the first path is a non-transcoding path, and the source block is directly transmitted to the scrambling code.
  • the second path is a transcoding path.
  • the source code block is transcoded to obtain the code block to be encoded, and then scrambled.
  • the transcoding path includes two sub-paths, sub-path 1 is a 128B / 132B transcoding path, and sub-path 2 is a 256B / 257B or 256B / 258B transcoding path.
  • the source code block is transcoded to obtain a code block to be encoded.
  • the transcoder can receive a single source code block output by a single encoder for transcoding, or it can receive multiple source code blocks output by multiple different encoders for transcoding.
  • At least one bit of synchronization header information is added to a single source block to obtain a code block to be encoded, and the synchronization header information is used to indicate a data type of the source block.
  • each source code block is divided into two sub-code blocks; then the first sub-code block of the two sub-code blocks of the multiple source code blocks is combined to generate the to-be-encoded In the front part of the code block, add bit data in front of the front part of the code block to be encoded; finally, combine the second sub code block of the two sub code blocks of the multiple source code blocks to generate the latter part of the code block .
  • multiple source code blocks are all data code blocks
  • at least one bit of synchronization header information is added in front of the previous part of the code block to be encoded, and the synchronization header information is used to indicate multiple source code blocks.
  • the blocks are all data code blocks.
  • multiple source code blocks include a control code block
  • at least one bit of synchronization header information is added in front of the previous part of the code block to be encoded, and multiple pieces of synchronization header information are added after the synchronization header information.
  • Bit hot code The synchronization header information is used to indicate that multiple source code blocks contain control code blocks.
  • the hot code is used to indicate the data type of each source code block.
  • the first control code block in the previous part of the code block to be encoded is deleted. Multiple bits in the first byte of the.
  • multi-bit hot code the hot code is used to indicate that multiple source code blocks contain at least one invalid source code block; at the same time, delete the multiple in the first byte of the first source code block in the previous part of the code block to be encoded Bits.
  • the encoding overhead can be reduced from 1.5625% to 0.4%, thereby providing a higher encoding overhead space for FEC encoding.
  • the 256B / 257B transcoding method can also be connected to the Ethernet standard.
  • the transcoding operation only targets the first sub-code block in the source code block (130-bit code block). For application scenarios where the number of links is greater than or equal to 2, two 130-bit source code blocks are obtained from two different 128B / 130B encoders.
  • the first sub-code block (64 bits) of the two 130-bit source code blocks is transmitted first, so the frame format after transcoding is conducive to completing the transcoding required in the first clock cycle. Operation, thereby effectively reducing the delay caused by transcoding.
  • the encoding overhead can be reduced from 1.5625% to 0.8%, thereby providing a higher encoding overhead space for FEC encoding.
  • the transcoding operation only targets the first sub-code block in the source code block (130-bit code block). For application scenarios where the number of links is greater than or equal to 2, two 130-bit source code blocks are obtained from two different 128B / 130B encoders. During the data transmission process, two 130-bit fast source subcode blocks (64 bits) are transmitted first, so the frame format after transcoding is conducive to completing the transcoding required in the first clock cycle. Operation, thereby effectively reducing the delay caused by transcoding.
  • the synchronization header data of each source block in multiple source blocks can be deleted to obtain the remaining valid information; the remaining valid information in multiple source blocks is combined to generate a long code block; Add bit data to get the code block to be encoded. Finally, multiple bits in the first byte of the first control code block in the long code block are deleted.
  • the transcoding frame format in the embodiment of the present application does not require segmentation of source code blocks, and directly performs transcoding operations on the entire 130-bit source code block, which can provide a frame format reference for transcoding operations.
  • multiple source code blocks include a control code block
  • at least one bit of synchronization header information is added in front of the long code block, and multiple bits of hot code are added after the synchronization header information.
  • the synchronization header information is used to indicate that multiple source code blocks contain control code blocks.
  • the hot code is used to indicate the data type of each source code block.
  • the first control code block in the previous part of the code block to be encoded is deleted. Multiple bits in a byte.
  • the hot code is used to indicate that multiple source code blocks contain at least one invalid source code block, and at the same time delete multiple bits in the first byte of the first source block of the multiple code blocks to be encoded.
  • the source code block is first transcoded to obtain the code block to be encoded, and then the FEC codeword is designed according to the prime factorization method, and the code block to be encoded is encoded to obtain the FEC code.
  • the source code block is obtained by encoding based on the 128B / 130B encoding method.
  • Transcoding methods include 256B / 258B transcoding or 128B / 132B transcoding.
  • RS (72, 66, T 3) and other short codes.
  • the FEC code is distributed to multiple physical layer links for transmission.
  • the FEC code can be sequentially distributed to multiple physical layer links in units of symbols, and each link is sequentially distributed with one symbol.
  • the Begin a new round of distribution.
  • the number of symbols of the FEC code distributed in each physical layer link is a ratio of the total number of codeword symbols of the FEC code to the number of multiple physical layer links.
  • multiple FEC codes may be interleaved and mapped into the gearbox in units of symbols, where the number of columns of the gearbox is the number of multiple physical layer links. Then the FEC codes in the gearbox are sequentially distributed to multiple physical layer links. This method is applied to an application scenario in which multiple FEC encoder output multiple FEC codewords are distributed to different physical layer links, and a data distribution scheme is provided for a multilink transmission scenario.
  • a plurality of empty bits are added to the FEC code.
  • the number of symbols in the FEC code can be matched with the number of physical layer links. This can simplify the design of the gearbox and optimize it in the process of distributing FEC codes to multiple physical layer links.
  • an embodiment of the present application provides an encoding device configured to implement the methods and functions performed by the FEC encoder in the first aspect, and implemented by hardware / software, and the hardware / software includes Function corresponding unit.
  • the present application provides an encoding device, including: a processor, a memory, and a communication bus, where the communication bus is used to implement connection and communication between the processor and the memory, and the processor executes a program stored in the memory to implement The steps in the encoding processing method provided by the first aspect above.
  • the encoding device provided in the present application may include a module corresponding to the behavior of the encoding device in the above method design.
  • Modules can be software and / or hardware.
  • the present application provides a computer-readable storage medium having instructions stored in the computer-readable storage medium, which when executed on a computer, causes the computer to execute the methods of the above aspects.
  • the present application provides a computer program product containing instructions that, when run on a computer, causes the computer to perform the methods of the above aspects.
  • FIG. 1 is a schematic structural diagram of a CCIX standard system according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a 400GE Ethernet standard provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a physical layer coding architecture according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a high-speed interface physical layer coding system according to an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of an FEC encoding method according to an embodiment of the application.
  • FIG. 6 is a schematic flowchart of an encoding method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of transcoding a 130-bit source code block of 1 frame according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a mapping relationship between a 130-bit source code block and a 257-bit code block to be encoded according to an embodiment of the present application
  • FIG. 9 is a schematic diagram of a 2-frame 130-bit source code block transcoding provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a mapping relationship between a 130-bit source code block and a 258-bit code block to be encoded according to an embodiment of the present application;
  • FIG. 11 is a schematic diagram of another 2-frame 130-bit source code block transcoding provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another 2-frame 130-bit source code block transcoding according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of another 2-frame 130-bit source code block transcoding according to an embodiment of the present application.
  • FIG. 14 is a schematic diagram of FEC code distribution provided by an embodiment of the present application.
  • FIG. 15 is a schematic diagram of another FEC code distribution according to an embodiment of the present application.
  • FIG. 16 is a schematic diagram of another FEC code distribution according to an embodiment of the present application.
  • FIG. 17 is a schematic diagram of another FEC code distribution according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of an encoding device according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of an encoding device according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of an architecture of an accelerator cache coherent interconnect (CCIX) standard system provided by an embodiment of the present application.
  • the CCIX standard system is an interconnection method based on the PCIE architecture.
  • the application layer and above layers, the CCIX protocol layer, the CCIX link layer, the CCIX transport layer, the PCIE transport layer, the PCIE data link layer, and the CCIX physical layer are sequentially included from top to bottom, among which CCIX
  • the physical layer includes two logical sub-layers (Logical Sub-Block) and Electronic Sub-layer (Electrical Sub-Block).
  • FIG. 2 is a schematic structural diagram of a 400GE Ethernet standard provided by an embodiment of the present application.
  • the right part of the diagram is a detailed block diagram corresponding to the physical coding sublayer (PCS) in the physical layer.
  • the physical layer is firstly encoded using 64B / 66B encoding, and then 256B / 257B transcoding is used for transcoding.
  • a FEC codeword KP4-RS (544, 514) designed based on a 257-bit code block length is provided.
  • RS is a Reed-Solomon code word.
  • the RS (544,514) codeword used in the 400GE Ethernet interface standard has a decoding delay of about 100 nanoseconds, which has a large delay, and is not suitable for application scenarios with high delay requirements.
  • FIG. 3 is a schematic structural diagram of a physical layer coding architecture according to an embodiment of the present application.
  • the physical layer coding architecture is a physical layer coding architecture corresponding to the Serial Small Computer System Interface (Serial Attached SCSI 4) standard.
  • the link rate can reach 22.5Gbps.
  • FEC is introduced in the physical layer to compensate link loss.
  • the SAS standard is first encoded using 8B / 10B encoding, then 128B / 130B encoding, and then FEC encoding. In terms of FEC codeword selection, SAS-4 selects RS (30, 26) corresponding to a 130-bit code block length.
  • the coding method of 128B / 130B used by SAS-4 is the same as that of CCIX, PCIE3.0 and above, the net coding gain (Net Coding Gain, NCG) of the FEC codeword selected by SAS-4 is only 3.46dB, which is much lower than KP4-RS (544, 514) gain level, so this FEC codeword cannot be applied to the application scenario where the link loss is large.
  • NCG Network Coding Gain
  • FIG. 4 is a schematic structural diagram of a high-speed interface physical layer coding system according to an embodiment of the present application.
  • the main application scenarios of this application are CCIX and PCIE.
  • Figure 4 is a schematic diagram of the overall system architecture in this scenario.
  • the left side is the overall architecture of CCIX / PCIE.
  • This architecture includes the application layer and above, the CCIX protocol layer, CCIX link layer, CCIX transport layer, PCIE transport layer, PCIE data link layer and CCIX physical layer.
  • the physical layer includes two sublayers: a logic sublayer and an electron sublayer.
  • the embodiment of the present application is a coding method proposed for a logical sub-layer part of a physical layer in the architecture.
  • On the right is a schematic diagram of the physical layer coding method of the high-speed interface in the logical sublayer section.
  • the sending side from top to bottom, it mainly includes: encoding, transcoding, scrambling, FEC encoding, and sending.
  • steps from the bottom to the top include receiving, FEC decoding, descrambling code, reverse code, and link reordering. Since the principles of the transmitting side and the receiving side are the same, the embodiments of the present application are described only with the encoding method on the transmitting side.
  • FIG. 5 is a schematic flowchart of an FEC encoding method provided by the embodiment of the application. include:
  • S501 Receive a code block to be encoded with a length of L, where L is a positive integer.
  • the unit of L is bits.
  • the number of code blocks received can be one or more, and the number can be integer or non-integer.
  • the number of code blocks to be encoded can be obtained by encoding.
  • S502 Encode the code block to be encoded to obtain a forward error correction code FEC, wherein the effective information length K of the FEC code is an integer multiple of the maximum prime factor of L, and the total length of the FEC code N is the sum of twice the error correction capability T of the FEC code and K.
  • the FEC codeword is in units of symbols, K is the effective information length of the FEC code, and N is the total length of the FEC code, that is, N is the total number of symbols output after the FEC encoder, T is the number of symbols that the FEC code can correct, and M Is the number of bits contained in each symbol.
  • RS Reed-Solomon
  • its representation is RS (N, K, T, M).
  • RS (N, K, T, M) is RS (544,514,15, 10).
  • the total length N of the FEC code is 544 symbols
  • the effective information length K is 514 symbols
  • the error correction capability T is 15 symbols
  • the number of bits included in each symbol is 10.
  • the FEC code in the embodiment of the present application may also be referred to as an FEC codeword.
  • a short code with low overhead can be obtained by encoding, which can meet the requirements of low delay
  • a long code with strong error correction capability can also be obtained by encoding, which meets the requirements of high gain. Therefore, the FEC codeword obtained by FEC coding can meet the requirements of low delay and high gain.
  • P 13
  • the embodiment of the present application provides a corresponding FEC codeword design method in combination with a 128B / 130B encoding scheme, and provides CCIX and PCIE with a codeword selection in a 128B / 130B encoding scenario.
  • a prime factorization is performed on the coded code block length 130, and the maximum prime factor is used as the basis for the code word design, which can simplify the gearbox design during the FEC frame receiving process.
  • FIG. 6 is a schematic flowchart of an encoding method according to an embodiment of the present application.
  • the embodiment of the present application describes the physical layer encoding in combination with the FEC encoding in the above embodiment.
  • the physical layer encoding is exemplary.
  • the encoding method can also be used elsewhere.
  • the encoding method in the embodiment of the present application includes at least The following steps:
  • the source code block is obtained by encoding based on a 128B / 130B encoding method.
  • the physical layer includes a plurality of different 128/130 encoders such as encoder # 0, encoder # 1, ..., encoder #P, and the physical layer first receives the data link layer.
  • Data, Link, Layer, DLL sends the received data according to bytes (each byte includes 8 bits) as a group and distributes them to different encoders each time. For example, byte 0, byte 1, byte 2, byte 3, ... and so on are received in turn from the DLL layer.
  • the received bytes are sequentially distributed to different links. Each link corresponds to an encoder, byte 0—> link 0 (corresponding to encoder # 0), so byte 0 is distributed to encoder # 0.
  • Link 1 (corresponding to encoder # 1), so byte 1 is distributed to encoder # 1.
  • each link receives 128-bit information, it adds 2-bit synchronization header information to generate a 130-bit code block.
  • different encoders can output different source blocks.
  • the encoder involved in the embodiment of the present application is mainly based on a 128B / 130B encoding method for encoding, and other encoding methods may also be used for encoding.
  • the source code block after the source code block is encoded based on the 128B / 130B encoding method, it can be transmitted downward through two paths: the first path is a non-transcode path (No Transcode (NTC)), and skip to S603 , Directly transmit the source code block to the scrambler for scrambling; the second path is the transcoding path (Transcode, TC), skip to S602, transcode the source block to obtain the code block to be encoded, and then scramble code.
  • the transcoding path includes two sub-paths. Sub-path 1 is to transcode a single source block, and sub-path 2 is to transcode multiple source blocks.
  • subpath 1 receives a frame of 130-bit source blocks from a single 128B / 130B encoder, and generates a 132-bit code block to be encoded through a 128B / 132B transcoder.
  • Subpath 2 receives 2 frames of 130-bit source code blocks from different 128B / 130B encoders and inputs them into a 256B / 257B or 256B / 258B transcoder to generate a 257-bit or 258-bit code block to be encoded.
  • the transcoder may receive a single source code block output by a single encoder for transcoding, or may receive multiple source code blocks output by multiple different encoders for transcoding.
  • Transcoding methods include the following optional methods:
  • At least one bit of synchronization header information can be added to a single source block to obtain the code block to be encoded, where the synchronization header information is used to indicate a data type of the source block.
  • FIG. 7 is a schematic diagram of a 1-frame 130-bit source code block transcoding provided by an embodiment of the present application.
  • H 0 H 1 represents 2-bit synchronization header information, where bit H 0 is Least Significant Bit (LSB).
  • Bit H 1 is the most significant bit (MSB). It is then transcoded into 132-bit code blocks to be encoded.
  • LSB Least Significant Bit
  • MSB most significant bit
  • the synchronization header information added may be the same as the synchronization header data of the source block itself.
  • the synchronization header data of each source block in multiple source blocks may be deleted first to obtain the remaining valid information, and the remaining valid information in the multiple source blocks may be combined to generate the to-be-encoded A code block, where the remaining valid information is a code block after the synchronization header data is removed. Further, the remaining valid information of each source code block may be divided into two sub-code blocks; and then the first sub-code block of the two sub-code blocks of the plurality of source code blocks is combined to generate the The first part of the code block to be encoded is described, and bit data is added in front of the first part of the code block to be encoded.
  • the bit data may include synchronization header information or hot codes.
  • the plurality of source code blocks are data code blocks
  • at least one bit of synchronization header information is added to the front of the front part of the code block to be encoded, where the synchronization header information is used to indicate the Multiple source code blocks are all data code blocks.
  • the plurality of source code blocks includes a control code block
  • at least one bit of synchronization header information is added to the front of the front part of the code block to be encoded, and multiple bits are added after the synchronization header information.
  • the synchronization header information is used to indicate that the multiple source code blocks contain the control code block, and the hot code is used to indicate the data type of each source code block; delete the code to be encoded Multiple bits in the first byte of the first said control code block in the previous part of the block.
  • a second sub-code block of the two sub-code blocks of the plurality of source code blocks is combined to generate a second part of the code block to be encoded.
  • each source code block can be divided into X sub-code blocks, and X can be a positive integer such as 3, 4, or 5. Then combine the first sub-code block in the first source block, the first sub-code block in the second source block, ..., and the first sub-code block in the Y source block to generate a code block to be encoded The first part; combining the second sub-code block in the first source block, the second sub-code block in the second source block, ..., and the second sub-code block in the Y source block The second part of the code block to be encoded; the third sub-code block in the first source block, the third sub-code block in the second source block, ..., and the third in the Y source block The three sub-code blocks are combined to generate the third part of the code block to be encoded, etc., and others are transcoded according to the same method described above, and Y is a positive integer.
  • FIG. 8 is a schematic diagram of a mapping relationship between a 130-bit source code block and a 257-bit code block to be encoded according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a 2-frame 130-bit source code block transcoding provided by an embodiment of the present application.
  • Receive the source code blocks from two different 128B / 130B encoders assuming that the bit width of the data transmission is 64 bits, delete the 2-bit sync header data in the 130-bit source block, and the length of the remaining valid information is 128 bits, divide it into Two 64-bit subcode blocks.
  • the first frame source block D0 is divided into D00 and D01
  • the second frame source block D1 is divided into D10 and D11
  • the first child of the first frame source block D0 is divided.
  • the code block D00 and the first sub-code block D10 in the second frame source block D1 are combined to generate the first part (D00 and D10) of the code block to be encoded. Because the received 2 frames of data are all data code blocks (Data Block ), You can add 1-bit synchronization header information (such as 1) in front of the previous part of the code block to be encoded, and at the same time the first sub-code block D01 and the second frame source block in the first frame source block D0 The first sub-code block D11 in D1 is combined to generate the latter part (D01 and D11) of the code block to be coded, and finally the 257-bit code block to be coded is combined.
  • 1-bit synchronization header information such as 1
  • the first sub-code block D11 in D1 is combined to generate the latter part (D01 and D11) of the code block to be coded, and finally the 257-bit code block to be coded is combined.
  • the first frame source block is the control code block
  • the second frame source block is the data code block
  • the first frame source block O0 is divided into O00 and O01
  • the second The frame source block D1 is divided into D10 and D11.
  • the first subcode block O00 in the first frame source block O0 and the first subcode block D10 in the second frame source block D1 are combined to generate a code block to be encoded.
  • a 1-bit synchronization header (such as 0) can be added in front of the first part of the code block to be encoded.
  • the two bits in the first byte in the first control code block in the previous part of the code block to be encoded are deleted accordingly, where the first byte is used to indicate the type of the control code block,
  • the two deleted bits can be the two most significant bits of the first byte in the first control code block, or the two least significant bits of the first byte in the first control code block.
  • first sub-code block O01 in the first frame source block O0 and the first sub-code block D11 in the second frame source block D1 are combined to generate the latter part (O01 and D11) of the code block to be encoded, Finally, a 257-bit code block to be encoded is generated.
  • the other combinations containing control code block types are similar and will not be repeated here. If a source block contains invalid synchronization header information (such as 00), the source block is an invalid source block.
  • the first frame source block is an invalid source block
  • the second frame source block is a data code block
  • the first frame source block O0 is divided into O00 and O01
  • the second frame The source code block D1 is divided into D10 and D11
  • the first subcode block O00 in the first frame source block O0 and the first subcode block D10 in the second frame source block D1 are combined to generate the front of the code block to be encoded.
  • first sub-code block O01 in the first frame source block O0 and the first sub-code block D11 in the second frame source block D1 are combined to generate the latter part (O01 and D11) of the code block to be encoded, Finally, a 257-bit code block to be encoded is generated.
  • the encoding overhead is compressed from 1.5625% to 0.4%, thereby providing a higher encoding overhead space for FEC encoding.
  • the 256B / 257B transcoding method can also be connected to the Ethernet standard.
  • the transcoding operation only targets the first sub-code block in the source code block (130-bit code block). For application scenarios where the number of links is greater than or equal to 2, two 130-bit source code blocks are obtained from two different 128B / 130B encoders.
  • the first sub-code block (64 bits) of the two 130-bit source code blocks is transmitted first, so the frame format after transcoding is conducive to completing the transcoding required in the first clock cycle. Operation, thereby effectively reducing the delay caused by transcoding.
  • FIG. 10 is a schematic diagram of a mapping relationship between a 130-bit source code block and a 258-bit code block to be encoded according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a 2-frame 130-bit source code block transcoding provided by an embodiment of the present application.
  • Receive the source code blocks from two different 128B / 130B encoders assuming that the bit width of the data transmission is 64 bits, delete the 2-bit sync header data in the 130-bit source block, and the length of the remaining valid information is 128 bits, divide it into Two 64-bit subcode blocks.
  • the first frame source block D0 is divided into D00 and D01
  • the second frame source block D1 is divided into D10 and D11
  • the first child of the first frame source block D0 is divided.
  • the code block D00 and the first sub-code block D10 in the second frame source block D1 are combined to generate the first part (D00 and D10) of the code block to be encoded. Because the received 2 frames of data are all data code blocks (Data Block ), You can add 2 bits of synchronization header information (such as 01) in front of the previous part of the code block to be encoded, and at the same time the first sub code block D01 and the second frame source block in the first frame source block D0
  • the first sub-code block D11 in D1 is combined to generate the latter part (D01 and D11) of the code block to be encoded, and finally a 258-bit code block to be encoded is generated.
  • the first frame source block is the control code block
  • the second frame source block is the data code block
  • the first frame source block O0 is divided into O00 and O01
  • the second The frame source block D1 is divided into D10 and D11.
  • the first subcode block O00 in the first frame source block O0 and the first subcode block D10 in the second frame source block D1 are combined to generate a code block to be encoded.
  • a 2-bit synchronization header information (such as 10) can be added in front of the first part of the code block to be encoded.
  • two bits in the first byte in the first control code block in the previous part of the code block to be encoded may be deleted, where the first byte is used to indicate the type of the control code block, The two deleted bits can be the two most significant bits of the first byte in the first control code block, or the two least significant bits of the first byte in the first control code block.
  • first sub-code block O01 in the first frame source block O0 and the first sub-code block D11 in the second frame source block D1 are combined to generate the latter part (O01 and D11) of the code block to be encoded, Finally, a 258-bit code block to be encoded is generated.
  • the other combinations containing control code block types are similar and will not be repeated here. If a source code block contains invalid synchronization header information (such as 00), this source code block is an invalid source code block, as shown in Figure 11 (Invalid Header + Data Block).
  • the first frame source block is invalid source code.
  • the second frame source block is a data code block
  • the first frame source block O0 is divided into O00 and O01
  • the second frame source block D1 is divided into D10 and D11
  • the first subcode in the first frame source block O0 is Block O00 and the first sub-code block D10 in the second frame source block D1 are combined to generate the first part of the code block to be encoded (O00 and D10).
  • the received 2 frames of data include invalid source code blocks
  • Add 2 bits of synchronization header information such as 10) in front of the first part of the code block to be encoded
  • add 2 bits of hot code such as 11
  • two bits in the first byte in the first source block in the previous part of the code block to be encoded may be deleted, where the two bits deleted may be the first in the first source block
  • the two most significant bits of each byte can also be the two least significant bits of the first byte in the first source block.
  • the first sub-code block O01 in the first frame source block O0 and the first sub-code block D11 in the second frame source block D1 are combined to generate the latter part (O01 and D11) of the code block to be encoded, Finally, a 258-bit code block to be encoded is generated.
  • the transcoding operation only targets the first sub-code block in the source code block (130-bit code block).
  • the source code block 130-bit code block
  • two 130-bit source code blocks are obtained from two different 128B / 130B encoders.
  • two 130-bit fast source subcode blocks 64 bits are transmitted first, so the frame format after transcoding is conducive to completing the transcoding required in the first clock cycle. Operation, thereby effectively reducing the delay caused by transcoding.
  • the synchronization header data of each source block in multiple source blocks may be deleted to obtain the remaining valid information; second, the remaining valid information in the multiple source blocks is combined to generate a long code block; Then, adding bit data in front of the long code block to obtain the code block to be encoded, the bit data may include synchronization header information or a hot code.
  • the bit data may include synchronization header information or a hot code.
  • the plurality of source code blocks includes a control code block
  • at least one bit of synchronization header information is added in front of the long code block, and a multi-bit hot code is added after the synchronization header information, and the synchronization is performed.
  • the header information is used to indicate that the multiple source code blocks include the control code block, and the hot code is used to indicate the data type of each source code block; finally, the first one in the long code block is deleted. Multiple bits in the first byte of a control code block.
  • FIG. 12 is a schematic diagram of transcoding of another 2-frame 130-bit source code block according to an embodiment of the present application.
  • (All Data Block) in FIG. 12 the synchronization header data 01 in the source code blocks D_0 and D_1 is deleted, and the remaining valid information in the source code blocks D_0 and D_1 is combined to generate a long code block.
  • a 1-bit sync header (such as 1) is added to the front, indicating that the 2 frames of source code blocks are all data code blocks, and finally 257-bit code blocks to be encoded are generated.
  • Figure 12 (Ordered Set + Block + Data Block) delete the synchronization header data 10 in source code block O_0 and synchronization header data 01 in D_1, and combine the remaining valid information in source code blocks O_0 and D_1 to generate a long code block.
  • 1-bit synchronization header information (such as 0) is added in front of the long code block, indicating that the 2-frame source code block includes a control code block.
  • a 2-bit hot code (such as 01) is added after the synchronization header information to mark the data type of the received 2 frames of data, where 0 represents the control code block and 1 represents the data code block.
  • the two bits in the first byte of the first control code block in the long code block are deleted, where the first byte is used to indicate the type of the control code block, and the deleted two bits can be These are the two most significant bits of the first byte in the first control code block, and may also be the least significant two bits of the first byte in the first control code block.
  • a 257-bit code block to be encoded is generated. The other combinations containing control code block types are similar and will not be repeated here.
  • a source block contains invalid synchronization header information (such as 00), the source block is an invalid source block.
  • the first frame source block is an invalid source block
  • the second frame source block is a data code block
  • the invalid sync header data 00 and D_1 in the source block O_0 are deleted.
  • Sync header data 01 combining the remaining valid information in source code blocks O_0 and D_1 to generate a long code block. Since the received 2 frame source code blocks contain invalid source code blocks, a 1-bit synchronization can be added in front of the long code block.
  • Header information (such as 0), and a 2-bit hot code (such as 11) is added after the synchronization header information to mark that the received 2 frames of data contain invalid source code blocks.
  • the two bits in the first byte of the first source block in the long code block are deleted.
  • the two bits that are deleted can be the two most significant bits in the first byte in the first source block.
  • the bit can also be the two lowest bits of the first byte in the first source block.
  • a 257-bit code block to be encoded is generated.
  • FIG. 13 is a schematic diagram of transcoding of a source frame block of 2 frames of 130 bits according to another embodiment of the present application.
  • (All Data Block) in FIG. 13 the synchronization header data 01 in the source code blocks D_0 and D_1 is deleted, and the remaining valid information in the source code blocks D_0 and D_1 is combined to generate a long code block.
  • a 2-bit sync header (such as 01) is added to the front, indicating that the source frames of the two frames are all data code blocks, and finally 258-bit code blocks to be encoded are generated.
  • Figure 13 (Ordered Set + Block + Data Block) delete the synchronization header data 10 in source code block O_0 and synchronization header data 01 in D_1, and combine the remaining valid information in source code blocks O_0 and D_1 to generate a long code block.
  • 2-bit synchronization header information (such as 10) is added in front of the long code block, indicating that the 2-frame source code block includes a control code block.
  • a 2-bit hot code (such as 01) is added after the synchronization header information to mark the data type of the received 2 frames of data, where 0 represents the control code block and 1 represents the data code block.
  • the two bits in the first byte of the first control code block in the long code block are deleted, where the first byte is used to indicate the type of the control code block, and the deleted two bits can be These are the two most significant bits of the first byte in the first control code block, and may also be the least significant two bits of the first byte in the first control code block.
  • a 258-bit code block to be encoded is generated. The other combinations containing control code block types are similar and will not be repeated here.
  • a source block contains invalid synchronization header information (such as 00), the source block is an invalid source block.
  • the first frame source block is an invalid source block
  • the second frame source block is a data code block
  • the invalid sync header data 00 and D_1 in the source block O_0 are deleted.
  • Sync header data 01 combining the remaining valid information in the source code blocks O_0 and D_1 to generate a long code block. Since the received 2 frame source code blocks contain invalid source code blocks, a 2-bit synchronization can be added in front of the long code block.
  • the header information (such as 10), and a 2-bit hot code (such as 11) is added after the synchronization header information to mark that the received 2 frames of data contain invalid source code blocks.
  • the two bits in the first byte of the first source block in the long code block are deleted.
  • the two bits that are deleted can be the two most significant bits in the first byte in the first source block.
  • the bit can also be the two lowest bits of the first byte in the first source block.
  • a 258-bit code block to be encoded is generated.
  • the transcoding frame format in the embodiment of the present application does not need to split the source code block, and directly performs the transcoding operation on the entire 130-bit source code block.
  • the transcoding operation provides a frame format reference.
  • transcoding method in the embodiment of the present application can be implemented as an independent method. For example, transcoding through a 256B / 258B transcoding method to obtain a 258-bit code block, or using 128B / 132B transcoding Transcoding results in a 132-bit code block.
  • the source code block can be transcoded to obtain the code block to be encoded, and then the FEC codeword can be designed according to the prime factorization method, and the code block to be encoded is encoded to obtain the FEC code.
  • the method of prime factorization reference may be made to the steps shown in FIG. 5 in the previous embodiment, and this step is not described again.
  • different code blocks to be encoded can be obtained by transcoding or non-transcoding.
  • the preferred transcoding method in this embodiment of the present application includes 256B / 258B transcoding method or 128B / 132B transcoding method. After encoding different code blocks to be encoded, different code words can be obtained.
  • the preferred code words in the embodiment of the present application include: when the source code block is transcoded by the 256B / 258B transcoding method to obtain
  • the code block to be encoded is a 130-bit code block
  • FEC codes can be sequentially distributed to multiple physical layer links in units of symbols, and each link is sequentially distributed with one symbol. After all physical layer links are distributed with one symbol, a new round of distribution is restarted. . For example, for an x16 link, symbol 0 is distributed to link 0, symbol 1 is distributed to link 1, symbol 2 is distributed to link 2, and so on, and symbol 15 is distributed to link 15. At this time, all physical layer links are distributed once, and then a new round of FEC code distribution is started, that is, symbol 16 is distributed to link 0, symbol 17 is distributed to link 1, and so on.
  • the total number of symbols of the FEC code distributed in each physical layer link is the ratio of the total number of codeword symbols of the FEC code to the number of multiple physical layer links.
  • FIG. 14 is a schematic diagram of FEC code distribution provided by an embodiment of the present application.
  • x16 physical layer links the total number of codeword symbols of the FEC code is 144.
  • the distribution mapping of FEC codes in multiple physical layer links is described in the form of a two-dimensional array, which does not exist in an actual system.
  • the FEC code is mapped into a two-dimensional array in the form of 16 symbols per line to generate a 9 * 16 two-dimensional array.
  • the two-dimensional array has 16 columns in total, and each column corresponds to a physical layer link, and then the FEC codes are mapped to the physical layer links.
  • FEC can be mapped into a 18 * 8 two-dimensional array with 8 symbols per line, and then the FEC codes in the two-dimensional array can be mapped into eight physical layer links.
  • the mapping relationship of x4, x2, and x1 links can be deduced by analogy according to the same rules.
  • FIG. 15 is a schematic diagram of another FEC code distribution provided by an embodiment of the present application.
  • the mapping rules can be deduced by analogy.
  • FIG. 16 is a schematic diagram of another FEC code distribution according to an embodiment of the present application.
  • multiple FEC codes may be interleaved and mapped into the gearbox in units of symbols, where the number of columns of the gearbox is the number of multiple physical layer links.
  • the FEC codes in the gearbox are then sequentially distributed to different physical layer links. This method is applied to an application scenario in which multiple FEC encoders output multiple FEC codes to different physical layer links, and provides a data distribution scheme for multi-link transmission scenarios.
  • the mapping relationship between multiple FEC codes on multiple physical layer links is described in the form of a two-dimensional array, which does not exist in an actual system.
  • FEC codes can be mapped into a two-dimensional array, where the number of columns in the two-dimensional array is the ratio of the number of multiple physical layer links to the number of multiple FEC codes, and the number of rows in the two-dimensional array is the number of FEC codes.
  • the number of columns in the gearbox is the number of multiple physical layer links.
  • the number of rows of the gearbox is the number of rows of the two-dimensional array; finally, the FEC codes in the gearbox are mapped to multiple physical layer links according to the columns for transmission.
  • FIG. 16 is a schematic diagram of another FEC code distribution provided by an embodiment of the present application.
  • the code blocks to be encoded are distributed to two FEC encoders, and the FEC codes obtained after encoding by the two FEC encoders are interleaved and distributed to 16 physical layer links.
  • each physical layer link sends one symbol at a time, and the 16 physical layer links send 16 symbols at a time.
  • the gearbox needs to be designed based on the ratio of the total length of the FEC code to the number of physical layer links. (Gearbox).
  • a 1: 2 transmission needs to be designed to correspond to two FEC codes.
  • Device First, the data in the two FEC encoders are mapped into two two-dimensional arrays according to 8 symbols per line (the number of symbols in each line is the number of links divided by the number of FEC encoders) and a total of 9 lines.
  • the FEC codes in these two two-dimensional arrays are interleaved and mapped into the gearbox.
  • the size of the mapped gearbox array is 9 rows and 16 columns.
  • the FEC in line 0 and line 1 in Codec1 is mapped into line 1 in the gearbox.
  • the FEC codes in the gearbox are distributed to 16 physical layer links according to the columns.
  • FIG. 17 is a schematic diagram of another FEC code distribution provided by an embodiment of the present application.
  • x4, x2, x1 physical layer links the same rules can be used for analogy.
  • a plurality of empty bits may be added to the FEC code.
  • the number of symbols in the FEC code can be matched with the number of physical layer links. This can simplify the design of the gearbox and optimize it in the process of distributing FEC codes to multiple physical layer links.
  • FIG. 18 is a schematic structural diagram of an encoding device according to an embodiment of the present application.
  • the encoding device may include a receiving module 1801, an encoding module 1802, a transcoding module 1803, and a distribution module 1804. Described as follows.
  • the receiving module 1801 is configured to receive a code block to be encoded having a length of L, where L is a positive integer;
  • An encoding module 1802 is configured to encode the code block to be encoded to obtain a forward error correction code FEC, wherein the effective information length K of the FEC code is an integer multiple of the maximum prime factor of L, and the FEC The total length N of the code is the sum of twice the error correction capability T of the FEC code and the K.
  • the transcoding module 1803 is further configured to transcode a source block to obtain the code block to be encoded.
  • the transcoding module 1803 is further configured to add at least one bit of synchronization header information to a single source block to obtain the code block to be encoded, where the synchronization header information is used to indicate a data type of the source block.
  • the transcoding module 1803 is further configured to delete synchronization header data of each source block in multiple source blocks to obtain remaining valid information; and combine the remaining valid information in the multiple source blocks to generate the waiting information. Encoded code block.
  • the transcoding module 1803 is further configured to divide the remaining valid information of each source code block into two sub-code blocks; and divide a first of the two sub-code blocks of the plurality of source code blocks. Combine the two sub-code blocks to generate the first part of the code block to be encoded, and add bit data in front of the first part of the code block to be encoded; The second sub-code block is combined to generate the latter part of the code block to be encoded.
  • the transcoding module 1803 is further configured to add at least one bit of synchronization header information in front of a front part of the code block to be encoded when the multiple source code blocks are all data code blocks.
  • the synchronization header information is used to indicate that the multiple source code blocks are all data code blocks.
  • the transcoding module 1803 is further configured to add at least one bit of synchronization header information in front of a front part of the code block to be encoded when the multiple source code blocks include a control code block, and A multi-bit hot code is added after the synchronization header information, the synchronization header information is used to indicate that the multiple source code blocks include the control code block, and the hot code is used to indicate the Data type; deleting multiple bits in the first byte of the first control code block in the previous part of the code block to be encoded.
  • the transcoding module 1803 is further configured to delete synchronization header data of each source block in multiple source blocks to obtain remaining valid information; combine the remaining valid information in the multiple source blocks to generate a long code block; Adding bit data in front of the long code block to generate the code block to be encoded.
  • the transcoding module 1803 is further configured to add at least one bit of synchronization header information in front of the long code block when the multiple source code blocks are all data code blocks, and the synchronization header information is used for It indicates that the multiple source code blocks are all data code blocks.
  • the transcoding module 1803 is further configured to add at least one bit of synchronization header information in front of the long code block when the multiple source code blocks include a control code block, and add the synchronization header information to the synchronization header information.
  • the synchronization header information is used to indicate that the multiple source code blocks contain the control code block, and the hot code is used to indicate the data type of each source code block; delete all A plurality of bits in a first byte of the first code block of the long code block.
  • the encoding module 1802 is further configured to encode the source code block based on a 128B / 130B encoding mode.
  • the transcoding module 1804 is further configured to transcode the source block by using a 256B / 258B transcoding manner or a 128B / 132B transcoding manner to obtain the code block to be encoded.
  • the distribution module 1804 is further configured to distribute the FEC code to multiple physical layer links for transmission.
  • each module may also correspond to the corresponding description of the method embodiments shown in FIG. 5 and FIG. 6, and execute the methods and functions performed by the encoder, transcoder, and FEC encoder in the above embodiments.
  • FIG. 19 is a schematic structural diagram of an encoding device according to the present application.
  • the encoding device may include: at least one processor 1901, at least one communication interface 1902, at least one memory 1903, and at least one communication bus 1904.
  • the processor 1901 may be a central processing unit, a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute various exemplary logical blocks, modules, and circuits described in connection with the disclosure of this application.
  • the processor may also be a combination that implements computing functions, such as a combination including one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on.
  • the communication bus 1904 may be a peripheral component interconnect standard PCI bus or an extended industry standard structure EISA bus. The bus can be divided into an address bus, a data bus, a control bus, and the like.
  • the communication bus 1904 is used to implement connection communication between these components.
  • the communication interface 1902 of the device in the embodiment of the present application is used to perform signaling or data communication with other node devices.
  • the memory 1903 may include volatile memory, such as nonvolatile dynamic random access memory (NVRAM), phase change random access memory (Phase, Change RAM, PRAM), magnetoresistive random access memory (Magetoresistive RAM, MRAM), etc., may also include non-volatile memory, such as at least one disk storage device, Electronically Erasable Programmable Read-Only Memory (EEPROM), flash memory devices, such as flash memory (NOR flash memory) or anti-flash memory (NAND flash memory), semiconductor devices, such as solid state drives (Solid State Disk (SSD), etc.).
  • EEPROM Electronically Erasable Programmable Read-Only Memory
  • flash memory devices such as flash memory (NOR flash memory) or anti-flash memory (NAND flash memory
  • SSD Solid State Disk
  • the memory 1903 may optionally be at least one storage device located far from the foregoing processor 1901.
  • the memory 1903 may also store a set of program code, and the processor 1901 may optionally execute a program executed in the memory 1903.
  • FEC forward error correction code
  • the effective information length K of the FEC code is an integer multiple of the maximum prime factor of L
  • the total length N of the FEC code is The sum of 2 times the error correction capability T of the FEC code and K.
  • processor 1901 is further configured to perform the following operations:
  • the source code block is transcoded to obtain the code block to be encoded.
  • processor 1901 is further configured to perform the following operations:
  • the synchronization header information is used to indicate a data type of the source block.
  • processor 1901 is further configured to perform the following operations:
  • processor 1901 is further configured to perform the following operations:
  • processor 1901 is further configured to perform the following operations:
  • the plurality of source code blocks are all data code blocks
  • at least one bit of synchronization header information is added in front of a front part of the code block to be encoded, where the synchronization header information is used to indicate the plurality of source code blocks. All are data code blocks.
  • processor 1901 is further configured to perform the following operations:
  • the plurality of source code blocks includes a control code block
  • at least one bit of synchronization header information is added in front of a front part of the code block to be encoded, and a plurality of bits of heat are added after the synchronization header information.
  • the synchronization header information is used to indicate that the multiple source code blocks include the control code block
  • the hot code is used to indicate the data type of each source code block;
  • processor 1901 is further configured to perform the following operations:
  • processor 1901 is further configured to perform the following operations:
  • At least one bit of synchronization header information is added in front of the long code block, where the synchronization header information is used to indicate that the multiple source code blocks are all data code blocks.
  • processor 1901 is further configured to perform the following operations:
  • the plurality of source code blocks includes a control code block
  • at least one bit of synchronization header information is added in front of the long code block, and a multi-bit hot code is added after the synchronization header information, and the synchronization is performed.
  • Header information is used to indicate that the multiple source code blocks include the control code block, and the hot code is used to indicate the data type of each source code block;
  • processor 1901 is further configured to perform the following operations:
  • the source code block is obtained by encoding based on a 128B / 130B encoding mode.
  • processor 1901 is further configured to perform the following operations:
  • the source code block is transcoded in a 256B / 258B transcoding manner or a 128B / 132B transcoding manner to obtain the code block to be encoded.
  • processor 1901 is further configured to perform the following operations:
  • the FEC code is distributed to multiple physical layer links for transmission.
  • processor may also cooperate with the memory and the communication interface to perform operations of the encoder, the transcoder, and the FEC encoder in the foregoing embodiments in the foregoing application embodiments.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, a computer, a server, or a data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that includes one or more available medium integration.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (Solid State Disk (SSD)), and the like.

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Abstract

本申请实施例公开了一种编码方法及相关设备，包括：接收长度为L的待编码的码块，其中，所述L为正整数；对所述待编码的码块进行编码得到前向纠错码FEC，其中，所述FEC码的有效信息长度K为所述L的最大质因数的整数倍，所述FEC码的总长度N为所述FEC码的纠错能力T的2倍与所述K之和。采用本申请实施例，可以保证FEC码字满足低时延和高增益的要求。

Description

一种编码方法及相关设备 技术领域
本申请涉及网络技术领域，尤其涉及一种编码方法及相关设备。
背景技术
随着信息技术的发展，用户对信息的需求量越来越大，日益增长的信息需求使得互联接口的速率不断提升。例如外部设备互联(Peripheral Component Interconnect Express，PCIE)，一种高速串行计算机扩展总线标准，接口速率从PCIE1.0时代开始，先后经历了2.5GT/s、5GT/s、8GT/s，再到最新发布的PCIE4.0的16GT/s。未来PCIE还将向32GT/s、56GT/s演进，传输速率的越来越高，链路的损耗也越来越大。另外，随着速率及处理能力的提升，中央处理器(Central Processing Unit，CPU)、图形处理器(Graphics Processing Unit，GPU)和现场可编程门阵列(Field-Programmable Gate Array，FPGA)等芯片的封装尺寸也变得越来越大，封装损耗也越来越高，且优化困难。在56G时代，即使不考虑主板走线，单纯由两端芯片的封装带来的损耗已经非常接近串行器和解串器(Serializer/Deserializer，SerDes)的驱动能力，因此必然需要引入前向纠错码(Forward Error Correction，FEC)来对链路的损耗进行补偿，进而支持更大的链路损耗。但是，现有的技术方案中的FEC码字无法满足低时延和高增益的要求。
发明内容
本申请实施例提供一种编码方法及相关设备，通过FEC编码得到的FEC码字可以满足低时延和高增益的要求。
第一方面，本申请实施例提供了一种编码方法，包括：
首先接收长度为L的待编码的码块，其中，L为正整数；然后对待编码的码块进行编码得到前向纠错码FEC，其中，FEC码的有效信息长度K为L的最大质因数的整数倍，FEC码的总长度N为FEC码的纠错能力T的2倍与K之和。
实施本申请实施例，可以编码得到低开销的短码，满足低时延的要求，也可以编码得到纠错能力强的长码，满足高增益的要求。因此通过FEC编码得到的FEC码字可以满足低时延和高增益的要求。
在一种可能的设计中，FEC码中每个符号所包含的比特数为M，其中，M为满足(2 M-1)>＝N的最小偶数。
在另一种可能的设计中，在基于128B/130B编码方式进行编码得到源码块之后，可以通过两条路径向下传输：第一条路径为非转码路径，直接将源码块传输到扰码器进行扰码；第二条路径为转码路径，对源码块进行转码得到待编码的码块，然后再进行扰码。其中，转码路径包括两条子路径，子路径1是128B/132B转码路径，子路径2为256B/257B或256B/258B转码路径。
在另一种可能的设计中，对源码块进行转码得到待编码的码块。
在另一种可能的设计中，转码器可以接收单个编码器输出的单个源码块进行转码，也可以接收多个不同编码器输出的多个源码块进行转码。
在另一种可能的设计中，在单个源码块上添加至少一个比特的同步头信息得到待编码的码块，同步头信息用于指示源码块的数据类型。通过在每帧源码块的前面添加额外至少一个比特的帧头保护，从而有效降低帧头出错的概率。
在另一种可能的设计中，删除多个源码块中每个源码块的同步头数据得到剩余有效信息；将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块。
在另一种可能的设计中，首先将每个源码块的剩余有效信息划分为两个子码块；然后将多个源码块的两个子码块中的第一个子码块组合生成待编码的码块的前部分，在待编码的码块的前部分的前面添加比特数据；最后，将多个源码块的两个子码块中的第二个子码块组合生成待编码的码块的后部分。
在另一种可能的设计中，当多个源码块全部为数据码块时，在待编码的码块的前部分的前面添加至少一个比特的同步头信息，同步头信息用于指示多个源码块全部为数据码块。
在另一种可能的设计中，当多个源码块包含有控制码块时，在待编码的码块的前部分的前面添加至少一个比特的同步头信息，并在同步头信息后添加多个比特的热码，同步头信息用于指示多个源码块包含有控制码块，热码用于指示每个源码块的数据类型；删除待编码的码块的前部分中第一个控制码块中第一个字节中的多个比特。
在另一种可能的设计中，当多个源码块包含有无效的源码块时，在待编码的码块的前部分的前面添加至少一个比特的同步头信息，并在同步头信息后添加多个比特的热码，热码用于指示多个源码块中包含有至少一个无效的源码块；同时删除待编码的码块的前部分中第一个源码块中第一个字节中的多个比特。
通过以上可选方式，可以实现对128B/130B编码器输出的源码块进行128B/132B转码处理，对128B/130B编码器输出的源码块进行256B/257B转码处理，以及对128B/130B编码器输出的源码块进行256B/258B转码处理，或对其他类型的编码方式进行相应的转码处理。包括如下有益效果：
通过对128B/130B编码器输出的源码块进行128B/132B转码处理，在每帧源码块的前面添加额外至少一个比特的帧头保护，从而有效降低帧头出错的概率。
通过对128B/130B编码器输出的源码块进行256B/257B转码处理，可以将编码开销从1.5625％压缩到0.4％，从而为FEC编码提供了更高的编码开销空间。同时256B/257B转码方式也可以对接以太标准。另外，本实施例中给出的转码后的帧格式，转码操作只针对源码块(130比特码块)中的第一个子码块。对于链路数量大于等于2的应用场景，2个130比特的源码块从两个不同的128B/130B编码器获取。由于在数据传输过程中，首先传输两个130比特的源码块的第一个子码块(64比特)，因此转码后的帧格式有利于在第一个时钟周期内完成转码所需的操作，从而有效降低转码带来的时延。
通过对128B/130B编码器输出的源码块进行256B/258B转码处理，可以将编码开销从1.5625％压缩到0.8％，从而为FEC编码提供了更高的编码开销空间。另外，本实施例中给出的转码后的帧格式，转码操作只针对源码块(130比特码块)中的第一个子码块。 对于链路数量大于等于2的应用场景，2个130比特的源码块从两个不同的128B/130B编码器获取。由于在数据传输过程中，首先传输两个130比特的源码快的第一个子码块(64比特)，因此转码后的帧格式有利于在第一个时钟周期内完成转码所需的操作，从而有效降低转码带来的时延。
在另一种可能的设计中，可以删除多个源码块中每个源码块的同步头数据得到剩余有效信息；将多个源码块中剩余有效信息组合生成一个长码块；在长码块的前面添加比特数据得到待编码的码块。最后删除长码块中第一个控制码块中第一个字节中的多个比特。本申请实施例中的转码帧格式不需要对源码块进行切分，直接以整个130比特的源码块进行转码操作，可以为转码操作提供帧格式参考。
在另一种可能的设计中，当多个源码块全部为数据码块时，在长码块的前面添加至少一个比特的同步头信息，同步头信息用于指示多个源码块全部为数据码块。
在另一种可能的设计中，当多个源码块包含有控制码块时，在长码块的前面添加至少一个比特的同步头信息，并在同步头信息后添加多个比特的热码，同步头信息用于指示多个源码块包含有控制码块，热码用于指示每个源码块的数据类型，同时删除待编码的码块的前部分中第一个控制码块中第一个字节中的多个比特。
在另一种可能的设计中，当多个源码块包含有无效的源码块时，在长码块的前面添加至少一个比特的同步头信息，并在同步头信息后添加多个比特的热码，热码用于指示多个源码块中包含有至少一个无效的源码块，同时删除多个待编码的码块中第一个源码块中第一个字节中的多个比特。
在另一种可能的设计中，首先对源码块进行转码得到待编码的码块，然后按照质因数分解方法进行FEC码字的设计，并对待编码的码块进行编码得到FEC码。
在另一种可能的设计中，基于128B/130B编码方式进行编码得到源码块。
在另一种可能的设计中，在基于128B/130B编码方式进行编码得到源码块之后，可以通过转码方式或非转码方式得到不同的待编码的码块，其中，本申请实施例优选的转码方式包括256B/258B转码方式或128B/132B转码方式。
在另一种可能的设计中，当L＝258时，N＝192，K＝172，T＝10，M＝8；或N＝184，K＝172，T＝6，M＝8；或N＝96，K＝86，T＝5，M＝8。
在另一种可能的设计中，当L＝132时，N＝136，K＝132，T＝2，M＝8；或N＝144，K＝132，T＝6，M＝8；或N＝152，K＝132，T＝10，M＝8；或N＝72，K＝66，T＝3，M＝8。
在另一种可能的设计中，当L＝130时，N＝136，K＝130，T＝3，M＝8；或N＝144，K＝130，T＝7，M＝8；或N＝152，K＝130，T＝11，M＝8。
在另一种可能的设计中，对于长距离、损耗高、时延要求低的应用场景，可以优先选择RS(272，258，T＝7)或RS(544，514，T＝15)等长码。而对于短距离、损耗低、时延要求高的应用场景，可以优先选择RS(144，132，T＝6)、RS(144，130，T＝7)、RS(192，172，T＝10)或RS(72，66，T＝3)等短码。
在另一种可能的设计中，将FEC码分发到多条物理层链路上进行发送。
在另一种可能的设计中，可以将FEC码以符号为单位依次分发到多条物理层链路中，每条链路依次分发一个符号，当所有物理层链路都分发一个符号后，重新开始新一轮分发。 其中，每条物理层链路中分发的FEC码的符号数为FEC码的码字总符号数与多条物理层链路的数量的比值。该方式应用于将一个FEC编码器输出单个FEC码字分发到不同的物理层链路的应用场景，为多链路传输场景提供数据分发方案。
另一种可能的设计中，可以将多个FEC码以符号为单位交织处理并映射到变速箱中，其中，变速箱的列数为多条物理层链路的条数。然后将变速箱中的FEC码依次分发到多条物理层链路中。该方式应用于将多个FEC编码器输出多个FEC码字分发到不同的物理层链路的应用场景，为多链路传输场景提供数据分发方案。
在另一种可能的设计中，可以在对待编码的码块进行编码得到FEC码之后，在FEC码中添加多个比特的空比特。通过添加空比特，可以使FEC码中符号数量与物理层链路的数量相匹配，这样可以使得向多条物理层链路分发FEC码的过程中简化变速箱的设计，起到优化作用。
第二方面，本申请实施例提供了一种编码装置，该编码装置被配置为实现上述第一方面中FEC编码器所执行的方法和功能，由硬件/软件实现，其硬件/软件包括与上述功能相应的单元。
第三方面，本申请提供了一种编码设备，包括：处理器、存储器和通信总线，其中，通信总线用于实现处理器和存储器之间连接通信，处理器执行存储器中存储的程序用于实现上述第一方面提供的一种编码处理方法中的步骤。
在一个可能的设计中，本申请提供的编码设备可以包含用于执行上述方法设计中编码装置行为相对应的模块。模块可以是软件和/或是硬件。
第四方面，本申请提供了一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面的方法。
第五方面，本申请提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面的方法。
附图说明
图1是本申请实施例提供的一种CCIX标准系统的架构示意图；
图2是本申请实施例提供了一种400GE以太网标准的结构示意图；
图3本申请实施例提供了一种物理层编码架构的结构示意图；
图4是本申请实施例提供的一种高速接口物理层编码系统的结构示意图；
图5是申请实施例提供的一种FEC编码方法的流程示意图；
图6是本申请实施例提供的一种编码方法的流程示意图；
图7是本申请实施例提供的一种1帧130比特的源码块转码的示意图；
图8是本申请实施例提供的一种130比特的源码块与257比特的待编码的码块的映射关系示意图；
图9是本申请实施例提供的一种2帧130比特的源码块转码的示意图；
图10是本申请实施例提供的一种130比特的源码块与258比特的待编码的码块的映射关系示意图；
图11是本申请实施例提供的另一种2帧130比特的源码块转码的示意图；
图12是本申请实施例提供的又一种2帧130比特的源码块转码的示意图；
图13是本申请实施例提供的又一种2帧130比特的源码块转码的示意图；
图14是本申请实施例提供的一种FEC码分发的示意图；
图15是本申请实施例提供的另一种FEC码分发的示意图；
图16是本申请实施例提供的又一种FEC码分发的示意图；
图17是本申请实施例提供的又一种FEC码分发的示意图；
图18是本申请实施例提供的一种编码装置的结构示意图；
图19是本申请实施例提供的一种编码设备的结构示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
请参见图1，图1是本申请实施例提供的一种加速器缓存一致性互联(Cache Coherent Interconnect for Accelerators，CCIX)标准系统的架构示意图，该CCIX标准系统为依附于PCIE架构的一种互联方式。在该CCIX标准系统中，从上至下依次包括应用层及以上各层、CCIX协议层、CCIX链路层、CCIX传输层、PCIE传输层、PCIE数据链路层和CCIX物理层，其中，CCIX物理层包含逻辑子层(Logical Sub-Block)和电子子层(Electrical Sub-Block)两个子层。
对于PCIE、CCIX架构，当接口速率提升时，存在链路损耗的问题，针对PCIE、CCIX的应用场景，互联距离本身较短，系统对时延的要求较高。在提升接口速率并引入FEC之后，若FEC的时延较高，则在相同时间内可传输的数据总量增长有限。因此对引入FEC后的FEC本身的时延提出了较高要求。在现有技术方案中，提供了如下FEC的设计方案。
请参考图2，图2是本申请实施例提供了一种400GE以太网标准的结构示意图。该示意图的右侧部分为物理层中的物理编码子层(Physical Coding Sublayer，PCS)对应的详细框图。该标准方案中在物理层中首先采用64B/66B编码方式进行编码，然后采用256B/257B转码方式进行转码。在该转码方案的基础上，提供了基于257比特码块长度设计的FEC码字KP4-RS(544，514)。其中，RS为里德所罗门(Reed-Solomon)码字。但是，在400GE以太网接口标准中使用的RS(544，514)码字的解码时延达到百纳秒左右，时延较大，不适合应用于时延要求较高的应用场景。
请参考图3，图3本申请实施例提供了一种物理层编码架构的结构示意图。该物理层编码架构为串行小型计算机系统接口(Serial Attached SCSI 4，SAS-4)标准对应的物理层编码架构。链路速率可以达到22.5Gbps，在物理层引入FEC进行链路损耗补偿。该SAS标准首先采用8B/10B编码方式进行编码，然后采用128B/130B编码方式再进行编码，最后进行FEC编码。在FEC码字选择上，SAS-4选择与130比特码块长度相对应的RS(30，26)。虽然SAS-4采用的128B/130B的编码方式与CCIX、PCIE3.0及以上标准相同，但是SAS-4所选FEC码字的净编码增益(Net Coding Gain，NCG)只有3.46dB，远低于KP4-RS(544，514)的增益水平，因此该FEC码字无法应用到链路损耗较大的应用场景。
综上所述，现有的CCIX、PCIE架构中没有FEC，随着CCIX、PCIE速率提升(比如56Gbps或更高速率)，链路损耗增大，需要引入FEC进行增益补偿。CCIX、PCIE为 时延高敏感性型系统，引入FEC后对FEC的解码时延提出较高的要求，另外CCIX、PCIE提升接口速率引入FEC后，对FEC的增益要求接近KP4，现有的技术方案中的FEC码字不能同时满足低时延和高增益的要求。针对上述技术问题，本申请实施例提供了如下解决方案。
如图4所示，图4是本申请实施例提供的一种高速接口物理层编码系统的结构示意图。本申请的主要应用场景是CCIX及PCIE，图4是该场景下的整体系统的架构示意图，其中左侧为CCIX/PCIE的整体架构，该架构中包括应用层及以上各层、CCIX协议层、CCIX链路层、CCIX传输层、PCIE传输层、PCIE数据链路层和CCIX物理层。其中，物理层包含逻辑子层和电子子层两个子层。本申请实施例是针对该架构中的物理层中的逻辑子层部分提出的编码方法。右侧为在逻辑子层部分中高速接口物理层编码方法的示意图。在发送侧，从上至下主要包括：编码、转码、扰码、FEC编码和发送等步骤。而在接收侧，从下至上主要包括接收、FEC解码、解扰码、反转码和链路重排序等步骤。由于发送侧和接收侧原理相同，本申请实施例仅以发送侧的编码方法进行描述。
针对上述系统中FEC编码，本申请实施例提供了一种FEC编码方法，如图5所示，图5是申请实施例提供的一种FEC编码方法的流程示意图。包括：
S501，接收长度为L的待编码的码块，所述L为正整数。其中，L的单位为比特，接收到待编码的码块的个数可以为1个或多个，多个可以为整数个或非整数个，待编码的码块的的个数可以由编码得到的FEC码的有效信息长度确定。例如，当待编码的码块为256B/258B的码块时，L＝258比特，当待编码的码块为128B/132B的码块时，L＝132比特。
S502，对所述待编码的码块进行编码得到前向纠错码FEC，其中，所述FEC码的有效信息长度K为所述L的最大质因数的整数倍，所述FEC码的总长度N为所述FEC码的纠错能力T的2倍与所述K之和。所述FEC码中每个符号所包含的比特数M由所述N确定，其中，M可以为满足(2 M-1)>＝N的正整数。可选的，M也可以为满足(2 M-1)>＝N的最小偶数。FEC码字以符号为单位，K为FEC码的有效信息长度，N为FEC码的总长度，即N表示经过FEC编码器后输出的符号总数，T表示FEC码能纠错的符号数，M为每个符号中包含的比特数。以里德所罗门(Reed-Solomon，RS)码为例，其表示方式为RS(N，K，T，M)，例如RS(N，K，T，M)为RS(544，514，15，10)，该FEC码的总长度N为544个符号，有效信息长度K为514个符号，纠错能力T为15个符号，每个符号中所包含的比特数为10。本申请实施例中的FEC码也可以称为FEC码字。
实施本申请实施例，可以编码得到低开销的短码，满足低时延的要求，也可以编码得到纠错能力强的长码，满足高增益的要求。因此通过FEC编码得到的FEC码字可以满足低时延和高增益的要求。
例如，针对128B/130B编码方案，FEC编码器接收到长度L＝130比特的待编码的码块，将130进行质因数分解，130＝13*5*2。以其中最大的质因数P＝13为基，对FEC码中的有效信息长度K进行设计，选取K为P的整数倍，即K＝a*13，其中a＝1、2、3……，纠错能力T＝1、2、3……。FEC码的总长度N＝K+2T。在FEC码中，M可以由N确定，M可以为满足(2 M-1)>＝N条件的最小偶数，例如6、8、10、……，以RS(144，130，T＝7)为例，M优选值为8。
需要说明的是，本申请实施例结合128B/130B编码方案，提供了相应的FEC码字设计方法，为CCIX和PCIE提供了在128B/130B编码场景下的码字选择。根据质因数分解方法，对编码后的码块长度130进行质因数分解，利用最大的质因数为基进行码字设计，可以简化FEC收帧过程中的变速箱(Gearbox)设计。
请参考图6，图6是本申请实施例提供的一种编码方法的流程示意图。本申请实施例是结合上述实施例中FEC编码，对物理层编码进行整体描述，该物理层编码是示例性的，该编码方法也可以用在其它地方，本申请实施例中的编码方法至少包括如下步骤：
S601，基于128B/130B编码方式进行编码得到所述源码块。
具体实现中，如图4所示，在物理层包括编码器#0、编码器#1、……、编码器#P等多个不同的128/130编码器，物理层首先接收数据链路层(Data Link Layer，DLL)下发的数据，将接收到的数据按照字节(每个字节包括8比特)为一组，每次分发到不同的编码器中。例如，从DLL层依次接收到字节0、字节1、字节2、字节3、……等等，在进行链路分发时，将接收到的字节依次分发到不同的链路上去，每条链路对应一个编码器，字节0—>链路0(对应编码器#0)，因此字节0分发到编码器#0。字节1—>链路1(对应编码器#1)，因此字节1分发到编码器#1。当每条链路接到128比特信息后，添加2比特同步头信息，生成130比特的码块。其中，不同的编码器可以输出不同的源码块。本申请实施例所涉及的编码器主要基于128B/130B编码方式进行编码，也可以采用其他编码方式进行编码。
需要说明的是，在基于128B/130B编码方式进行编码得到所述源码块之后，可以通过两条路径向下传输：第一条路径为非转码路径(No Transcode，NTC)，跳转到S603，直接将源码块传输到扰码器进行扰码；第二条路径为转码路径(Transcode，TC)，跳转到S602，对源码块进行转码得到待编码的码块，然后再进行扰码。其中，转码路径包括两条子路径，子路径1是对单个源码块进行转码，子路径2是对多个源码块进行转码。例如，子路径1从单个128B/130B编码器接收到1帧130比特的源码块，经过128B/132B转码器生成132比特的待编码的码块。子路径2从不同的128B/130B编码器接收到2帧130比特的源码块，输入到256B/257B或256B/258B转码器中，生成一个257比特或258比特的待编码的码块。
S602，对源码块进行转码得到所述待编码的码块。
具体实现中，转码器可以接收单个编码器输出的单个源码块进行转码，也可以接收多个不同编码器输出的多个源码块进行转码。转码方式包括以下几种可选方式：
第一种可选方式，可以在单个源码块上添加至少一个比特的同步头信息得到所述待编码的码块，所述同步头信息用于指示所述源码块的数据类型。通过在每帧源码块的前面添加额外至少一个比特的帧头保护，从而有效降低帧头出错的概率。
例如，如图7所示，图7是本申请实施例提供的一种1帧130比特的源码块转码的示意图。从单个128B/130B编码器接收1帧130比特的源码块，对该源码块进行128B/132B转码操作。首先保留130比特的源码块的格式，然后在130比特的源码块的基础上，在前面添加2比特的同步头信息，例如H 0H 1表示2比特的同步头信息，其中，比特H 0为最 低有效位(Least Significant Bit，LSB)，比特H 1为最高有效位(Most Significant Bit，MSB)。然后转码为132比特的待编码的码块。其中，当接收到的源码块的数据类型为数据码块(Data Block)时，添加2比特同步头信息，如H 0H 1＝01；当接收到的源码块的数据类型为控制码块(Ordered Set Block)时，添加的2比特同步头信息，如H 0H 1＝10；当接收到的源码块的数据类型为无效同步头(Invalid Header)时，添加的2比特同步头信息，如H 0H 1＝00。其中，添加的同步头信息与源码块自身的同步头数据可以相同。
第二种可选的方式，可以首先删除多个源码块中每个源码块的同步头数据得到剩余有效信息，将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块，其中，剩余有效信息为除去同步头数据后的码块。进一步的，可以将所述每个源码块的所述剩余有效信息划分为两个子码块；然后将所述多个源码块的所述两个子码块中的第一个子码块组合生成所述待编码的码块的前部分，在所述待编码的码块的前部分的前面添加比特数据，该比特数据可以包括同步头信息或热码。其中，当所述多个源码块全部为数据码块时，在所述待编码的码块的前部分的所述前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。当所述多个源码块包含有控制码块时，在所述待编码的码块的前部分的所述前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；删除所述待编码的码块的前部分中第一个所述控制码块中第一个字节中的多个比特。最后，将所述多个源码块的所述两个子码块中的第二个子码块组合生成所述待编码的码块的后部分。
需要说明的是，可以将每个源码块中的剩余有效信息划分为X个子码块，X可以为3、4、5等正整数。然后将第1个源码块中的第1个子码块、第2个源码块的第1个子码块、……、以及第Y个源码块中的第1个子码块组合生成待编码的码块的第一个部分；将第1个源码块中的第2个子码块、第2个源码块的第2个子码块、……、以及第Y个源码块中的第2个子码块组合生成待编码的码块的第二个部分；将第1个源码块中的第3个子码块、第2个源码块的第3个子码块、……、以及第Y个源码块中的第3个子码块组合生成待编码的码块的第三个部分等等，其他按照上述相同的方法进行转码，Y为正整数。
例如，如图8所示，图8是本申请实施例提供的一种130比特的源码块与257比特的待编码的码块的映射关系示意图。对于存在多个128B/130B编码器的系统来说，可以从两个不同的128B/130B编码器接收2帧130比特的源码块，对该2帧130比特的源码块进行256B/257B转码操作，进而得到257比特待编码的码块。
又如图9所示，图9是本申请实施例提供的一种2帧130比特的源码块转码的示意图。从两个不同的128B/130B编码器中接收源码块，假设数据传输的位宽为64比特，删除130比特源码块中的2比特同步头数据，剩余有效信息的长度为128比特，将其分成两个64比特的子码块。如图9中的(All Data Block)所示，第一帧源码块D0划分为D00和D01，第二帧源码块D1划分为D10和D11，将第一帧源码块D0中的第一个子码块D00和第二帧源码块D1中的第一个子码块D10组合生成待编码的码块的前部分(D00和D10)，由于接收到的2帧数据全部为数据码块(Data Block)，可以在待编码的码块的前部分的前 面添加1个比特的同步头信息(如1)，同时将第一帧源码块D0中的第一个子码块D01和第二帧源码块D1中的第一个子码块D11组合生成待编码的码块的后部分(D01和D11)，最后组合生成257比特的待编码的码块。又如图9中(Ordered Set Block+Data Block)所示，第一帧源码块为控制码块，第二帧源码块为数据码块，第一帧源码块O0划分为O00和O01，第二帧源码块D1划分为D10和D11,将第一帧源码块O0中的第一个子码块O00和第二帧源码块D1中的第一个子码块D10组合生成待编码的码块的前部分(O00和D10),由于接收到的2帧数据包括控制码块和数据码块，可以在待编码的码块的前部分的前面添加1个比特的同步头信息(如0)，同时在同步头信息后面添加2比特的热码(如01)，用于标记接收到的2帧数据的数据类型，其中，0表示控制码块，1表示数据码块。并且，相应地删除待编码的码块的前部分中第一个控制码块中的第一个字节中的两个比特，其中，该第一个字节用于指示控制码块的类型，该删除的两个比特可以为第一个控制码块中第一个字节中最高位的两个比特，也可以为第一个控制码块中第一个字节中最低位的两个比特。另外，将第一帧源码块O0中的第一个子码块O01和第二帧源码块D1中的第一个子码块D11组合生成待编码的码块的后部分(O01和D11)，最后生成257比特的待编码的码块。其他含有控制码块类型的组合相类似，此处不再赘述。如果某个源码块中包含有无效的同步头信息(如00)，此源码块为无效的源码块。如图9中(Invalid Header+Data Block)所示，第一帧源码块为无效的源码块，第二帧源码块为数据码块，第一帧源码块O0划分为O00和O01，第二帧源码块D1划分为D10和D11,将第一帧源码块O0中的第一个子码块O00和第二帧源码块D1中的第一个子码块D10组合生成待编码的码块的前部分(O00和D10)，由于接收到的2帧数据包括有无效的源码块，可以在待编码的码块的前部分的前面添加1个比特的同步头信息(如0)，同时在同步头信息后面添加2比特的热码(如11)，用于标记接收到的2帧源码块中含有无效的源码块。相应地，可以删除待编码的码块的前部分中第一个源码块中的第一个字节中的两个比特，其中，该删除的两个比特可以为第一个源码块中第一个字节中最高位的两个比特，也可以为第一个源码块中第一个字节中最低位的两个比特。另外，将第一帧源码块O0中的第一个子码块O01和第二帧源码块D1中的第一个子码块D11组合生成待编码的码块的后部分(O01和D11)，最后生成257比特的待编码的码块。
需要说明的是，通过对128B/130B编码器输出的源码块进行256B/257B转码处理，将编码开销从1.5625％压缩到0.4％，从而为FEC编码提供了更高的编码开销空间。同时256B/257B转码方式也可以对接以太标准。另外，本实施例中给出的转码后的帧格式，转码操作只针对源码块(130比特码块)中的第一个子码块。对于链路数量大于等于2的应用场景，2个130比特的源码块从两个不同的128B/130B编码器获取。由于在数据传输过程中，首先传输两个130比特的源码块的第一个子码块(64比特)，因此转码后的帧格式有利于在第一个时钟周期内完成转码所需的操作，从而有效降低转码带来的时延。
例如，如图10所示，图10是本申请实施例提供的一种130比特的源码块与258比特的待编码的码块的映射关系示意图。对于存在多个128B/130B编码器的系统来说，可以从两个不同的128B/130B编码器接收2帧130比特的源码块，对该2帧130比特的源码块进行256B/258B转码操作，进而得到258比特待编码的码块。
又如图11所示，图11是本申请实施例提供的一种2帧130比特的源码块转码的示意图。从两个不同的128B/130B编码器中接收源码块，假设数据传输的位宽为64比特，删除130比特源码块中的2比特同步头数据，剩余有效信息的长度为128比特，将其分成两个64比特的子码块。如图11中的(All Data Block)所示，第一帧源码块D0划分为D00和D01，第二帧源码块D1划分为D10和D11，将第一帧源码块D0中的第一个子码块D00和第二帧源码块D1中的第一个子码块D10组合生成待编码的码块的前部分(D00和D10)，由于接收到的2帧数据全部为数据码块(Data Block)，可以在待编码的码块的前部分的前面添加2个比特的同步头信息(如01)，同时将第一帧源码块D0中的第一个子码块D01和第二帧源码块D1中的第一个子码块D11组合生成待编码的码块的后部分(D01和D11)，最后生成258比特的待编码的码块。又如图11中(Ordered Set Block+Data Block)所示，第一帧源码块为控制码块，第二帧源码块为数据码块，第一帧源码块O0划分为O00和O01，第二帧源码块D1划分为D10和D11,将第一帧源码块O0中的第一个子码块O00和第二帧源码块D1中的第一个子码块D10组合生成待编码的码块的前部分(O00和D10)，由于接收到的2帧数据包括控制码块和数据码块，可以在待编码的码块的前部分的前面添加2个比特的同步头信息(如10)，同时在同步头信息后面添加2比特的热码(如01)，用于标记接收到的2帧数据的数据类型，其中，0表示控制码块，1表示数据码块。相应地，可以删除待编码的码块的前部分中第一个控制码块中的第一个字节中的两个比特，其中，该第一个字节用于指示控制码块的类型，该删除的两个比特可以为第一个控制码块中第一个字节中最高位的两个比特，也可以为第一个控制码块中第一个字节中最低位的两个比特。另外，将第一帧源码块O0中的第一个子码块O01和第二帧源码块D1中的第一个子码块D11组合生成待编码的码块的后部分(O01和D11)，最后生成258比特的待编码的码块。其他含有控制码块类型的组合相类似，此处不再赘述。如果某个源码块中包含有无效的同步头信息(如00)，此源码块为无效的源码块，如图11中(Invalid Header+Data Block)所示，第一帧源码块为无效的源码块，第二帧源码块为数据码块，第一帧源码块O0划分为O00和O01，第二帧源码块D1划分为D10和D11,将第一帧源码块O0中的第一个子码块O00和第二帧源码块D1中的第一个子码块D10组合生成待编码的码块的前部分(O00和D10)，由于接收到的2帧数据包括有无效的源码块，可以在待编码的码块的前部分的前面添加2个比特的同步头信息(如10)，同时在同步头信息后面添加2比特的热码(如11)，用于标记接收到的2帧源码块中含有无效的源码块。相应地，可以删除待编码的码块的前部分中第一个源码块中的第一个字节中的两个比特，其中，该删除的两个比特可以为第一个源码块中第一个字节中最高位的两个比特，也可以为第一个源码块中第一个字节中最低位的两个比特。另外，将第一帧源码块O0中的第一个子码块O01和第二帧源码块D1中的第一个子码块D11组合生成待编码的码块的后部分(O01和D11)，最后生成258比特的待编码的码块。
需要说明的是，通过对128B/130B编码器输出的源码块进行256B/258B转码处理，将编码开销从1.5625％压缩到0.8％，从而为FEC编码提供了更高的编码开销空间。另外，本实施例中给出的转码后的帧格式，转码操作只针对源码块(130比特码块)中的第一个子码块。对于链路数量大于等于2的应用场景，2个130比特的源码块从两个不同的 128B/130B编码器获取。由于在数据传输过程中，首先传输两个130比特的源码快的第一个子码块(64比特)，因此转码后的帧格式有利于在第一个时钟周期内完成转码所需的操作，从而有效降低转码带来的时延。
第三种可选的方式，可以首先删除多个源码块中每个源码块的同步头数据得到剩余有效信息；其次将所述多个源码块中所述剩余有效信息组合生成一个长码块；然后，在所述长码块的前面添加比特数据得到所述待编码的码块，该比特数据可以包括同步头信息或热码。其中，当所述多个源码块全部为数据码块时，在所述长码块的所述前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。当所述多个源码块包含有控制码块时，在所述长码块的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；最后，删除所述长码块中第一个所述控制码块中第一个字节中的多个比特。
如图12所示，图12是本申请实施例提供的另一种2帧130比特的源码块转码的示意图。首先从两个不同的128B/130B编码器接收2帧130比特的源码块，删除每帧130比特的源码块中的同步头数据，每帧包括2个比特同步头数据，删除后得到2帧128比特的剩余有效信息。然后将128比特的剩余有效信息组成一个256比特的长码块。如图12中的(All Data Block)所示，删除源码块D_0和D_1中的同步头数据01，将源码块D_0和D_1中剩余有效信息组合生成一个长码块，并且在该长码块的前面添加1比特的同步头信息(如1)，表示2帧源码块全部为数据码块，最后生成257比特的待编码的码块。又如图12中(Ordered Set Block+Data Block)所示，删除源码块O_0同步头数据10和D_1中的同步头数据01，将源码块O_0和D_1中剩余有效信息组合生成一个长码块，并且在该长码块的前面添加1比特的同步头信息(如0)，表示2帧源码块包含有控制码块。同时在同步头信息后面添加2比特的热码(如01)，用于标记接收到的2帧数据的数据类型，其中，0表示控制码块，1表示数据码块。并且，删除长码块中第一个控制码块中的第一个字节中的两个比特，其中，该第一个字节用于指示控制码块的类型，该删除的两个比特可以为第一个控制码块中第一个字节中最高位的两个比特，也可以为第一个控制码块中第一个字节中最低位的两个比特。最后生成257比特的待编码的码块。其他含有控制码块类型的组合相类似，此处不再赘述。如果某个源码块中包含有无效的同步头信息时(如00)，此源码块为无效的源码块。如图12中(Invalid Header+Data Block)所示，第一帧源码块为无效的源码块，第二帧源码块为数据码块，删除源码块O_0中无效的同步头数据00和D_1中的同步头数据01，将源码块O_0和D_1中剩余有效信息组合生成一个长码块，由于接收到的2帧源码块中含有无效的源码块，可以在该长码块的前面添加1比特的同步头信息(如0)，同时在同步头信息后面添加2比特的热码(如11)，用于标记接收到的2帧数据中含有无效的源码块。并且，删除长码块中第一个源码块中的第一个字节中的两个比特，该删除的两个比特可以为第一个源码块中第一个字节中最高位的两个比特，也可以为第一个源码块中第一个字节中最低位的两个比特。最后生成257比特的待编码的码块。
如图13所示，图13是本申请实施例提供的又一种2帧130比特的源码块转码的示意 图。首先从两个不同的128B/130B编码器接收2帧130比特的源码块，删除每帧130比特的源码块中的同步头数据，每帧包括2个比特同步头数据，删除后得到2帧128比特的剩余有效信息。然后将128比特的剩余有效信息组成一个256比特的长码块。如图13中的(All Data Block)所示，删除源码块D_0和D_1中的同步头数据01，将源码块D_0和D_1中剩余有效信息组合生成一个长码块，并且在该长码块的前面添加2比特的同步头信息(如01)，表示2帧源码块全部为数据码块，最后生成258比特的待编码的码块。又如图13中(Ordered Set Block+Data Block)所示，删除源码块O_0同步头数据10和D_1中的同步头数据01，将源码块O_0和D_1中剩余有效信息组合生成一个长码块，并且在该长码块的前面添加2比特的同步头信息(如10)，表示2帧源码块包含有控制码块。同时在同步头信息后面添加2比特的热码(如01)，用于标记接收到的2帧数据的数据类型，其中，0表示控制码块，1表示数据码块。并且，删除长码块中第一个控制码块中的第一个字节中的两个比特，其中，该第一个字节用于指示控制码块的类型，该删除的两个比特可以为第一个控制码块中第一个字节中最高位的两个比特，也可以为第一个控制码块中第一个字节中最低位的两个比特。最后生成258比特的待编码的码块。其他含有控制码块类型的组合相类似，此处不再赘述。如果某个源码块中包含有无效的同步头信息时(如00)，此源码块为无效的源码块。如图13中(Invalid Header+Data Block)所示，第一帧源码块为无效的源码块，第二帧源码块为数据码块，删除源码块O_0中无效的同步头数据00和D_1中的同步头数据01，将源码块O_0和D_1中剩余有效信息组合生成一个长码块，由于接收到的2帧源码块中含有无效的源码块，可以在该长码块的前面添加2比特的同步头信息(如10)，同时在同步头信息后面添加2比特的热码(如11)，用于标记接收到的2帧数据中含有无效的源码块。并且，删除长码块中第一个源码块中的第一个字节中的两个比特，该删除的两个比特可以为第一个源码块中第一个字节中最高位的两个比特，也可以为第一个源码块中第一个字节中最低位的两个比特。最后生成258比特的待编码的码块。
需要说明的是，相对于前一实施例的转码方式，本申请实施例中的转码帧格式不需要对源码块进行切分，直接以整个130比特的源码块进行转码操作，可以为转码操作提供帧格式参考。
需要说明的是，本申请实施例中的以上转码方法可以作为独立方法来实施，例如，通过256B/258B转码方式进行转码得到258比特的码块，或者通过128B/132B转码方式进行转码得到132比特的码块。
S603，对所述待编码的码块进行扰码。
S604，对所述待编码的码块进行编码得到前向纠错码FEC。
具体实现中，可以首先对源码块进行转码得到待编码的码块，然后按照质因数分解方法进行FEC码字的设计，并对待编码的码块进行编码得到FEC码。其中，质因数分解方法可以参考上一实施例中图5所涉及的步骤，本步骤不再赘述。
需要说明的是，在基于128B/130B编码方式进行编码得到源码块之后，可以通过转码方式或非转码方式得到不同的待编码的码块，其中，本申请实施例优选的转码方式包括256B/258B转码方式或128B/132B转码方式。在对不同的待编码的码块进行编码之后，可 以得到不同的码字，本申请实施例优选的码字包括：当通过所述256B/258B转码方式对所述源码块进行转码得到待编码的码块时，通过编码得到的FEC码的码字包括：N＝192，K＝172，T＝10，M＝8；或N＝184，K＝172，T＝6，M＝8；或N＝96，K＝86，T＝5，M＝8。当通过所述128B/132B转码方式对所述源码块进行转码时，通过编码得到的FEC码的码字包括：N＝136，K＝132，T＝2，M＝8；或N＝144，K＝132，T＝6，M＝8；或N＝152，K＝132，T＝10，M＝8；或N＝72，K＝66，T＝3，M＝8。当待编码的码块为130比特的码块时，通过编码得到的FEC码的码字包括：N＝136，K＝130，T＝3，M＝8；或N＝144，K＝130，T＝7，M＝8；或N＝152，K＝130，T＝11，M＝8。可以理解的是，上述码字是示例性的，还可以编码得到其它码字，此处不做限定。
另外，对于长距离、损耗高、时延要求低的应用场景，可以优先选择RS(272，258，T＝7)或RS(544，514，T＝15)等长码。而对于短距离、损耗低、时延要求高的应用场景，可以优先选择RS(144，132，T＝6)、RS(144，130，T＝7)、RS(192，172，T＝10)或RS(72，66，T＝3)等短码。
S605，将所述FEC码分发到多条物理层链路上进行发送。
具体实现中，可以将FEC码以符号为单位依次分发到多条物理层链路中，每条链路依次分发一个符号，当所有物理层链路都分发一个符号后，重新开始新一轮分发。例如，对于x16链路，符号0分发到链路0中，符号1分发到链路1中，符号2分发到链路2中，依次类推，符号15分发到链路15中。此时所有物理层链路完成一次分发，然后开始新一轮FEC码分发，即符号16分发到链路0中，符号17分发到链路1中，依次类推。其中，每条物理层链路中分发的FEC码的符号总数为FEC码的码字总符号数与多条物理层链路的数量的比值。该方式应用于将一个FEC编码器输出单个FEC码字分发到不同的物理层链路的应用场景，为多链路传输场景提供数据分发方案。
例如，如图14所示，图14是本申请实施例提供的一种FEC码分发的示意图。对于RS(144，130，M＝8)，x16条物理层链路，FEC码的码字总符号数为144。按照x16物理层链路，每条物理层链路每次发送一个符号(M＝8比特)，16条链路每次发送16符号。此处以二维数组的形式对FEC码在多条物理层链路中的分发映射进行说明，该二维数组在实际系统中不存在。将FEC码按照每行16个符号的形式映射到二维数组中，生成一个9*16的二维数组。其中，二维数组的行数为FEC码的码字总符号数与多条物理层链路的条数的比值，即144/16＝9。然后将二维数组中的FEC码按照列分发到16条物理层链路中，二维数组共16列，每列对应一条物理层链路，进而完成FEC码映射到物理层链路中。对于x8物理层链路，可以将FEC映射到18*8的二维数组中，每行8个符号，然后将二维数组中的FEC码映射到8条物理层链路中。对于x4、x2、x1链路的映射关系可以按照相同规律进行类推。
例如，如图15所示，图15是本申请实施例提供的另一种FEC码分发的示意图。对于RS(192，172，M＝8)，x16条物理层链路。该FEC码共有192个符号，，可以将FEC映射到16条物理层链路上进行发送，192/16＝12，因此无需设计变速箱即可完成FEC码映射到16条物理层链路中。对于x8、x4、x2、x1物理层链路，映射规则可依次类推。
又如图16所示，图16是本申请实施例提供的又一种FEC码分发的示意图。对于 RS(192，172，M＝8)，其中，FEC码的有效信息长度为172*8＝1376比特。以256B/258B转码方式为例，在进行FEC编码时，需要从258比特的源码块中收集有效信息比特。由于
Figure PCTCN2019087728-appb-000001
因此需要收集
Figure PCTCN2019087728-appb-000002
个258比特的源码块组成RS(192，172，M＝8)编码所需的信息比特数，也就是收集
Figure PCTCN2019087728-appb-000003
个258比特的源码块进行编码到3个RS(192，172，M＝8)的FEC码字中，从而实现FEC码字与源码块的对齐。图16仅给出了3个RS(192，172，M＝8)码字中第一个FEC码字与物理层链路的映射关系。对于x8、x4、x2、x1物理层链路，映射规则可依次类推。
可选的，可以将多个FEC码以符号为单位交织处理并映射到变速箱中，其中，变速箱的列数为多条物理层链路的条数。然后将变速箱中的FEC码依次分发到不同的物理层链路中。该方式应用于将多个FEC编码器输出多个FEC码分发到不同的物理层链路的应用场景，为多链路传输场景提供数据分发方案。
在本申请实施例中，以二维数组的形式对多个FEC码在多条物理层链路的映射关系进行说明，该二维数组在实际系统中不存在。可以将FEC码映射到一个二维数组中，其中，二维数组的列数为多条物理层链路的条数与多个FEC码的数量的比值，二维数组的行数为FEC码的码字总符号数与二维数组的列数的比值；然后将多个二维数组中的FEC码进行交织处理并映射到变速箱中，变速箱的列数为多条物理层链路的条数，变速箱的行数为二维数组的行数；最后按照列将变速箱中的FEC码映射到多条物理层链路上进行发送。
例如，如图16所示，图16是本申请实施例提供的又一种FEC码分发的示意图。对于RS(72，66，M＝8)，x16物理层链路。首先将待编码的码块分发到两个FEC编码器中，经过两个FEC编码器进行编码得到的FEC码向下交织分发到16条物理层链路上。其中，FEC码的总长度为72个符号，每个FEC符号包含M个比特(此处M＝8)。按照x16物理层链路，每条物理层链路每次发送一个符号，16条物理层链路每次发送16个符号。由于72/16＝4.5非整数，因此单个FEC码无法完全映射到16条物理层链路中，在这种场景下，需要根据FEC码的总长度和物理层链路的数量的比值设计变速箱(Gearbox)。本申请实施例中，72/16＝4.5，小数部分为0.5(1/0.5＝2)，为了实现FEC码与传输链路的匹配，需要设计一个1:2的变速箱来对应两个FEC编码器。首先将两个FEC编码器中的数据按照每行8个符号(每行的符号数量为链路数量除以FEC编码器的数量)、共9行的方式映射到两个二维数组中，然后将这两个二维数组中的FEC码进行交织处理并映射到变速箱中，映射后的变速箱数组尺寸为9行16列。如RS(72，66，M＝8)Codec0中的第0行(行编号从0开始编号)和第1行的FEC映射到变速箱中的第0行中，而RS(72，66，M＝8)Codec1中的第0行和第1行的FEC映射到变速箱中的第1行中。最后按照列将变速箱中的FEC码分发到16条物理层链路中。
如图17所示，图17是本申请实施例提供的又一种FEC码分发的示意图，对于RS(72，66，M＝8)，x8物理层链路，由于72/8＝9为整数，单个FEC码可以完全映射到8条物理 层链路中，无需设计变速箱。对于x4、x2、x1物理层链路来说，可以利用相同的规则进行类推。
可选的，可以在对待编码的码块进行编码得到FEC码之后，在FEC码中添加多个比特的空比特。通过添加空比特，可以使FEC码中符号数量与物理层链路的数量相匹配，这样可以使得向多条物理层链路分发FEC码的过程中简化变速箱的设计，起到优化作用。
例如，对于RS(271，257，M＝10)，x4物理层链路，无法直接将该FEC码按照符号形式直接映射到4条物理层链路中。可以在271个FEC符号的基础上添加1个符号(1*10＝10比特)，添加后的FEC码的总长度N为272个FEC符号，从而在RS(271，257，M＝10)基础上通过添加空比特得到272个FEC符号，272/4＝68，因此可以直接映射x4链路中。
上述详细阐述了本申请实施例的方法，下面提供了本申请实施例的装置。
请参见图18，图18是本申请实施例提供的一种编码装置的结构示意图，该编码装置可以包括接收模块1801、编码模块1802、转码模块1803和分发模块1804，其中，各个模块的详细描述如下。
接收模块1801，用于接收长度为L的待编码的码块，其中，所述L为正整数；
编码模块1802，用于对所述待编码的码块进行编码得到前向纠错码FEC，其中，所述FEC码的有效信息长度K为所述L的最大质因数的整数倍，所述FEC码的总长度N为所述FEC码的纠错能力T的2倍与所述K之和。
其中，所述FEC码中每个符号所包含的比特数为M，所述M为满足(2 M-1)>＝N的最小偶数。
可选的，转码模块1803还用于对源码块进行转码得到所述待编码的码块。
可选的，转码模块1803，还用于在单个源码块上添加至少一个比特的同步头信息得到所述待编码的码块，所述同步头信息用于指示所述源码块的数据类型。
可选的，转码模块1803，还用于删除多个源码块中每个源码块的同步头数据得到剩余有效信息；将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块。
可选的，转码模块1803，还用于将所述每个源码块的所述剩余有效信息划分为两个子码块；将所述多个源码块的所述两个子码块中的第一个子码块组合生成所述待编码的码块的前部分，在所述待编码的码块的前部分的前面添加比特数据；将所述多个源码块的所述两个子码块中的第二个子码块组合生成所述待编码的码块的后部分。
可选的，转码模块1803，还用于当所述多个源码块全部为数据码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。
可选的，转码模块1803，还用于当所述多个源码块包含有控制码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；删除所述待编码的码块的前部分中第一个所述控制码块中第一个字节中的多个比特。
可选的，转码模块1803还用于删除多个源码块中每个源码块的同步头数据得到剩余 有效信息；将所述多个源码块中所述剩余有效信息组合生成一个长码块；在所述长码块的前面添加比特数据生成得到所述待编码的码块。
可选的，转码模块1803，还用于当所述多个源码块全部为数据码块时，在所述长码块的前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。
可选的，转码模块1803，还用于当所述多个源码块包含有控制码块时，在所述长码块的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；删除所述长码块中第一个所述控制码块中第一个字节中的多个比特。
可选的，编码模块1802，还用于基于128B/130B编码方式进行编码得到所述源码块。
可选的，转码模块1804，还用于通过256B/258B转码方式或128B/132B转码方式对所述源码块进行转码得到所述待编码的码块。
其中，当L＝258时，N＝192，K＝172，T＝10，M＝8；或N＝184，K＝172，T＝6，M＝8；或N＝96，K＝86，T＝5，M＝8。
其中，当L＝132时，N＝136，K＝132，T＝2，M＝8；或N＝144，K＝132，T＝6，M＝8；或N＝152，K＝132，T＝10，M＝8；或N＝72，K＝66，T＝3，M＝8。
其中，当L＝130时，N＝136，K＝130，T＝3，M＝8；或N＝144，K＝130，T＝7，M＝8；或N＝152，K＝130，T＝11，M＝8。
可选的，分发模块1804，还用于将所述FEC码分发到多条物理层链路上进行发送。
需要说明的是，各个模块的实现还可以对应参照图5和图6所示的方法实施例的相应描述，执行上述实施例中编码器、转码器和FEC编码器所执行的方法和功能。
请继续参考图19，图19是本申请提出的一种编码设备的结构示意图。如图19所示，该编码设备可以包括：至少一个处理器1901，至少一个通信接口1902，至少一个存储器1903和至少一个通信总线1904。
其中，处理器1901可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。通信总线1904可以是外设部件互连标准PCI总线或扩展工业标准结构EISA总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图19中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。通信总线1904用于实现这些组件之间的连接通信。其中，本申请实施例中设备的通信接口1902用于与其他节点设备进行信令或数据的通信。存储器1903可以包括易失性存储器，例如非挥发性动态随机存取内存(Nonvolatile Random Access Memory，NVRAM)、相变化随机存取内存(Phase Change RAM，PRAM)、磁阻式随机存取内存(Magetoresistive RAM，MRAM)等，还可以包括非易失性存储器，例如至少一个磁盘存储器件、电子可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only Memory， EEPROM)、闪存器件，例如反或闪存(NOR flash memory)或是反及闪存(NAND flash memory)、半导体器件，例如固态硬盘(Solid State Disk，SSD)等。存储器1903可选的还可以是至少一个位于远离前述处理器1901的存储装置。存储器1903中可选的还可以存储一组程序代码，且处理器1901可选的还可以执行存储器1903中所执行的程序。
接收长度为L的待编码的码块，其中，所述L为正整数；
对所述待编码的码块进行编码得到前向纠错码FEC，其中，所述FEC码的有效信息长度K为所述L的最大质因数的整数倍，所述FEC码的总长度N为所述FEC码的纠错能力T的2倍与所述K之和。
其中，所述FEC码中每个符号所包含的比特数M，所述M为满足(2 M-1)>＝N的最小偶数。
可选的，处理器1901还用于执行如下操作：
对源码块进行转码得到所述待编码的码块。
可选的，处理器1901还用于执行如下操作：
在单个源码块上添加至少一个比特的同步头信息得到所述待编码的码块，所述同步头信息用于指示所述源码块的数据类型。
可选的，处理器1901还用于执行如下操作：
删除多个源码块中每个源码块的同步头数据得到剩余有效信息；
将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块。
可选的，处理器1901还用于执行如下操作：
将所述每个源码块的所述剩余有效信息划分为两个子码块；
将所述多个源码块的所述两个子码块中的第一个子码块组合生成所述待编码的码块的前部分，在所述待编码的码块的前部分的前面添加比特数据；
将所述多个源码块的所述两个子码块中的第二个子码块组合生成所述待编码的码块的后部分。
可选的，处理器1901还用于执行如下操作：
当所述多个源码块全部为数据码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。
可选的，处理器1901还用于执行如下操作：
当所述多个源码块包含有控制码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；
删除所述待编码的码块的前部分中第一个所述控制码块中第一个字节中的多个比特。
可选的，处理器1901还用于执行如下操作：
删除多个源码块中每个源码块的同步头数据得到剩余有效信息；
将所述多个源码块中所述剩余有效信息组合生成一个长码块；
在所述长码块的前面添加比特数据生成得到所述待编码的码块。
可选的，处理器1901还用于执行如下操作：
当所述多个源码块全部为数据码块时，在所述长码块的前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。
可选的，处理器1901还用于执行如下操作：
当所述多个源码块包含有控制码块时，在所述长码块的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；
删除所述长码块中第一个所述控制码块中第一个字节中的多个比特。
可选的，处理器1901还用于执行如下操作：
基于128B/130B编码方式进行编码得到所述源码块。
可选的，处理器1901还用于执行如下操作：
通过256B/258B转码方式或128B/132B转码方式对所述源码块进行转码得到所述待编码的码块。
其中，当L＝258时，N＝192，K＝172，T＝10，M＝8；或N＝184，K＝172，T＝6，M＝8；或N＝96，K＝86，T＝5，M＝8。
其中，当L＝132时，N＝136，K＝132，T＝2，M＝8；或N＝144，K＝132，T＝6，M＝8；或N＝152，K＝132，T＝10，M＝8；或N＝72，K＝66，T＝3，M＝8。
其中，当L＝130时，N＝136，K＝130，T＝3，M＝8；或N＝144，K＝130，T＝7，M＝8；或N＝152，K＝130，T＝11，M＝8。
可选的，处理器1901还用于执行如下操作：
将所述FEC码分发到多条物理层链路上进行发送。
进一步的，处理器还可以与存储器和通信接口相配合，执行上述申请实施例中上述实施例中编码器、转码器和FEC编码器的操作。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (29)

  1. 一种编码方法，其特征在于，所述方法包括：
    接收长度为L的待编码的码块，其中，所述L为正整数；
    对所述待编码的码块进行编码得到前向纠错码FEC，其中，所述FEC码的有效信息长度K为所述L的最大质因数的整数倍，所述FEC码的总长度N为所述FEC码的纠错能力T的2倍与所述K之和。
  2. 如权利要求1所述的方法，其特征在于，所述FEC码中每个符号所包含的比特数为M，其中，所述M为满足(2 M-1)>＝N的最小偶数。
  3. 如权利要求1或2所述的方法，其特征在于，所述对所述待编码的码块进行编码得到前向纠错码FEC码之前，还包括：
    对源码块进行转码得到所述待编码的码块。
  4. 如权利要求3所述的方法，其特征在于，所述对源码块进行转码得到所述待编码的码块包括：
    删除多个源码块中每个源码块的同步头数据得到剩余有效信息；
    将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块。
  5. 如权利要求4所述的方法，其特征在于，所述将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块包括：
    将所述每个源码块的所述剩余有效信息划分为两个子码块；
    将所述多个源码块的所述两个子码块中的第一个子码块组合生成所述待编码的码块的前部分，在所述待编码的码块的前部分的前面添加比特数据；
    将所述多个源码块的所述两个子码块中的第二个子码块组合生成所述待编码的码块的后部分。
  6. 如权利要求5所述的方法，其特征在于，所述在所述待编码的码块的前部分的前面添加比特数据包括：
    当所述多个源码块全部为数据码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。
  7. 如权利要求5所述的方法，其特征在于，所述在所述待编码的码块的前部分的前面添加比特数据包括：
    当所述多个源码块包含有控制码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用 于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；
    删除所述待编码的码块的前部分中第一个所述控制码块中第一个字节中的多个比特。
  8. 如权利要求3-7任一项所述的方法，其特征在于，所述对源码块进行转码得到所述待编码的码块之前，还包括：
    基于128B/130B编码方式进行编码得到所述源码块。
  9. 如权利要求3-8任一项所述的方法，其特征在于，所述对源码块进行转码得到所述待编码的码块包括：
    通过256B/258B转码方式或128B/132B转码方式对所述源码块进行转码得到所述待编码的码块。
  10. 如权利要求1-9任一项所述的方法，其特征在于，当L＝258时，N＝192，K＝172，T＝10，M＝8；或N＝184，K＝172，T＝6，M＝8；或N＝96，K＝86，T＝5，M＝8。
  11. 如权利要求1-9任一项所述的方法，其特征在于，当L＝132时，N＝136，K＝132，T＝2，M＝8；或N＝144，K＝132，T＝6，M＝8；或N＝152，K＝132，T＝10，M＝8；或N＝72，K＝66，T＝3，M＝8。
  12. 如权利要求1-9任一项所述的方法，其特征在于，当L＝130时，N＝136，K＝130，T＝3，M＝8；或N＝144，K＝130，T＝7，M＝8；或N＝152，K＝130，T＝11，M＝8。
  13. 如权利要求1-12任一项所述的方法，其特征在于，所述对所述待编码的码块进行编码得到前向纠错码FEC码之后，还包括：
    将所述FEC码分发到多条物理层链路上进行发送。
  14. 一种编码装置，其特征在于，所述装置包括：
    接收模块，用于接收长度为L的待编码的码块，其中，所述L为正整数；
    编码模块，用于对所述待编码的码块进行编码得到前向纠错码FEC，其中，所述FEC码的有效信息长度K为所述L的最大质因数的整数倍，所述FEC码的总长度N为所述FEC码的纠错能力T的2倍与所述K之和，所述FEC码中每个符号所包含的比特数M由所述N确定。
  15. 如权利要求14所述的装置，其特征在于，所述FEC码中每个符号所包含的比特数为M，其中，所述M为满足(2 M-1)>＝N的最小偶数。
  16. 如权利要求14或15所述的装置，其特征在于，所述装置还包括：
    转码模块，用于对源码块进行转码得到所述待编码的码块。
  17. 如权利要求16所述的装置，其特征在于，
    所述转码模块，还用于删除多个源码块中每个源码块的同步头数据得到剩余有效信息；将所述多个源码块中的所述剩余有效信息组合生成所述待编码的码块。
  18. 如权利要求17所述的装置，其特征在于，
    所述转码模块，还用于删除多个源码块中每个源码块的同步头数据得到剩余有效信息；将所述每个源码块的所述剩余有效信息划分为两个子码块；将所述多个源码块的所述两个子码块中的第一个子码块组合生成所述待编码的码块的前部分，在所述待编码的码块的前部分的前面添加比特数据；将所述多个源码块的所述两个子码块中的第二个子码块组合生成所述待编码的码块的后部分。
  19. 如权利要求18所述的装置，其特征在于，
    所述转码模块，还用于当所述多个源码块全部为数据码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，所述同步头信息用于指示所述多个源码块全部为数据码块。
  20. 如权利要求18所述的装置，其特征在于，
    所述转码模块，还用于当所述多个源码块包含有控制码块时，在所述待编码的码块的前部分的前面添加至少一个比特的同步头信息，并在所述同步头信息后添加多个比特的热码，所述同步头信息用于指示所述多个源码块包含有所述控制码块，所述热码用于指示所述每个源码块的数据类型；删除所述待编码的码块的前部分中第一个所述控制码块中第一个字节中的多个比特。
  21. 如权利要求16-20任一项所述的装置，其特征在于，
    所述编码模块，还用于基于128B/130B编码方式进行编码得到所述源码块。
  22. 如权利要求16-21任一项所述的装置，其特征在于，
    所述转码模块，还用于通过256B/258B转码方式或128B/132B转码方式对所述源码块进行转码得到所述待编码的码块。
  23. 如权利要求14-22任一项所述的装置，其特征在于，当L＝258时，N＝192，K＝172，T＝10，M＝8；或N＝184，K＝172，T＝6，M＝8；或N＝96，K＝86，T＝5，M＝8。
  24. 如权利要求14-22任一项所述的装置，其特征在于，当L＝132时，N＝136，K＝132，T＝2，M＝8；或N＝144，K＝132，T＝6，M＝8；或N＝152，K＝132，T＝10，M＝8；或N＝72，K＝66，T＝3，M＝8。
  25. 如权利要求14-22任一项所述的装置，其特征在于，当L＝130时，N＝136，K＝130，T＝3，M＝8；或N＝144，K＝130，T＝7，M＝8；或N＝152，K＝130，T＝11，M＝8。
  26. 如权利要求14-25任一项所述的装置，其特征在于，所述装置还包括：
    分发模块，用于将所述FEC码分发到多条物理层链路上进行发送。
  27. 一种编码设备，其特征在于，包括：存储器、通信总线以及处理器，其中，所述存储器用于存储程序代码，所述处理器用于调用所述程序代码，用于执行权利要求1-13任一项所述的方法。
  28. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行权利要求1-13任一项所述的方法。
  29. 一种包含指令的计算机程序产品，其特征在于，当其在计算机上运行时，使得计算机执行权利要求1-13任一项所述的方法。
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