WO2019223187A1 - 数据存储方法及存储设备 - Google Patents

数据存储方法及存储设备 Download PDF

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Publication number
WO2019223187A1
WO2019223187A1 PCT/CN2018/105304 CN2018105304W WO2019223187A1 WO 2019223187 A1 WO2019223187 A1 WO 2019223187A1 CN 2018105304 W CN2018105304 W CN 2018105304W WO 2019223187 A1 WO2019223187 A1 WO 2019223187A1
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Prior art keywords
data
storage medium
cache unit
write command
storage
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PCT/CN2018/105304
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English (en)
French (fr)
Inventor
唐江
梁小庆
李志雄
邓恩华
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中山市江波龙电子有限公司
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Publication of WO2019223187A1 publication Critical patent/WO2019223187A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks

Definitions

  • the present application belongs to the field of data storage technology, and particularly relates to a data storage method and a storage device.
  • the existing data storage methods are mainly as follows:
  • the host computer sends a write command to the storage device.
  • the write command includes the logical address and data length of the pre-stored data.
  • the storage device After receiving the command, the storage device prepares a data buffer space in a dynamic random access memory (Dynamic Random Access Memory, DRAM);
  • DRAM Dynamic Random Access Memory
  • the storage device sends a data receiving request to the host, requesting the host to transmit data.
  • the host transmits and stores data to the cache space of the storage device.
  • the master After all the data is stored in the cache space, the master writes the data in the cache space to flash. After the flash completes writing, it returns the write completion status to the master of the storage device, and the master of the storage device releases the cache space.
  • the DRAM of the storage device acts as a high-speed data cache. There are two steps of writing and reading to the DRAM. In this process, whether it is Write or Read, the DRAM's The actual efficiency is only 50%, so the actual efficiency of the storage device on Write or Read is too low.
  • the embodiments of the present application provide a data storage method and a storage device to solve the problem that the actual efficiency of the storage device on Write or Read is too low in the prior art.
  • a first aspect of the embodiments of the present application provides a data storage method.
  • the data storage method is used for a storage device.
  • the storage device includes a main controller, a storage medium, and several data transmission channels.
  • the main controller includes A central processing unit CPU, a storage medium controller, and several cache units.
  • the data storage method includes a data writing process, and specifically includes:
  • S106 Apply for a first buffer unit for each data channel to be transmitted, send a data reception request to the host computer, start data transmission from the host computer to the first buffer unit, and transfer the data block in the host computer to the first Cache unit
  • a second aspect of the embodiments of the present application provides a storage device.
  • the storage device includes a main controller, a storage medium, and several data transmission channels.
  • the main controller includes a central processing unit CPU, a storage medium controller, and several Cache units,
  • the CPU is used to receive a write command sent by a host computer, and is used to determine whether the write command contains a logical address of data to be stored, and if the write command contains a logical address of data to be stored, analyze the write command, Convert the write command into a storage medium write command, submit the storage medium write command to the storage medium controller, and update and store a new mapping relationship table at the same time, if the write command does not contain the logic of the data to be stored Address, if it is determined that the write command is a storage medium write command, the storage medium write command is submitted to the storage medium controller;
  • the storage medium controller is configured to cut the data to be executed in each write command of the storage medium into several data blocks, and the data length of the data blocks is less than or equal to the size of the cache unit;
  • the data channel for data transmission applies for the first cache unit, sends a data reception request to the upper computer, initiates data transmission from the upper computer to the first cache unit, and transmits the data block in the upper computer to the first cache unit; and After the writing of the data in the first cache unit is completed, start the data writing process from the first cache unit to the storage medium, and simultaneously apply for a second cache unit for each data channel for data transmission, and start from the upper computer to the second Data transmission of the cache unit; when the data of the first cache unit is completely written into the storage medium, the first cache unit is released, and the cycle is repeated until all data block transmissions are completed.
  • the storage device of this application includes several cache units, and after receiving a storage medium write command, the data to be executed in each of the storage medium write commands is cut into several data blocks, and the data of the data blocks is guaranteed at the same time.
  • the length is less than or equal to the size of the cache unit. Therefore, the data to be executed in the write command of the storage medium can be transmitted to the cache unit in blocks, and the data is released from the cache unit to the storage medium, and then the cache unit is released.
  • Improve the utilization of the cache unit which greatly improves the continuous read and write performance of the storage device.
  • FIG. 1 is a flowchart of a first data storage method according to an embodiment of the present application
  • FIG. 2 is a flowchart of a second data storage method according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a third data storage method according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a storage device according to an embodiment of the present application.
  • FIG. 1 shows a flowchart of a first data storage method according to an embodiment of the present application.
  • the data storage method is used for a storage device.
  • the storage device includes a main controller, a storage medium, and several data transmission channels.
  • the data transmission channel is a channel for data transmission between the main controller and the storage medium;
  • the main controller includes a central processing unit (CPU), a storage medium controller, and a plurality of cache units, and the data storage
  • the method includes a data writing process, including:
  • Step S101 Receive a write command sent by a host computer
  • a write command is sent to the storage device, and the main controller of the corresponding storage device receives the write command sent by the upper computer.
  • step S102 it is determined whether the write command contains a logical address of data to be stored. If yes, step S103 is performed; if not, it is determined that the write command is a storage medium write command, then step S104 is performed.
  • the host computer when the user needs to store data from the host computer into the storage device, the host computer sends a data write request to the storage device, that is, sends a write command, and the main controller of the corresponding storage device receives the write command sent by the host computer.
  • step S103 If the write command sent by the host computer contains the logical address of the data to be stored, the write command needs to be parsed and converted into a physical address recognizable by the storage medium, that is, step S103 is performed.
  • the write command sent by the host computer is a storage medium write command
  • the write command includes the physical address of the storage medium, indicating that the host computer has previously parsed the write command into a write command that can be recognized by the storage medium, and writes a command for each storage medium.
  • the physical address is assigned.
  • the main controller only needs to execute the write command according to the physical address of the write command, and write the data corresponding to the write command to the corresponding physical address. There is no need to parse the command, that is, Go to step S104.
  • Step S103 Parse the write command, convert the write command into a storage medium write command, and update and store a new mapping relationship table.
  • the write command is analyzed to obtain a logical address and a data length of the write command, and a physical storage space of a storage medium is allocated according to the data length, and the logical address of the write command and the storage allocated by the write command are allocated.
  • the physical addresses in the space correspond one-to-one, forming a new mapping relationship, updating and storing a new mapping relationship table, and forming at least one storage medium write command according to the allocated physical address.
  • the data length refers to the length or size of the data contained in the write command that needs to be written.
  • the storage medium write command refers to a command that can be recognized by the storage medium.
  • the storage medium write command includes a physical address to which data corresponding to the write command is to be written.
  • Step S104 Submit the storage medium write command to the storage medium controller.
  • the main controller submits at least one storage medium write command to the storage medium controller sequentially or simultaneously, so that the storage medium controller performs the next operation according to the storage medium write command.
  • the storage medium controller is a flash controller.
  • step S105 the data to be executed in each write command of the storage medium is cut into several data blocks, and the data length of the data blocks is less than or equal to the size of the cache unit.
  • the plurality of cache units are obtained by cutting the internal memory.
  • the data storage method of the present invention further includes: cutting the internal memory to form a plurality of cache units.
  • the internal memory refers to a random access memory (RAM) which is integrated with the CPU and the storage medium controller in the main controller.
  • the internal memory may be a Static Random Access Memory (SRAM).
  • the sizes of the cut buffer units may be the same or different. It should be noted that in this application, the same internal memory may be cut once and cut multiple times. When the cut once is adopted, it may be cut before the storage device writes the data for the first time, and then written again later. It will not be cut before entering new data. When the method of cutting multiple times is adopted, the cutting can be performed before the data is written to the storage device for the first time.
  • the internal memory is re-cut based on the average length of data written in a period of time.
  • the number of the cache units is at least twice that of a data transmission channel of the storage device.
  • each data transmission channel can be guaranteed to correspond to at least two cache units.
  • step S105 the storage medium controller cuts the data to be executed into several data blocks smaller than or equal to the size of the cache unit according to the size of the cache unit.
  • the step S105 is specifically: the storage medium controller cuts the data to be executed in the write command of the storage medium according to the size of any cache unit of the storage device.
  • the step S105 is specifically: the storage medium controller determines the size of the cache unit to be used for storing data, and according to the cache to be used for storing data The size of the unit cuts the data to be executed in the storage medium write command. For example, assuming that the storage device will use three cache units A, B, and C to cache data this time, the storage device first determines the sizes of the three cache units respectively, and then according to the order of the sizes of the three cache units. Data to be executed in the storage medium write command are sequentially cut.
  • Step S106 Apply for a first buffer unit for each data channel to be transmitted, send a data reception request to the host computer, start data transmission from the host computer to the first buffer unit, and transfer the data block in the host computer to the first A cache unit.
  • a first buffer unit is applied for each data channel to be transmitted, and a data receiving request is sent to the upper computer. After receiving the data receiving request, the upper computer starts data transmission and transfers data of one data block from the upper computer. Machine to the first buffer unit.
  • the storage device has multiple data transmission channels, and each data transmission channel has its corresponding storage medium. Only when the storage medium corresponding to the data channel needs data transmission, the data transmission of the data channel is started. Data read and write channels do not work. For example: if the storage device has 4 data transmission channels (such as CH0, CH1, CH2, CH3); when the write command only needs to use the storage medium of 2 data transmission channels (such as CH0, CH1), only Start the data transmission of the two data channels CH0 and CH1. At this time, you only need to apply for a buffer unit for each data transmission channel.
  • the storage device may have multiple data channels. After receiving the storage medium write command, some data channels need to transmit data, and some data channels are left empty. At this time, in order to avoid unnecessary waste, the storage medium is controlled.
  • the processor only applies a cache unit to the internal memory for each data channel that needs to perform data transmission.
  • the cache unit applied for each data channel to be used for data transmission is a different cache unit.
  • step S106 may also apply to the internal memory for two or more cache units for each data channel that needs to perform data transmission, which is not repeated here.
  • step S107 after the data writing of the first buffer unit is completed, the data writing process from the first buffer unit to the storage medium is started, and at the same time, a second buffer unit is applied for each data channel for data transmission, and a slave computer is started. Data transmission to the second buffer unit. After the data of the first cache unit is completely written into the storage medium, the first cache unit is released, and the cycle is repeated until all data blocks are transmitted.
  • the data storage method of the present application includes setting a plurality of cache units in a storage device, and cutting data to be written into a storage medium into a plurality of data blocks. After receiving the data of the corresponding data block in the first cache unit, the slave device starts The process of writing data from the cache unit to the storage medium, while applying for a second cache unit, and concurrently cache the data of the new data block to the second cache unit. When the data of the first cache unit is completely written into the storage medium, the first cache unit The cache unit is released, and this loop is repeated until all data block transfers are completed.
  • the method of the present application links the data cache and write processes, and the two steps are performed concurrently, which greatly improves the storage device data access speed.
  • FIG. 2 shows a flowchart of a second data storage method provided by an embodiment of the present application.
  • the storage device further includes an external memory, which is detailed as follows:
  • Steps S101 to S107 in this embodiment of the present application are the same, and details are not described herein again.
  • Step S108 While transmitting the data block in the upper computer to the first buffer unit, the data block in the upper computer is transmitted to the external memory for backup.
  • the external memory refers to the RAM selected by the user and connected to the reserved drive interface of the main controller.
  • the external memory may be a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • the internal memory is SRAM
  • the external memory is DRAM
  • the storage medium is flash
  • the method may further include step S109, as shown in FIG. 2:
  • step S109 after the data of the first cache unit is completely written into the storage medium, the data backed up by the external memory is released, and the data ordered by the next storage medium is backed up.
  • FIG. 3 shows a flowchart of a third data storage method provided by an embodiment of the present application.
  • the data reading process in the data storage method is mainly described, as follows:
  • step S301 a read command sent by a host computer is received.
  • the upper computer when the upper computer needs to read the data in the storage device, it sends a read command to the storage device, and the main controller of the corresponding storage device receives the read command sent by the upper computer.
  • step S302 it is determined whether the read command includes a logical address for storing data. If so, step 303 is performed; otherwise, it is determined that the read command is a storage medium read command, and step 304 is performed.
  • Step S303 Look up the mapping relationship table, and convert the read command into a storage medium read command.
  • step S304 After converting to a storage medium read command, step S304 is performed.
  • Step S304 Submit the storage medium read command to the storage medium controller.
  • the storage medium controller is a flash controller.
  • step S305 the data to be executed in each of the storage medium read commands is cut into several data blocks, and the data length of the data blocks is less than or equal to the size of the cache unit.
  • Step S306 Apply for a third cache unit for each data channel to be transmitted, send a data reception request to the storage medium controller, start data transmission from the storage medium to the third cache unit, and transfer data blocks in the storage medium. To the third buffer unit.
  • step S307 after the writing of the data in the third buffer unit is completed, the data transmission process from the third buffer unit to the upper computer is started. At the same time, a fourth buffer unit is applied for each data channel for data transmission, and the storage medium to Data transmission of the fourth buffer unit. After the data of the third buffer unit is completely transmitted to the host computer, the third buffer unit is released, and the cycle is repeated until all data reading is completed.
  • first cache unit and the second cache unit of the first embodiment have been released during the process of reading data
  • third cache unit and the fourth cache unit applied in this embodiment of the present application may also be The first buffer unit and the second buffer unit in the first embodiment are not repeated here.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 4 shows a first storage device provided by an embodiment of the present application.
  • the storage device includes a main controller 41, a storage medium 42, and a plurality of data transmission channels.
  • the data transmission channel is one of the main controller and the storage medium.
  • the main controller 41 includes a central processing unit CPU 411, a storage medium controller 412, and a plurality of cache units 413.
  • the CPU 411 is used to receive a write command sent by a host computer, and is used to determine whether the write command includes a logical address of data to be stored. If the write command includes a logical address of data to be stored, the write command is parsed. , Converting the write command into a storage medium write command, submitting the storage medium write command to the storage medium controller, and updating and storing a new mapping relationship table, if the write command does not include data to be stored, A logical address, determining that the write command is a storage medium write command, and submitting the storage medium write command to the storage medium controller 412;
  • the write command sent by the upper computer contains a logical address of the data to be stored
  • the write command needs to be parsed, converted into a physical address that can be recognized by the storage medium, and the storage medium write command is submitted to
  • the storage medium controller if the write command sent by the host computer is a storage medium write command, the write command includes the physical address of the storage medium, indicating that the host computer has previously parsed the write command into a write command recognizable by the storage medium.
  • the main controller only needs to execute the write command according to the physical address of the write command, and write the data corresponding to the write command to the corresponding physical address, and there is no need to parse the command.
  • the CPU may choose to send the more than one command to the storage medium controller at the same time or one by one according to the processing capacity of the storage medium controller 412 412.
  • the storage medium controller 412 is configured to cut the data to be executed in each of the storage medium write commands into several data blocks, and the data length of the data blocks is less than or equal to the size of the cache unit 413;
  • Each data channel to be used for data transmission applies for a first cache unit, sends a data reception request to the upper computer, initiates data transmission from the upper computer to the first cache unit, and transmits the data block in the upper computer to the first cache unit; And after the data writing of the first cache unit is completed, the data writing process from the first cache unit to the storage medium is started, and at the same time, a second cache unit is applied for each data channel for data transmission, and the slave computer is started. Data transmission to the second cache unit; after the data of the first cache unit is completely written into the storage medium, the first cache unit is released, and this cycle is repeated until all data block transfers are completed.
  • the plurality of cache units are obtained by cutting the internal memory. Specifically, the internal memory is cut to form a plurality of cache units.
  • the sizes of the cut buffer units may be the same or different. It should be noted that, in the present application, the same internal memory may be cut once and cut multiple times.
  • the number of the cache units is at least twice that of a data transmission channel of the storage device.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the storage device in this embodiment of the present application includes a main controller 41, a storage medium 42, and several data transmission channels in the fourth embodiment.
  • the main controller 41 includes a central processing unit CPU 411, a storage medium controller 412, and a plurality of cache units 413.
  • the CPU 411 is further configured to receive an upper machine-readable command; and if the read command includes a logical address for storing data, search a mapping relationship table and convert the read command into a storage medium read command Submit the storage medium read command to the storage medium controller; and for submitting the storage medium read command to the storage medium controller 412 if the read command is a storage medium read command;
  • the storage medium controller 412 is further configured to cut the data to be executed in each of the storage medium read commands into several data blocks, and the data length of the data blocks is less than or equal to the size of the cache unit;
  • Each data channel for which data is to be transmitted applies for a third cache unit, sends a data reception request to the storage medium controller, initiates data transmission from the storage medium to the third cache unit, and transfers data blocks in the storage medium to the third cache
  • start the data transmission process from the third buffer unit to the upper computer and at the same time apply for a fourth buffer unit for each data channel for data transmission, and start the slave storage.
  • the CPU 411 is further configured to transmit data in the upper computer to an external memory for backup while transmitting data blocks in the upper computer to the first buffer unit.
  • the external memory may be a DRAM.
  • the CPU 411 is further configured to release the data backed up by the external memory after the data of the first cache unit is completely written into the storage medium, and The data of the storage medium command is backed up.
  • the storage device of the present application since the storage device of the present application includes several cache units, and after receiving a storage medium write command, the data to be executed in each of the storage medium write commands is cut into several data blocks, and at the same time, it is guaranteed
  • the data length of the data block is less than or equal to the size of the cache unit. Therefore, the data to be executed in the storage medium write command can be transmitted to the cache unit in blocks and released after the data is written from the cache unit to the storage medium.
  • the cache unit can improve the utilization rate of the cache unit, thereby greatly improving the continuous reading and writing performance of the storage device.
  • the disclosed apparatus / terminal device and method may be implemented in other ways.
  • the device / terminal device embodiments described above are only schematic.
  • the division of the modules or units is only a logical function division.
  • components can be combined or integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the integrated module / unit When the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the method of the above embodiment, and can also be completed by a computer program instructing related hardware.
  • the computer program can be stored in a computer-readable storage medium.
  • the computer When the program is executed by a processor, the steps of the foregoing method embodiments can be implemented.
  • the computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file, or some intermediate form.
  • the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, Random Access Memory), electric carrier signals, telecommunication signals, and software distribution media.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • electric carrier signals telecommunication signals
  • software distribution media any entity or device capable of carrying the computer program code
  • a recording medium a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, Random Access Memory), electric carrier signals, telecommunication signals, and software distribution media.

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Abstract

一种数据存储方法及存储设备，所述方法包括：接收写命令；若接收的写命令包含待存储数据的逻辑地址，对接收的写命令进行解析，并转换成存储介质写命令；将每个存储介质写命令中待执行数据切割成若干个数据块；向上位机发送数据接收请求，将上位机中的数据传输至预先申请的第一缓存单元；待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输；当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。通过上述方法能够提高存储设备的读写性能。

Description

数据存储方法及存储设备 【技术领域】
本申请属于数据存储技术领域，尤其涉及数据存储方法及存储设备。
【背景技术】
目前，人们通常通过存储设备(如移动硬盘、U盘、计算机存储器)存储数据。
现有的数据存储方法主要如下：
S1，上位机(host)发送写命令至存储设备，写命令中包括预存储数据的逻辑地址、数据长度等；
S2，存储设备接收到命令后，在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中准备数据缓存空间；
S3，存储设备向host发送数据接收请求，请求host传输数据。
S4，host将数据传输并存储至存储设备的缓存空间。
S5，数据全部存储至缓存空间后，主控将缓存空间中的数据写入flash，flash完成写入后反馈写完成状态给存储设备的主控，存储设备的主控再释放缓存空间。
由于在逻辑读写过程中，存储设备的DRAM作为高速数据缓存(Data Cache)，存在对DRAM进行写(Write)、读(Read)两步操作，此过程中，无论是Write还是Read，DRAM的实际效率都只有50％，因此导致存储设备在Write或Read上的实际效率过低。
【发明内容】
有鉴于此，本申请实施例提供了数据存储方法及存储设备，以解决现有技术中存储设备在Write或Read上的实际效率过低的问题。
本申请实施例的第一方面提供了一种数据存储方法，所述数据存储方法用于存储设备，所述存储设备包括主控制器、存储介质及若干个数据传输通道，所述主控制器包括中央处理器CPU、存储介质控制器及若 干个缓存单元，所述数据存储方法包括数据写入过程，具体包括：
S101，接收上位机发送的写命令；
S102，判断所述写命令是否包含待存储数据的逻辑地址，若是，执行S103，若否，判定所述写命令为存储介质写命令，则执行S104；
S103，对所述写命令进行解析，将所述写命令转换成存储介质写命令，同时更新并存储新的映射关系表；
S104，将所述存储介质写命令提交至所述存储介质控制器；
S105，将每个所述存储介质写命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小；
S106，对每个待进行数据传输的数据通道申请第一缓存单元，向上位机发送数据接收请求，启动从上位机至第一缓存单元的数据传输，将上位机中的数据块传输至第一缓存单元；
S107，待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输；当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。
本申请实施例的第二方面提供了一种存储设备，所述存储设备包括主控制器、存储介质及若干个数据传输通道，所述主控制器包括中央处理器CPU、存储介质控制器及若干个缓存单元，
所述CPU用于接收上位机发送的写命令，用于判断所述写命令是否包含待存储数据的逻辑地址，若所述写命令包含待存储数据的逻辑地址，对所述写命令进行解析，将所述写命令转换成存储介质写命令，将所述存储介质写命令提交至所述存储介质控制器，同时更新并存储新的映射关系表，若所述写命令没有包含待存储数据的逻辑地址，判定所述写命令为存储介质写命令，则将所述存储介质写命令提交至所述存储介质控制器；
所述存储介质控制器用于将每个所述存储介质写命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单 元的大小；用于对每个待进行数据传输的数据通道申请第一缓存单元，向上位机发送数据接收请求，启动从上位机至第一缓存单元的数据传输，将上位机中的数据块传输至第一缓存单元；以及用于待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输；当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。
本申请实施例与现有技术相比存在的有益效果是：
由于本申请的存储设备包括若干个缓存单元，且在接收到存储介质写命令后，将每个所述存储介质写命令中待执行数据切割成若干个数据块，同时保证所述数据块的数据长度小于或等于所述缓存单元的大小，因此，可将存储介质写命令中待执行数据分块传输至缓存单元，并在将数据从缓存单元写入存储介质后，释放缓存单元，这样，能够提高缓存单元的利用率，从而极大提高了存储设备的持续读写性能。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的第一种数据存储方法的流程图；
图2是本申请实施例提供的第二种数据存储方法的流程图；
图3是本申请实施例提供的第三种数据存储方法的流程图；
图4是本申请实施例提供的存储设备的结构示意图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申 请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
为了说明本申请所述的技术方案，下面通过具体实施例来进行说明。
实施例一：
图1示出了本申请实施例提供的第一种数据存储方法的流程图，所述数据存储方法用于存储设备，所述存储设备包括主控制器、存储介质及若干个数据传输通道，所述数据传输通道为主控制器和存储介质之间进行数据传输的通道；所述主控制器包括中央处理器(Central Processing Unit，CPU)、存储介质控制器及若干个缓存单元，所述数据存储方法包括数据写入过程，具体包括：
步骤S101，接收上位机发送的写命令；
具体地，当上位机需要对存储设备进行数据写入时，向存储设备发送写命令，相应的存储设备的主控制器接收上位机发送的写命令。
步骤S102，判断所述写命令是否包含待存储数据的逻辑地址，若是，执行S103，若否，判定所述写命令为存储介质写命令，则执行S104。
该步骤中，当用户需要将数据从上位机存入存储设备时，上位机会向存储设备发送数据写入请求，即发送写命令，相应的存储设备的主控制器接收上位机发送的写命令。
若上位机发送的写命令包含待存储数据的逻辑地址，则需要对写命令进行解析，将其转换成存储介质可识别的物理地址，即执行步骤S103。
若上位机发送的写命令为存储介质写命令，所述写命令包含存储介质的物理地址，表明上位机已经事先将写命令解析成存储介质可识别的写命令，并为每条存储介质写命令分配好物理地址，此时，主控制器只需要根据写命令的物理地址，执行该写命令，将该写命令对应的数据写入相应的物理地址即可，无需再对该命令进行解析，即执行步骤S104。
步骤S103，对所述写命令进行解析，将所述写命令转换成存储介质写命令，同时更新并存储新的映射关系表。
具体地：对所述写命令进行解析，获取所述写命令的逻辑地址及数 据长度，并根据该数据长度分配存储介质的物理存储空间，将该写命令的逻辑地址和该写命令分配的存储空间的物理地址一一对应，形成新的映射关系，更新并存储新的映射关系表，同时根据分配的物理地址形成至少一个存储介质写命令。数据长度指的是该写命令所包含的需要进行写入的数据的长度或者大小。存储介质写命令指的是存储介质可以识别的命令，该存储介质写命令包括该写命令对应的数据即将写入的物理地址。
步骤S104，将所述存储介质写命令提交至所述存储介质控制器。
具体地，主控制器将至少一个存储介质写命令依次或者同时提交给存储介质控制器，以便存储介质控制器根据该存储介质写命令执行下一步的操作。
该步骤中，若存储介质为flash，则存储介质控制器为flash控制器。
步骤S105，将每个所述存储介质写命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小。
可选地，所述若干个缓存单元由内存储器切割得到，此时，本发明的数据存储方法还包括：将内存储器进行切割，形成若干个缓存单元。
其中，内存储器是指与CPU、存储介质控制器一体封装在主控制器内部的随机存取存储器(random access memory，RAM)。可选地，该内存储器可为静态随机存取存储器(Static Random-Access Memory，SRAM)。
可选地，切割的缓存单元的大小可以相同，也可以不同。需要指出的是，在本申请中，对同一个内存储器可采取切割一次和切割多次的方式，当采取切割一次的方式时，可在存储设备首次写入数据之前切割，且在后续再写入新的数据之前也不再切割。当采用切割多次的方式时，可在存储设备首次写入数据之前切割，在后续写入多次数据后，若判断出写入的数据长度基本相同，且不是单个缓存单元的大小的倍数(针对存储设备的各个缓存单元的大小都相同的情况)，则为了提高缓存单元的利用率，根据一段时间内写入的数据的平均长度对内存储器重新切割。
可选地，所述缓存单元的数量至少为所述存储设备的数据传输通道的两倍。这样，能够保证每个数据传输通道至少对应两个缓存单元，当需要同时读写数据时，可以通过数据传输通道将数据写入一个缓存单元，再读取另一个缓存单元的数据写入存储介质，从而极大提高了存储设备的持续读写性能。
可选地，该步骤S105中，存储介质控制器根据缓存单元的大小，将待执行数据切割成若干个小于或等于缓存单元大小的数据块。在所述存储设备的各个缓存单元大小都相同时，所述步骤S105具体为：所述存储介质控制器根据所述存储设备的任一个缓存单元大小切割所述存储介质写命令中待执行数据。
在所述存储设备的各个缓存单元大小不都相同时，所述步骤S105具体为：所述存储介质控制器确定将用于存储数据的缓存单元的大小，根据所述将用于存储数据的缓存单元的大小切割所述存储介质写命令中待执行的数据。例如，假设存储设备本次将采用A、B、C这三个缓存单元缓存数据，则该存储设备首先分别确定该三个缓存单元的大小，再分别根据该三个缓存单元的大小的先后顺序依次切割所述存储介质写命令中待执行的数据。
步骤S106，对每个待进行数据传输的数据通道申请第一缓存单元，向上位机发送数据接收请求，启动从上位机至第一缓存单元的数据传输，将上位机中的数据块传输至第一缓存单元。
具体地，对每个待进行数据传输的数据通道申请第一缓存单元，并向上位机发送数据接收请求，上位机接收到该数据接收请求后，启动数据传输，将一个数据块的数据从上位机传输至第一缓存单元。
存储设备具有多个数据传输通道，每个数据传输通道都有其对应的存储介质，只有该数据通道对应的存储介质需要进行数据传输时，才会启动该数据通道的数据传输，对于不需要进行数据读写的通道，则不进行工作。例如：若存储设备有4个数据传输通道(例如CH0，CH1，CH2，CH3)；当该次写命令只需要用到其中2个数据传输通道(例如CH0，CH1)的存储介质时，则只启动CH0，CH1两个数据通道的数据传输， 这时，只需要对每个数据传输通道申请一个缓存单元即可。
具体地，存储设备可能有多个数据通道，而在接收到存储介质写命令后，存在有些数据通道需要传输数据，有些数据通道则空置，此时，为了避免不必要的浪费，则存储介质控制器只对每个需要进行数据传输的数据通道向内存储器申请一个缓存单元，当然，每个待进行数据传输的数据通道申请的缓存单元为不同的缓存单元。可选地，该步骤S106也可为每个需要进行数据传输的数据通道向内存储器申请2个或更多的缓存单元，此处不再赘述。
步骤S107，待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输。当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。
本申请的数据存储方法通过在存储设备中设置若干个缓存单元，并将需要写入存储介质的数据切割成若干个数据块，在第一缓存单元接收完对应的数据块的数据后，启动从缓存单元到存储介质的数据写入过程，同时申请第二缓存单元，并行将新的数据块的数据缓存至第二缓存单元，当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。本申请的方法将数据的缓存和写入过程联动起来，两个步骤并发进行，大大提高了存储设备数据的存取速度。
实施例二：
图2示出了本申请实施例提供的第二种数据存储方法的流程图，在本申请实施例中，存储设备还包括外存储器，详述如下：
本申请实施例的步骤S101～步骤S107的相同，此处不再赘述。
步骤S108，在将上位机中的数据块传输至第一缓存单元的同时，将上位机中的数据块传输至外存储器备份。
其中，外存储器是指由用户自行选配，并与主控制器的预留驱动接口连接的RAM。可选地，该外存储器可为动态随机存取存储器(Dynamic  Random Access Memory，DRAM)。例如，假设内存储器为SRAM，外存储器为DRAM，存储介质为flash，则当通过SRAM的缓存单元对flash进行数据写入出错时(例如，写入的flash是坏块，或者是不稳定块时)，可以调用DRAM中的数据进行备份，重新将该数据写入新的flash块中，从而避免数据丢失。
进一步地，为了避免数据冗余，提高外存储器的利用率，该方法还可以包括步骤S109，具体如图2所示：
步骤S109，当第一缓存单元的数据完全写入存储介质后，释放该外存储器备份的数据，并对下一条存储介质命令的数据进行备份。
实施例三：
图3示出了本申请实施例提供的第三种数据存储方法的流程图，在本申请实施例中，主要描述了数据存储方法中的数据读取过程，详述如下：
步骤S301，接收上位机发送的读命令。
具体地，当上位机需要读取存储设备中的数据时，向存储设备发送读命令，相应的存储设备的主控制器接收上位机发送的读命令。
步骤S302，判断所述读命令是否包括存储数据的逻辑地址，若是，执行步骤303，否则，判定所述读命令为存储介质读命令，执行步骤304。
步骤S303，查找映射关系表，将所述读命令转换为存储介质读命令。
在转换为存储介质读命令之后，执行步骤S304。
步骤S304，将所述存储介质读命令提交至所述存储介质控制器。
在存储介质为flash时，该存储介质控制器为flash控制器。
步骤S305，将每个所述存储介质读命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小。
步骤S306，对每个待进行数据传输的数据通道申请第三缓存单元，向存储介质控制器发送数据接收请求，启动从存储介质至第三缓存单元的数据传输，将存储介质中的数据块传输至第三缓存单元。
步骤S307，待第三缓存单元的数据写入完成后，启动从第三缓存单元至上位机的数据传输过程，同时对每个进行数据传输的数据通道申请 第四缓存单元，启动从存储介质至第四缓存单元的数据传输。当第三缓存单元的数据完全传输至上位机后，将第三缓存单元释放，如此循环，直至完成所有数据读取。
当然，若第三缓存单元将数据传输至上位机后，所有数据读取完成，则无需申请第四缓存单元。
需要指出的是，若在读取数据的过程中，实施例一的第一缓存单元、第二缓存单元已经被释放，则本申请实施例申请的第三缓存单元、第四缓存单元也可能为实施例一的第一缓存单元、第二缓存单元，此处不再赘述。
实施例四：
图4示出了本申请实施例提供的第一种存储设备，所述存储设备包括主控制器41、存储介质42及若干个数据传输通道，所述数据传输通道为主控制器和存储介质之间进行数据传输的通道，所述主控制器41包括中央处理器CPU411、存储介质控制器412及若干个缓存单元413。
所述CPU 411用于接收上位机发送的写命令，用于判断所述写命令是否包含待存储数据的逻辑地址，若所述写命令包含待存储数据的逻辑地址，对所述写命令进行解析，将所述写命令转换成存储介质写命令，将所述存储介质写命令提交至所述存储介质控制器，同时更新并存储新的映射关系表，若所述写命令没有包含待存储数据的逻辑地址，判定所述写命令为存储介质写命令，则将所述存储介质写命令提交至所述存储介质控制器412；
具体地，CPU 411若上位机发送的写命令包含待存储数据的逻辑地址，则需要对写命令进行解析，将其转换成存储介质可识别的物理地址，以及将所述存储介质写命令提交至所述存储介质控制器，若上位机发送的写命令为存储介质写命令，所述写命令包含存储介质的物理地址，表明上位机已经事先将写命令解析成存储介质可识别的写命令，此时，主控制器只需要根据写命令的物理地址，执行该写命令，将该写命令对应的数据写入相应的物理地址即可，无需再对该命令进行解析。
若CPU 411转换写命令得到的存储介质写命令的数量为1条以上， 则CPU可根据存储介质控制器412的处理能力，选择同时或选择逐条将该1条以上命令发送至该存储介质控制器412。
所述存储介质控制器412用于将每个所述存储介质写命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元413的大小；用于对每个待进行数据传输的数据通道申请第一缓存单元，向上位机发送数据接收请求，启动从上位机至第一缓存单元的数据传输，将上位机中的数据块传输至第一缓存单元；以及用于待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输；当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。
本申请实施例中，由于将数据的缓存和写入过程联动起来，两个步骤并发进行，因此大大提高了存储设备数据的存取速度。
可选地，所述若干个缓存单元由内存储器切割得到，具体地，将内存储器进行切割，形成若干个缓存单元。
可选地，切割的缓存单元的大小可以相同，也可以不同。需要指出的是，在本申请中，对同一个内存储器可采取切割一次和切割多次的方式。
可选地，所述缓存单元的数量至少为所述存储设备的数据传输通道的两倍。
实施例五：
本申请实施例的存储设备包括实施例四的主控制器41、存储介质42及若干个数据传输通道。其中，所述主控制器41包括中央处理器CPU411、存储介质控制器412及若干个缓存单元413。
在本申请实施例中，所述CPU411还用于接收上位机读命令；用于若所述读命令包括存储数据的逻辑地址，则查找映射关系表，将所述读命令转换为存储介质读命令，将所述存储介质读命令提交至所述存储介质控制器；以及用于若所述读命令为存储介质读命令，将所述存储介质读命令提交至所述存储介质控制器412；
所述存储介质控制器412还用于将每个所述存储介质读命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小；用于对每个待进行数据传输的数据通道申请第三缓存单元，向存储介质控制器发送数据接收请求，启动从存储介质至第三缓存单元的数据传输，将存储介质中的数据块传输至第三缓存单元；以及用于待第三缓存单元的数据写入完成后，启动从第三缓存单元至上位机的数据传输过程，同时对每个进行数据传输的数据通道申请第四缓存单元，启动从存储介质至第四缓存单元的数据传输；当第三缓存单元的数据完全传输至上位机后，将第三缓存单元释放，如此循环，直至完成所有数据读取。
可选地，为避免数据丢失，所述CPU411还用于在将上位机中的数据块传输至第一缓存单元的同时，将上位机中的数据传输至外存储器备份。
可选地，该外存储器可为DRAM。
可选地，为了避免数据冗余，提高外存储器的利用率，所述CPU411还用于当第一缓存单元的数据完全写入存储介质后，释放所述外存储器备份的数据，并对下一条存储介质命令的数据进行备份。
本申请实施例中，由于本申请的存储设备包括若干个缓存单元，且在接收到存储介质写命令后，将每个所述存储介质写命令中待执行数据切割成若干个数据块，同时保证所述数据块的数据长度小于或等于所述缓存单元的大小，因此，可将存储介质写命令中待执行数据分块传输至缓存单元，并在将数据从缓存单元写入存储介质后，释放缓存单元，这样，能够提高缓存单元的利用率，从而极大提高了存储设备的持续读写性能。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根 据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的装置/终端设备和方法，可以通过其它的方式实现。例如，以上所描述的装置/终端设备实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的模块/单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括电载波信号和电信信号。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种数据存储方法，所述数据存储方法用于存储设备，所述存储设备包括主控制器、存储介质及若干个数据传输通道，其特征在于，所述主控制器包括中央处理器CPU、存储介质控制器及若干个缓存单元，所述数据存储方法包括数据写入过程，具体包括：
    S101，接收上位机发送的写命令；
    S102，判断所述写命令是否包含待存储数据的逻辑地址，若是，执行S103，若否，判定所述写命令为存储介质写命令，则执行S104；
    S103，对所述写命令进行解析，将所述写命令转换成存储介质写命令，同时更新并存储新的映射关系表；
    S104，将所述存储介质写命令提交至所述存储介质控制器；
    S105，将每个所述存储介质写命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小；
    S106，对每个待进行数据传输的数据通道申请第一缓存单元，向上位机发送数据接收请求，启动从上位机至第一缓存单元的数据传输，将上位机中的数据块传输至第一缓存单元；
    S107，待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输；当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。
  2. 根据权利要求1所述的数据存储方法，其特征在于，则所述方法还包括数据读取过程，具体包括：
    S301，接收上位机发送的读命令；
    S302，判断所述读命令是否包括存储数据的逻辑地址，若是，执行步骤303，否则，判定所述读命令为存储介质读命令，执行步骤304；
    S303，查找映射关系表，将所述读命令转换为存储介质读命令；
    S304，将所述存储介质读命令提交至所述存储介质控制器；
    S305，将每个所述存储介质读命令中待执行数据的数据长度切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小；
    S306，对每个待进行数据传输的数据通道申请第三缓存单元，向存储介质控制器发送数据接收请求，启动从存储介质至第三缓存单元的数据传输，将存储介质中的数据块传输至第三缓存单元；
    S307，待第三缓存单元的数据写入完成后，启动从第三缓存单元至上位机的数据传输过程，同时对每个进行数据传输的数据通道申请第四缓存单元，启动从存储介质至第四缓存单元的数据传输；当第三缓存单元的数据完全传输至上位机后，将第三缓存单元释放，如此循环，直至完成所有数据读取。
  3. 根据权利要求1所述的数据存储方法，其特征在于，所述对所述写命令进行解析，将所述写命令转换成存储介质写命令，同时更新并存储新的映射关系表，具体包括：
    对所述写命令进行解析，获取所述写命令的逻辑地址及数据长度，并根据数据长度分配存储介质的物理存储空间，同时更新并存储新的映射关系表。
  4. 根据权利要求1所述的数据存储方法，其特征在于，所述若干个缓存单元由内存储器切割得到，则所述数据存储方法还包括：将所述内存储器进行切割，形成若干个缓存单元。
  5. 根据权利要求1至4任一项所述的数据存储方法，其特征在于，所述存储设备还包括外存储器，所述数据存储方法还包括：
    在将所述上位机中的数据传输至所述第一缓存单元的同时，将所述上位机中的数据传输至外存储器备份。
  6. 根据权利要求5所述的数据存储方法，其特征在于，在所述当第一缓存单元的数据完全写入存储介质后，包括：
    释放所述外存储器备份的数据，并对下一条存储介质命令的数据进行备份。
  7. 一种存储设备，所述存储设备包括主控制器、存储介质及若干个 数据传输通道，其特征在于，所述主控制器包括中央处理器CPU、存储介质控制器及若干个缓存单元，
    所述CPU用于接收上位机发送的写命令，用于判断所述写命令是否包含待存储数据的逻辑地址，若所述写命令包含待存储数据的逻辑地址，对所述写命令进行解析，将所述写命令转换成存储介质写命令，将所述存储介质写命令提交至所述存储介质控制器，同时更新并存储新的映射关系表，若所述写命令没有包含待存储数据的逻辑地址，判定所述写命令为存储介质写命令，则将所述存储介质写命令提交至所述存储介质控制器；
    所述存储介质控制器用于将每个所述存储介质写命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小；用于对每个待进行数据传输的数据通道申请第一缓存单元，向上位机发送数据接收请求，启动从上位机至第一缓存单元的数据传输，将上位机中的数据块传输至第一缓存单元；以及用于待第一缓存单元的数据写入完成后，启动从第一缓存单元至存储介质的数据写入过程，同时对每个进行数据传输的数据通道申请第二缓存单元，启动从上位机至第二缓存单元的数据传输；当第一缓存单元的数据完全写入存储介质后，将第一缓存单元释放，如此循环，直至完成所有数据块传输。
  8. 如权利要求7所述的存储设备，其特征在于，所述存储设备还包括：
    所述CPU还用于接收上位机发送的读命令；用于判断所述读命令是否包括存储数据的逻辑地址，若所述读命令包括存储数据的逻辑地址，则查找映射关系表，将所述读命令转换为存储介质读命令，将所述存储介质读命令提交至所述存储介质控制器；若没有包括存储数据的逻辑地址，判定所述读命令为存储介质读命令，将所述存储介质读命令提交至所述存储介质控制器；
    所述存储介质控制器还用于将每个所述存储介质读命令中待执行数据切割成若干个数据块，所述数据块的数据长度小于或等于所述缓存单元的大小；用于对每个待进行数据传输的数据通道申请第三缓存单 元，向存储介质控制器发送数据接收请求，启动从存储介质至第三缓存单元的数据传输，将存储介质中的数据块传输至第三缓存单元；以及用于待第三缓存单元的数据写入完成后，启动从第三缓存单元至上位机的数据传输过程，同时对每个进行数据传输的数据通道申请第四缓存单元，启动从存储介质至第四缓存单元的数据传输；当第三缓存单元的数据完全传输至上位机后，将第三缓存单元释放，如此循环，直至完成所有数据读取。
  9. 如权利要求7或8任一项所述的存储设备，其特征在于，所述CPU还用于将上位机中的数据传输至外存储器备份。
  10. 根据权利要求9所述的存储设备，其特征在于，所述CPU还用于释放所述外存储器备份的数据。
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