WO2019220868A1 - Discharge device - Google Patents

Discharge device Download PDF

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Publication number
WO2019220868A1
WO2019220868A1 PCT/JP2019/016932 JP2019016932W WO2019220868A1 WO 2019220868 A1 WO2019220868 A1 WO 2019220868A1 JP 2019016932 W JP2019016932 W JP 2019016932W WO 2019220868 A1 WO2019220868 A1 WO 2019220868A1
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Prior art keywords
switch
pulse
discharge
circuit unit
series
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PCT/JP2019/016932
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French (fr)
Japanese (ja)
Inventor
正樹 金▲崎▼
宜久 山口
江 偉華
太一 須貝
Original Assignee
株式会社デンソー
国立大学法人長岡技術科学大学
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Publication of WO2019220868A1 publication Critical patent/WO2019220868A1/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback

Definitions

  • the present disclosure relates to a discharge device.
  • a pulse generator that supplies a pulse voltage to a load using a Marx circuit has been proposed.
  • This pulse generator charges a plurality of capacitors from a power supply in a state where a plurality of capacitors in a Marx circuit are connected in parallel. Thereby, a lot of charges can be charged at a low voltage. And when supplying the charge charged in the Marx circuit to the load, a plurality of capacitors are connected in series connection. Thereby, a high voltage can be supplied to the load.
  • This disclosure intends to provide a discharge device with excellent energy efficiency.
  • One aspect of the present disclosure includes a first discharge electrode and a second discharge electrode, and a dielectric layer disposed on an inner surface of at least one of the first discharge electrode and the second discharge electrode.
  • Pulse discharge load A discharge device having a pulse power power supply circuit unit that periodically outputs a pulse voltage to the pulse discharge load,
  • the pulse power power supply circuit unit has an energy storage unit capable of storing electrical energy,
  • the pulse power power supply circuit unit is in a discharge device configured to reversibly move electrical energy between the energy storage unit and the pulse discharge load.
  • the pulse power power supply circuit unit is configured to reversibly move electrical energy between the energy storage unit and the pulse discharge load. As a result, even when electric charges remain in the dielectric layer after the pulse discharge load performs discharge, the electric energy generated by the electric charges can be recovered and stored in the energy storage unit of the pulse power power supply circuit unit. it can.
  • the electric energy stored in the energy storage unit can be supplied to the pulse discharge load. Therefore, the electrical energy repeatedly supplied to the pulse discharge load can be saved. As a result, a discharge device with excellent energy efficiency can be obtained.
  • the discharge device excellent in energy efficiency can be provided.
  • FIG. 1 is a circuit diagram of a discharge device in Embodiment 1.
  • FIG. 2 is an explanatory diagram of a pulse discharge load in the first embodiment.
  • FIG. 3 is a circuit diagram of the discharge device in a series state according to the first embodiment.
  • FIG. 4 is a circuit diagram of the discharge device in the parallel state according to the first embodiment.
  • FIG. 5 is a diagram showing temporal changes in the interelectrode voltage and current of the pulse discharge load in Embodiment 1.
  • FIG. 6 is a circuit diagram of a discharge device according to the second embodiment.
  • FIG. 7 is a circuit diagram of a discharge device in a parallel state according to the second embodiment.
  • FIG. 8 is a circuit diagram of the discharge device in a state where both electrodes of the pulse discharge load are short-circuited in the second embodiment.
  • FIG. 9 is a circuit diagram of the discharge device in the series state according to the second embodiment.
  • FIG. 10 is a circuit diagram of the discharge device in a series state according to the third embodiment.
  • FIG. 11 is a circuit diagram of a discharge device in a parallel state according to the third embodiment.
  • FIG. 12 is a circuit diagram of the discharge device in the series state after the parallel state in the third embodiment,
  • FIG. 13 is a circuit diagram of the discharge device in a series state in the fourth embodiment.
  • FIG. 14 is a circuit diagram of a discharge device in a parallel state according to the fourth embodiment.
  • FIG. 15 is a circuit diagram of a discharge device in a parallel state according to the fourth embodiment, and shows a state in which charge is collected to a capacitor.
  • FIG. 16 is a circuit diagram of a discharge device in a series state according to the fifth embodiment.
  • FIG. 17 is a circuit diagram of the discharge device in the parallel state in the fifth embodiment.
  • FIG. 18 is a circuit diagram of a discharge device in a parallel state according to the fifth embodiment, and shows a state in which charge is collected to a capacitor.
  • FIG. 19 is a circuit diagram of a discharge device in Embodiment 6.
  • FIG. 20 is a circuit diagram of the discharge device in a series state according to the sixth embodiment.
  • FIG. 21 is a circuit diagram of a discharge device in a parallel state according to the sixth embodiment.
  • the discharge device 1 of this embodiment includes a pulse discharge load 2 and a pulse power power supply circuit unit 3.
  • the pulse discharge load 2 includes a first discharge electrode 211, a second discharge electrode 212, and a dielectric layer 22.
  • the dielectric layer 22 is disposed on the inner surface of at least one of the first discharge electrode 211 and the second discharge electrode 212. In this embodiment, the dielectric layer 22 is disposed on the inner side surfaces of both the first discharge electrode 211 and the second discharge electrode 212.
  • the pulse power power supply circuit unit 3 periodically outputs a pulse voltage to the pulse discharge load 2. As shown in FIG. 1, the pulse power power supply circuit unit 3 includes an energy storage unit 31 that can store electrical energy. The pulse power power supply circuit unit 3 is configured to reversibly move electrical energy between the energy storage unit 31 and the pulse discharge load 2.
  • the pulse power power supply circuit unit 3 includes a plurality of capacitors Cm and a plurality of switches SW.
  • the pulse power power supply circuit unit 3 is configured to be able to switch between a serial state and a parallel state by switching on and off the plurality of switches SW.
  • the series state is a state in which a plurality of capacitors Cm are connected in series as shown in FIG.
  • the parallel state is a state in which a plurality of capacitors Cm are connected in parallel as shown in FIG.
  • the pulse power power supply circuit unit 3 forms a Marx circuit. As shown in FIG. 3, a pulse voltage is output to the pulse discharge load 2 in a series state. As shown in FIG. 4, electrical energy is recovered from the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2 to the energy storage unit 31 in a parallel state.
  • a broken line arrow Ip in FIG. 3 and a broken line arrow Ic in FIG. 4 indicate current flows. These current flows Ip and Ic are also positive charge flows. The same applies to broken line arrows Ip and Ic in other figures.
  • the energy storage unit 31 is configured by a plurality of capacitors Cm. That is, electric charge is accumulated in each of the plurality of capacitors Cm, and electric energy is accumulated.
  • the pulse power power supply circuit section 3 includes a plurality of stages of circuit units 4 (4A, 4B, 4Z), a DC power supply 5, and a series switch unit 6.
  • the DC power source 5 has a positive electrode connected to the first stage circuit unit 4A.
  • the series switch unit 6 is connected between the circuit unit 4Z at the final stage and the negative electrode of the DC power supply 5.
  • the pulse power power supply circuit unit 3 includes a first switch SW1 and a second switch SW2 belonging to the circuit unit 4 and a third switch SW3 belonging to the series switch unit 6 as a plurality of switches SW.
  • the circuit unit 4 includes a switch series body 41 and a capacitor Cm.
  • the switch series body 41 is formed by connecting a first switch SW1 and a second switch SW2 in series at an intermediate connection point 41M.
  • the capacitor Cm is connected in parallel to the switch series body 41.
  • the circuit unit 4 includes a first connection part 421 and a second connection part 422 as a connection part between the switch series body 41 and the capacitor Cm.
  • the series switch unit 6 is formed by connecting a plurality of third switches SW3 in series.
  • the first connection part 421 of the circuit unit 4Z at the final stage is connected to the first discharge electrode 211 of the pulse discharge load 2.
  • the negative electrode of the DC power supply 5 and one end of the series switch unit 6 are connected to each other and to the second discharge electrode 212 of the pulse discharge load 2.
  • the positive electrode of the DC power supply 5 is connected to the intermediate connection point 41M of the first-stage circuit unit 4A.
  • the first connection portion 421 of the (k ⁇ 1) -th stage circuit unit 4 is connected to the intermediate connection point 41M of the k-th stage circuit unit 4.
  • k is a natural number of 2 or more.
  • the number of stages of the circuit unit 4 included in the pulse power power supply circuit unit 3 is N.
  • k is a natural number of 2 to N.
  • N is a natural number of 2 or more.
  • the third switch SW3 in the series switch unit 6 is interposed. ing.
  • the third switch SW3 in the series switch unit 6 is also interposed between the second connection portion 422 of the first-stage circuit unit 4A and the negative electrode of the DC power supply 5.
  • the pulse power power supply circuit unit 3 includes three circuit units 4. Therefore, in the present embodiment, the N is 3 and the k is 2 or 3.
  • the pulse power power supply circuit unit 3 includes, as a plurality of circuit units 4, from the side close to the DC power supply 5, a first stage circuit unit 4A, a second stage circuit unit 4B, and a third stage circuit unit 4Z. And have.
  • the third-stage circuit unit 4Z becomes the final-stage circuit unit 4Z.
  • the number of stages of the circuit unit 4 is not particularly limited as long as it is a plurality of stages.
  • the series switch unit 6 has three third switches SW3 connected in series with each other. One end of the series switch unit 6 is connected to the second connection part 422 of the circuit unit 4 ⁇ / b> Z at the final stage, and the other end is connected to the negative electrode of the DC power supply 5. Further, one third switch SW3 is interposed between the second connection portion 422 of the k-th stage circuit unit 4 and the second connection portion 422 of the (k ⁇ 1) -th stage circuit unit 4. ing. One third switch SW3 is also interposed between the second connection part 422 of the first-stage circuit unit 4A and the negative electrode of the DC power supply 5.
  • a diode is connected in parallel to each switch SW.
  • the diode connected in parallel to the first switch SW1 is connected in the direction in which the intermediate connection point 41M side becomes the anode.
  • the diode connected in parallel to the second switch SW2 is connected in such a direction that the intermediate connection point 41M side becomes the cathode.
  • the diode connected in parallel to the third switch SW3 is connected in such a direction that the side close to the negative electrode of the DC power supply 5 becomes the anode.
  • the switch SW is made of a power semiconductor element. Then, the switch SW composed of these power semiconductor elements can be appropriately turned on and off by a signal from the drive circuit.
  • the switch SW for example, IGBT (abbreviation of insulated gate bipolar transistor), MOSFET (abbreviation of MOS field effect transistor) or the like can be used.
  • IGBT abbreviation of insulated gate bipolar transistor
  • MOSFET abbreviation of MOS field effect transistor
  • a power semiconductor element what was formed with silicon carbide (SiC) and what was formed with silicon (Si) can be used, for example.
  • the first switch SW1 and the third switch SW3 are turned off (that is, opened) and the second switch SW2 is turned on (that is, short-circuited), thereby forming a series state.
  • the parallel state is formed by turning on the first switch SW1 and the third switch SW3 and turning off the second switch SW2.
  • All the first switches SW1 and all the third switches SW3 can be configured to be turned on / off in synchronization by the same signal from the drive circuit. Further, all the second switches SW2 can be configured to be turned on / off in synchronization by the same signal from the drive circuit. However, the second switch SW2 is turned on / off by a drive signal different from the drive signals of the first switch SW1 and the third switch SW3. More specifically, the second switch SW2 is turned off when the first switch SW1 and the third switch SW3 are on.
  • the pulse power power supply circuit unit 3 is switched to the series state shown in FIG. That is, a plurality of capacitors Cm in which electric charges are accumulated are connected in series, and a series circuit of these capacitors Cm is also connected in series with the DC power source 5. As a result, a voltage of Vin ⁇ (N + 1) is applied to the pulse discharge load 2.
  • the pulse power power supply circuit unit 3 is switched to the parallel state as shown in FIG. Then, the plurality of capacitors Cm connected in parallel to each other are connected to the pulse discharge load 2 and also connected to the DC power supply 5 in parallel. Thereby, a current flows from the pulse discharge load 2 to the pulse power power supply circuit unit 3 until the voltage between the electrodes in the pulse discharge load 2 decreases to the power supply voltage Vin. That is, charges are extracted from the capacitance component C2 of the dielectric layer 22 of the pulse discharge load 2, and the charges are recovered by the capacitors Cm of the Marx circuit.
  • the electric energy remaining in the pulse discharge load 2 is recovered and stored in the energy storage unit 31 of the pulse power power supply circuit unit 3. At the same time, the voltage between the electrodes of the pulse discharge load 2 is reduced.
  • the collected electrical energy is used for the next discharge in the discharge device 1.
  • a voltage is output from the pulse power power supply circuit unit 3 to the pulse discharge load 2. That is, similarly to the above, as shown in FIG. 3, the pulse power power supply circuit unit 3 is put in series. As a result, a voltage of Vin ⁇ (N + 1) is applied to the pulse discharge load 2.
  • the pulse discharge load 2 has a structure that generates a dielectric barrier discharge. As shown in FIG. 2, the pulse discharge load 2 includes a first discharge electrode 211 and a second discharge electrode 212 that are arranged to face each other. The dielectric layers 22 are provided on the inner surface of the first discharge electrode 211 and the inner surface of the second discharge electrode 212, respectively. A discharge gap 23 is formed between the pair of dielectric layers 22. By generating a discharge in the discharge gap 23, for example, plasma can be generated. Further, for example, ozone can be generated by generating plasma in the discharge gap 23 while supplying a gas containing oxygen to the discharge gap 23.
  • the pulse power power supply circuit unit 3 is configured to reversibly move electrical energy between the energy storage unit 31 and the pulse discharge load 2. Thereby, even after the pulse discharge load 2 performs the discharge, even when the electric charge remains in the dielectric layer 22, the electric energy due to this electric charge is recovered in the energy storage unit 31 of the pulse power power supply circuit unit 3, Can be accumulated.
  • the electrical energy stored in the energy storage unit 31 can be supplied to the pulse discharge load 2 at the time of the next discharge after the discharge in the pulse discharge load 2. Therefore, the electrical energy repeatedly supplied to the pulse discharge load 2 can be saved. As a result, the discharge device 1 excellent in energy efficiency can be obtained.
  • the pulse power power supply circuit unit 3 includes a plurality of capacitors Cm and a plurality of switches SW. By switching on / off of the plurality of switches SW, the serial state and the parallel state can be switched. The pulse voltage is output to the pulse discharge load 2 in the series state, and the electric energy is recovered from the capacitance component C2 of the dielectric layer 22 of the pulse discharge load 2 to the energy storage unit 31 in the parallel state. That is, the pulse power power supply circuit unit 3 forms a Marx circuit, and by repeatedly switching between the serial state and the parallel state, the pulse voltage output to the pulse discharge load 2 and the pulse discharge load 2 The recovery of electrical energy can be repeated alternately. Therefore, it is possible to efficiently output the pulse voltage and recover the electric energy.
  • the pulse power power supply circuit unit 3 includes a multi-stage circuit unit 4 and a series switch unit 6, and forms a Marx circuit as shown in FIG. Thereby, the series state and the parallel state can be realized easily and efficiently by appropriately turning on and off the plurality of switches SW. As a result, the discharge device 1 excellent in energy efficiency can be easily obtained.
  • FIG. 5 is a diagram showing temporal changes in the current in the pulse discharge load 2 and the interelectrode voltage (that is, the output voltage from the pulse power power supply circuit unit 3 to the pulse discharge load 2).
  • the output current from the pulse power supply circuit unit 3 to the first discharge electrode 211 of the pulse discharge load 2 is positive (that is, above the current 0 in the graph), and the flow in the opposite direction is negative (that is, the graph). The current is lower than 0).
  • a large amount of charges can be extracted from the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2 in a short time. Therefore, for example, when the discharge device 1 is applied to an ozonizer, the period during which ions existing between the discharge electrodes move to the electrodes can be shortened, so that heat generation of ions can be suppressed, and radical generation in the discharge gap 23 The rate can be improved.
  • the present embodiment is a discharge device 1 in which an attached switch series body 43 is connected in parallel to the circuit unit 4Z at the final stage.
  • the pulse power power supply circuit unit 3 in the discharge device 1 of the present embodiment further includes a fourth switch SW4 and a fifth switch SW5 connected in series as the switch SW.
  • the attached switch series body 43 is connected in parallel to the switch series body 41 and the capacitor Cm.
  • the attached switch series body 43 is a series body of the fourth switch SW4 and the fifth switch SW5.
  • connection point 43M between the fourth switch SW4 and the fifth switch SW5 in the attached switch series body 43 is connected to the first discharge electrode 211 of the pulse discharge load 2.
  • each switch SW is controlled as shown in FIG. That is, the first switch SW1, the third switch SW3, and the fourth switch SW4 are turned on, and the second switch SW2 and the fifth switch SW5 are turned off to form a parallel state. Thereby, the voltage between the electrodes of the pulse discharge load 2 decreases.
  • each switch SW is controlled as shown in FIG. That is, the fourth switch SW4 is switched off and the fifth switch SW5 is switched on. The other switches SW are not switched. As a result, the first discharge electrode 211 and the second discharge electrode 212 of the pulse discharge load 2 are short-circuited.
  • the pulse power power supply circuit unit 3 is switched to the serial state, and the fourth switch SW4 is turned on and the fifth switch SW5 is turned off in the attached switch series body 43. Switch. As a result, a high voltage of Vin ⁇ (N + 1) is applied from the pulse power power supply circuit unit 3 to the pulse discharge load 2, and discharge can be generated again.
  • the charge remaining in the capacitive component C2 of the pulse discharge load 2 can be extracted even after recovery to the energy storage unit 31, and the voltage between the electrodes of the pulse discharge load 2 can be reduced to substantially zero. That is, before the next discharge, the voltage between the electrodes of the pulse discharge load 2 can be sufficiently reduced, and the voltage difference from the output voltage of the pulse power power supply circuit unit 3 can be increased. As a result, it becomes easier to cause discharge in the pulse discharge load 2. In addition, the same effects as those of the first embodiment are obtained.
  • the pulse power power supply circuit unit 3 has an inductive component L connected in series with the pulse discharge load 2.
  • the inductive component L is configured to resonate with the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2.
  • the induction component L constitutes at least a part of the energy storage unit 31.
  • the capacitor Cm in each circuit unit 4 also constitutes a part of the energy storage unit 31.
  • the inductive component L may be provided with an inductor as a component, or may be a parasitic inductance that is parasitic on wiring or other components.
  • the pulse power power supply circuit unit 3 transfers electric energy from the energy storage unit 31 to the pulse discharge load 2 and transfers electric energy from the pulse discharge load 2 to the energy storage unit 31 (that is, the inductive component L and the capacitor Cm). Is executed during the resonance period of the inductive component L and the capacitive component C2.
  • the pulse power power supply circuit unit 3 is switched between the series state and the parallel state at a frequency close to the resonance frequency of the series resonance circuit.
  • the switching frequency is a frequency when the interval of the switching timing from the serial state to the parallel state or the interval of the switching timing from the parallel state to the serial state is one cycle.
  • the switching frequency f1 is set to, for example, 0.8 ⁇ f0 ⁇ f1 ⁇ 1.2 ⁇ f0 with respect to the resonance frequency f0.
  • Cm represents the value of the capacitance of the capacitor Cm.
  • the capacitance may be the same or different among the plurality of capacitors Cm.
  • the capacitance Cm is required to be a level that can hold a sufficient amount of charge with respect to the discharge charge in the pulse discharge load 2.
  • the state is switched from the state where charges are accumulated in each part to the serial state again at a predetermined timing.
  • the electric charge accumulated in the capacitors Cm of the plurality of stages of circuit units 4 is supplied to the first discharge electrode 211 of the pulse discharge load 2 (see broken line arrow Ip).
  • the positive charge accumulated on the second discharge electrode 212 side of the capacitive component C2 also flows into the first discharge electrode 211 side due to the resonance phenomenon (see the broken arrow Irp).
  • the output voltage due to the flow of the former charge is Vin ⁇ (N + 1) as in the first embodiment.
  • a voltage due to a resonance phenomenon is applied to the pulse discharge load 2 so as to be superimposed on the output voltage.
  • electric energy can be recovered by accumulating magnetic energy in the inductive component L in the resonance circuit in addition to collecting charge in the capacitor Cm of the Marx circuit. That is, more electrical energy can be recovered before the next discharge. Therefore, the power supplied from the DC power supply 5 can be further saved. In addition, the voltage between the electrodes of the pulse discharge load 2 can be further reduced before the next discharge. In addition, the same effects as those of the first embodiment are obtained.
  • the present embodiment is a form of the discharge device 1 in which the inductive component L shown in the third embodiment is provided in the discharge device of the second embodiment.
  • the attached switch series body 43 is provided in the circuit unit 4Z at the final stage in the pulse power power supply circuit unit 3.
  • the pulse power power supply circuit unit 3 has an inductive component L connected in series with the pulse discharge load 2.
  • the inductive component L can resonate with the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2.
  • this embodiment is a combination of the second embodiment and the third embodiment. Other configurations are the same as those of the first embodiment.
  • the induction component L constitutes at least a part of the energy storage unit 31.
  • the series state shown in FIG. 13 and the parallel state shown in FIG. 14 are repeated.
  • This switching frequency is set to a frequency close to the resonance frequency of the resonance circuit of the induction component L and the capacitance component C2.
  • the fourth switch SW4 is turned off and the fifth switch SW5 is turned on.
  • the other switches SW are the same as in the parallel state (see FIG. 11) in the third embodiment.
  • a closed circuit is formed in which the fifth switch SW5, the series switch unit 6, the capacitance component C2, and the induction component L are connected in series.
  • the electric charge charged on the first discharge electrode 211 side of the capacitive component C2 is extracted, and the capacitive component C2 of the capacitive component C2 is passed through the fifth switch SW5 and the series switch unit 6. It moves to the two-discharge electrode 212 side (see broken line arrow Irc).
  • the charge charged on the first discharge electrode 211 side of the capacitive component C2 without passing through the capacitor Cm of the Marx circuit is used for the second discharge of the capacitive component C2. Move to the electrode 212 side. Therefore, most of the charge charged on the first discharge electrode 211 side of the capacitive component C2 can be transferred to the second discharge electrode 212 side of the capacitive component C2. At this time, electric energy is converted into magnetic energy in the inductive component L and accumulated.
  • the DC power supply 5 is connected to capacitors Cm connected in parallel to each other. Therefore, current flows from the DC power source 5 to each capacitor Cm as indicated by the broken arrow Ib. As a result, a charge of Cm ⁇ Vin is accumulated in each of the plurality of capacitors Cm.
  • Cm represents the value of the capacitance of the capacitor Cm.
  • the electric charge accumulated in the capacitors Cm of the multiple-stage circuit unit 4 is supplied to the first discharge electrode 211 of the pulse discharge load 2 (broken arrow) Ip).
  • the positive charge accumulated on the second discharge electrode 212 side of the capacitive component C2 also flows into the first discharge electrode 211 side due to the resonance phenomenon (see the broken arrow Irp).
  • the output voltage due to the flow of the former charge is Vin ⁇ (N + 1) as in the first embodiment.
  • a voltage due to a resonance phenomenon is applied to the pulse discharge load 2 so as to be superimposed on the output voltage.
  • the state is switched from the series state shown in FIG. 13 to the state shown in FIG.
  • the state shown in FIG. 15 is a state in which the fifth switch SW5 is opened while the Marx circuit is in a parallel state. Thereby, a circuit equivalent to the parallel state of the third embodiment (see FIG. 11) is obtained. Then, charges are collected in the capacitors Cm of the plurality of stages of circuit units 4 and some positive charges are charged on the second discharge electrode 212 side of the dielectric layer 22.
  • the positive charge charged on the second discharge electrode 212 side can be increased, and the discharge power at the next discharge can be increased.
  • the same effects as those of the third embodiment are obtained.
  • the pulse power power supply circuit unit 3 includes a transformer 32.
  • the discharge device 1 of this embodiment has a circuit configuration in which a transformer 32 is connected between the Marx circuit and the pulse discharge load 2 in the discharge device of Embodiment 4.
  • the leakage inductance of the transformer 32 is used as the inductive component Le. That is, the inductive component Le composed of this leakage inductance and the capacitance component C2 of the dielectric layer 22 of the pulse discharge load 2 constitute a resonance circuit.
  • the switching between the serial state and the parallel state of the pulse power power supply circuit unit 3 is performed at a frequency at which the resonant circuit of the inductive component Le and the capacitive component C2 resonates, that is, near the resonant frequency.
  • the transformer 32 has a primary winding 321 on the Marx circuit side and a secondary winding 322 on the pulse discharge load 2 side.
  • the output voltage from the Marx circuit can be boosted and supplied to the pulse discharge load 2 by adjusting the turns ratio of the primary winding 321 and the secondary winding 322.
  • the transformer 32 can further boost the output voltage of the Marx circuit. Therefore, a high voltage can be easily applied to the pulse discharge load 2. It is also possible to reduce the number of Marx circuit stages while maintaining the output voltage to the pulse discharge load 2. In addition, the same effects as those of the fourth embodiment are obtained.
  • the present embodiment is a form of the discharge device 1 in which the pulse power power supply circuit unit 3 further includes a power supply protection unit 40. That is, as shown in FIG. 19, the pulse power power supply circuit unit 3 further includes a power supply protection unit 40 interposed between the first-stage circuit unit 4 ⁇ / b> A and the positive electrode of the DC power supply 5.
  • the power supply protection unit 40 includes a protection diode 401, a sixth switch SW6, a capacitor Cm, a third connection portion 423, and a fourth connection portion 424.
  • the sixth switch SW6 is a switch SW connected to the anode of the protection diode 401.
  • the capacitor Cm is connected in parallel to the protective series body 44, which is a serial body of the protective diode 401 and the sixth switch SW6.
  • the third connection portion 423 and the fourth connection portion 424 are connection portions between the protective series body 44 and the capacitor Cm.
  • the third connection portion 423 is connected to the intermediate connection point 41M of the first-stage circuit unit 4A.
  • a third switch SW3 of the series switch unit 6 is interposed between the fourth connection portion 424 and the negative electrode of the DC power supply 5.
  • the third switch SW3 of the series switch unit 6 is also interposed between the fourth connection portion 424 and the second connection portion 422 of the first-stage circuit unit 4A.
  • the discharge device 1 of the present embodiment has a configuration in which the first-stage circuit unit 4A in the discharge device 1 (see FIG. 1) of the first embodiment is replaced with a power protection unit 40.
  • the first switch SW1 in the first-stage circuit unit 4A in the discharge device 1 (see FIG. 1) of the first embodiment is replaced with the protective diode 401.
  • the second-stage circuit unit 4B in the discharge device 1 (see FIG. 1) of the first embodiment is replaced with the first-stage circuit unit 4A.
  • the circuit unit 4 has two stages. That is, the stage number N of the circuit unit 4 of the pulse power power supply circuit unit 3 is two.
  • the number of stages (N + 1) of the Marx circuit including the circuit unit 4 and the power supply protection unit 40 is 3.
  • the number of stages is not particularly limited as in the first embodiment.
  • the pulse power power supply circuit unit 3 In outputting the pulse voltage to the pulse discharge load 2, the pulse power power supply circuit unit 3 is switched to the serial state shown in FIG. As a result, the DC power supply 5 and (N + 1) capacitors Cm are connected in series, and a voltage of Vin ⁇ (N + 2) is applied to the pulse discharge load 2.
  • the pulse power power supply circuit unit 3 When recovering charges from the capacitive component of the dielectric layer 22 of the pulse discharge load 2, the pulse power power supply circuit unit 3 is placed in parallel as shown in FIG. Thereby, a current flows from the pulse discharge load 2 to the pulse power power supply circuit unit 3 until the voltage between the electrodes in the pulse discharge load 2 drops to the power supply voltage Vin (see the broken line arrow Ic).
  • a ripple current may flow from the pulse discharge load 2 to the pulse power power supply circuit unit 3. Even in this case, the ripple current is blocked by the protection diode 401 of the power supply protection unit 40. Therefore, the inflow of the ripple current to the DC power source 5 is prevented.
  • Other configurations are the same as those of the first embodiment.
  • the protection diode 401 of the power protection unit 40 supplies the DC power source 5. Current backflow can be prevented. Thereby, the DC power supply 5 can be protected. In addition, it is possible to prevent the ripple current from flowing into other devices connected to the DC power source 5 and to protect other devices. In addition, the same effects as those of the first embodiment are obtained.

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Abstract

A discharge device (1) which comprises: a pulse discharge load (2) which is provided with a first discharge electrode (211), a second discharge electrode (212) and a dielectric layer (22); and a pulse power supply circuit part (3) which periodically outputs a pulse voltage to the pulse discharge load (2). The pulse power supply circuit part (3) comprises an energy storage part (31) in which electrical energy is able to be stored. The pulse power supply circuit part (3) is configured such that electrical energy is able to be reversibly transferred between the energy storage part (31) and the pulse discharge load (2).

Description

放電装置Discharge device 関連出願の相互参照Cross-reference of related applications
 本出願は、2018年5月18日に出願された日本出願番号2018-95887号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Patent Application No. 2018-95887 filed on May 18, 2018, the contents of which are incorporated herein by reference.
 本開示は、放電装置に関する。 The present disclosure relates to a discharge device.
 マルクス回路を用いて、負荷にパルス電圧を供給するパルス発生装置が提案されている。このパルス発生装置は、マルクス回路における複数のコンデンサを並列接続した状態で、電源から複数のコンデンサに充電を行う。これにより、多くの電荷を低電圧にて充電できる。そして、マルクス回路に充電した電荷を負荷に供給する際には、複数のコンデンサを直列接続に繋ぎ替える。これにより、高電圧を負荷に供給することができる。 A pulse generator that supplies a pulse voltage to a load using a Marx circuit has been proposed. This pulse generator charges a plurality of capacitors from a power supply in a state where a plurality of capacitors in a Marx circuit are connected in parallel. Thereby, a lot of charges can be charged at a low voltage. And when supplying the charge charged in the Marx circuit to the load, a plurality of capacitors are connected in series connection. Thereby, a high voltage can be supplied to the load.
特開2008-11595号公報JP 2008-11595 A
 上記パルス発生装置によってパルス放電負荷へパルス電圧を供給するにあたっては、以下の課題がある。
 すなわち、パルス放電負荷において放電を生じさせた後においても、パルス放電負荷に存在する容量成分(例えば、等価電気回路として、パルス放電負荷に直列に接続される誘電体の容量成分)に電荷が残っている場合がある。この電荷を引き抜くことなく、パルス放電負荷に繰り返しパルス電圧を供給すると、パルス放電負荷端の電圧が印加電圧に近づいてしまうことで、電極間電圧が低下し、放電が生じにくくなってしまう。それゆえ、放電後にパルス放電負荷の容量成分に残った電荷を引き抜くべく、マルクス回路を短絡させて、電荷を熱として放出する。
In supplying a pulse voltage to a pulse discharge load by the pulse generator, there are the following problems.
That is, even after discharge is generated in the pulse discharge load, electric charge remains in the capacitive component existing in the pulse discharge load (for example, as an equivalent electric circuit, a capacitive component of a dielectric connected in series to the pulse discharge load). There may be. If a pulse voltage is repeatedly supplied to the pulse discharge load without extracting this charge, the voltage at the end of the pulse discharge load approaches the applied voltage, so that the voltage between the electrodes decreases and discharge is less likely to occur. Therefore, the Marx circuit is short-circuited and the charge is released as heat in order to extract the charge remaining in the capacitive component of the pulse discharge load after the discharge.
 ところが、電荷を熱として放出するということは、電気エネルギーを無駄に捨てていることにもなる。換言すると、捨てることとなる電気エネルギーを、所望の放電電力に上乗せして、パルス放電負荷に供給することが必要となる。それゆえ、エネルギー効率の点において、改善の余地がある。 However, releasing electric charge as heat also wastes electrical energy. In other words, it is necessary to add the electric energy to be discarded to the desired discharge power and supply it to the pulse discharge load. Therefore, there is room for improvement in terms of energy efficiency.
 本開示は、エネルギー効率に優れた放電装置を提供しようとするものである。 This disclosure intends to provide a discharge device with excellent energy efficiency.
 本開示の一態様は、第1放電用電極及び第2放電用電極と、上記第1放電用電極及び第2放電用電極の少なくとも一方の内側面に配された誘電体層と、を備えたパルス放電負荷と、
 上記パルス放電負荷にパルス電圧を周期的に出力するパルスパワー電源回路部と、を有する放電装置であって、
 上記パルスパワー電源回路部は、電気エネルギーを蓄積することができるエネルギー蓄積部を有し、
 上記パルスパワー電源回路部は、上記エネルギー蓄積部と上記パルス放電負荷との間において電気エネルギーを可逆的に移動させることができるよう構成されている、放電装置にある。
One aspect of the present disclosure includes a first discharge electrode and a second discharge electrode, and a dielectric layer disposed on an inner surface of at least one of the first discharge electrode and the second discharge electrode. Pulse discharge load,
A discharge device having a pulse power power supply circuit unit that periodically outputs a pulse voltage to the pulse discharge load,
The pulse power power supply circuit unit has an energy storage unit capable of storing electrical energy,
The pulse power power supply circuit unit is in a discharge device configured to reversibly move electrical energy between the energy storage unit and the pulse discharge load.
 上記放電装置において、上記パルスパワー電源回路部は、上記エネルギー蓄積部と上記パルス放電負荷との間において電気エネルギーを可逆的に移動させることができるよう構成されている。これにより、パルス放電負荷が放電を実行した後において、誘電体層に電荷が残った場合にも、この電荷による電気エネルギーをパルスパワー電源回路部のエネルギー蓄積部に回収して、蓄積することができる。 In the discharge device, the pulse power power supply circuit unit is configured to reversibly move electrical energy between the energy storage unit and the pulse discharge load. As a result, even when electric charges remain in the dielectric layer after the pulse discharge load performs discharge, the electric energy generated by the electric charges can be recovered and stored in the energy storage unit of the pulse power power supply circuit unit. it can.
 これにより、パルス放電負荷における当該放電の次の放電時に、エネルギー蓄積部に蓄積された電気エネルギーを、パルス放電負荷に供給することができる。それゆえ、パルス放電負荷に繰り返し供給する電気エネルギーを節約することができる。その結果、エネルギー効率に優れた放電装置を得ることができる。 Thereby, at the time of the next discharge of the discharge in the pulse discharge load, the electric energy stored in the energy storage unit can be supplied to the pulse discharge load. Therefore, the electrical energy repeatedly supplied to the pulse discharge load can be saved. As a result, a discharge device with excellent energy efficiency can be obtained.
 以上のごとく、上記態様によれば、エネルギー効率に優れた放電装置を提供することができる。 As mentioned above, according to the said aspect, the discharge device excellent in energy efficiency can be provided.
 本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図1は、実施形態1における、放電装置の回路図であり、 図2は、実施形態1における、パルス放電負荷の説明図であり、 図3は、実施形態1における、直列状態にある放電装置の回路図であり、 図4は、実施形態1における、並列状態にある放電装置の回路図であり、 図5は、実施形態1における、パルス放電負荷の電極間電圧及び電流の時間変化を示す線図であり、 図6は、実施形態2における、放電装置の回路図であり、 図7は、実施形態2における、並列状態にある放電装置の回路図であり、 図8は、実施形態2における、パルス放電負荷の両極を短絡させた状態にある放電装置の回路図であり、 図9は、実施形態2における、直列状態にある放電装置の回路図であり、 図10は、実施形態3における、直列状態にある放電装置の回路図であり、 図11は、実施形態3における、並列状態にある放電装置の回路図であり、 図12は、実施形態3における、並列状態後の直列状態にある放電装置の回路図であり、 図13は、実施形態4における、直列状態にある放電装置の回路図であり、 図14は、実施形態4における、並列状態にある放電装置の回路図であり、 図15は、実施形態4における、並列状態にある放電装置の回路図であって、コンデンサへの電荷の回収を行う状態を示す図であり、 図16は、実施形態5における、直列状態にある放電装置の回路図であり、 図17は、実施形態5における、並列状態にある放電装置の回路図であり、 図18は、実施形態5における、並列状態にある放電装置の回路図であって、コンデンサへの電荷の回収を行う状態を示す図であり、 図19は、実施形態6における、放電装置の回路図であり、 図20は、実施形態6における、直列状態にある放電装置の回路図であり、 図21は、実施形態6における、並列状態にある放電装置の回路図である。
The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a circuit diagram of a discharge device in Embodiment 1. FIG. 2 is an explanatory diagram of a pulse discharge load in the first embodiment. FIG. 3 is a circuit diagram of the discharge device in a series state according to the first embodiment. FIG. 4 is a circuit diagram of the discharge device in the parallel state according to the first embodiment. FIG. 5 is a diagram showing temporal changes in the interelectrode voltage and current of the pulse discharge load in Embodiment 1. FIG. 6 is a circuit diagram of a discharge device according to the second embodiment. FIG. 7 is a circuit diagram of a discharge device in a parallel state according to the second embodiment. FIG. 8 is a circuit diagram of the discharge device in a state where both electrodes of the pulse discharge load are short-circuited in the second embodiment. FIG. 9 is a circuit diagram of the discharge device in the series state according to the second embodiment. FIG. 10 is a circuit diagram of the discharge device in a series state according to the third embodiment. FIG. 11 is a circuit diagram of a discharge device in a parallel state according to the third embodiment. FIG. 12 is a circuit diagram of the discharge device in the series state after the parallel state in the third embodiment, FIG. 13 is a circuit diagram of the discharge device in a series state in the fourth embodiment. FIG. 14 is a circuit diagram of a discharge device in a parallel state according to the fourth embodiment. FIG. 15 is a circuit diagram of a discharge device in a parallel state according to the fourth embodiment, and shows a state in which charge is collected to a capacitor. FIG. 16 is a circuit diagram of a discharge device in a series state according to the fifth embodiment. FIG. 17 is a circuit diagram of the discharge device in the parallel state in the fifth embodiment. FIG. 18 is a circuit diagram of a discharge device in a parallel state according to the fifth embodiment, and shows a state in which charge is collected to a capacitor. FIG. 19 is a circuit diagram of a discharge device in Embodiment 6. FIG. 20 is a circuit diagram of the discharge device in a series state according to the sixth embodiment. FIG. 21 is a circuit diagram of a discharge device in a parallel state according to the sixth embodiment.
(実施形態1)
 放電装置に係る実施形態について、図1~図5を参照して説明する。
 本形態の放電装置1は、図1に示すごとく、パルス放電負荷2とパルスパワー電源回路部3とを有する。
(Embodiment 1)
An embodiment according to a discharge device will be described with reference to FIGS.
As shown in FIG. 1, the discharge device 1 of this embodiment includes a pulse discharge load 2 and a pulse power power supply circuit unit 3.
 パルス放電負荷2は、図2に示すごとく、第1放電用電極211及び第2放電用電極212と誘電体層22とを備えている。誘電体層22は、第1放電用電極211及び第2放電用電極212の少なくとも一方の内側面に配されている。本形態においては、誘電体層22は、第1放電用電極211及び第2放電用電極212の双方の内側面に配されている。 As shown in FIG. 2, the pulse discharge load 2 includes a first discharge electrode 211, a second discharge electrode 212, and a dielectric layer 22. The dielectric layer 22 is disposed on the inner surface of at least one of the first discharge electrode 211 and the second discharge electrode 212. In this embodiment, the dielectric layer 22 is disposed on the inner side surfaces of both the first discharge electrode 211 and the second discharge electrode 212.
 パルスパワー電源回路部3は、パルス放電負荷2にパルス電圧を周期的に出力する。
 図1に示すごとく、パルスパワー電源回路部3は、電気エネルギーを蓄積することができるエネルギー蓄積部31を有する。
 パルスパワー電源回路部3は、エネルギー蓄積部31とパルス放電負荷2との間において電気エネルギーを可逆的に移動させることができるよう構成されている。
The pulse power power supply circuit unit 3 periodically outputs a pulse voltage to the pulse discharge load 2.
As shown in FIG. 1, the pulse power power supply circuit unit 3 includes an energy storage unit 31 that can store electrical energy.
The pulse power power supply circuit unit 3 is configured to reversibly move electrical energy between the energy storage unit 31 and the pulse discharge load 2.
 パルスパワー電源回路部3は、複数のコンデンサCmと複数のスイッチSWとを有する。パルスパワー電源回路部3は、複数のスイッチSWのオンオフの切り替えにより、直列状態と並列状態とを切り替えることができるよう構成されている。直列状態は、図3に示すごとく、複数のコンデンサCmを互いに直列接続した状態である。並列状態は、図4に示すごとく、複数のコンデンサCmを互いに並列接続した状態である。 The pulse power power supply circuit unit 3 includes a plurality of capacitors Cm and a plurality of switches SW. The pulse power power supply circuit unit 3 is configured to be able to switch between a serial state and a parallel state by switching on and off the plurality of switches SW. The series state is a state in which a plurality of capacitors Cm are connected in series as shown in FIG. The parallel state is a state in which a plurality of capacitors Cm are connected in parallel as shown in FIG.
 すなわち、パルスパワー電源回路部3は、マルクス回路を形成している。
 図3に示すごとく、直列状態にて、パルス放電負荷2へのパルス電圧の出力を行う。図4に示すごとく、並列状態にて、パルス放電負荷2の誘電体層22の容量成分C2からエネルギー蓄積部31への電気エネルギーの回収を行う。
That is, the pulse power power supply circuit unit 3 forms a Marx circuit.
As shown in FIG. 3, a pulse voltage is output to the pulse discharge load 2 in a series state. As shown in FIG. 4, electrical energy is recovered from the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2 to the energy storage unit 31 in a parallel state.
 図3における破線矢印Ip及び図4における破線矢印Icは、それぞれの電流の流れを示す。これらの電流の流れIp、Icは、正電荷の流れでもある。他の図における、破線矢印Ip、Icも同様である。
 本形態において、エネルギー蓄積部31は、複数のコンデンサCmによって構成されている。つまり、複数のコンデンサCmのそれぞれに、電荷が充電され、電気エネルギーが蓄積される。
A broken line arrow Ip in FIG. 3 and a broken line arrow Ic in FIG. 4 indicate current flows. These current flows Ip and Ic are also positive charge flows. The same applies to broken line arrows Ip and Ic in other figures.
In the present embodiment, the energy storage unit 31 is configured by a plurality of capacitors Cm. That is, electric charge is accumulated in each of the plurality of capacitors Cm, and electric energy is accumulated.
 図1に示すごとく、パルスパワー電源回路部3は、互いに接続された複数段の回路ユニット4(4A、4B、4Z)と、直流電源5と、直列スイッチユニット6とを有する。直流電源5は、1段目の回路ユニット4Aに正極が接続されている。直列スイッチユニット6は、最終段の回路ユニット4Zと直流電源5の負極との間に接続されている。 As shown in FIG. 1, the pulse power power supply circuit section 3 includes a plurality of stages of circuit units 4 (4A, 4B, 4Z), a DC power supply 5, and a series switch unit 6. The DC power source 5 has a positive electrode connected to the first stage circuit unit 4A. The series switch unit 6 is connected between the circuit unit 4Z at the final stage and the negative electrode of the DC power supply 5.
 パルスパワー電源回路部3は、複数のスイッチSWとして、回路ユニット4に属する第1スイッチSW1及び第2スイッチSW2と、直列スイッチユニット6に属する第3スイッチSW3とを有する。 The pulse power power supply circuit unit 3 includes a first switch SW1 and a second switch SW2 belonging to the circuit unit 4 and a third switch SW3 belonging to the series switch unit 6 as a plurality of switches SW.
 回路ユニット4は、スイッチ直列体41とコンデンサCmとを有する。スイッチ直列体41は、第1スイッチSW1と第2スイッチSW2とを中間接続点41Mにおいて互いに直列接続してなる。コンデンサCmは、スイッチ直列体41に並列接続されている。回路ユニット4は、スイッチ直列体41とコンデンサCmとの接続部として、第1接続部421及び第2接続部422を有する。 The circuit unit 4 includes a switch series body 41 and a capacitor Cm. The switch series body 41 is formed by connecting a first switch SW1 and a second switch SW2 in series at an intermediate connection point 41M. The capacitor Cm is connected in parallel to the switch series body 41. The circuit unit 4 includes a first connection part 421 and a second connection part 422 as a connection part between the switch series body 41 and the capacitor Cm.
 直列スイッチユニット6は、複数の第3スイッチSW3を互いに直列接続してなる。
 最終段の回路ユニット4Zの第1接続部421が、パルス放電負荷2の第1放電用電極211に接続される。
 直流電源5の負極と直列スイッチユニット6の一端とは、互いに接続されると共に、パルス放電負荷2の第2放電用電極212に接続される。
The series switch unit 6 is formed by connecting a plurality of third switches SW3 in series.
The first connection part 421 of the circuit unit 4Z at the final stage is connected to the first discharge electrode 211 of the pulse discharge load 2.
The negative electrode of the DC power supply 5 and one end of the series switch unit 6 are connected to each other and to the second discharge electrode 212 of the pulse discharge load 2.
 1段目の回路ユニット4Aの中間接続点41Mに、直流電源5の正極が接続されている。
 k段目の回路ユニット4の中間接続点41Mに、(k-1)段目の回路ユニット4の第1接続部421が接続されている。ここで、上記kは、2以上の自然数である。なお、パルスパワー電源回路部3が備える回路ユニット4の段数をN段とする。このとき、上記kは、2~Nの自然数である。また、Nは、2以上の自然数である。
The positive electrode of the DC power supply 5 is connected to the intermediate connection point 41M of the first-stage circuit unit 4A.
The first connection portion 421 of the (k−1) -th stage circuit unit 4 is connected to the intermediate connection point 41M of the k-th stage circuit unit 4. Here, k is a natural number of 2 or more. Note that the number of stages of the circuit unit 4 included in the pulse power power supply circuit unit 3 is N. At this time, k is a natural number of 2 to N. N is a natural number of 2 or more.
 k段目の回路ユニット4の第2接続部422と、(k-1)段目の回路ユニット4の第2接続部422との間には、直列スイッチユニット6における第3スイッチSW3が介在している。
 1段目の回路ユニット4Aの第2接続部422と直流電源5の負極との間にも、直列スイッチユニット6における第3スイッチSW3が介在している。
Between the second connection portion 422 of the k-th stage circuit unit 4 and the second connection portion 422 of the (k−1) -th stage circuit unit 4, the third switch SW3 in the series switch unit 6 is interposed. ing.
The third switch SW3 in the series switch unit 6 is also interposed between the second connection portion 422 of the first-stage circuit unit 4A and the negative electrode of the DC power supply 5.
 本形態において、パルスパワー電源回路部3は、回路ユニット4を3段有する。それゆえ、本形態においては、上記Nは3であり、上記kは2又は3である。そして、パルスパワー電源回路部3は、複数の回路ユニット4として、直流電源5に近い側から、1段目の回路ユニット4Aと、2段目の回路ユニット4Bと、3段目の回路ユニット4Zとを有する。3段目の回路ユニット4Zが、最終段の回路ユニット4Zとなる。なお、回路ユニット4の段数は、複数段であれば、特に限定されるものではない。 In this embodiment, the pulse power power supply circuit unit 3 includes three circuit units 4. Therefore, in the present embodiment, the N is 3 and the k is 2 or 3. The pulse power power supply circuit unit 3 includes, as a plurality of circuit units 4, from the side close to the DC power supply 5, a first stage circuit unit 4A, a second stage circuit unit 4B, and a third stage circuit unit 4Z. And have. The third-stage circuit unit 4Z becomes the final-stage circuit unit 4Z. The number of stages of the circuit unit 4 is not particularly limited as long as it is a plurality of stages.
 また、直列スイッチユニット6は、互いに直列接続された3個の第3スイッチSW3を有する。直列スイッチユニット6の一端が、最終段の回路ユニット4Zの第2接続部422に接続され、他端が、直流電源5の負極に接続されている。また、k段目の回路ユニット4の第2接続部422と、(k-1)段目の回路ユニット4の第2接続部422との間には、第3スイッチSW3が一つずつ介在している。また、1段目の回路ユニット4Aの第2接続部422と直流電源5の負極との間にも、一つの第3スイッチSW3が介在している。 The series switch unit 6 has three third switches SW3 connected in series with each other. One end of the series switch unit 6 is connected to the second connection part 422 of the circuit unit 4 </ b> Z at the final stage, and the other end is connected to the negative electrode of the DC power supply 5. Further, one third switch SW3 is interposed between the second connection portion 422 of the k-th stage circuit unit 4 and the second connection portion 422 of the (k−1) -th stage circuit unit 4. ing. One third switch SW3 is also interposed between the second connection part 422 of the first-stage circuit unit 4A and the negative electrode of the DC power supply 5.
 また、各スイッチSWには、ダイオードがそれぞれ並列接続されている。第1スイッチSW1に並列接続されたダイオードは、中間接続点41M側がアノードとなる向きに接続されている。第2スイッチSW2に並列接続されたダイオードは、中間接続点41M側がカソードとなる向きに接続されている。第3スイッチSW3に並列接続されたダイオードは、直流電源5の負極に近い側がアノードとなる向きに接続されている。 Also, a diode is connected in parallel to each switch SW. The diode connected in parallel to the first switch SW1 is connected in the direction in which the intermediate connection point 41M side becomes the anode. The diode connected in parallel to the second switch SW2 is connected in such a direction that the intermediate connection point 41M side becomes the cathode. The diode connected in parallel to the third switch SW3 is connected in such a direction that the side close to the negative electrode of the DC power supply 5 becomes the anode.
 また、スイッチSWは、パワー半導体素子からなる。そして、これらのパワー半導体素子からなるスイッチSWを、駆動回路からの信号によって、適宜オンオフさせることができる。スイッチSWとしては、例えば、IGBT(絶縁ゲートバイポーラトランジスタの略)、MOSFET(MOS型電界効果トランジスタの略)等を用いることができる。また、パワー半導体素子としては、例えば、炭化珪素(SiC)にて形成したものや、シリコン(Si)にて形成したものを用いることができる。 The switch SW is made of a power semiconductor element. Then, the switch SW composed of these power semiconductor elements can be appropriately turned on and off by a signal from the drive circuit. As the switch SW, for example, IGBT (abbreviation of insulated gate bipolar transistor), MOSFET (abbreviation of MOS field effect transistor) or the like can be used. Moreover, as a power semiconductor element, what was formed with silicon carbide (SiC) and what was formed with silicon (Si) can be used, for example.
 図3に示すごとく、第1スイッチSW1及び第3スイッチSW3をオフ(すなわち開放)にすると共に第2スイッチSW2をオン(すなわち短絡)にすることにより、直列状態が形成される。また、図4に示すごとく、第1スイッチSW1及び第3スイッチSW3をオンにすると共に第2スイッチSW2をオフにすることにより、並列状態が形成される。 As shown in FIG. 3, the first switch SW1 and the third switch SW3 are turned off (that is, opened) and the second switch SW2 is turned on (that is, short-circuited), thereby forming a series state. As shown in FIG. 4, the parallel state is formed by turning on the first switch SW1 and the third switch SW3 and turning off the second switch SW2.
 すなわち、直列状態を形成する際には、図3に示すごとく、すべての回路ユニット4において、第1スイッチSW1をオフにすると共に第2スイッチSW2をオンにする。また、直列スイッチユニット6のすべての第3スイッチSW3をオフにする。 That is, when forming the series state, as shown in FIG. 3, in all the circuit units 4, the first switch SW1 is turned off and the second switch SW2 is turned on. Further, all the third switches SW3 of the series switch unit 6 are turned off.
 並列状態を形成する際には、図4に示すごとく、すべての回路ユニット4において、第1スイッチSW1をオンにすると共に第2スイッチSW2をオフにする。また、直列スイッチユニット6のすべての第3スイッチSW3をオンにする。 When forming the parallel state, as shown in FIG. 4, in all the circuit units 4, the first switch SW1 is turned on and the second switch SW2 is turned off. Further, all the third switches SW3 of the series switch unit 6 are turned on.
 すべての第1スイッチSW1とすべての第3スイッチSW3とは、駆動回路からの同じ信号によって、同期してオンオフするよう構成することができる。また、すべての第2スイッチSW2は、駆動回路からの同じ信号によって、同期してオンオフするよう構成することができる。ただし、第2スイッチSW2は、第1スイッチSW1および第3スイッチSW3の駆動信号とは異なる駆動信号によって、オンオフする。より具体的には、第2スイッチSW2は、第1スイッチSW1及び第3スイッチSW3がオンのときにオフとする。 All the first switches SW1 and all the third switches SW3 can be configured to be turned on / off in synchronization by the same signal from the drive circuit. Further, all the second switches SW2 can be configured to be turned on / off in synchronization by the same signal from the drive circuit. However, the second switch SW2 is turned on / off by a drive signal different from the drive signals of the first switch SW1 and the third switch SW3. More specifically, the second switch SW2 is turned off when the first switch SW1 and the third switch SW3 are on.
 なお、放電装置1の起動時においては、まず最初に、パルスパワー電源回路部3のエネルギー蓄積部31に電気エネルギーを蓄積する。すなわち、このときは、パルスパワー電源回路部3を、図4に示す並列状態として、直流電源5の電源電圧Vinを各コンデンサCmに印加する。 Note that when the discharge device 1 is started, first, electric energy is stored in the energy storage unit 31 of the pulse power power supply circuit unit 3. That is, at this time, the pulse power power supply circuit unit 3 is placed in the parallel state shown in FIG. 4, and the power supply voltage Vin of the DC power supply 5 is applied to each capacitor Cm.
 次に、パルス放電負荷2へ、パルス電圧を出力するにあたっては、パルスパワー電源回路部3を、図3に示す直列状態に切り替える。すなわち、電荷が蓄積された複数のコンデンサCmが直列接続された状態となると共に、これらのコンデンサCmの直列回路が直流電源5とも直列接続されることとなる。これにより、パルス放電負荷2には、Vin×(N+1)の電圧が印加されることとなる。 Next, when outputting the pulse voltage to the pulse discharge load 2, the pulse power power supply circuit unit 3 is switched to the series state shown in FIG. That is, a plurality of capacitors Cm in which electric charges are accumulated are connected in series, and a series circuit of these capacitors Cm is also connected in series with the DC power source 5. As a result, a voltage of Vin × (N + 1) is applied to the pulse discharge load 2.
 すなわち、回路ユニット4の段数Nに1を加えた数を、電源電圧Vinに乗じた電圧が、パルス放電負荷2に印加されることとなる。これにより、パルス放電負荷2において、パルス放電が生じる。ただし、放電後においても、パルス放電負荷2の誘電体層22の容量成分C2に、一部の電荷が残る。 That is, a voltage obtained by multiplying the number N of stages of the circuit unit 4 by 1 and the power supply voltage Vin is applied to the pulse discharge load 2. As a result, pulse discharge occurs in the pulse discharge load 2. However, even after discharge, some charges remain in the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2.
 この状態から、図4に示すごとく、パルスパワー電源回路部3を並列状態に切り替える。すると、互いに並列接続された複数のコンデンサCmが、パルス放電負荷2に接続されると共に、直流電源5にも並列接続された状態となる。これにより、パルス放電負荷2における電極間電圧が、電源電圧Vinに下がるまで、パルス放電負荷2からパルスパワー電源回路部3へ電流が流れる。すなわち、パルス放電負荷2の誘電体層22の容量成分C2から電荷が引き抜かれ、マルクス回路の各コンデンサCmに、電荷が回収される。 From this state, the pulse power power supply circuit unit 3 is switched to the parallel state as shown in FIG. Then, the plurality of capacitors Cm connected in parallel to each other are connected to the pulse discharge load 2 and also connected to the DC power supply 5 in parallel. Thereby, a current flows from the pulse discharge load 2 to the pulse power power supply circuit unit 3 until the voltage between the electrodes in the pulse discharge load 2 decreases to the power supply voltage Vin. That is, charges are extracted from the capacitance component C2 of the dielectric layer 22 of the pulse discharge load 2, and the charges are recovered by the capacitors Cm of the Marx circuit.
 その結果、パルス放電負荷2に残っていた電気エネルギーが、パルスパワー電源回路部3のエネルギー蓄積部31に回収され、蓄積される。それとともに、パルス放電負荷2の電極間電圧が、低減される。 As a result, the electric energy remaining in the pulse discharge load 2 is recovered and stored in the energy storage unit 31 of the pulse power power supply circuit unit 3. At the same time, the voltage between the electrodes of the pulse discharge load 2 is reduced.
 回収された電気エネルギーは、放電装置1における次の放電に用いられる。次の周期のパルス放電の際には、パルスパワー電源回路部3から、パルス放電負荷2に電圧を出力する。すなわち、上記と同様に、図3に示すごとく、パルスパワー電源回路部3を直列状態とする。これにより、Vin×(N+1)の電圧がパルス放電負荷2に印加される。 The collected electrical energy is used for the next discharge in the discharge device 1. In the next period of pulse discharge, a voltage is output from the pulse power power supply circuit unit 3 to the pulse discharge load 2. That is, similarly to the above, as shown in FIG. 3, the pulse power power supply circuit unit 3 is put in series. As a result, a voltage of Vin × (N + 1) is applied to the pulse discharge load 2.
 このとき、前回のパルス放電の後に誘電体層22から引き抜かれてエネルギー蓄積部31に回収されていた電荷が、直流電源5からの電荷に重畳して、パルス放電負荷2へ供給される。これにより、再び、パルス放電負荷2において放電が生じる。そして、誘電体層22の容量成分C2に電荷が充電される。 At this time, the charge that has been extracted from the dielectric layer 22 after the previous pulse discharge and collected in the energy storage unit 31 is superimposed on the charge from the DC power supply 5 and supplied to the pulse discharge load 2. Thereby, discharge occurs again in the pulse discharge load 2. Then, a charge is charged in the capacitive component C2 of the dielectric layer 22.
 以降、図4に示す並列状態と図3に示す直列状態とが、交互に繰り返される。これにより、エネルギーを節約しつつ、パルス放電負荷2におけるパルス放電が効率よく生じる。 Thereafter, the parallel state shown in FIG. 4 and the serial state shown in FIG. 3 are alternately repeated. Thereby, the pulse discharge in the pulse discharge load 2 is efficiently generated while saving energy.
 パルス放電負荷2は、誘電体バリア放電を生じさせる構造を有する。図2に示すごとく、パルス放電負荷2は、互いに対向配置された第1放電用電極211と第2放電用電極212とを有する。そして、第1放電用電極211の内側面と第2放電用電極212の内側面とに、それぞれ誘電体層22を設けている。一対の誘電体層22の間に、放電ギャップ23が形成されている。この放電ギャップ23に放電を生じさせることで、例えば、プラズマを発生させることができる。また、例えば、放電ギャップ23に酸素を含む気体を供給しつつ、放電ギャップ23にプラズマを生じさせることによって、オゾンを発生させることができる。 The pulse discharge load 2 has a structure that generates a dielectric barrier discharge. As shown in FIG. 2, the pulse discharge load 2 includes a first discharge electrode 211 and a second discharge electrode 212 that are arranged to face each other. The dielectric layers 22 are provided on the inner surface of the first discharge electrode 211 and the inner surface of the second discharge electrode 212, respectively. A discharge gap 23 is formed between the pair of dielectric layers 22. By generating a discharge in the discharge gap 23, for example, plasma can be generated. Further, for example, ozone can be generated by generating plasma in the discharge gap 23 while supplying a gas containing oxygen to the discharge gap 23.
 次に、本実施形態の作用効果につき説明する。
 上記放電装置1において、パルスパワー電源回路部3は、エネルギー蓄積部31とパルス放電負荷2との間において電気エネルギーを可逆的に移動させることができるよう構成されている。これにより、パルス放電負荷2が放電を実行した後において、誘電体層22に電荷が残った場合にも、この電荷による電気エネルギーをパルスパワー電源回路部3のエネルギー蓄積部31に回収して、蓄積することができる。
Next, the effect of this embodiment is demonstrated.
In the discharge device 1, the pulse power power supply circuit unit 3 is configured to reversibly move electrical energy between the energy storage unit 31 and the pulse discharge load 2. Thereby, even after the pulse discharge load 2 performs the discharge, even when the electric charge remains in the dielectric layer 22, the electric energy due to this electric charge is recovered in the energy storage unit 31 of the pulse power power supply circuit unit 3, Can be accumulated.
 これにより、パルス放電負荷2における当該放電の次の放電時に、エネルギー蓄積部31に蓄積された電気エネルギーを、パルス放電負荷2に供給することができる。それゆえ、パルス放電負荷2に繰り返し供給する電気エネルギーを節約することができる。その結果、エネルギー効率に優れた放電装置1を得ることができる。 Thereby, the electrical energy stored in the energy storage unit 31 can be supplied to the pulse discharge load 2 at the time of the next discharge after the discharge in the pulse discharge load 2. Therefore, the electrical energy repeatedly supplied to the pulse discharge load 2 can be saved. As a result, the discharge device 1 excellent in energy efficiency can be obtained.
 パルスパワー電源回路部3は、複数のコンデンサCmと複数のスイッチSWとを有する。複数のスイッチSWのオンオフの切り替えにより、直列状態と並列状態とを切り替えることができるよう構成されている。直列状態にて、パルス放電負荷2へのパルス電圧の出力を行い、並列状態にて、パルス放電負荷2の誘電体層22の容量成分C2からエネルギー蓄積部31への電気エネルギーの回収を行う。すなわち、パルスパワー電源回路部3は、マルクス回路を形成しており、その直列状態と並列状態との切り替えを繰り返すことによって、パルス放電負荷2へのパルス電圧の出力と、パルス放電負荷2からの電気エネルギーの回収とを、交互に繰り返すことができる。それゆえ、効率よく、パルス電圧の出力と電気エネルギーの回収とを行うことができる。 The pulse power power supply circuit unit 3 includes a plurality of capacitors Cm and a plurality of switches SW. By switching on / off of the plurality of switches SW, the serial state and the parallel state can be switched. The pulse voltage is output to the pulse discharge load 2 in the series state, and the electric energy is recovered from the capacitance component C2 of the dielectric layer 22 of the pulse discharge load 2 to the energy storage unit 31 in the parallel state. That is, the pulse power power supply circuit unit 3 forms a Marx circuit, and by repeatedly switching between the serial state and the parallel state, the pulse voltage output to the pulse discharge load 2 and the pulse discharge load 2 The recovery of electrical energy can be repeated alternately. Therefore, it is possible to efficiently output the pulse voltage and recover the electric energy.
 パルスパワー電源回路部3は、複数段の回路ユニット4と直列スイッチユニット6とを有し、図1に示すようなマルクス回路を形成している。これにより、複数のスイッチSWを適宜オンオフさせることで、容易かつ効率的に、直列状態と並列状態を実現することができる。その結果、容易に、エネルギー効率に優れた放電装置1を得ることができる。 The pulse power power supply circuit unit 3 includes a multi-stage circuit unit 4 and a series switch unit 6, and forms a Marx circuit as shown in FIG. Thereby, the series state and the parallel state can be realized easily and efficiently by appropriately turning on and off the plurality of switches SW. As a result, the discharge device 1 excellent in energy efficiency can be easily obtained.
 具体的には、第1スイッチSW1及び第3スイッチSW3をオフにすると共に第2スイッチSW2をオンにすることにより、直列状態を形成し、第1スイッチSW1及び第3スイッチSW3をオンにすると共に第2スイッチSW2をオフにすることにより、並列状態を形成する。これにより、パルス放電負荷2へのパルス電圧の出力と、パルス放電負荷2からの電気エネルギーの回収を、容易かつ確実に行うことができる。 Specifically, by turning off the first switch SW1 and the third switch SW3 and turning on the second switch SW2, a series state is formed, and the first switch SW1 and the third switch SW3 are turned on. A parallel state is formed by turning off the second switch SW2. Thereby, the output of the pulse voltage to the pulse discharge load 2 and the collection | recovery of the electrical energy from the pulse discharge load 2 can be performed easily and reliably.
 また、上述のように、パルス放電負荷2の誘電体層22の容量成分C2からの電荷の引き抜きを、パルスパワー電源回路部3の並列状態にて行うため、短時間に多くの電荷を引き抜くことが可能となる。図5は、パルス放電負荷2における電流と、電極間電圧(すなわち、パルスパワー電源回路部3からパルス放電負荷2への出力電圧)の時間変化を示す線図である。ここで、パルスパワー電源回路部3からパルス放電負荷2の第1放電用電極211へ向かう出力電流をプラス(すなわち、グラフの電流0よりも上側)、その逆向きの流れをマイナス(すなわち、グラフの電流0よりも下側)として表記してある。 Further, as described above, since the charge is extracted from the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2 in the parallel state of the pulse power power supply circuit unit 3, a large amount of charge is extracted in a short time. Is possible. FIG. 5 is a diagram showing temporal changes in the current in the pulse discharge load 2 and the interelectrode voltage (that is, the output voltage from the pulse power power supply circuit unit 3 to the pulse discharge load 2). Here, the output current from the pulse power supply circuit unit 3 to the first discharge electrode 211 of the pulse discharge load 2 is positive (that is, above the current 0 in the graph), and the flow in the opposite direction is negative (that is, the graph). The current is lower than 0).
 図5に示す時刻t1において、パルスパワー電源回路部3を直列状態に切り替えて、パルス放電負荷2への出力を開始すると、出力電圧が、Vin×(N+1)まで立ち上がる。このとき、パルス放電負荷2にプラスのパルス電流が供給される。その後、時刻t2において、パルスパワー電源回路部3を並列状態に切り替えると、印加電圧がVinまで低下すると共に、電流がマイナス方向に急峻に立ち上がる。つまり、パルス放電負荷2の誘電体層22の容量成分C2から、多くの電荷が短時間の間に引き抜かれる。 At time t1 shown in FIG. 5, when the pulse power power supply circuit unit 3 is switched to the serial state and output to the pulse discharge load 2 is started, the output voltage rises to Vin × (N + 1). At this time, a positive pulse current is supplied to the pulse discharge load 2. Thereafter, when the pulse power power supply circuit unit 3 is switched to the parallel state at time t2, the applied voltage decreases to Vin and the current rises sharply in the negative direction. That is, a large amount of charge is extracted from the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2 in a short time.
 このように、本形態においては、パルス放電負荷2の誘電体層22の容量成分C2から、多くの電荷を短時間の間に引き抜くことができる。そのため、例えば、放電装置1をオゾナイザに適用した場合、放電電極間に存在するイオンが電極に移動する期間を短くすることができるため、イオンの発熱を抑えることができ、放電ギャップ23におけるラジカル生成率を向上させることができる。 Thus, in this embodiment, a large amount of charges can be extracted from the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2 in a short time. Therefore, for example, when the discharge device 1 is applied to an ozonizer, the period during which ions existing between the discharge electrodes move to the electrodes can be shortened, so that heat generation of ions can be suppressed, and radical generation in the discharge gap 23 The rate can be improved.
 以上のごとく、本形態によれば、エネルギー効率に優れた放電装置を提供することができる。 As described above, according to this embodiment, it is possible to provide a discharge device with excellent energy efficiency.
(実施形態2)
 本形態は、図6~図9に示すごとく、最終段の回路ユニット4Zに、付属スイッチ直列体43を並列接続した、放電装置1の形態である。
(Embodiment 2)
As shown in FIGS. 6 to 9, the present embodiment is a discharge device 1 in which an attached switch series body 43 is connected in parallel to the circuit unit 4Z at the final stage.
 すなわち、本形態の放電装置1におけるパルスパワー電源回路部3は、スイッチSWとして、互いに直列接続された第4スイッチSW4及び第5スイッチSW5をさらに有する。そして、最終段の回路ユニット4Zは、スイッチ直列体41及びコンデンサCmに、付属スイッチ直列体43を、並列接続してある。付属スイッチ直列体43は、第4スイッチSW4と第5スイッチSW5との直列体である。 That is, the pulse power power supply circuit unit 3 in the discharge device 1 of the present embodiment further includes a fourth switch SW4 and a fifth switch SW5 connected in series as the switch SW. In the circuit unit 4Z at the final stage, the attached switch series body 43 is connected in parallel to the switch series body 41 and the capacitor Cm. The attached switch series body 43 is a series body of the fourth switch SW4 and the fifth switch SW5.
 付属スイッチ直列体43における第4スイッチSW4と第5スイッチSW5との接続点43Mが、パルス放電負荷2の第1放電用電極211に接続されている。 The connection point 43M between the fourth switch SW4 and the fifth switch SW5 in the attached switch series body 43 is connected to the first discharge electrode 211 of the pulse discharge load 2.
 パルス放電負荷2の誘電体層22の容量成分からエネルギー蓄積部31への電気エネルギーの回収を行う際には、図7に示すように、各スイッチSWを制御する。すなわち、第1スイッチSW1、第3スイッチSW3、第4スイッチSW4をオンにすると共に第2スイッチSW2及び第5スイッチSW5をオフにして、並列状態を形成する。これにより、パルス放電負荷2の電極間電圧が低下する。 When the electrical energy is recovered from the capacitive component of the dielectric layer 22 of the pulse discharge load 2 to the energy storage unit 31, each switch SW is controlled as shown in FIG. That is, the first switch SW1, the third switch SW3, and the fourth switch SW4 are turned on, and the second switch SW2 and the fifth switch SW5 are turned off to form a parallel state. Thereby, the voltage between the electrodes of the pulse discharge load 2 decreases.
 その後、パルス放電負荷2の電極間電圧が、直流電源5の電源電圧Vinまで低下したとき、図8に示すように、各スイッチSWを制御する。すなわち、第4スイッチSW4をオフに切り替えるとともに、第5スイッチSW5をオンに切り替える。なお、他のスイッチSWは切り替えない。これにより、パルス放電負荷2の第1放電用電極211と第2放電用電極212とを短絡させる。 Thereafter, when the voltage between the electrodes of the pulse discharge load 2 drops to the power supply voltage Vin of the DC power supply 5, each switch SW is controlled as shown in FIG. That is, the fourth switch SW4 is switched off and the fifth switch SW5 is switched on. The other switches SW are not switched. As a result, the first discharge electrode 211 and the second discharge electrode 212 of the pulse discharge load 2 are short-circuited.
 そうすると、パルス放電負荷2の誘電体層22に残っていた電荷が引き抜かれ、第5スイッチSW5及び直列スイッチユニット6(すなわち複数の第3スイッチSW3)を含む短絡回路における抵抗成分において、熱となって放出される。そして、パルス放電負荷2の電極間電圧は、略ゼロとなる。図8における破線矢印Ieは、このときの電流の流れを示す。 Then, the electric charge remaining in the dielectric layer 22 of the pulse discharge load 2 is extracted, and heat is generated in the resistance component in the short circuit including the fifth switch SW5 and the series switch unit 6 (that is, the plurality of third switches SW3). Released. And the voltage between electrodes of the pulse discharge load 2 becomes substantially zero. A broken line arrow Ie in FIG. 8 indicates a current flow at this time.
 その後、次の放電のタイミングにて、図9に示すごとく、パルスパワー電源回路部3を直列状態に切り替えると共に、付属スイッチ直列体43において、第4スイッチSW4をオン、第5スイッチSW5をオフに切り替える。これにより、パルスパワー電源回路部3からパルス放電負荷2に、Vin×(N+1)の高電圧が印加され、再び放電を生じさせることができる。 Thereafter, at the timing of the next discharge, as shown in FIG. 9, the pulse power power supply circuit unit 3 is switched to the serial state, and the fourth switch SW4 is turned on and the fifth switch SW5 is turned off in the attached switch series body 43. Switch. As a result, a high voltage of Vin × (N + 1) is applied from the pulse power power supply circuit unit 3 to the pulse discharge load 2, and discharge can be generated again.
 その他の構成は、実施形態1と同様である。なお、実施形態2以降において用いた符号のうち、既出の実施形態において用いた符号と同一のものは、特に示さない限り、既出の実施形態におけるものと同様の構成要素等を表す。 Other configurations are the same as those in the first embodiment. Of the reference numerals used in the second and subsequent embodiments, the same reference numerals as those used in the above-described embodiments represent the same components as those in the above-described embodiments unless otherwise indicated.
 本形態においては、エネルギー蓄積部31への回収後もパルス放電負荷2の容量成分C2に残る電荷を引き抜くことができ、パルス放電負荷2の電極間電圧を略ゼロに低下させることができる。すなわち、次の放電の前に、パルス放電負荷2の電極間電圧を充分に低下させ、パルスパワー電源回路部3の出力電圧との電圧差を大きくすることができる。その結果、パルス放電負荷2における放電をより生じさせやすくなる。
 その他、実施形態1と同様の作用効果を有する。
In the present embodiment, the charge remaining in the capacitive component C2 of the pulse discharge load 2 can be extracted even after recovery to the energy storage unit 31, and the voltage between the electrodes of the pulse discharge load 2 can be reduced to substantially zero. That is, before the next discharge, the voltage between the electrodes of the pulse discharge load 2 can be sufficiently reduced, and the voltage difference from the output voltage of the pulse power power supply circuit unit 3 can be increased. As a result, it becomes easier to cause discharge in the pulse discharge load 2.
In addition, the same effects as those of the first embodiment are obtained.
(実施形態3)
 本形態は、図10~図12に示すごとく、パルスパワー電源回路部3が、パルス放電負荷2と直列接続される誘導成分Lを有する形態である。
 誘導成分Lは、パルス放電負荷2の誘電体層22の容量成分C2と共振可能に構成されている。本形態においては、誘導成分Lが、エネルギー蓄積部31の少なくとも一部を構成している。なお、本形態においては、各回路ユニット4におけるコンデンサCmも、エネルギー蓄積部31の一部を構成する。
(Embodiment 3)
In the present embodiment, as shown in FIGS. 10 to 12, the pulse power power supply circuit unit 3 has an inductive component L connected in series with the pulse discharge load 2.
The inductive component L is configured to resonate with the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2. In this embodiment, the induction component L constitutes at least a part of the energy storage unit 31. In this embodiment, the capacitor Cm in each circuit unit 4 also constitutes a part of the energy storage unit 31.
 なお、誘導成分Lは、部品としてのインダクタを設けてもよいし、配線や他の部品に寄生する寄生インダクタンス等を利用してもよい。 Note that the inductive component L may be provided with an inductor as a component, or may be a parasitic inductance that is parasitic on wiring or other components.
 パルスパワー電源回路部3は、エネルギー蓄積部31からパルス放電負荷2への電気エネルギーの移動と、パルス放電負荷2からエネルギー蓄積部31(すなわち誘導成分L及びコンデンサCm)への電気エネルギーの移動とを、誘導成分Lと容量成分C2との共振周期の間に実行するよう構成されている。 The pulse power power supply circuit unit 3 transfers electric energy from the energy storage unit 31 to the pulse discharge load 2 and transfers electric energy from the pulse discharge load 2 to the energy storage unit 31 (that is, the inductive component L and the capacitor Cm). Is executed during the resonance period of the inductive component L and the capacitive component C2.
 すなわち、誘導成分Lと誘電体層22の容量成分C2との直列共振回路における共振周期の間に、図10に示す直列状態と、図11に示す並列状態とが、1回ずつ実行されるように、スイッチSWを切り替える。 That is, the series state shown in FIG. 10 and the parallel state shown in FIG. 11 are executed once each during the resonance period in the series resonance circuit of the inductive component L and the capacitance component C2 of the dielectric layer 22. Then, the switch SW is switched.
 図10に示す、パルスパワー電源回路部3における直列状態においては、パルス放電負荷2に、Vin×(N+1)の電圧が印加される。そして、パルス放電負荷2における第1放電用電極211に、プラス電荷が流れ込むように、パルス電流が流れる。このパルス電流は、誘導成分Lと容量成分C2との直列共振回路に流れる。 In the series state in the pulse power supply circuit unit 3 shown in FIG. 10, a voltage of Vin × (N + 1) is applied to the pulse discharge load 2. Then, a pulse current flows so that a positive charge flows into the first discharge electrode 211 in the pulse discharge load 2. This pulse current flows through a series resonance circuit of an inductive component L and a capacitive component C2.
 この直列共振回路の共振周波数に近い周波数にて、パルスパワー電源回路部3を、直列状態と並列状態との間で切り替える。ここで、切り替え周波数は、直列状態から並列状態への切り替えのタイミングの間隔、又は、並列状態から直列状態への切り替えのタイミングの間隔を1周期としたときの周波数である。そして、この切り替え周波数f1が、共振周波数f0に対して、例えば、0.8×f0≦f1≦1.2×f0となるようにする。 The pulse power power supply circuit unit 3 is switched between the series state and the parallel state at a frequency close to the resonance frequency of the series resonance circuit. Here, the switching frequency is a frequency when the interval of the switching timing from the serial state to the parallel state or the interval of the switching timing from the parallel state to the serial state is one cycle. Then, the switching frequency f1 is set to, for example, 0.8 × f0 ≦ f1 ≦ 1.2 × f0 with respect to the resonance frequency f0.
 図11に示す並列状態においては、共振回路の共振現象によって、パルス放電負荷2の第1放電用電極211から、パルスパワー電源回路部3を介して、第2放電用電極212へ向かう電流が流れる。すなわち、誘電体層22の容量成分C2における、第1放電用電極211側に溜まっていた正電荷が、パルスパワー電源回路部3を介して、容量成分C2における第2放電用電極212側に移動する。 In the parallel state shown in FIG. 11, a current flowing from the first discharge electrode 211 of the pulse discharge load 2 to the second discharge electrode 212 through the pulse power power supply circuit unit 3 flows due to the resonance phenomenon of the resonance circuit. . That is, the positive charge accumulated on the first discharge electrode 211 side in the capacitive component C2 of the dielectric layer 22 moves to the second discharge electrode 212 side in the capacitive component C2 via the pulse power power supply circuit unit 3. To do.
 このとき、電流は、複数段の回路ユニット4のコンデンサCmに分岐して、再びパルス放電負荷2において合流し、容量成分C2の第2放電用電極212側に流れ込む。これにより、正電荷が、容量成分C2の第2放電用電極212側に充電される。 At this time, the current branches to the capacitor Cm of the circuit unit 4 in a plurality of stages, merges again in the pulse discharge load 2, and flows into the second discharge electrode 212 side of the capacitive component C2. As a result, positive charges are charged on the second discharge electrode 212 side of the capacitive component C2.
 これと共に、複数段の回路ユニット4のコンデンサCmにも、一部の電荷が回収される。また、この並列状態においては、直流電源5が、互いに並列接続されたコンデンサCmに接続されているため、これら複数のコンデンサCmのそれぞれには、Cm×Vinの電荷が蓄積される。ここで、Cmは、コンデンサCmの静電容量の値を示す。なお、複数のコンデンサCmの間において、静電容量は同じであってもよいし、異なっていてもよい。ただし、静電容量Cmは、パルス放電負荷2における放電電荷に対して充分な電荷量を保持できる程度であることは求められる。 At the same time, a part of the electric charge is recovered also in the capacitor Cm of the circuit unit 4 in a plurality of stages. In this parallel state, since the DC power supply 5 is connected to the capacitors Cm connected in parallel to each other, a charge of Cm × Vin is accumulated in each of the plurality of capacitors Cm. Here, Cm represents the value of the capacitance of the capacitor Cm. Note that the capacitance may be the same or different among the plurality of capacitors Cm. However, the capacitance Cm is required to be a level that can hold a sufficient amount of charge with respect to the discharge charge in the pulse discharge load 2.
 このように、各部に電荷が蓄積された状態から、所定のタイミングにて、再び直列状態に切り替わる。そうすると、図12に示すごとく、複数段の回路ユニット4のコンデンサCmに蓄積された電荷が、パルス放電負荷2の第1放電用電極211へ供給される(破線矢印Ip参照)。それと共に、容量成分C2の第2放電用電極212側に蓄積されていた正電荷も、共振現象によって第1放電用電極211側へ流れ込む(破線矢印Irp参照)。前者の電荷の流れ込みによる出力電圧は、実施形態1と同様に、Vin×(N+1)である。この出力電圧に重畳して、共振現象による電圧がパルス放電負荷2に加わる。 In this way, the state is switched from the state where charges are accumulated in each part to the serial state again at a predetermined timing. Then, as shown in FIG. 12, the electric charge accumulated in the capacitors Cm of the plurality of stages of circuit units 4 is supplied to the first discharge electrode 211 of the pulse discharge load 2 (see broken line arrow Ip). At the same time, the positive charge accumulated on the second discharge electrode 212 side of the capacitive component C2 also flows into the first discharge electrode 211 side due to the resonance phenomenon (see the broken arrow Irp). The output voltage due to the flow of the former charge is Vin × (N + 1) as in the first embodiment. A voltage due to a resonance phenomenon is applied to the pulse discharge load 2 so as to be superimposed on the output voltage.
 これにより、パルス放電負荷2において、放電が生じる。そして、この放電後においても、誘電体層22における容量成分C2には、第1放電用電極211側に正電荷が残る。この正電荷は、次の並列状態(図11参照)において、共振現象によって引き抜かれ、上記と同様に、マルクス回路における複数のコンデンサCm、及び誘電体層22の容量成分C2における第2放電用電極212側に、回収される。 This causes discharge in the pulse discharge load 2. Even after this discharge, a positive charge remains on the first discharge electrode 211 side in the capacitive component C2 in the dielectric layer 22. This positive charge is extracted by a resonance phenomenon in the next parallel state (see FIG. 11), and similarly to the above, the plurality of capacitors Cm in the Marx circuit and the second discharge electrode in the capacitive component C2 of the dielectric layer 22 Collected on the 212 side.
 このように、並列状態においては、マルクス回路のコンデンサCmに電荷が蓄積されると共に、誘電体層22の第2放電用電極212側に、正電荷が蓄積される。誘電体層22の第2放電用電極212側への正電荷の回収は、換言すると、電荷移動による電気エネルギーが、共振回路における誘導成分Lにおいて磁気エネルギーとして回収されることとも言える。つまり、エネルギー蓄積部31の一部としての誘導成分Lに、電気エネルギーが蓄積されていることになる。
 その他の構成は、実施形態1と同様である。
As described above, in the parallel state, charges are accumulated in the capacitor Cm of the Marx circuit, and positive charges are accumulated on the second discharge electrode 212 side of the dielectric layer 22. In other words, the recovery of the positive charge toward the second discharge electrode 212 side of the dielectric layer 22 can be said to be that the electric energy due to the charge transfer is recovered as magnetic energy in the inductive component L in the resonance circuit. That is, electric energy is stored in the induction component L as a part of the energy storage unit 31.
Other configurations are the same as those of the first embodiment.
 本形態においては、マルクス回路のコンデンサCmへの電荷の回収に加え、共振回路における誘導成分Lへの磁気エネルギーの蓄積によって、電気エネルギーを回収することができる。すなわち、より多くの電気エネルギーを次の放電の前に回収しておくことができる。そのため、直流電源5から供給する電力を、より節約することができる。また、次の放電の前に、パルス放電負荷2の電極間電圧をより低減させることができる。
 その他、実施形態1と同様の作用効果を有する。
In this embodiment, electric energy can be recovered by accumulating magnetic energy in the inductive component L in the resonance circuit in addition to collecting charge in the capacitor Cm of the Marx circuit. That is, more electrical energy can be recovered before the next discharge. Therefore, the power supplied from the DC power supply 5 can be further saved. In addition, the voltage between the electrodes of the pulse discharge load 2 can be further reduced before the next discharge.
In addition, the same effects as those of the first embodiment are obtained.
(実施形態4)
 本形態は、図13~図15に示すごとく、実施形態2の放電装置に、実施形態3に示した誘導成分Lを設けた、放電装置1の形態である。
(Embodiment 4)
As shown in FIGS. 13 to 15, the present embodiment is a form of the discharge device 1 in which the inductive component L shown in the third embodiment is provided in the discharge device of the second embodiment.
 すなわち、本形態の放電装置1は、パルスパワー電源回路部3における最終段の回路ユニット4Zに、付属スイッチ直列体43を設けている。そのうえで、パルスパワー電源回路部3が、パルス放電負荷2と直列接続される誘導成分Lを有する。そして、誘導成分Lは、パルス放電負荷2の誘電体層22の容量成分C2と共振可能となっている。換言すると、本形態は、実施形態2と実施形態3とを組み合わせたものである。
 その他の構成は、実施形態1と同様である。
That is, in the discharge device 1 of this embodiment, the attached switch series body 43 is provided in the circuit unit 4Z at the final stage in the pulse power power supply circuit unit 3. In addition, the pulse power power supply circuit unit 3 has an inductive component L connected in series with the pulse discharge load 2. The inductive component L can resonate with the capacitive component C2 of the dielectric layer 22 of the pulse discharge load 2. In other words, this embodiment is a combination of the second embodiment and the third embodiment.
Other configurations are the same as those of the first embodiment.
 本形態においても、誘導成分Lが、エネルギー蓄積部31の少なくとも一部を構成する。
 本形態においては、図13に示す直列状態と、図14に示す並列状態とを繰り返す。この切り替え周波数を、誘導成分Lと容量成分C2との共振回路の共振周波数に近い周波数とする。
Also in this embodiment, the induction component L constitutes at least a part of the energy storage unit 31.
In this embodiment, the series state shown in FIG. 13 and the parallel state shown in FIG. 14 are repeated. This switching frequency is set to a frequency close to the resonance frequency of the resonance circuit of the induction component L and the capacitance component C2.
 直列状態においては、図13に示すごとく、第1スイッチSW1をオフ、第2スイッチSW2をオン、第3スイッチSW3をオフ、第4スイッチSW4をオン、第5スイッチSW5をオフとする。これにより、実施形態3における直列状態(図10参照)と等価な回路となる。これにより、Vin×(N+1)の電圧が、パルス放電負荷2に印加される。また、このとき、パルス電流が、共振回路に流れ、誘電体層22の容量成分C2の第1放電用電極211側に正電荷が供給される。 In the serial state, as shown in FIG. 13, the first switch SW1 is turned off, the second switch SW2 is turned on, the third switch SW3 is turned off, the fourth switch SW4 is turned on, and the fifth switch SW5 is turned off. Thereby, it becomes a circuit equivalent to the serial state (refer FIG. 10) in Embodiment 3. FIG. As a result, a voltage of Vin × (N + 1) is applied to the pulse discharge load 2. At this time, a pulse current flows through the resonance circuit, and positive charge is supplied to the first discharge electrode 211 side of the capacitive component C2 of the dielectric layer 22.
 次に、図14に示す並列状態に切り替える。同図に示すように、第4スイッチSW4をオフにするとともに、第5スイッチSW5をオンとする。その他のスイッチSWは、実施形態3における並列状態(図11参照)と同様とする。これにより、第5スイッチSW5と直列スイッチユニット6と、容量成分C2及び誘導成分Lとが直列に接続された閉回路が形成される。この状態において、共振回路の共振現象によって、容量成分C2の第1放電用電極211側に充電されていた電荷が引き抜かれ、第5スイッチSW5及び直列スイッチユニット6を介して、容量成分C2の第2放電用電極212側に移動する(破線矢印Irc参照)。 Next, switch to the parallel state shown in FIG. As shown in the figure, the fourth switch SW4 is turned off and the fifth switch SW5 is turned on. The other switches SW are the same as in the parallel state (see FIG. 11) in the third embodiment. As a result, a closed circuit is formed in which the fifth switch SW5, the series switch unit 6, the capacitance component C2, and the induction component L are connected in series. In this state, due to the resonance phenomenon of the resonance circuit, the electric charge charged on the first discharge electrode 211 side of the capacitive component C2 is extracted, and the capacitive component C2 of the capacitive component C2 is passed through the fifth switch SW5 and the series switch unit 6. It moves to the two-discharge electrode 212 side (see broken line arrow Irc).
 本形態においては、図14に示す並列状態において、マルクス回路のコンデンサCmを通らずに、容量成分C2の第1放電用電極211側に充電されていた電荷が、容量成分C2の第2放電用電極212側に移動する。それゆえ、容量成分C2の第1放電用電極211側に充電されていた電荷の多くを、容量成分C2の第2放電用電極212側に移すことができる。なお、このとき、電気エネルギーが、誘導成分Lにおいて磁気エネルギーに変換されて蓄積される。 In the present embodiment, in the parallel state shown in FIG. 14, the charge charged on the first discharge electrode 211 side of the capacitive component C2 without passing through the capacitor Cm of the Marx circuit is used for the second discharge of the capacitive component C2. Move to the electrode 212 side. Therefore, most of the charge charged on the first discharge electrode 211 side of the capacitive component C2 can be transferred to the second discharge electrode 212 side of the capacitive component C2. At this time, electric energy is converted into magnetic energy in the inductive component L and accumulated.
 また、この並列状態においては、直流電源5が、互いに並列接続されたコンデンサCmに接続されている。そのため、直流電源5から各コンデンサCmに、破線矢印Ibに示すように、電流が流れ込む。これにより、これら複数のコンデンサCmのそれぞれには、Cm×Vinの電荷が蓄積される。ここで、Cmは、コンデンサCmの静電容量の値を示す。 Further, in this parallel state, the DC power supply 5 is connected to capacitors Cm connected in parallel to each other. Therefore, current flows from the DC power source 5 to each capacitor Cm as indicated by the broken arrow Ib. As a result, a charge of Cm × Vin is accumulated in each of the plurality of capacitors Cm. Here, Cm represents the value of the capacitance of the capacitor Cm.
 そして、次の直列状態(図13参照)への切り替えによって、複数段の回路ユニット4のコンデンサCmに蓄積された電荷が、パルス放電負荷2の第1放電用電極211へ供給される(破線矢印Ip参照)。それと共に、容量成分C2の第2放電用電極212側に蓄積されていた正電荷も、共振現象によって第1放電用電極211側へ流れ込む(破線矢印Irp参照)。前者の電荷の流れ込みによる出力電圧は、実施形態1と同様に、Vin×(N+1)である。この出力電圧に重畳して、共振現象による電圧がパルス放電負荷2に加わる。 Then, by switching to the next serial state (see FIG. 13), the electric charge accumulated in the capacitors Cm of the multiple-stage circuit unit 4 is supplied to the first discharge electrode 211 of the pulse discharge load 2 (broken arrow) Ip). At the same time, the positive charge accumulated on the second discharge electrode 212 side of the capacitive component C2 also flows into the first discharge electrode 211 side due to the resonance phenomenon (see the broken arrow Irp). The output voltage due to the flow of the former charge is Vin × (N + 1) as in the first embodiment. A voltage due to a resonance phenomenon is applied to the pulse discharge load 2 so as to be superimposed on the output voltage.
 これにより、パルス放電負荷2において、放電が生じる。そして、この放電後においても、誘電体層22における容量成分C2には、第1放電用電極211側に正電荷が残る。この正電荷は、次の並列状態(図14参照)において、共振現象によって引き抜かれ、上記と同様に、誘電体層22の容量成分C2における第2放電用電極212側に、回収される。 This causes discharge in the pulse discharge load 2. Even after this discharge, a positive charge remains on the first discharge electrode 211 side in the capacitive component C2 in the dielectric layer 22. This positive charge is extracted by the resonance phenomenon in the next parallel state (see FIG. 14), and is collected on the second discharge electrode 212 side in the capacitive component C2 of the dielectric layer 22 in the same manner as described above.
 上記のようなパルス放電負荷2への断続的な電力の供給動作を、一旦停止させる際には、図13の直列状態から、図15に示す状態に切り替える。図15に示す状態は、マルクス回路を並列状態としつつ、第5スイッチSW5を開放した状態である。これにより、実施形態3の並列状態(図11参照)と等価な回路となる。そして、複数段の回路ユニット4のコンデンサCmに電荷が回収されると共に、誘電体層22の第2放電用電極212側に、一部の正電荷が充電される。 In order to temporarily stop the intermittent power supply operation to the pulse discharge load 2 as described above, the state is switched from the series state shown in FIG. 13 to the state shown in FIG. The state shown in FIG. 15 is a state in which the fifth switch SW5 is opened while the Marx circuit is in a parallel state. Thereby, a circuit equivalent to the parallel state of the third embodiment (see FIG. 11) is obtained. Then, charges are collected in the capacitors Cm of the plurality of stages of circuit units 4 and some positive charges are charged on the second discharge electrode 212 side of the dielectric layer 22.
 そして、再び放電装置1を起動する際に、これらの電荷として回収された電気エネルギーが、次の放電電力の一部として利用される。
 その他の構成は、実施形態3と同様である。
And when starting up the discharge device 1 again, the electric energy recovered as these charges is used as a part of the next discharge power.
Other configurations are the same as those of the third embodiment.
 本形態においては、図14に示すごとく、第2放電用電極212側に充電される正電荷を多くすることができ、次の放電の際における放電電力をより大きくすることができる。
 その他、実施形態3と同様の作用効果を有する。
In this embodiment, as shown in FIG. 14, the positive charge charged on the second discharge electrode 212 side can be increased, and the discharge power at the next discharge can be increased.
In addition, the same effects as those of the third embodiment are obtained.
(実施形態5)
 本形態は、図16~図18に示すごとく、パルスパワー電源回路部3がトランス32を備えた放電装置1の形態である。
 本形態の放電装置1は、図16に示すごとく、実施形態4の放電装置における、マルクス回路とパルス放電負荷2との間に、トランス32を接続した回路構成を有する。
(Embodiment 5)
In this embodiment, as shown in FIGS. 16 to 18, the pulse power power supply circuit unit 3 includes a transformer 32.
As shown in FIG. 16, the discharge device 1 of this embodiment has a circuit configuration in which a transformer 32 is connected between the Marx circuit and the pulse discharge load 2 in the discharge device of Embodiment 4.
 また、本形態においては、トランス32の漏れインダクタンスを、誘導成分Leとして利用している。つまり、この漏れインダクタンスからなる誘導成分Leと、パルス放電負荷2の誘電体層22の容量成分C2とが、共振回路を構成する。そして、パルスパワー電源回路部3の直列状態と並列状態との切り替えを、誘導成分Leと容量成分C2との共振回路が共振するような周波数、すなわち共振周波数近傍にて行う。 In this embodiment, the leakage inductance of the transformer 32 is used as the inductive component Le. That is, the inductive component Le composed of this leakage inductance and the capacitance component C2 of the dielectric layer 22 of the pulse discharge load 2 constitute a resonance circuit. The switching between the serial state and the parallel state of the pulse power power supply circuit unit 3 is performed at a frequency at which the resonant circuit of the inductive component Le and the capacitive component C2 resonates, that is, near the resonant frequency.
 トランス32は、マルクス回路側の一次巻線321と、パルス放電負荷2側の二次巻線322とを有する。そして、一次巻線321と二次巻線322との巻き数比を調整することにより、マルクス回路からの出力電圧を昇圧して、パルス放電負荷2へ供給することができるよう構成されている。 The transformer 32 has a primary winding 321 on the Marx circuit side and a secondary winding 322 on the pulse discharge load 2 side. The output voltage from the Marx circuit can be boosted and supplied to the pulse discharge load 2 by adjusting the turns ratio of the primary winding 321 and the secondary winding 322.
 本形態においても、図16に示す直列状態と図17に示す並列状態とを、所定の周波数にて切り替えることにより、共振回路の共振現象を利用しつつ、電気エネルギーの回収及び出力を行うことができる。そして、出力時においては、マルクス回路におけるVin×(N+1)という電圧が、トランス32においてさらに昇圧される。この昇圧後の電圧に、さらに、共振現象によって、第2放電用電極212側からの第1放電用電極211への正電荷供給分の電圧が重畳されて、パルス放電負荷2に印加される。 Also in this embodiment, by switching the series state shown in FIG. 16 and the parallel state shown in FIG. 17 at a predetermined frequency, it is possible to collect and output electrical energy while utilizing the resonance phenomenon of the resonance circuit. it can. At the time of output, the voltage of Vin × (N + 1) in the Marx circuit is further boosted in the transformer 32. Further, a voltage corresponding to the supply of positive charges from the second discharge electrode 212 side to the first discharge electrode 211 is superimposed on the voltage after the boosting and applied to the pulse discharge load 2 by a resonance phenomenon.
 そして、パルス放電負荷2への断続的な電力の供給動作を一旦停止させる際には、図16の直列状態から、図18に示す状態に切り替える。これにより、実施形態3の並列状態(図11参照)と等価な回路となる。そして、複数段の回路ユニット4のコンデンサCmに電荷が回収されると共に、誘電体層22の第2放電用電極212側に、一部の正電荷が回収される。
 その他の構成は、実施形態4と同様である。
When the intermittent power supply operation to the pulse discharge load 2 is temporarily stopped, the series state shown in FIG. 16 is switched to the state shown in FIG. Thereby, a circuit equivalent to the parallel state of the third embodiment (see FIG. 11) is obtained. Then, electric charges are collected in the capacitors Cm of the multi-stage circuit unit 4 and some positive charges are collected on the second discharge electrode 212 side of the dielectric layer 22.
Other configurations are the same as those of the fourth embodiment.
 本形態においては、トランス32によって、マルクス回路の出力電圧をさらに昇圧することができる。それゆえ、パルス放電負荷2に高電圧を容易に印加することができる。また、パルス放電負荷2への出力電圧を維持しつつ、マルクス回路の段数を低減することも可能となる。
 その他、実施形態4と同様の作用効果を有する。
In this embodiment, the transformer 32 can further boost the output voltage of the Marx circuit. Therefore, a high voltage can be easily applied to the pulse discharge load 2. It is also possible to reduce the number of Marx circuit stages while maintaining the output voltage to the pulse discharge load 2.
In addition, the same effects as those of the fourth embodiment are obtained.
(実施形態6)
 本形態は、図19~図21に示すごとく、パルスパワー電源回路部3が電源保護ユニット40をさらに有する、放電装置1の形態である。
 すなわち、図19に示すごとく、パルスパワー電源回路部3は、1段目の回路ユニット4Aと直流電源5の正極との間に介在した電源保護ユニット40を、さらに有する。
(Embodiment 6)
As shown in FIGS. 19 to 21, the present embodiment is a form of the discharge device 1 in which the pulse power power supply circuit unit 3 further includes a power supply protection unit 40.
That is, as shown in FIG. 19, the pulse power power supply circuit unit 3 further includes a power supply protection unit 40 interposed between the first-stage circuit unit 4 </ b> A and the positive electrode of the DC power supply 5.
 電源保護ユニット40は、保護用ダイオード401と、第6スイッチSW6と、コンデンサCmと、第3接続部423及び第4接続部424と、を有する。第6スイッチSW6は、保護用ダイオード401のアノードに接続されたスイッチSWである。コンデンサCmは、保護用ダイオード401と第6スイッチSW6との直列体である保護用直列体44に並列接続されている。第3接続部423及び第4接続部424は、保護用直列体44とコンデンサCmとの接続部である。 The power supply protection unit 40 includes a protection diode 401, a sixth switch SW6, a capacitor Cm, a third connection portion 423, and a fourth connection portion 424. The sixth switch SW6 is a switch SW connected to the anode of the protection diode 401. The capacitor Cm is connected in parallel to the protective series body 44, which is a serial body of the protective diode 401 and the sixth switch SW6. The third connection portion 423 and the fourth connection portion 424 are connection portions between the protective series body 44 and the capacitor Cm.
 第3接続部423が、1段目の回路ユニット4Aの中間接続点41Mに接続されている。第4接続部424と、直流電源5の負極との間に、直列スイッチユニット6の第3スイッチSW3が介在している。第4接続部424と1段目の回路ユニット4Aの第2接続部422との間にも、直列スイッチユニット6の第3スイッチSW3が介在している。 The third connection portion 423 is connected to the intermediate connection point 41M of the first-stage circuit unit 4A. A third switch SW3 of the series switch unit 6 is interposed between the fourth connection portion 424 and the negative electrode of the DC power supply 5. The third switch SW3 of the series switch unit 6 is also interposed between the fourth connection portion 424 and the second connection portion 422 of the first-stage circuit unit 4A.
 本形態の放電装置1は、実施形態1の放電装置1(図1参照)における1段目の回路ユニット4Aを、電源保護ユニット40に置き換えた構成となっている。換言すると、実施形態1の放電装置1(図1参照)における1段目の回路ユニット4Aにおける第1スイッチSW1を、保護用ダイオード401に置き換えている。また、実施形態1の放電装置1(図1参照)における2段目の回路ユニット4Bを、1段目の回路ユニット4Aに置き換えている。 The discharge device 1 of the present embodiment has a configuration in which the first-stage circuit unit 4A in the discharge device 1 (see FIG. 1) of the first embodiment is replaced with a power protection unit 40. In other words, the first switch SW1 in the first-stage circuit unit 4A in the discharge device 1 (see FIG. 1) of the first embodiment is replaced with the protective diode 401. Further, the second-stage circuit unit 4B in the discharge device 1 (see FIG. 1) of the first embodiment is replaced with the first-stage circuit unit 4A.
 そして、本形態においては、回路ユニット4は2段となっている。つまり、パルスパワー電源回路部3の回路ユニット4の段数Nは2である。そして、回路ユニット4と電源保護ユニット40とを併せたマルクス回路の段数(N+1)は、3となる。この段数については、実施形態1と同様に、特に限定されるものではない。 In this embodiment, the circuit unit 4 has two stages. That is, the stage number N of the circuit unit 4 of the pulse power power supply circuit unit 3 is two. The number of stages (N + 1) of the Marx circuit including the circuit unit 4 and the power supply protection unit 40 is 3. The number of stages is not particularly limited as in the first embodiment.
 パルス放電負荷2へパルス電圧を出力するにあたっては、パルスパワー電源回路部3を、図20に示す直列状態に切り替える。これにより、直流電源5と(N+1)個のコンデンサCmとが直列接続され、パルス放電負荷2には、Vin×(N+2)の電圧が印加されることとなる。 In outputting the pulse voltage to the pulse discharge load 2, the pulse power power supply circuit unit 3 is switched to the serial state shown in FIG. As a result, the DC power supply 5 and (N + 1) capacitors Cm are connected in series, and a voltage of Vin × (N + 2) is applied to the pulse discharge load 2.
 パルス放電負荷2の誘電体層22の容量成分から、電荷を回収する際には、図21に示すごとく、パルスパワー電源回路部3を並列状態にする。これにより、パルス放電負荷2における電極間電圧が、電源電圧Vinに下がるまで、パルス放電負荷2からパルスパワー電源回路部3へ電流が流れる(破線矢印Ic参照)。ここで、パルス放電負荷2からパルスパワー電源回路部3へリプル電流が流入することもある。この場合でも、電源保護ユニット40の保護用ダイオード401によって、リプル電流が堰き止められる。それゆえ、直流電源5へのリプル電流の流入が防がれる。
 その他の構成は、実施形態1と同様である。
When recovering charges from the capacitive component of the dielectric layer 22 of the pulse discharge load 2, the pulse power power supply circuit unit 3 is placed in parallel as shown in FIG. Thereby, a current flows from the pulse discharge load 2 to the pulse power power supply circuit unit 3 until the voltage between the electrodes in the pulse discharge load 2 drops to the power supply voltage Vin (see the broken line arrow Ic). Here, a ripple current may flow from the pulse discharge load 2 to the pulse power power supply circuit unit 3. Even in this case, the ripple current is blocked by the protection diode 401 of the power supply protection unit 40. Therefore, the inflow of the ripple current to the DC power source 5 is prevented.
Other configurations are the same as those of the first embodiment.
 本形態においては、上記のように、パルス放電負荷2からパルスパワー電源回路部3のエネルギー蓄積部31への電気エネルギー回収の際に、電源保護ユニット40の保護用ダイオード401によって、直流電源5への電流の逆流を防ぐことができる。これにより、直流電源5を保護することができる。また、直流電源5に接続された他の機器へのリプル電流の流入をも防ぐことができ、他の機器の保護にもつながる。
 その他、実施形態1と同様の作用効果を有する。
In the present embodiment, as described above, when the electrical energy is recovered from the pulse discharge load 2 to the energy storage unit 31 of the pulse power power supply circuit unit 3, the protection diode 401 of the power protection unit 40 supplies the DC power source 5. Current backflow can be prevented. Thereby, the DC power supply 5 can be protected. In addition, it is possible to prevent the ripple current from flowing into other devices connected to the DC power source 5 and to protect other devices.
In addition, the same effects as those of the first embodiment are obtained.
 本開示は上記各実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々の実施形態に適用することが可能である。 The present disclosure is not limited to the above embodiments, and can be applied to various embodiments without departing from the scope of the disclosure.
 本開示は、実施形態に準拠して記述されたが、本開示は当該実施形態や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or the structure. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (9)

  1.  第1放電用電極(211)及び第2放電用電極(212)と、上記第1放電用電極及び第2放電用電極の少なくとも一方の内側面に配された誘電体層(22)と、を備えたパルス放電負荷(2)と、
     上記パルス放電負荷にパルス電圧を周期的に出力するパルスパワー電源回路部(3)と、を有する放電装置(1)であって、
     上記パルスパワー電源回路部(3)は、電気エネルギーを蓄積することができるエネルギー蓄積部(31)を有し、
     上記パルスパワー電源回路部は、上記エネルギー蓄積部と上記パルス放電負荷との間において電気エネルギーを可逆的に移動させることができるよう構成されている、放電装置。
    A first discharge electrode (211) and a second discharge electrode (212); and a dielectric layer (22) disposed on an inner surface of at least one of the first discharge electrode and the second discharge electrode. A provided pulse discharge load (2);
    A discharge device (1) having a pulse power power supply circuit section (3) for periodically outputting a pulse voltage to the pulse discharge load,
    The pulse power power supply circuit unit (3) has an energy storage unit (31) capable of storing electrical energy,
    The pulse power power supply circuit unit is a discharge device configured to reversibly move electrical energy between the energy storage unit and the pulse discharge load.
  2.  上記パルスパワー電源回路部は、複数のコンデンサ(Cm)と複数のスイッチ(SW)とを有し、複数の上記スイッチのオンオフの切り替えにより、複数の上記コンデンサを互いに直列接続した直列状態と、複数の上記コンデンサを互いに並列接続した並列状態と、を切り替えることができるよう構成されており、上記直列状態にて、上記パルス放電負荷へのパルス電圧の出力を行い、上記並列状態にて、上記パルス放電負荷の上記誘電体層の容量成分(C2)から上記エネルギー蓄積部への電気エネルギーの回収を行うよう構成されている、請求項1に記載の放電装置。 The pulse power power supply circuit unit includes a plurality of capacitors (Cm) and a plurality of switches (SW), and a plurality of capacitors connected in series by switching on and off the plurality of switches, Of the capacitors connected in parallel to each other, and the pulse voltage is output to the pulse discharge load in the series state, and the pulse is output in the parallel state. The discharge device according to claim 1, wherein the discharge device is configured to recover electric energy from a capacitance component (C2) of the dielectric layer of the discharge load to the energy storage unit.
  3.  上記パルスパワー電源回路部は、互いに接続された複数段の回路ユニット(4)と、1段目の上記回路ユニットに正極が接続された直流電源(5)と、最終段の上記回路ユニット(4、4Z)と上記直流電源の負極との間に接続された直列スイッチユニット(6)と、を有し、
     複数の上記スイッチとして、上記回路ユニットに属する第1スイッチ(SW1)及び第2スイッチ(SW2)と、上記直列スイッチユニットに属する第3スイッチ(SW3)とを有し、
     上記回路ユニットは、上記第1スイッチと上記第2スイッチとを中間接続点(41M)において互いに直列接続してなるスイッチ直列体(41)と、該スイッチ直列体に並列接続された上記コンデンサと、を有し、上記スイッチ直列体と上記コンデンサとの接続部として、第1接続部(421)及び第2接続部(422)を有し、
     上記直列スイッチユニットは、複数の上記第3スイッチを互いに直列接続してなり、
     最終段の上記回路ユニットの上記第1接続部が、上記パルス放電負荷の上記第1放電用電極に接続され、
     上記直流電源の負極と上記直列スイッチユニットの一端とは、互いに接続されると共に、上記パルス放電負荷の上記第2放電用電極に接続され、
     1段目の上記回路ユニット(4、4A)の上記中間接続点に、上記直流電源の正極が接続されており、
     k段目の上記回路ユニットの上記中間接続点に、(k-1)段目の上記回路ユニットの上記第1接続部が接続されており、
     上記kは、2以上の自然数であり、
     k段目の上記回路ユニットの上記第2接続部と、(k-1)段目の上記回路ユニットの上記第2接続部との間には、上記直列スイッチユニットにおける上記第3スイッチが介在しており、
     1段目の上記回路ユニットの上記第2接続部と上記直流電源の負極との間にも、上記直列スイッチユニットにおける上記第3スイッチが介在している、請求項2に記載の放電装置。
    The pulse power power supply circuit unit includes a plurality of circuit units (4) connected to each other, a DC power supply (5) having a positive electrode connected to the first circuit unit, and the circuit unit (4) in the final stage. 4Z) and a series switch unit (6) connected between the negative electrode of the DC power source,
    As the plurality of switches, a first switch (SW1) and a second switch (SW2) belonging to the circuit unit, and a third switch (SW3) belonging to the series switch unit,
    The circuit unit includes a switch series body (41) in which the first switch and the second switch are connected in series to each other at an intermediate connection point (41M), and the capacitor connected in parallel to the switch series body, As a connection part between the switch series body and the capacitor, the first connection part (421) and the second connection part (422),
    The series switch unit is formed by connecting a plurality of the third switches in series with each other,
    The first connection portion of the circuit unit at the final stage is connected to the first discharge electrode of the pulse discharge load;
    The negative electrode of the DC power source and one end of the series switch unit are connected to each other and connected to the second discharge electrode of the pulse discharge load,
    The positive terminal of the DC power source is connected to the intermediate connection point of the circuit unit (4, 4A) in the first stage,
    The first connection portion of the (k−1) -th stage circuit unit is connected to the intermediate connection point of the k-th stage circuit unit,
    K is a natural number of 2 or more,
    The third switch in the series switch unit is interposed between the second connection portion of the circuit unit at the k-th stage and the second connection portion of the circuit unit at the (k−1) -th stage. And
    3. The discharge device according to claim 2, wherein the third switch in the series switch unit is interposed between the second connection portion of the circuit unit at the first stage and the negative electrode of the DC power supply.
  4.  上記第1スイッチ及び上記第3スイッチをオフにすると共に上記第2スイッチをオンにすることにより、上記直列状態を形成し、上記第1スイッチ及び上記第3スイッチをオンにすると共に上記第2スイッチをオフにすることにより、上記並列状態を形成する、請求項3に記載の放電装置。 By turning off the first switch and the third switch and turning on the second switch, the series state is formed, and the first switch and the third switch are turned on and the second switch is turned on. The discharge device according to claim 3, wherein the parallel state is formed by turning off the power supply.
  5.  上記パルスパワー電源回路部は、上記スイッチとして、互いに直列接続された第4スイッチ(SW4)及び第5スイッチ(SW5)をさらに有し、最終段の上記回路ユニットは、上記スイッチ直列体及び上記コンデンサに、上記第4スイッチと上記第5スイッチとの直列体である付属スイッチ直列体(43)を、並列接続してあり、上記付属スイッチ直列体における上記第4スイッチと上記第5スイッチとの接続点(43M)が、上記パルス放電負荷の上記第1放電用電極に接続されている、請求項3又は4に記載の放電装置。 The pulse power power supply circuit unit further includes a fourth switch (SW4) and a fifth switch (SW5) connected in series as the switch, and the circuit unit in the final stage includes the switch series body and the capacitor In addition, an attached switch series body (43) which is a series body of the fourth switch and the fifth switch is connected in parallel, and the connection between the fourth switch and the fifth switch in the attached switch series body is performed. The discharge device according to claim 3 or 4, wherein the point (43M) is connected to the first discharge electrode of the pulse discharge load.
  6.  上記パルス放電負荷の上記誘電体層の容量成分から上記エネルギー蓄積部への電気エネルギーの回収を行う際には、上記第1スイッチ、上記第3スイッチ、及び上記第4スイッチをオンにすると共に上記第2スイッチ及び上記第5スイッチをオフにして、上記直列状態を形成し、その後、上記パルス放電負荷の電極間電圧が、上記直流電源の電源電圧まで低下したとき、上記第4スイッチをオフに切り替えるとともに、上記第5スイッチをオンに切り替えることで、上記パルス放電負荷の上記第1放電用電極と上記第2放電用電極とを短絡させるよう構成されている、請求項5に記載の放電装置。 When recovering electrical energy from the capacitive component of the dielectric layer of the pulse discharge load to the energy storage unit, the first switch, the third switch, and the fourth switch are turned on and The second switch and the fifth switch are turned off to form the series state, and then the fourth switch is turned off when the interelectrode voltage of the pulse discharge load drops to the power supply voltage of the DC power supply. 6. The discharge device according to claim 5, wherein the discharge device is configured to short-circuit the first discharge electrode and the second discharge electrode of the pulse discharge load by switching on the fifth switch. .
  7.  上記パルスパワー電源回路部は、1段目の上記回路ユニットと上記直流電源の正極との間に介在した電源保護ユニット(40)を、さらに有し、
     上記電源保護ユニットは、保護用ダイオード(401)と、該保護用ダイオードのアノードに接続された上記スイッチである第6スイッチ(SW6)と、上記保護用ダイオードと上記第6スイッチとの直列体である保護用直列体(44)に並列接続された上記コンデンサと、上記保護用直列体と上記コンデンサとの接続部である第3接続部(423)及び第4接続部(424)と、を有し、
     上記第3接続部が、1段目の上記回路ユニットの上記中間接続点に接続され、上記第4接続部と、上記直流電源の負極との間に、上記直列スイッチユニットの上記第3スイッチが介在し、上記第4接続部と1段目の上記回路ユニットの上記第2接続部との間にも、上記直列スイッチユニットの上記第3スイッチが介在している、請求項3~6のいずれか一項に記載の放電装置。
    The pulse power power circuit unit further includes a power protection unit (40) interposed between the circuit unit at the first stage and the positive electrode of the DC power source,
    The power protection unit includes a protection diode (401), a sixth switch (SW6) that is the switch connected to the anode of the protection diode, and a series body of the protection diode and the sixth switch. The capacitor connected in parallel to a certain protective series body (44), and a third connection part (423) and a fourth connection part (424) which are connection parts of the protective series body and the capacitor are provided. And
    The third connection portion is connected to the intermediate connection point of the circuit unit at the first stage, and the third switch of the series switch unit is connected between the fourth connection portion and the negative electrode of the DC power supply. The third switch of the series switch unit is interposed between the fourth connection portion and the second connection portion of the first-stage circuit unit. The discharge device according to claim 1.
  8.  上記パルスパワー電源回路部は、上記パルス放電負荷と直列接続される誘導成分(L)を有し、上記誘導成分は、上記パルス放電負荷の上記誘電体層の容量成分と共振可能に構成されており、上記誘導成分が、上記エネルギー蓄積部の少なくとも一部を構成している、請求項1~7のいずれか一項に記載の放電装置。 The pulse power power supply circuit unit has an inductive component (L) connected in series with the pulse discharge load, and the inductive component is configured to resonate with a capacitive component of the dielectric layer of the pulse discharge load. The discharge device according to any one of claims 1 to 7, wherein the inductive component constitutes at least a part of the energy storage unit.
  9.  上記パルスパワー電源回路部は、上記エネルギー蓄積部から上記パルス放電負荷への電気エネルギーの移動と、上記パルス放電負荷から上記エネルギー蓄積部への電気エネルギーの移動とを、上記誘導成分と上記容量成分との共振周期の間に実行するよう構成されている、請求項8に記載の放電装置。 The pulse power power supply circuit unit transfers the electric energy from the energy storage unit to the pulse discharge load and the electric energy transfer from the pulse discharge load to the energy storage unit. The discharge device according to claim 8, wherein the discharge device is configured to be executed during a resonance period of.
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JPH118043A (en) * 1997-06-19 1999-01-12 Takuma Co Ltd Self-discharge type spark gap switch and pulse power source device
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