WO2019205482A1 - Tft阵列基板 - Google Patents

Tft阵列基板 Download PDF

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Publication number
WO2019205482A1
WO2019205482A1 PCT/CN2018/107831 CN2018107831W WO2019205482A1 WO 2019205482 A1 WO2019205482 A1 WO 2019205482A1 CN 2018107831 W CN2018107831 W CN 2018107831W WO 2019205482 A1 WO2019205482 A1 WO 2019205482A1
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WO
WIPO (PCT)
Prior art keywords
opening
via hole
bottom edge
vertical direction
projection
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Ceased
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PCT/CN2018/107831
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English (en)
French (fr)
Inventor
廖作敏
李彦阳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/319,819 priority Critical patent/US11094718B2/en
Publication of WO2019205482A1 publication Critical patent/WO2019205482A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate.
  • a flat panel display device such as a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display has gradually replaced a cathode ray tube (CRT) display device.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • CRT cathode ray tube
  • the liquid crystal display device has many advantages such as thin body, power saving, no radiation, and the like, and has been widely used.
  • the liquid crystal display panel comprises a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the OLED generally includes a substrate, an anode disposed on the substrate, a Hole Inject Layer (HIL) disposed on the anode, and a Hole Transport Layer (HTL) disposed on the hole injection layer.
  • HIL Hole Inject Layer
  • HTL Hole Transport Layer
  • a light-emitting layer disposed on the hole transport layer
  • an electron transport layer ETL
  • EIL electron injection layer
  • the cathode on the layer.
  • the principle of luminescence of OLED display devices is that semiconductor materials and organic luminescent materials are driven by electric fields, causing luminescence by carrier injection and recombination.
  • a touch signal is generally input into a metal layer of the TFT array substrate.
  • the metal layer of the layer is connected to another metal layer above it, and the other metal layer is connected to the sensing terminal to realize touch display.
  • a conventional TFT array substrate includes a first metal layer 910 , a first insulating layer 920 disposed on the first metal layer 910 , and a second metal disposed on the first insulating layer 920 .
  • the second insulating layer 940 is provided with two first vias 941 located above the second metal layer 930 and two second vias 942 above the first metal layer 910.
  • the first insulating layer 920 is disposed on the first insulating layer 920.
  • a third via 921 is disposed above the first metal layer 910.
  • Each of the second vias 942 is located in a third via 921.
  • the indium tin oxide layer 950 passes through the first via 941 and the second via.
  • the indium tin oxide layer 950 is easily formed at the bottom edge of the first via 941 and the bottom edge of the second via 942. Breaking, the fracture will extend to the outside of the via. Referring to FIG. 3, when the fracture continues to extend to both sides of the indium tin oxide layer 950, the indium tin oxide layer 950 is broken into spaces and respectively associated with the first metal. The two portions of the layer 910 and the second metal layer 930 are connected, and the first metal layer 910 and the second metal layer 930 are no longer connected, which affects the realization of the function of the display panel, and the reliability is low.
  • An object of the present invention is to provide a TFT array substrate capable of avoiding breakage of a conductive layer due to electrostatic breakdown and having high reliability.
  • the present invention first provides a TFT array substrate, including a first conductive layer, a first insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the first insulating layer. a second conductive layer on the second conductive layer and the first insulating layer; and a third conductive layer disposed on the second insulating layer;
  • the second insulating layer is provided with a first via hole above the second conductive layer and a second via hole above the first conductive layer
  • the first insulating layer is provided with a first layer above the first conductive layer a third via hole, the second via hole is located in the third via hole
  • the third conductive layer is respectively connected to the second conductive layer and the first conductive layer via the first via hole and the second via hole;
  • the third conductive layer is provided with a first opening and a second opening.
  • the projection of the first opening in the vertical direction is located on one side of the bottom edge of the second via and one end protrudes from the bottom edge of the second via.
  • One end of the first via hole; the projection of the second opening in the vertical direction is located on one side of the bottom edge of the first via hole and one end protrudes from the bottom edge of the first via hole near the end of the second via hole.
  • the projection of the first opening in the vertical direction protrudes from the bottom of the second via hole near the end of the first via hole and the projection of the second opening in the vertical direction protrudes from the bottom edge of the first via hole to the second via hole
  • the sum of the lengths of the one end portion in the direction in which the first via hole and the second via hole are arranged is greater than or equal to the distance between the bottom edge of the first via hole and the bottom edge of the second via hole projected on the same horizontal plane;
  • the projections of the first opening and the second opening in the vertical direction are respectively located on two sides of the through-hole row composed of the first via hole and the second via hole;
  • the first opening and the second opening are both elongated; the extending direction of the first opening is parallel to the extending direction of the second opening.
  • the second insulating layer further includes a fourth via hole above the second conductive layer and a fifth via hole above the first conductive layer, wherein the first insulating layer is disposed above the first conductive layer a sixth via hole, the fifth via hole is located in the sixth via hole, and the third conductive layer is connected to the second conductive layer and the first conductive layer via the fourth via hole and the fifth via hole respectively;
  • the holes, the first via holes, the second via holes, and the fifth via holes are sequentially arranged in a row.
  • the other end of the first opening projecting in the vertical direction protrudes from the bottom edge of the second via hole near one end of the fifth via hole; the other end of the second opening protrudes from the other end of the projection in the vertical direction
  • the bottom edge of the via is near one end of the fourth via;
  • the third conductive layer is further provided with a spaced third opening and a fourth opening;
  • the projection of the third opening in the vertical direction is located on one side of the bottom edge of the fourth via hole, and one end protrudes from the bottom edge of the fourth via hole Adjacent to one end of the first via hole, the other end protrudes from an end of the fourth via hole away from the first via hole;
  • the projection of the fourth opening in the vertical direction is located on one side of the bottom edge of the fifth via hole, and one end protrudes
  • the bottom edge of the fifth via is close to one end of the second via, and the other end protrudes from the bottom edge of the fifth via away from the end of the second via;
  • the arrangement direction of the third opening and the first opening is parallel to the arrangement direction of the first via hole and the second via hole; the arrangement direction of the second opening and the fourth opening is the same as that of the first via hole and the second via hole
  • the alignment direction is parallel.
  • the projection of the first opening in the vertical direction protrudes from the bottom portion of the second via hole near the end of the fifth via hole and the projection of the fourth opening in the vertical direction protrudes from the bottom edge of the fifth via hole to the second via hole a sum of lengths of the one end portion in the direction in which the second via hole and the fifth via hole are arranged is greater than or equal to a distance between a bottom edge of the second via hole and a bottom edge of the fifth via hole;
  • the projection of the second opening in the vertical direction protrudes from the bottom of the first via hole near the end of the fourth via hole and the projection of the third opening in the vertical direction protrudes from the bottom edge of the fourth via hole to the first via hole a sum of a length of a portion of one end in a direction in which the fourth via hole and the first via hole are arranged is greater than or equal to a distance between a bottom edge of the fourth via hole and a bottom edge of the first via hole;
  • the third opening and the fourth opening are both elongated, and the extending directions of the third opening and the fourth opening are both parallel to the extending direction of the first opening; the extending direction of the first opening and the first through hole It is parallel to the arrangement direction of the second via holes.
  • the third conductive layer is further provided with a third opening, a fourth opening, a fifth opening, a sixth opening, a seventh opening and an eighth opening;
  • the projection of the third opening in the vertical direction is located on one side of the bottom edge of the first via hole, and one end protrudes from the bottom edge of the first via hole near one end of the fourth via hole; the projection of the fourth opening in the vertical direction a side of the bottom edge of the fourth via hole, and one end of the fourth via hole protrudes from the end of the first via hole; the projection of the fifth opening in the vertical direction is located at one side of the bottom edge of the fourth via hole.
  • the projection of the sixth opening in the vertical direction is located on one side of the bottom edge of the fifth via hole, and one end protrudes from the bottom edge of the fifth via hole to be close to the first edge
  • the projection of the seventh opening in the vertical direction is located on one side of the bottom edge of the second via, and one end protrudes from the bottom edge of the second via near the end of the fifth via
  • the eighth opening The projection in the vertical direction is located on one side of the bottom edge of the fifth via hole, and one end protrudes from the end of the bottom edge of the fifth via hole away from the second via hole;
  • the fifth opening, the third opening, the first opening and the sixth opening are sequentially arranged in a row, and the fifth opening, the third opening, the first opening and the sixth opening are arranged in the direction of the first via and the first The arrangement direction of the two via holes is parallel;
  • the fourth opening, the second opening, the seventh opening and the eighth opening are sequentially arranged in a row, and the fourth opening, the second opening, the seventh opening and the eighth opening are arranged in the direction of the first via and the first The arrangement of the two via holes is parallel.
  • the projection of the third opening in the vertical direction protrudes from the bottom portion of the first via hole near the end of the fourth via hole and the projection of the fourth opening in the vertical direction protrudes from the bottom edge of the fourth via hole near the end of the first via hole
  • the sum of the lengths of the portions in the direction in which the first via holes and the fourth via holes are arranged is greater than or equal to the distance between the bottom edges of the first via holes and the bottom edges of the fourth via holes;
  • the projection of the sixth opening in the vertical direction protrudes from the bottom edge of the fifth via hole near the end of the second via hole and the projection of the seventh opening in the vertical direction protrudes from the bottom edge of the second via hole near the end of the fifth via hole
  • the sum of the lengths of the portions in the direction in which the second via holes and the fifth via holes are arranged is greater than or equal to the distance between the bottom edges of the second via holes and the bottom edges of the fifth via holes;
  • the third opening, the fourth opening, the fifth opening, the sixth opening, the seventh opening, and the eighth opening are all elongated, and the third opening, the fourth opening, the fifth opening, the sixth opening, and the The extending directions of the seven openings and the eighth opening are both parallel to the extending direction of the first opening;
  • An angle between the extending direction of the first opening and the direction in which the first via hole and the second via hole are arranged is 45°.
  • the projection of the first opening in the vertical direction protrudes from the bottom edge of the second via hole near the end of the first via hole, and the length of the first via hole and the second via hole arrangement direction is greater than the first via hole.
  • the length in the direction in which one of the via holes and the second via holes are arranged is greater than the distance between the bottom edge of the first via hole and the bottom edge of the second via hole projected on the same horizontal plane;
  • the third conductive layer is further provided with a third opening, a fourth opening, a fifth opening, a sixth opening, a seventh opening, an eighth opening, a ninth opening and a tenth opening;
  • the projections of the third opening and the fourth opening in the vertical direction are respectively located on two sides of the bottom edge of the fourth via hole and one end protrudes from the end of the bottom edge of the fourth via hole near the first via hole; the third opening and The projection of the fourth opening in the vertical direction protrudes from the bottom edge of the fourth via hole near the end of the first via hole, and the lengths in the direction of the arrangement of the first via hole and the fourth via hole are larger than the bottom edge of the first via hole and the fourth The distance between the bottom edges of the vias;
  • the projections of the fifth opening and the sixth opening in the vertical direction are respectively located at two sides of the bottom edge of the fifth via hole and one end protrudes from one end of the bottom edge of the fifth via hole near the second via hole; the fifth opening and The projection of the sixth opening in the vertical direction protrudes from the bottom edge of the fifth via hole near the end of the second via hole in the direction of the arrangement of the second via hole and the fifth via hole is greater than the bottom edge of the second via hole and the fifth The distance between the bottom edges of the vias;
  • the projections of the seventh opening and the eighth opening in the vertical direction are respectively located on two sides of the bottom edge of the fourth via hole and one end protrudes from one end of the bottom edge of the fourth via hole away from the first via hole;
  • the projections of the ninth opening and the tenth opening in the vertical direction are respectively located on two sides of the bottom edge of the fifth via hole and one end protrudes from one end of the bottom edge of the fifth via hole away from the second via hole.
  • the third opening, the fourth opening, the fifth opening, the sixth opening, the seventh opening, the eighth opening, the ninth opening, and the tenth opening are all elongated, and the third opening, the fourth opening, and the fifth opening
  • the extending directions of the sixth opening, the seventh opening, the eighth opening, the ninth opening, and the tenth opening are all parallel to the extending direction of the first opening;
  • the direction in which the first opening extends is parallel to the direction in which the first via and the second via are arranged.
  • the third conductive layer is further provided with an eleventh opening, a twelfth opening, a thirteenth opening and a fourteenth opening; the eleventh opening, the twelfth opening, the thirteenth opening and the tenth
  • the four openings are long strips;
  • the projection of the eleventh opening in the vertical direction is located at an end of the bottom edge of the fourth via away from the first via and is connected to the seventh opening; the extending direction of the eleventh opening is perpendicular to the extending direction of the seventh opening ;
  • the projection of the twelfth opening in the vertical direction is located at an end of the bottom edge of the fourth via away from the first via and is connected to the eighth opening; the extending direction of the twelfth opening is perpendicular to the extending direction of the eighth opening ;
  • the projection of the thirteenth opening in the vertical direction is located at an end of the bottom edge of the fifth via away from the second via and is connected to the ninth opening; the extending direction of the thirteenth opening is perpendicular to the extending direction of the ninth opening ;
  • the projection of the fourteenth opening in the vertical direction is located at an end of the bottom edge of the fifth via away from the second via and is connected to the tenth opening; the extending direction of the fourteenth opening is perpendicular to the extending direction of the tenth opening .
  • the present invention provides a TFT array substrate provided with a third conductive layer through which the first conductive layer and the second conductive layer are respectively connected to the first conductive layer and the second conductive layer, and are disposed on the third conductive layer.
  • a first opening and a second opening the projection of the first opening in the vertical direction is located on one side of the bottom edge of the second via hole and the one end protrudes from the bottom edge of the second via hole near the end of the first via hole
  • the second opening is The projection in the vertical direction is located on one side of the bottom edge of the first via hole and one end protrudes from the bottom edge of the first via hole near the end of the second via hole, so that the third conductive layer is in the corresponding first via hole due to electrostatic breakdown
  • the first opening and the second opening can block the break, preventing the breakage from causing the first conductive layer to be disconnected from the second conductive layer, and ensuring the first conductive layer and the second conductive layer.
  • 1 is a schematic plan view of a conventional TFT array substrate
  • Figure 2 is a cross-sectional view taken along line A-A' of Figure 1;
  • FIG. 3 is a schematic view showing a fracture of an indium tin oxide layer of the TFT array substrate shown in FIG. 1 due to electrostatic breakdown;
  • FIG. 4 is a top plan view showing a first embodiment of a TFT array substrate of the present invention.
  • Figure 5 is a cross-sectional view taken along line B-B' of Figure 4.
  • FIG. 6 is a schematic view showing the third conductive layer of the first embodiment of the TFT array substrate of the present invention being broken due to electrostatic breakdown;
  • Figure 7 is a top plan view showing a second embodiment of the TFT array substrate of the present invention.
  • Fig. 8 is a top plan view showing a third embodiment of the TFT array substrate of the present invention.
  • the first embodiment of the TFT array substrate of the present invention includes a first conductive layer 100 , a first insulating layer 200 disposed on the first conductive layer 100 , and a first insulating layer 200 .
  • the first insulating layer 400 is provided with a first via hole 410 above the second conductive layer 300 and a second via hole 420 above the first conductive layer 100.
  • the first insulating layer 200 is provided on the first insulating layer 200.
  • a third via 210 above the conductive layer 100 and a second via 420 are located in the third via 210.
  • the third conductive layer 500 is connected to the second conductive layer 300 and the first conductive layer 100 via the first via 410 and the second via 420, respectively.
  • the third conductive layer 500 is provided with a first opening 510 and a second opening 520.
  • the projection of the first opening 510 in the vertical direction is located on one side of the bottom edge of the second via 420 and protrudes at one end.
  • the bottom edge of the via 420 is adjacent to one end of the first via 410; the projection of the second opening 520 in the vertical direction is located on one side of the bottom edge of the first via 410 and one end protrudes from the bottom edge of the first via 410 to the second edge One end of the via 420.
  • the projection of the first opening 510 in the vertical direction protrudes from the bottom edge of the second via hole 420 near the end of the first via 410 and the portion
  • the projection of the second opening 520 in the vertical direction protrudes from the bottom edge of the first via hole 410 near the end of the second via hole 420.
  • the sum of the lengths in the direction in which the first via hole 410 and the second via hole 420 are arranged is equal to the first pass.
  • the projection of the first opening 510 in the vertical direction may also be disposed to protrude from the bottom edge of the second via hole 420 near the end of the first via 410 and the second opening 520.
  • the projection in the vertical direction protrudes from the bottom edge of the first via hole 410 near the end of the second via hole 420, and the sum of the lengths in the direction in which the first via hole 410 and the second via hole 420 are arranged is larger than the bottom edge of the first via hole 410
  • the distance between the two when the bottom edge of the second via 420 is projected on the same level does not affect the implementation of the present invention.
  • the projections of the first opening 510 and the second opening 520 in the vertical direction are respectively located on two sides of the via column composed of the first via 410 and the second via 420 .
  • the first opening 510 and the second opening 520 are both elongated.
  • the extending direction of the first opening 510 is parallel to the extending direction of the second opening 520.
  • the second insulating layer 400 further includes a fourth via 440 above the second conductive layer 300 and a fifth via 450 above the first conductive layer 100 .
  • the first insulating layer 200 is provided with a sixth via hole 220 above the first conductive layer 100
  • the fifth via 450 is located in the sixth via 220
  • the third conductive layer 500 passes through the fourth via 440.
  • the fifth via 450 is connected to the second conductive layer 300 and the first conductive layer 100, respectively.
  • the fourth via 440, the first via 410, the second via 420, and the fifth via 450 are sequentially arranged in a row.
  • the other end of the first opening 510 protruding from the vertical direction protrudes from the bottom edge of the second via hole 420 near one end of the fifth via 450 .
  • the other end of the second opening 520 projecting from the vertical direction protrudes from the bottom edge of the first via hole 410 near one end of the fourth via hole 440.
  • the third conductive layer 500 is further provided with a third opening 530 and a fourth opening 540 which are spaced apart.
  • the projection of the third opening 530 in the vertical direction is located on one side of the bottom edge of the fourth via hole 440, and one end protrudes from the bottom edge of the fourth via hole 440 near one end of the first via hole 410, and the other end protrudes from the fourth via hole.
  • the bottom edge of the 440 is away from one end of the first via hole 410.
  • the projection of the fourth opening 540 in the vertical direction is located on one side of the bottom edge of the fifth via 450, and one end protrudes from the bottom edge of the fifth via 450 to the second edge.
  • One end of the hole 420 protrudes from the other end of the fifth through hole 450 away from the end of the second through hole 420.
  • the arrangement direction of the third opening 530 and the first opening 510 is parallel to the arrangement direction of the first via hole 410 and the second via hole 420.
  • the arrangement direction of the second opening 520 and the fourth opening 540 is parallel to the arrangement direction of the first via hole 410 and the second via hole 420.
  • the projection of the first opening 510 in the vertical direction protrudes from the bottom edge of the second via hole 420 near the end of the fifth via 450 and the portion
  • the projection of the fourth opening 540 in the vertical direction protrudes from the bottom edge of the fifth via 450 to the end of the second via 420.
  • the sum of the lengths of the second via 420 and the fifth via 450 is equal to the second pass.
  • the projection of the second opening 520 in the vertical direction protrudes from the bottom edge of the first via hole 410 near the end of the fourth via hole 440 and the projection of the third opening 530 in the vertical direction protrudes from the bottom edge of the fourth via hole 440
  • the sum of the lengths of the portions near the one end of the first via 410 in the direction in which the fourth via 440 and the first via 410 are arranged is equal to the distance between the bottom edge of the fourth via 440 and the bottom edge of the first via 410.
  • the projection of the first opening 510 in the vertical direction protrudes from the bottom edge of the second via hole 420 near the end of the fifth via 450 and the fourth opening 540 is vertical.
  • the projection of the direction protruding from the bottom edge of the fifth via 450 close to the end of the second via 420 may also be greater than the bottom edge of the second via 420 in the direction in which the second via 420 and the fifth via 450 are arranged. a distance from the bottom edge of the fifth via 450, the projection of the second opening 520 protruding in the vertical direction protruding from the bottom edge of the first via 410 near the end of the fourth via 440 and the third opening 530
  • the projection of the vertical direction protruding from the bottom edge of the fourth via hole 440 near the end of the first via hole 410 may also be greater than the length of the fourth via hole 440 in the direction in which the fourth via hole 440 and the first via hole 410 are arranged. The distance between the bottom edge and the bottom edge of the first via 410 does not affect the implementation of the present invention.
  • the third opening 530 and the fourth opening 540 are all elongated, and the third opening 530 and the fourth opening 540 extend in a direction parallel to the extending direction of the first opening 510 .
  • the extending direction of the first opening 510 is parallel to the arrangement direction of the first via hole 410 and the second via hole 420.
  • the material of the first conductive layer 100 and the second conductive layer 300 is metal
  • the material of the third conductive layer 500 is indium tin oxide (ITO).
  • the first opening 510 and the second opening 520 spaced apart on the third conductive layer 500 please refer to FIG. 6, in the third conductive layer 500.
  • the first via 410 and the second via 420 are broken by the electrostatic breakdown, the two ends of the first opening 510 and the second opening 520 cannot simultaneously extend outward until the first opening 510 and the second opening 520 are simultaneously broken.
  • the edges of the three conductive layers 500 are such that the third conductive layer 500 is always in communication as a whole, thereby ensuring the reliability of the connection between the first conductive layer 100 and the second conductive layer 300 that are in communication via the third conductive layer 500.
  • the fourth via 440 and the fifth via 450 are further disposed to increase the connection between the third conductive layer 500 and the second conductive layer 300 and the first conductive layer 100, respectively.
  • the first via 530 and the fourth opening 540 are disposed on the third conductive layer 500, and the first via 410 and the fourth via 440 are adjacent to each other in the third conductive layer 500 due to electrostatic breakdown.
  • the edge is broken, due to the presence of the third opening 530 and the second opening 520, the two ends of the fracture cannot continue to extend outward to the edge of the third conductive layer 500 at the same time, so that the third conductive layer 500 is always connected as a whole to ensure communication.
  • the third conductive layer 500 is broken at the edge where the second via 420 and the fifth via 450 are close to each other due to electrostatic breakdown, the first opening 510 and the fourth opening 540 are broken due to the presence of the first opening 510 and the fourth opening 540.
  • the two ends cannot continue to extend outward to the edge of the third conductive layer 500 at the same time, so that the third conductive layer 500 is always connected as a whole, thereby ensuring the reliability of the connection.
  • the second embodiment of the TFT array substrate of the present invention is different from the above-described first embodiment in that the other end of the projection of the first opening 510' in the vertical direction is not prominent.
  • the bottom edge of the second via 420 is adjacent to one end of the fifth via 450.
  • the other end of the projection of the second opening 520' in the vertical direction does not protrude from the bottom edge of the first via hole 410 near one end of the fourth via hole 440.
  • the third conductive layer 500' is further provided with a spaced third opening 530', a fourth opening 540', a fifth opening 550', a sixth opening 560', a seventh opening 570', and an eighth opening 580'.
  • the projection of the third opening 530' in the vertical direction is located on one side of the bottom edge of the first via hole 410, and one end protrudes from the bottom edge of the first via hole 410 near one end of the fourth via hole 440.
  • the projection of the fourth opening 540' in the vertical direction is located on one side of the bottom edge of the fourth via 440, and one end protrudes from the bottom edge of the fourth via 440 near the end of the first via 410.
  • the projection of the fifth opening 550' in the vertical direction is located on one side of the bottom edge of the fourth via hole 440, and one end protrudes from the end of the bottom edge of the fourth via hole 440 away from the first via hole 410.
  • the projection of the sixth opening 560' in the vertical direction is located on one side of the bottom edge of the fifth via 450, and one end protrudes from the bottom edge of the fifth via 450 near the end of the second via 420.
  • the projection of the seventh opening 570' in the vertical direction is located on one side of the bottom edge of the second via hole 420, and one end protrudes from the bottom edge of the second via hole 420 near one end of the fifth via hole 450.
  • the projection of the eighth opening 580' in the vertical direction is located on one side of the bottom edge of the fifth via 450, and one end protrudes from the bottom edge of the fifth via 450 away from the end of the second via 420.
  • the fifth opening 550', the third opening 530', the first opening 510', and the sixth opening 560' are sequentially arranged in a row, and The arrangement direction of the fifth opening 550', the third opening 530', the first opening 510', and the sixth opening 560' is parallel to the arrangement direction of the first via hole 410 and the second via hole 420.
  • the fourth opening 540', the second opening 520', the seventh opening 570', and the eighth opening 580' are sequentially arranged in a row, and the fourth opening 540', the second opening 520', and the seventh opening 570'
  • the arrangement direction of the eighth opening 580' is parallel to the arrangement direction of the first via hole 410 and the second via hole 420.
  • the projection of the third opening 530' in the vertical direction protrudes from the bottom of the first via hole 410 near the end of the fourth via 440 and the projection of the fourth opening 540' in the vertical direction.
  • the sum of the lengths of the portions of the fourth via hole 440 near the end of the first via hole 410 in the direction in which the first via hole 410 and the fourth via hole 440 are arranged is larger than the bottom edge of the first via hole 410 and the fourth via hole 440. The distance between the bottom edges.
  • the projection of the sixth opening 560' in the vertical direction protrudes from the bottom edge of the fifth via 450 near the end of the second via 420 and the projection of the seventh opening 570' in the vertical direction protrudes from the bottom of the second via 420
  • the sum of the lengths of the portions near the end of the fifth via 450 in the direction in which the second via 420 and the fifth via 450 are arranged is greater than the distance between the bottom edge of the second via 420 and the bottom edge of the fifth via 450.
  • the projection of the third opening 530 ′ in the vertical direction protrudes from the bottom edge of the first via hole 410 near the end of the fourth via hole 440 and the fourth opening 540 ′ in the vertical direction.
  • the projection of the direction protruding from the bottom edge of the fourth via 440 near the end of the first via 410 may be equal to the sum of the lengths of the first via 410 and the fourth via 440 in the direction of the arrangement of the first via 410 and the bottom edge of the first via 410.
  • the sum of the lengths of the portions near the end of the fifth via 450 in the direction in which the second via 420 and the fifth via 450 are arranged may also be equal to the difference between the bottom edge of the second via 420 and the bottom edge of the fifth via 450. Distance does not affect the implementation of the present invention.
  • the third opening 530 ′, the fourth opening 540 ′, the fifth opening 550 ′, the sixth opening 560 ′, the seventh opening 570 ′, and the eighth opening 580 ′ are all elongated, and the third The extending direction of the opening 530', the fourth opening 540', the fifth opening 550', the sixth opening 560', the seventh opening 570', and the eighth opening 580' are all parallel to the extending direction of the first opening 510'.
  • An angle between the extending direction of the first opening 510' and the direction in which the first via hole 410 and the second via hole 420 are arranged is 45°.
  • the first opening 510 ′ and the second opening 520 ′ are disposed on the third conductive layer 500 ′, and the first opening 510 ′ and the second opening 520 ′ are used.
  • the third conductive layer 500' is also A third opening 530 ′, a fourth opening 540 ′, a fifth opening 550 ′, a sixth opening 560 ′, a seventh opening 570 ′, and an eighth opening 580 ′ are disposed, and the third opening 530 ′ and the fourth opening 540 are utilized.
  • the third embodiment of the TFT array substrate of the present invention is different from the above-described first embodiment in that the other end of the projection of the first opening 510" in the vertical direction is not prominent.
  • the bottom edge of the second via 420 is adjacent to one end of the fifth via 450.
  • the other end of the projection of the second opening 520" in the vertical direction does not protrude from the bottom edge of the first via 410 near the end of the fourth via 440 .
  • the projection of the first opening 510 ′ in the vertical direction protrudes from the bottom edge of the second via hole 420 near the end of the first via hole 410 in the direction in which the first via hole 410 and the second via hole 420 are arranged in a direction larger than the first
  • the distance between the bottom edge of the via 410 and the bottom edge of the second via 420 is projected on the same horizontal plane.
  • the projection of the second opening 520" in the vertical direction protrudes from the bottom edge of the first via 410 to the second edge.
  • the length of the portion of one end of the via hole 420 in the direction in which the first via hole 410 and the second via hole 420 are arranged is larger than when the bottom edge of the first via hole 410 is projected on the same horizontal plane as the bottom edge of the second via hole 420. distance.
  • the third conductive layer 500" is further provided with a third opening 530", a fourth opening 540", a fifth opening 550", and a sixth The opening 560", the seventh opening 570", the eighth opening 580", the ninth opening 590", and the tenth opening 5100".
  • the projections of the third opening 530 ′′ and the fourth opening 540 ′′ in the vertical direction are respectively located on two sides of the bottom edge of the fourth via hole 440 and one end protrudes from the bottom edge of the fourth via hole 440 near the end of the first via hole 410 .
  • the projection of the third opening 530" and the fourth opening 540" in the vertical direction protrudes from the bottom portion of the fourth via hole 440 near the end of the first via hole 410 in the first via hole 410 and the fourth via hole 440.
  • the length in the direction is greater than the distance between the bottom edge of the first via 410 and the bottom edge of the fourth via 440.
  • the projections of the fifth opening 550" and the sixth opening 560" in the vertical direction are respectively located on both sides of the bottom edge of the fifth via 450 and one end protrudes from the bottom edge of the fifth via 450 near the end of the second via 420.
  • a projection of the fifth opening 550" and the sixth opening 560" in the vertical direction protrudes from a portion of the bottom edge of the fifth via 450 near the end of the second via 420 in the second via 420 and the fifth via 450
  • the length in the direction is greater than the distance between the bottom edge of the second via 420 and the bottom edge of the fifth via 450.
  • the projections of the seventh opening 570" and the eighth opening 580" in the vertical direction are respectively located at two sides of the bottom edge of the fourth via hole 440 and one end protrudes from the end of the bottom edge of the fourth via hole 440 away from the first via hole 410. .
  • the projections of the ninth opening 590" and the tenth opening 5100" in the vertical direction are respectively located on both sides of the bottom edge of the fifth via 450 and one end protrudes from the end of the bottom edge of the fifth via 450 away from the second via 420. .
  • the tenth opening 5100 is a strip shape, a third opening 530", a fourth opening 540", a fifth opening 550", a sixth opening 560", a seventh opening 570", an eighth opening 580", and a
  • the extending direction of the nine opening 590" and the tenth opening 5100" is parallel to the extending direction of the first opening 510".
  • the extending direction of the first opening 510" is parallel to the direction in which the first via hole 410 and the second via hole 420 are arranged.
  • the third conductive layer 500" is further provided with a spaced eleventh opening 5110", a twelfth opening 5120", and a thirteenth opening 5130. And the fourteenth opening 5140.
  • the eleventh opening 5110", the twelfth opening 5120", the thirteenth opening 5130", and the fourteenth opening 5140" are all elongated.
  • the projection of the eleventh opening 5110" in the vertical direction is located at an end of the bottom edge of the fourth via 440 away from the first via 410 and is connected to the seventh opening 570".
  • the extending direction of the eleventh opening 5110" is perpendicular to the extending direction of the seventh opening 570".
  • the projection of the twelfth opening 5120" in the vertical direction is located at one end of the bottom edge of the fourth via 440 away from the first via 410 and is connected to the eighth opening 580".
  • the extending direction of the twelfth opening 5120" is perpendicular to the extending direction of the eighth opening 580".
  • the projection of the thirteenth opening 5130" in the vertical direction is located at one end of the bottom edge of the fifth via 450 away from the second via 420 and is connected to the ninth opening 590".
  • the extending direction of the thirteenth opening 5130" is perpendicular to the extending direction of the ninth opening 590".
  • the projection of the fourteenth opening 5140" in the vertical direction is located at one end of the bottom edge of the fifth via 450 away from the second via 420 and is connected to the tenth opening 5100".
  • the extending direction of the fourteenth opening 5140" is perpendicular to the extending direction of the tenth opening 5100".
  • the third embodiment of the TFT array substrate of the present invention is provided with a first opening 510" and a second opening 520" on the third conductive layer 500", and the first opening 510" and the second opening 520" are used to make The two ends of the fracture formed at the edges of the first via hole 410 and the second via hole 420 which are adjacent to each other cannot continue to extend outward until the edge of the third conductive layer 500", and at the same time, the third conductive layer 500"
  • a third opening 530", a fourth opening 540", a fifth opening 550", a sixth opening 560", a seventh opening 570", an eighth opening 580", a ninth opening 590", and a tenth opening 5100" are disposed thereon.
  • the third opening 530 ′′ and the fourth opening 540 ′′ are used to prevent the two ends of the rupture formed at the edges of the first via hole 410 and the fourth via hole 440 from continuing to extend outward until the third conductive layer 500 ”
  • the edge is shaped by the seventh opening 570" and the eighth opening 580"
  • the two ends of the fracture at the edge of the fourth via 440 away from the first via 410 cannot continue to extend outward until the edge of the third conductive layer 500", using the ninth opening 590", the tenth opening 5100"
  • Both ends of the fracture formed at the edge of the fifth via 450 away from the second via 420 cannot continue to extend outward until the edge of the third conductive layer 500", and further, are also disposed on the third conductive layer 500"
  • the TFT array substrate of the present invention is provided with a third conductive layer connecting the first conductive layer and the second conductive layer through the first via hole and the second via hole, respectively, and the first gap is disposed on the third conductive layer.
  • the opening and the second opening, the projection of the first opening in the vertical direction is located on one side of the bottom edge of the second via hole and the one end protrudes from the bottom end of the second via hole near the end of the first via hole, and the second opening is in the vertical direction Projecting is located on one side of the bottom edge of the first via hole and one end protrudes from the bottom edge of the first via hole near the end of the second via hole, so that the third conductive layer is corresponding to the first via hole and the second via hole due to electrostatic breakdown
  • the first opening and the second opening can block the fracture, preventing the first conductive layer from being disconnected from the second conductive layer, and ensuring reliable connection between the first conductive layer and the second conductive layer. Sex, improve the quality of products

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Abstract

本发明提供一种TFT阵列基板。该TFT阵列基板设置第三导电层通过第一过孔及第二过孔分别连接第一导电层及第二导电层，并在第三导电层上设置间隔的第一开口与第二开口，第一开口在竖直方向的投影位于第二过孔底部边缘的一侧且一端突出第二过孔底部边缘靠近第一过孔的一端，第二开口在竖直方向的投影位于第一过孔底部边缘的一侧且一端突出第一过孔底部边缘靠近第二过孔的一端，从而在第三导电层因静电击穿而在对应第一过孔与第二过孔互相靠近的边缘产生断裂时，第一开口及第二开口能够对断裂进行阻隔，防止断裂导致第一导电层与第二导电层断开，保证第一导电层与第二导电层连接的可靠性，提升产品的品质。

Description

TFT阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板。
背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
OLED通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层(Hole Inject Layer，HIL)、设于空穴注入层上的空穴传输层(Hole Transport Layer，HTL)、设于空穴传输层上的发光层、设于发光层上的电子传输层(Electron Transport Layer，ETL)、设于电子传输层上的电子注入层(Electron Inject Layer，EIL)及设于电子注入层上的阴极。OLED显示器件的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。
现有的显示面板的设计中，常有需要将两层互相绝缘的金属层进行连接的设计，例如采用触屏技术的显示面板中，一般将触控信号输入TFT阵列基板的一层金属层，并使该层金属层与其上方的另一层金属层连接，由该另一层金属层与感测端子连接，从而实现触控显示。请参阅图1及图2，现有的一种TFT阵列基板包括第一金属层910、设于第一金属层910上的第一绝缘层920、设于第一绝缘层920上的第二金属层930、设于第一绝缘层920及第二金属层930上的第二绝缘层940及设于第二绝缘层940上的氧化铟锡层950。所述第二绝缘层940上设有位于第二金属层930上方的两 个第一过孔941及位于第一金属层910上方的两个第二过孔942，所述第一绝缘层920上设有位于第一金属层910上方的第三过孔921，每一第二过孔942对应位于一第三过孔921内，氧化铟锡层950穿过第一过孔941及第二过孔942分别与第二金属层930及第一金属层910连接，从而实现第一金属层910与第二金属层930之间的连接。当工艺制程产生以及外界进入的静电在氧化铟锡层950上积累，会产生静电击穿效应，使得氧化铟锡层950容易在第一过孔941的底部边缘及第二过孔942的底部边缘处断裂，该断裂会向过孔外部延伸，请参阅图3，当断裂不断延伸直至氧化铟锡层950的两侧边缘后，会导致氧化铟锡层950断裂为间隔的且分别与第一金属层910及第二金属层930连接的两个部分，此时第一金属层910与第二金属层930不再连接，影响显示面板的功能的实现，可靠性较低。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够避免由于静电击穿导致的导电层断裂，可靠性高。
为实现上述目的，本发明首先提供一种TFT阵列基板，包括第一导电层、设于第一导电层上的第一绝缘层、设于第一绝缘层上的第二导电层、设于第二导电层及第一绝缘层上的第二绝缘层以及设于第二绝缘层上的第三导电层；
所述第二绝缘层上设有位于第二导电层上方的第一过孔及位于第一导电层上方的第二过孔，所述第一绝缘层上设有位于第一导电层上方的第三过孔，第二过孔位于第三过孔内；第三导电层经第一过孔及第二过孔分别与第二导电层及第一导电层连接；
所述第三导电层上设有间隔的第一开口与第二开口，所述第一开口在竖直方向的投影位于第二过孔底部边缘的一侧且一端突出第二过孔底部边缘靠近第一过孔的一端；所述第二开口在竖直方向的投影位于第一过孔底部边缘的一侧且一端突出第一过孔底部边缘靠近第二过孔的一端。
所述第一开口在竖直方向的投影突出第二过孔底部边缘靠近第一过孔一端的部分与所述第二开口在竖直方向的投影突出第一过孔底部边缘靠近第二过孔一端的部分在第一过孔和第二过孔排列方向上的长度之和大于等于第一过孔底部边缘与第二过孔底部边缘投影在同一水平面上时两者之间的距离；
所述第一开口及第二开口在竖直方向的投影分别位于由第一过孔及第二过孔组成的过孔列的两侧；
所述第一开口及第二开口均为长条状；所述第一开口的延伸方向与第二开口的延伸方向平行。
所述第二绝缘层上还设有位于第二导电层上方的第四过孔及位于第一导电层上方的第五过孔，所述第一绝缘层上设有位于第一导电层上方的第六过孔，第五过孔位于第六过孔内，所述第三导电层经第四过孔与第五过孔分别与第二导电层及第一导电层连接；所述第四过孔、第一过孔、第二过孔及第五过孔依次设置排成一列。
可选地，所述第一开口在竖直方向的投影的另一端突出第二过孔底部边缘靠近第五过孔的一端；所述第二开口在竖直方向的投影的另一端突出第一过孔底部边缘靠近第四过孔的一端；
所述第三导电层还设有间隔的第三开口及第四开口；所述第三开口在竖直方向的投影位于第四过孔底部边缘的一侧，且一端突出第四过孔底部边缘靠近第一过孔的一端，另一端突出第四过孔底部边缘远离第一过孔的一端；所述第四开口在竖直方向的投影位于第五过孔底部边缘的一侧，且一端突出第五过孔底部边缘靠近第二过孔的一端，另一端突出第五过孔底部边缘远离第二过孔的一端；
所述第三开口和第一开口的排列方向与第一过孔和第二过孔的排列方向平行；所述第二开口和第四开口的排列方向与第一过孔和第二过孔的排列方向平行。
所述第一开口在竖直方向的投影突出第二过孔底部边缘靠近第五过孔一端的部分与所述第四开口在竖直方向的投影突出第五过孔底部边缘靠近第二过孔一端的部分在第二过孔和第五过孔排列方向上的长度之和大于等于第二过孔的底部边缘与第五过孔底部边缘之间的距离；
所述第二开口在竖直方向的投影突出第一过孔底部边缘靠近第四过孔一端的部分与所述第三开口在竖直方向的投影突出第四过孔底部边缘靠近第一过孔一端的部分在第四过孔和第一过孔排列方向上的长度之和大于等于第四过孔的底部边缘与第一过孔底部边缘之间的距离；
所述第三开口及第四开口均为长条状，所述第三开口及第四开口的延伸方向均与第一开口的延伸方向平行；所述第一开口的延伸方向与第一过孔和第二过孔的排列方向平行。
可选地，所述第三导电层还设有间隔的第三开口、第四开口、第五开口、第六开口、第七开口及第八开口；
所述第三开口在竖直方向的投影位于第一过孔底部边缘的一侧，且一端突出第一过孔底部边缘靠近第四过孔的一端；所述第四开口在竖直方向 的投影位于第四过孔底部边缘的一侧，且一端突出第四过孔底部边缘靠近第一过孔的一端；所述第五开口在竖直方向的投影位于第四过孔底部边缘的一侧，且一端突出第四过孔底部边缘远离第一过孔的一端；所述第六开口在竖直方向的投影位于第五过孔底部边缘的一侧，且一端突出第五过孔底部边缘靠近第二过孔的一端；所述第七开口在竖直方向的投影位于第二过孔底部边缘的一侧，且一端突出第二过孔底部边缘靠近第五过孔的一端；所述第八开口在竖直方向的投影位于第五过孔底部边缘的一侧，且一端突出第五过孔底部边缘远离第二过孔的一端；
所述第五开口、第三开口、第一开口及第六开口依次排成一列，且所述第五开口、第三开口、第一开口和第六开口的排列方向与第一过孔和第二过孔的排列方向平行；
所述第四开口、第二开口、第七开口及第八开口依次排成一列，且所述第四开口、第二开口、第七开口和第八开口的排列方向与第一过孔和第二过孔的排列方向平行。
所述第三开口在竖直方向的投影突出第一过孔底部边缘靠近第四过孔一端的部分与第四开口在竖直方向的投影突出第四过孔底部边缘靠近第一过孔一端的部分在第一过孔和第四过孔排列方向上的长度之和大于等于第一过孔底部边缘与第四过孔底部边缘之间的距离；
所述第六开口在竖直方向的投影突出第五过孔底部边缘靠近第二过孔一端的部分与第七开口在竖直方向的投影突出第二过孔底部边缘靠近第五过孔一端的部分在第二过孔和第五过孔排列方向上的长度之和大于等于第二过孔底部边缘与第五过孔底部边缘之间的距离；
所述第三开口、第四开口、第五开口、第六开口、第七开口及第八开口均为长条状，所述第三开口、第四开口、第五开口、第六开口、第七开口及第八开口的延伸方向均与第一开口的延伸方向平行；
所述第一开口的延伸方向与第一过孔和第二过孔的排列方向之间的夹角为45°。
可选地，所述第一开口在竖直方向的投影突出第二过孔底部边缘靠近第一过孔一端的部分在第一过孔和第二过孔排列方向上的长度大于第一过孔底部边缘与第二过孔底部边缘投影在同一水平面上时两者之间的距离；所述第二开口在竖直方向的投影突出第一过孔底部边缘靠近第二过孔一端的部分在第一过孔和第二过孔排列方向上的长度大于第一过孔底部边缘与第二过孔底部边缘投影在同一水平面上时两者之间的距离；
所述第三导电层还设有间隔的第三开口、第四开口、第五开口、第六 开口、第七开口、第八开口、第九开口、第十开口；
所述第三开口及第四开口在竖直方向的投影分别位于第四过孔底部边缘的两侧且一端均突出第四过孔底部边缘靠近第一过孔的一端；所述第三开口及第四开口在竖直方向的投影突出第四过孔底部边缘靠近第一过孔一端的部分在第一过孔和第四过孔排列方向上的长度均大于第一过孔底部边缘与第四过孔底部边缘之间的距离；
所述第五开口及第六开口在竖直方向的投影分别位于第五过孔底部边缘的两侧且一端均突出第五过孔底部边缘靠近第二过孔的一端；所述第五开口及第六开口在竖直方向的投影突出第五过孔底部边缘靠近第二过孔一端的部分在第二过孔和第五过孔排列方向上的长度均大于第二过孔底部边缘与第五过孔底部边缘之间的距离；
所述第七开口及第八开口在竖直方向的投影分别位于第四过孔底部边缘的两侧且一端均突出第四过孔底部边缘远离第一过孔的一端；
所述第九开口及第十开口在竖直方向的投影分别位于第五过孔底部边缘的两侧且一端均突出第五过孔底部边缘远离第二过孔的一端。
所述第三开口、第四开口、第五开口、第六开口、第七开口、第八开口、第九开口、第十开口均为长条状，第三开口、第四开口、第五开口、第六开口、第七开口、第八开口、第九开口、第十开口的延伸方向均与第一开口的延伸方向平行；
第一开口的延伸方向与第一过孔和第二过孔的排列方向平行。
所述第三导电层还设有间隔的第十一开口、第十二开口、第十三开口及第十四开口；所述第十一开口、第十二开口、第十三开口及第十四开口均为长条状；
所述第十一开口在竖直方向的投影位于第四过孔底部边缘远离第一过孔的一端且与第七开口连接；所述第十一开口的延伸方向与第七开口的延伸方向垂直；
所述第十二开口在竖直方向的投影位于第四过孔底部边缘远离第一过孔的一端且与第八开口连接；所述第十二开口的延伸方向与第八开口的延伸方向垂直；
所述第十三开口在竖直方向的投影位于第五过孔底部边缘远离第二过孔的一端且与第九开口连接；所述第十三开口的延伸方向与第九开口的延伸方向垂直；
所述第十四开口在竖直方向的投影位于第五过孔底部边缘远离第二过孔的一端且与第十开口连接；所述第十四开口的延伸方向与第十开口的延 伸方向垂直。
本发明的有益效果：本发明提供的一种TFT阵列基板设置第三导电层通过第一过孔及第二过孔分别连接第一导电层及第二导电层，并在第三导电层上设置间隔的第一开口与第二开口，第一开口在竖直方向的投影位于第二过孔底部边缘的一侧且一端突出第二过孔底部边缘靠近第一过孔的一端，第二开口在竖直方向的投影位于第一过孔底部边缘的一侧且一端突出第一过孔底部边缘靠近第二过孔的一端，从而在第三导电层因静电击穿而在对应第一过孔与第二过孔互相靠近的边缘产生断裂时，第一开口及第二开口能够对断裂进行阻隔，防止断裂导致第一导电层与第二导电层断开，保证第一导电层与第二导电层连接的可靠性，提升产品的品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种TFT阵列基板的俯视示意图；
图2为沿图1中的A-A’线的剖视示意图；
图3为图1所示的TFT阵列基板的氧化铟锡层因静电击穿而发生断裂的示意图；
图4为本发明的TFT阵列基板的第一实施例的俯视示意图；
图5为沿图4中的B-B’线的剖视示意图；
图6为本发明的TFT阵列基板的第一实施例的第三导电层因静电击穿而发生断裂的示意图；
图7为本发明的TFT阵列基板的第二实施例的俯视示意图；
图8为本发明的TFT阵列基板的第三实施例的俯视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4及图5，本发明的TFT阵列基板的第一实施例包括第一导电层100、设于第一导电层100上的第一绝缘层200、设于第一绝缘层200上的第二导电层300、设于第二导电层300及第一绝缘层200上的第二绝缘 层400以及设于第二绝缘层400上的第三导电层500。
所述第二绝缘层400上设有位于第二导电层300上方的第一过孔410及位于第一导电层100上方的第二过孔420，所述第一绝缘层200上设有位于第一导电层100上方的第三过孔210，第二过孔420位于第三过孔210内。第三导电层500经第一过孔410及第二过孔420分别与第二导电层300及第一导电层100连接。
所述第三导电层500上设有间隔的第一开口510与第二开口520，所述第一开口510在竖直方向的投影位于第二过孔420底部边缘的一侧且一端突出第二过孔420底部边缘靠近第一过孔410的一端；所述第二开口520在竖直方向的投影位于第一过孔410底部边缘的一侧且一端突出第一过孔410底部边缘靠近第二过孔420的一端。
具体地，请参阅图4，在本发明的第一实施例中，所述第一开口510在竖直方向的投影突出第二过孔420底部边缘靠近第一过孔410一端的部分与所述第二开口520在竖直方向的投影突出第一过孔410底部边缘靠近第二过孔420一端的部分在第一过孔410和第二过孔420排列方向上的长度之和等于第一过孔410底部边缘与第二过孔420底部边缘投影在同一水平面上时两者之间的距离。当然，在本发明的其他实施例中，也可设置所述第一开口510在竖直方向的投影突出第二过孔420底部边缘靠近第一过孔410一端的部分与所述第二开口520在竖直方向的投影突出第一过孔410底部边缘靠近第二过孔420一端的部分在第一过孔410和第二过孔420排列方向上的长度之和大于第一过孔410底部边缘与第二过孔420底部边缘投影在同一水平面上时两者之间的距离，并不会影响本发明的实现。
优选地，请参阅图4，所述第一开口510及第二开口520在竖直方向的投影分别位于由第一过孔410及第二过孔420组成的过孔列的两侧。所述第一开口510及第二开口520均为长条状。所述第一开口510的延伸方向与第二开口520的延伸方向平行。
具体地，请参阅图4及图5，所述第二绝缘层400上还设有位于第二导电层300上方的第四过孔440及位于第一导电层100上方的第五过孔450，所述第一绝缘层200上设有位于第一导电层100上方的第六过孔220，第五过孔450位于第六过孔220内，所述第三导电层500经第四过孔440与第五过孔450分别与第二导电层300及第一导电层100连接。所述第四过孔440、第一过孔410、第二过孔420及第五过孔450依次设置排成一列。
进一步地，请参阅图4，所述第一开口510在竖直方向的投影的另一端突出第二过孔420底部边缘靠近第五过孔450的一端。所述第二开口520 在竖直方向的投影的另一端突出第一过孔410底部边缘靠近第四过孔440的一端。所述第三导电层500还设有间隔的第三开口530及第四开口540。所述第三开口530在竖直方向的投影位于第四过孔440底部边缘的一侧，且一端突出第四过孔440底部边缘靠近第一过孔410的一端，另一端突出第四过孔440底部边缘远离第一过孔410的一端，所述第四开口540在竖直方向的投影位于第五过孔450底部边缘的一侧，且一端突出第五过孔450底部边缘靠近第二过孔420的一端，另一端突出第五过孔450底部边缘远离第二过孔420的一端。
具体地，所述第三开口530和第一开口510的排列方向与第一过孔410和第二过孔420的排列方向平行。所述第二开口520和第四开口540的排列方向与第一过孔410和第二过孔420的排列方向平行。
具体地，请参阅图4，在本发明的第一实施例中，所述第一开口510在竖直方向的投影突出第二过孔420底部边缘靠近第五过孔450一端的部分与所述第四开口540在竖直方向的投影突出第五过孔450底部边缘靠近第二过孔420一端的部分在第二过孔420和第五过孔450排列方向上的长度之和等于第二过孔420的底部边缘与第五过孔450底部边缘之间的距离。所述第二开口520在竖直方向的投影突出第一过孔410底部边缘靠近第四过孔440一端的部分与所述第三开口530在竖直方向的投影突出第四过孔440底部边缘靠近第一过孔410一端的部分在第四过孔440和第一过孔410排列方向上的长度之和等于第四过孔440的底部边缘与第一过孔410底部边缘之间的距离。当然，在本发明的其他实施例中，所述第一开口510在竖直方向的投影突出第二过孔420底部边缘靠近第五过孔450一端的部分与所述第四开口540在竖直方向的投影突出第五过孔450底部边缘靠近第二过孔420一端的部分在第二过孔420和第五过孔450排列方向上的长度之和也可以大于第二过孔420的底部边缘与第五过孔450底部边缘之间的距离，所述第二开口520在竖直方向的投影突出第一过孔410底部边缘靠近第四过孔440一端的部分与所述第三开口530在竖直方向的投影突出第四过孔440底部边缘靠近第一过孔410一端的部分在第四过孔440和第一过孔410排列方向上的长度之和也可以大于第四过孔440的底部边缘与第一过孔410底部边缘之间的距离，这并不会影响本发明的实现。
优选地，请参阅图4，所述第三开口530及第四开口540均为长条状，所述第三开口530及第四开口540的延伸方向均与第一开口510的延伸方向平行。所述第一开口510的延伸方向与第一过孔410和第二过孔420的排列方向平行。
具体地，所述第一导电层100及第二导电层300的材料为金属，第三导电层500的材料为氧化铟锡(ITO)。
需要说明的是，本发明的TFT阵列基板的第一实施例中，通过在第三导电层500上设置间隔的第一开口510与第二开口520，请参阅图6，在第三导电层500因静电击穿而在第一过孔410与第二过孔420互相靠近的边缘产生断裂时，由于第一开口510及第二开口520的存在，断裂的两端无法同时继续向外延伸直至第三导电层500的边缘，使得第三导电层500整体始终连通，从而保证经第三导电层500连通的第一导电层100及第二导电层300之间的连接的可靠性。进一步的，本发明的第一实施例中，还设置第四过孔440及第五过孔450，分别增加了第三导电层500与第二导电层300及第一导电层100之间的连接通路，保证连接效果，同时在第三导电层500上设置第三开口530及第四开口540，在第三导电层500因静电击穿而在第一过孔410与第四过孔440互相靠近的边缘产生断裂时，由于第三开口530及第二开口520的存在，断裂的两端无法同时继续向外延伸直至第三导电层500的边缘，使得第三导电层500整体始终连通，保证连通的可靠性，而在第三导电层500因静电击穿而在第二过孔420与第五过孔450互相靠近的边缘产生断裂时，由于第一开口510及第四开口540的存在，断裂的两端无法同时继续向外延伸直至第三导电层500的边缘，使得第三导电层500整体始终连通，保证连通的可靠性。
请参阅图7，并结合图5，本发明的TFT阵列基板的第二实施例与上述第一实施例的区别在于，所述第一开口510’在竖直方向的投影的另一端并不突出第二过孔420底部边缘靠近第五过孔450的一端。所述第二开口520’在竖直方向的投影的另一端并不突出第一过孔410底部边缘靠近第四过孔440的一端。所述第三导电层500’还设有间隔的第三开口530’、第四开口540’、第五开口550’、第六开口560’、第七开口570’及第八开口580’。所述第三开口530’在竖直方向的投影位于第一过孔410底部边缘的一侧，且一端突出第一过孔410底部边缘靠近第四过孔440的一端。所述第四开口540’在竖直方向的投影位于第四过孔440底部边缘的一侧，且一端突出第四过孔440底部边缘靠近第一过孔410的一端。所述第五开口550’在竖直方向的投影位于第四过孔440底部边缘的一侧，且一端突出第四过孔440底部边缘远离第一过孔410的一端。所述第六开口560’在竖直方向的投影位于第五过孔450底部边缘的一侧，且一端突出第五过孔450底部边缘靠近第二过孔420的一端。所述第七开口570’在竖直方向的投影位于第二过孔420底部边缘的一侧，且一端突出第二过孔420底部边缘靠近第五过孔450 的一端。所述第八开口580’在竖直方向的投影位于第五过孔450底部边缘的一侧，且一端突出第五过孔450底部边缘远离第二过孔420的一端。
具体地，请参阅图7，在本发明的第二实施例中，所述第五开口550’、第三开口530’、第一开口510’及第六开口560’依次排成一列，且所述第五开口550’、第三开口530’、第一开口510’和第六开口560’的排列方向与第一过孔410和第二过孔420的排列方向平行。所述第四开口540’、第二开口520’、第七开口570’及第八开口580’依次排成一列，且所述第四开口540’、第二开口520’、第七开口570’和第八开口580’的排列方向与第一过孔410和第二过孔420的排列方向平行。
进一步地，请参阅图7，所述第三开口530’在竖直方向的投影突出第一过孔410底部边缘靠近第四过孔440一端的部分与第四开口540’在竖直方向的投影突出第四过孔440底部边缘靠近第一过孔410一端的部分在第一过孔410和第四过孔440排列方向上的长度之和大于第一过孔410底部边缘与第四过孔440底部边缘之间的距离。而所述第六开口560’在竖直方向的投影突出第五过孔450底部边缘靠近第二过孔420一端的部分与第七开口570’在竖直方向的投影突出第二过孔420底部边缘靠近第五过孔450一端的部分在第二过孔420和第五过孔450排列方向上的长度之和大于第二过孔420底部边缘与第五过孔450底部边缘之间的距离。当然，在本发明的其他实施例中，所述第三开口530’在竖直方向的投影突出第一过孔410底部边缘靠近第四过孔440一端的部分与第四开口540’在竖直方向的投影突出第四过孔440底部边缘靠近第一过孔410一端的部分在第一过孔410和第四过孔440排列方向上的长度之和也可等于第一过孔410底部边缘与第四过孔440底部边缘之间的距离。而所述第六开口560’在竖直方向的投影突出第五过孔450底部边缘靠近第二过孔420一端的部分与第七开口570’在竖直方向的投影突出第二过孔420底部边缘靠近第五过孔450一端的部分在第二过孔420和第五过孔450排列方向上的长度之和也可等于第二过孔420底部边缘与第五过孔450底部边缘之间的距离，这并不会影响本发明的实现。
具体地，所述第三开口530’、第四开口540’、第五开口550’、第六开口560’、第七开口570’及第八开口580’均为长条状，所述第三开口530’、第四开口540’、第五开口550’、第六开口560’、第七开口570’及第八开口580’的延伸方向均与第一开口510’的延伸方向平行。所述第一开口510’的延伸方向与第一过孔410和第二过孔420的排列方向之间的夹角为45°。
其余结构均与第一实施例相同，在此不再赘述。
需要说明的是，本发明的TFT阵列基板的第二实施例在第三导电层500’上设置第一开口510’及第二开口520’，利用第一开口510’及第二开口520’使形成于第一过孔410及第二过孔420互相靠近的边缘的断裂的两端无法同时继续向外延伸直至第三导电层500’的边缘，与此同时，还在第三导电层500’上设置了第三开口530’、第四开口540’、第五开口550’、第六开口560’、第七开口570’及第八开口580’，利用第三开口530’及第四开口540’使形成于第一过孔410及第四过孔440互相靠近的边缘的断裂的两端无法同时继续向外延伸直至第三导电层500’的边缘，利用第七开口570’及第六开口560’使形成于第二过孔420及第五过孔450互相靠近的边缘的断裂的两端无法同时继续向外延伸直至第三导电层500’的边缘，利用第五开口550’使第四过孔440远离第一过孔410边缘处产生的断裂的两端无法同时继续向外延伸直至第三导电层500’的边缘，利用第八开口580’使第五过孔450远离第二过孔420边缘处产生的断裂的两端无法同时继续向外延伸直至第三导电层500’的边缘，并且设置各个开口的延伸方向与第一过孔410及第二过孔420的排列方向呈45°角，能够防止沿第一过孔410及第二过孔420延伸方向的断裂两端延伸至第三导电层500’的边缘，从而使第三导电层500’即使发生静电击穿整体仍能够连通，保证通过第三导电层500’连通的第一导电层100及第二导电层300的连接可靠，提升产品的品质。
请参阅图8，并结合图5，本发明的TFT阵列基板的第三实施例与上述第一实施例的区别在于，所述第一开口510”在竖直方向的投影的另一端并不突出第二过孔420底部边缘靠近第五过孔450的一端。所述第二开口520”在竖直方向的投影的另一端并不突出第一过孔410底部边缘靠近第四过孔440的一端。所述第一开口510”在竖直方向的投影突出第二过孔420底部边缘靠近第一过孔410一端的部分在第一过孔410和第二过孔420排列方向上的长度大于第一过孔410底部边缘与第二过孔420底部边缘投影在同一水平面上时两者之间的距离。所述第二开口520”在竖直方向的投影突出第一过孔410底部边缘靠近第二过孔420一端的部分在第一过孔410和第二过孔420排列方向上的长度大于第一过孔410底部边缘与第二过孔420底部边缘投影在同一水平面上时两者之间的距离。
具体地，请参阅图8，在本发明的第三实施中，所述第三导电层500”还设有间隔的第三开口530”、第四开口540”、第五开口550”、第六开口560”、第七开口570”、第八开口580”、第九开口590”、第十开口5100”。
所述第三开口530”及第四开口540”在竖直方向的投影分别位于第四过孔440底部边缘的两侧且一端均突出第四过孔440底部边缘靠近第一过 孔410的一端；所述第三开口530”及第四开口540”在竖直方向的投影突出第四过孔440底部边缘靠近第一过孔410一端的部分在第一过孔410和第四过孔440排列方向上的长度均大于第一过孔410底部边缘与第四过孔440底部边缘之间的距离。
所述第五开口550”及第六开口560”在竖直方向的投影分别位于第五过孔450底部边缘的两侧且一端均突出第五过孔450底部边缘靠近第二过孔420的一端；所述第五开口550”及第六开口560”在竖直方向的投影突出第五过孔450底部边缘靠近第二过孔420一端的部分在第二过孔420和第五过孔450排列方向上的长度均大于第二过孔420底部边缘与第五过孔450底部边缘之间的距离。
所述第七开口570”及第八开口580”在竖直方向的投影分别位于第四过孔440底部边缘的两侧且一端均突出第四过孔440底部边缘远离第一过孔410的一端。
所述第九开口590”及第十开口5100”在竖直方向的投影分别位于第五过孔450底部边缘的两侧且一端均突出第五过孔450底部边缘远离第二过孔420的一端。
具体地，请参阅图8，所述第三开口530”、第四开口540”、第五开口550”、第六开口560”、第七开口570”、第八开口580”、第九开口590”、第十开口5100”均为长条状，第三开口530”、第四开口540”、第五开口550”、第六开口560”、第七开口570”、第八开口580”、第九开口590”、第十开口5100”的延伸方向均与第一开口510”的延伸方向平行。第一开口510”的延伸方向与第一过孔410和第二过孔420的排列方向平行。
进一步地，请参阅图8，在本发明的第三实施例中，所述第三导电层500”还设有间隔的第十一开口5110”、第十二开口5120”、第十三开口5130”及第十四开口5140”。所述第十一开口5110”、第十二开口5120”、第十三开口5130”及第十四开口5140”均为长条状。
所述第十一开口5110”在竖直方向的投影位于第四过孔440底部边缘远离第一过孔410的一端且与第七开口570”连接。所述第十一开口5110”的延伸方向与第七开口570”的延伸方向垂直。
所述第十二开口5120”在竖直方向的投影位于第四过孔440底部边缘远离第一过孔410的一端且与第八开口580”连接。所述第十二开口5120”的延伸方向与第八开口580”的延伸方向垂直。
所述第十三开口5130”在竖直方向的投影位于第五过孔450底部边缘远离第二过孔420的一端且与第九开口590”连接。所述第十三开口5130” 的延伸方向与第九开口590”的延伸方向垂直。
所述第十四开口5140”在竖直方向的投影位于第五过孔450底部边缘远离第二过孔420的一端且与第十开口5100”连接。所述第十四开口5140”的延伸方向与第十开口5100”的延伸方向垂直。
需要说明的是，本发明的TFT阵列基板的第三实施例在第三导电层500”上设置第一开口510”及第二开口520”，利用第一开口510”及第二开口520”使形成于第一过孔410及第二过孔420互相靠近的边缘的断裂的两端均不能继续向外延伸直至第三导电层500”的边缘，与此同时，还在第三导电层500”上设置了第三开口530”、第四开口540”、第五开口550”、第六开口560”、第七开口570”、第八开口580”、第九开口590”、第十开口5100”，利用第三开口530”、第四开口540”使形成于第一过孔410及第四过孔440互相靠近的边缘的断裂的两端均不能继续向外延伸直至第三导电层500”的边缘，利用第五开口550”、第六开口560”使形成于第二过孔420及第五过孔450互相靠近的边缘的断裂的两端均不能继续向外延伸直至第三导电层500”的边缘，利用第七开口570”、第八开口580”使形成于第四过孔440远离第一过孔410的边缘处的断裂的两端均不能继续向外延伸直至第三导电层500”的边缘，利用第九开口590”、第十开口5100”使形成于第五过孔450远离第二过孔420的边缘处的断裂的两端均不能继续向外延伸直至第三导电层500”的边缘，进一步地，还在第三导电层500”上设置了第十一开口5110”、第十二开口5120”、第十三开口5130”及第十四开口5140”，能够防止沿第一过孔410及第二过孔420延伸方向的断裂两端延伸至第三导电层500”的边缘，从而使第三导电层500”即使发生静电击穿整体仍能够连通，保证通过第三导电层500”连通的第一导电层100及第二导电层300的连接可靠，提升产品的品质。
综上所述，本发明的TFT阵列基板设置第三导电层通过第一过孔及第二过孔分别连接第一导电层及第二导电层，并在第三导电层上设置间隔的第一开口与第二开口，第一开口在竖直方向的投影位于第二过孔底部边缘的一侧且一端突出第二过孔底部边缘靠近第一过孔的一端，第二开口在竖直方向的投影位于第一过孔底部边缘的一侧且一端突出第一过孔底部边缘靠近第二过孔的一端，从而在第三导电层因静电击穿而在对应第一过孔与第二过孔边互相靠近的缘产生断裂时，第一开口及第二开口能够对断裂进行阻隔，防止断裂导致第一导电层与第二导电层断开，保证第一导电层与第二导电层连接的可靠性，提升产品的品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板，包括第一导电层、设于第一导电层上的第一绝缘层、设于第一绝缘层上的第二导电层、设于第二导电层及第一绝缘层上的第二绝缘层以及设于第二绝缘层上的第三导电层；
    所述第二绝缘层上设有位于第二导电层上方的第一过孔及位于第一导电层上方的第二过孔，所述第一绝缘层上设有位于第一导电层上方的第三过孔，第二过孔位于第三过孔内；第三导电层经第一过孔及第二过孔分别与第二导电层及第一导电层连接；
    所述第三导电层上设有间隔的第一开口与第二开口，所述第一开口在竖直方向的投影位于第二过孔底部边缘的一侧且一端突出第二过孔底部边缘靠近第一过孔的一端；所述第二开口在竖直方向的投影位于第一过孔底部边缘的一侧且一端突出第一过孔底部边缘靠近第二过孔的一端。
  2. 如权利要求1所述的TFT阵列基板，其中，所述第一开口在竖直方向的投影突出第二过孔底部边缘靠近第一过孔一端的部分与所述第二开口在竖直方向的投影突出第一过孔底部边缘靠近第二过孔一端的部分在第一过孔和第二过孔排列方向上的长度之和大于等于第一过孔底部边缘与第二过孔底部边缘投影在同一水平面上时两者之间的距离；
    所述第一开口及第二开口在竖直方向的投影分别位于由第一过孔及第二过孔组成的过孔列的两侧；
    所述第一开口及第二开口均为长条状；所述第一开口的延伸方向与第二开口的延伸方向平行。
  3. 如权利要求2所述的TFT阵列基板，其中，所述第二绝缘层上还设有位于第二导电层上方的第四过孔及位于第一导电层上方的第五过孔，所述第一绝缘层上设有位于第一导电层上方的第六过孔，第五过孔位于第六过孔内，所述第三导电层经第四过孔与第五过孔分别与第二导电层及第一导电层连接；所述第四过孔、第一过孔、第二过孔及第五过孔依次设置排成一列。
  4. 如权利要求3所述的TFT阵列基板，其中，所述第一开口在竖直方向的投影的另一端突出第二过孔底部边缘靠近第五过孔的一端；所述第二开口在竖直方向的投影的另一端突出第一过孔底部边缘靠近第四过孔的一端；
    所述第三导电层还设有间隔的第三开口及第四开口；所述第三开口在 竖直方向的投影位于第四过孔底部边缘的一侧，且一端突出第四过孔底部边缘靠近第一过孔的一端，另一端突出第四过孔底部边缘远离第一过孔的一端；所述第四开口在竖直方向的投影位于第五过孔底部边缘的一侧，且一端突出第五过孔底部边缘靠近第二过孔的一端，另一端突出第五过孔底部边缘远离第二过孔的一端；
    所述第三开口和第一开口的排列方向与第一过孔和第二过孔的排列方向平行；所述第二开口和第四开口的排列方向与第一过孔和第二过孔的排列方向平行。
  5. 如权利要求4所述的TFT阵列基板，其中，所述第一开口在竖直方向的投影突出第二过孔底部边缘靠近第五过孔一端的部分与所述第四开口在竖直方向的投影突出第五过孔底部边缘靠近第二过孔一端的部分在第二过孔和第五过孔排列方向上的长度之和大于等于第二过孔的底部边缘与第五过孔底部边缘之间的距离；
    所述第二开口在竖直方向的投影突出第一过孔底部边缘靠近第四过孔一端的部分与所述第三开口在竖直方向的投影突出第四过孔底部边缘靠近第一过孔一端的部分在第四过孔和第一过孔排列方向上的长度之和大于等于第四过孔的底部边缘与第一过孔底部边缘之间的距离；
    所述第三开口及第四开口均为长条状，所述第三开口及第四开口的延伸方向均与第一开口的延伸方向平行；所述第一开口的延伸方向与第一过孔和第二过孔的排列方向平行。
  6. 如权利要求3所述的TFT阵列基板，其中，所述第三导电层还设有间隔的第三开口、第四开口、第五开口、第六开口、第七开口及第八开口；
    所述第三开口在竖直方向的投影位于第一过孔底部边缘的一侧，且一端突出第一过孔底部边缘靠近第四过孔的一端；所述第四开口在竖直方向的投影位于第四过孔底部边缘的一侧，且一端突出第四过孔底部边缘靠近第一过孔的一端；所述第五开口在竖直方向的投影位于第四过孔底部边缘的一侧，且一端突出第四过孔底部边缘远离第一过孔的一端；所述第六开口在竖直方向的投影位于第五过孔底部边缘的一侧，且一端突出第五过孔底部边缘靠近第二过孔的一端；所述第七开口在竖直方向的投影位于第二过孔底部边缘的一侧，且一端突出第二过孔底部边缘靠近第五过孔的一端；所述第八开口在竖直方向的投影位于第五过孔底部边缘的一侧，且一端突出第五过孔底部边缘远离第二过孔的一端；
    所述第五开口、第三开口、第一开口及第六开口依次排成一列，且所述第五开口、第三开口、第一开口和第六开口的排列方向与第一过孔和第 二过孔的排列方向平行；
    所述第四开口、第二开口、第七开口及第八开口依次排成一列，且所述第四开口、第二开口、第七开口和第八开口的排列方向与第一过孔和第二过孔的排列方向平行。
  7. 如权利要求6所述的TFT阵列基板，其中，所述第三开口在竖直方向的投影突出第一过孔底部边缘靠近第四过孔一端的部分与第四开口在竖直方向的投影突出第四过孔底部边缘靠近第一过孔一端的部分在第一过孔和第四过孔排列方向上的长度之和大于等于第一过孔底部边缘与第四过孔底部边缘之间的距离；
    所述第六开口在竖直方向的投影突出第五过孔底部边缘靠近第二过孔一端的部分与第七开口在竖直方向的投影突出第二过孔底部边缘靠近第五过孔一端的部分在第二过孔和第五过孔排列方向上的长度之和大于等于第二过孔底部边缘与第五过孔底部边缘之间的距离；
    所述第三开口、第四开口、第五开口、第六开口、第七开口及第八开口均为长条状，所述第三开口、第四开口、第五开口、第六开口、第七开口及第八开口的延伸方向均与第一开口的延伸方向平行；
    所述第一开口的延伸方向与第一过孔和第二过孔的排列方向之间的夹角为45°。
  8. 如权利要求3所述的TFT阵列基板，其中，所述第一开口在竖直方向的投影突出第二过孔底部边缘靠近第一过孔一端的部分在第一过孔和第二过孔排列方向上的长度大于第一过孔底部边缘与第二过孔底部边缘投影在同一水平面上时两者之间的距离；所述第二开口在竖直方向的投影突出第一过孔底部边缘靠近第二过孔一端的部分在第一过孔和第二过孔排列方向上的长度大于第一过孔底部边缘与第二过孔底部边缘投影在同一水平面上时两者之间的距离；
    所述第三导电层还设有间隔的第三开口、第四开口、第五开口、第六开口、第七开口、第八开口、第九开口、第十开口；
    所述第三开口及第四开口在竖直方向的投影分别位于第四过孔底部边缘的两侧且一端均突出第四过孔底部边缘靠近第一过孔的一端；所述第三开口及第四开口在竖直方向的投影突出第四过孔底部边缘靠近第一过孔一端的部分在第一过孔和第四过孔排列方向上的长度均大于第一过孔底部边缘与第四过孔底部边缘之间的距离；
    所述第五开口及第六开口在竖直方向的投影分别位于第五过孔底部边缘的两侧且一端均突出第五过孔底部边缘靠近第二过孔的一端；所述第五 开口及第六开口在竖直方向的投影突出第五过孔底部边缘靠近第二过孔一端的部分在第二过孔和第五过孔排列方向上的长度均大于第二过孔底部边缘与第五过孔底部边缘之间的距离；
    所述第七开口及第八开口在竖直方向的投影分别位于第四过孔底部边缘的两侧且一端均突出第四过孔底部边缘远离第一过孔的一端；
    所述第九开口及第十开口在竖直方向的投影分别位于第五过孔底部边缘的两侧且一端均突出第五过孔底部边缘远离第二过孔的一端。
  9. 如权利要求8所述的TFT阵列基板，其中，所述第三开口、第四开口、第五开口、第六开口、第七开口、第八开口、第九开口、第十开口均为长条状，第三开口、第四开口、第五开口、第六开口、第七开口、第八开口、第九开口、第十开口的延伸方向均与第一开口的延伸方向平行；
    第一开口的延伸方向与第一过孔和第二过孔的排列方向平行。
  10. 如权利要求9所述的TFT阵列基板，其中，所述第三导电层还设有间隔的第十一开口、第十二开口、第十三开口及第十四开口；所述第十一开口、第十二开口、第十三开口及第十四开口均为长条状；
    所述第十一开口在竖直方向的投影位于第四过孔底部边缘远离第一过孔的一端且与第七开口连接；所述第十一开口的延伸方向与第七开口的延伸方向垂直；
    所述第十二开口在竖直方向的投影位于第四过孔底部边缘远离第一过孔的一端且与第八开口连接；所述第十二开口的延伸方向与第八开口的延伸方向垂直；
    所述第十三开口在竖直方向的投影位于第五过孔底部边缘远离第二过孔的一端且与第九开口连接；所述第十三开口的延伸方向与第九开口的延伸方向垂直；
    所述第十四开口在竖直方向的投影位于第五过孔底部边缘远离第二过孔的一端且与第十开口连接；所述第十四开口的延伸方向与第十开口的延伸方向垂直。
PCT/CN2018/107831 2018-04-27 2018-09-27 Tft阵列基板 Ceased WO2019205482A1 (zh)

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