WO2019205313A1 - 一种基于随机比特流更新的ldpc译码器 - Google Patents

一种基于随机比特流更新的ldpc译码器 Download PDF

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WO2019205313A1
WO2019205313A1 PCT/CN2018/096642 CN2018096642W WO2019205313A1 WO 2019205313 A1 WO2019205313 A1 WO 2019205313A1 CN 2018096642 W CN2018096642 W CN 2018096642W WO 2019205313 A1 WO2019205313 A1 WO 2019205313A1
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unit
information
decoding
check
variable node
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PCT/CN2018/096642
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French (fr)
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吕启福
李帅
罗志刚
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成都吉纬科技有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing

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  • the invention belongs to the field of digital communication technologies and relates to an LDPC decoder based on random bit stream updating.
  • Error correction control coding is a technique that can effectively solve such problems.
  • the error correction control code performs the coding operation by adding a redundancy check bit to the original information bit string according to a certain rule at the transmitting end, and performs decoding by the corresponding decoding means at the receiving end, thereby reducing the bit error rate.
  • LDPC Low Density Parity Check Code
  • 802.11ad The Quasi Cyclic Low Density Parity Check Code (QC-LDPC) defined in the 802.11ad standard belongs to an irregular LDPC code, and is easy to implement because of its compact coding. Due to its excellent performance close to the Shannon limit, LDPC codes have been used in many applications such as computers and digital communications.
  • QC-LDPC Quasi Cyclic Low Density Parity Check Code
  • the coding of QC-LDPC is relatively simple.
  • the decoding algorithm based on SPA algorithm is more complicated to implement.
  • the research on LDPC codec hardware implementation focuses on its decoding.
  • the SPA algorithm uses the post-update confidence information between the variable node and the check node obtained from the check matrix to achieve the decoding. Because of the inverse hyperbolic tangent function in the defined check node update formula, it is difficult to Direct implementation on the hardware.
  • the derived Min-Sum Algorithm (MSA) algorithm can solve this problem.
  • MSA Min-Sum Algorithm
  • the LDPC decoder based on the random bit stream update principle is an architecture based on the SPA algorithm but different from the traditional MSA algorithm. Unlike MSA, which uses logarithmic domain information, it operates directly in the probability domain. When performing calculations, he converts the probability into a Bernoulli sequence by means of random comparison. The number of 1 elements in the Bernoulli sequence is correspondingly represented. Probability, the subsequent operations are based on the Bernoulli sequence, which takes advantage of the stochastic computational algorithm and the single-bit operation, so that the connection width between the variable node and the check node is only a single bit, making the wiring The difficulty is greatly reduced, and the chip area utilization rate is effectively improved.
  • the architecture based on random bit stream update has problems such as slow convergence, redundancy in resource and architecture design, insufficient optimization of variable node update module design, and large decoding delay.
  • the object of the present invention is to solve the above problem and propose an LDPC decoder based on random bit stream update, which can effectively reduce hardware design redundancy, improve random decoding convergence speed, and improve decoding throughput.
  • the decoder architecture mainly comprises: a decoding control unit, an input buffer unit, an information conversion unit, a variable node update unit, a check node update unit, a code word check unit, and a serial output unit.
  • the decoding control unit generates various types of control signals by using a finite state machine and transmits them to the input buffer unit, the information conversion unit, the variable node update unit, and the check node update unit, driven by the clock signal.
  • a codeword check unit, a serial output unit to produce an effect that the generated control signal enables the input buffer unit to buffer the necessary channel original information and reserve a decoding time for the decoding process;
  • the generated control signal causes the information to be converted
  • the unit can start and stop the conversion information in time;
  • the generated control signal enables the variable node update unit to complete the initialization and decoding update of the internal registration unit and the information interaction with the check node unit, the code word check unit, and the output buffer unit;
  • the control signal enables the check node update unit to perform its own decoding update and information interaction with the variable node unit;
  • the generated control signal enables the codeword check unit to be decoded correctly and to reach the set maximum number of decoding iterations Generating and transmitting a termination de
  • the input buffer unit uses a certain length of BRAM or other FIFO-like memory unit to perform buffering of channel information that is not decoded in time.
  • the depth or size of the cache memory unit is set according to the throughput rate and the decoding delay, and can be determined according to the LDPC protocol standard used for simulation.
  • the input channel symbols are sequentially buffered by a clock control method. When the internal data is already full, the input information is directly transmitted to the information conversion unit for related processing, and is further cached until the memory unit has a storage space larger than one complete code word information.
  • the information conversion unit performs the following functions: converting logarithm Likelihood Ratio (LLR) of the channel into probability information according to the following formula;
  • s represents the received symbol
  • L' is the independent Dependent Scale (NDS).
  • NDS Independent Dependent Scale
  • the information conversion unit further converts the serial probability information into which the symbols in the code block are converted into parallel probability information strings, so that all codeword probability information is converted into random bit stream information in the same clock; the direct hardening of the channel information is completed. judgment.
  • the internal part is composed of 16 probability conversion lookup tables (LUTs). In the same clock, the lookup table array completes the conversion of the input 16 channel LLR information into probability values, and converts the probability values of these serial 672 into parallel 672. Probability values; internally including 42 linear feedback shift registers (LFSRs) to generate pseudo-random numbers, and 672 comparators for generating random bit streams corresponding to each channel symbol and passing them to the variable node update unit Perform related processing.
  • LFSRs linear feedback shift registers
  • variable node update unit performs different configurations according to different degrees. For a variable node with a degree greater than or equal to 3, a "combined test" structure is employed. A variable node of degree 2 uses a normal counter structure. The variable node with degree 1 is directly updated and outputted by means of hard decision.
  • the structural inputs described above are all single-bit random bit streams that are passed from the information conversion unit.
  • the variable node unit updates the definition of the variable node update processing procedure according to the SPA algorithm (probability domain, non-LLR domain), and transmits the updated random single-bit form confidence information to the check node update unit for updating.
  • variable node update unit hardly determines the codeword decoded by this iteration, and passes it to the codeword check unit for verification, and the serial output unit.
  • the input node of the variable node updating unit further includes an XOR preprocessing module to adapt to the Half-Flood Wiring or Routing used in the present invention to further reduce the connection complexity and improve the maximum clock operation. frequency.
  • the input and output of the preprocessing module are used for the first check in the double check.
  • the variable node update unit also includes a pseudo random number generator composed of LFSRs for generating a more reliable output when the input is in a "latched state". Different from existing random computing structures, when the internal registers are at height,
  • the check node update unit has only a simple XOR gate operation. Different degrees of check nodes use the XOR gate of the number of input ports corresponding to the degree. Using the half flooding technique, the output of all check node update units has only single bit data, and the data is passed to the variable node update unit for further processing. .
  • the codeword check unit is composed of different input OR gate array trees, and the path delay is reduced by using a first-stage pipeline manner; the OR gate array trees complete verification of the decision codeword transmitted by the variable node update unit. Whether the detector is the correct legal codeword, when the output of the OR gate array tree is 0, it means that the translated codeword is correct, otherwise it is wrong, and the second verification of "double check" is completed; Under the premise, the codeword check unit generates a termination decoding signal to notify the decoding control unit, and all the units of the decoder are restored to the initial state;
  • the serial output unit performs time-division serial output on the translated codeword at a rate greater than or equal to the data buffer throughput rate of the input buffer unit.
  • the LDPC decoder based on random bit stream update uses a decoding optimization strategy of "alternating parameters" and "re-decoding” to improve decoding performance and reduce error leveling.
  • the LDPC decoder designed by the present invention uses different continuous relaxation attenuation parameters in different decoding iteration stages, so that the decoding speed is faster.
  • the decoding phase is divided into two phases.
  • the decoding cycle of the two phases is 100 (which can be determined by simulation for the adopted LDPC standard).
  • the first phase uses the attenuation coefficient a, iteration 20 times, and the second phase uses the attenuation coefficient.
  • b(b ⁇ a), iteration is 80 times.
  • the pseudo-random number generator in the information conversion unit and the variable node updating unit maintains the existing state, and the decoding is performed.
  • the other units in the device resume their initial state and continue decoding, ie "re-decode".
  • the codeword decoding failure can be decoded correctly during re-decoding.
  • variable node and the check node unit are simple in structure based on the random calculation principle, and the wiring difficulty is reduced; the variable node update structure performs signal sharing, so that the unit resource occupation is less; and the variable nodes for different degrees are adopted.
  • Different construction methods make the decoder less resources and faster decoding speed; the decoding optimization strategy of "alternating parameters" and “re-decoding” can improve the decoding performance;
  • the line uses the "half flooding” technology, which can effectively improve the operating clock frequency and data throughput rate of the LDPC decoder; the "double parity” technology makes the decoding convergence faster.
  • FIG. 1 is a logic diagram of an LDPC decoder of the present invention
  • FIG. 2 is a schematic diagram of control of an input FIFO in the present invention
  • FIG. 3 is a schematic structural view of an information conversion unit of the present invention.
  • variable node updating unit of the degree 4 of the present invention is a schematic structural diagram of a variable node updating unit of the degree 4 of the present invention.
  • FIG. 5 is a schematic structural diagram of a probability tracker used in the present invention.
  • FIG. 6 is a schematic diagram of an internal hard decision structure of a variable node update unit used in the present invention.
  • FIG. 7 is a schematic diagram of a two-input equivalent judgment structure with an internal register 2_input_ecl_A;
  • 8 is a schematic diagram of a two-input equivalent judgment structure without an internal register 2_input_ecl_B;
  • FIG. 9 is a schematic diagram showing an implementation structure of a variable node update of degree 3.
  • FIG. 10 is a schematic diagram showing an implementation structure of a variable node update of degree 2;
  • FIG. 11 is a schematic diagram showing an implementation structure of a variable node update of degree 1;
  • FIG. 12 is a schematic structural diagram of a check node update unit under the “half flooding” technique
  • FIG. 13 is a schematic structural diagram of an implementation of a "double parity" codeword check unit unit in the present invention.
  • Figure 14 is a flow chart showing the steps of implementing TFM attenuation coefficient switching and "re-decoding".
  • FIG. 1 is an embodiment of an LDPC decoder based on random bit stream update as set forth herein.
  • Each box represents a unit, each unit being internally composed of different implementation components.
  • Bold arrows indicate data stream interaction, and the number above the arrow indicates the width of the data stream.
  • Figure 2 shows an implementation of an asynchronous FIFO for an input buffer unit.
  • the depth is 256
  • the width is 5 bits
  • the input and output are different bit widths.
  • the input enters 40 bits per clock and occupies 8 FIFO units.
  • 5bit represents a received channel symbol amplitude, that is, quantized into 5 bits.
  • the FIFO outputs 80 bits per clock.
  • the input buffer is completed in 84 clock cycles and one block output is completed in 42 clock cycles. This design minimizes the possibility of FIFO fullness.
  • 256 cache units are composed of 16 distributed FIFOs with a depth of 16 and a width of 5 bits.
  • the 80-bit wide output port outputs only 40 bits per clock, and the 672 symbols are completely transmitted after 84 clock cycles. Normal read and write operations to prevent misalignment of code blocks.
  • the read null signal is passed to the information conversion unit.
  • the table next to Figure 2 lists the input and output port descriptions for that memory unit. The I after the diagonal line indicates the input port and O indicates the output port.
  • FIG. 3 is an implementation of an information conversion unit.
  • the channel amplitude is converted into a probability value, which is implemented by 16 distributed lookup tables.
  • the lookup table converts 16 channel amplitude information transmitted from the input buffer unit into 16 7-bit probability information in the same clock cycle.
  • the conversion of 672 symbols was completed in 42 cycles.
  • the pseudo-random number generator consists of a 10-bit LSFR. Using 42 distributed pseudo-random generators, 672 probability values are converted into 672 random bits by comparison with the generated random numbers in one clock cycle. Different from the traditional stochastic computing architecture, the feedback coefficients and seeds of all distributed pseudo-random generators are the same. Experiments show that this design can effectively speed up the decoding convergence speed. Distributed can reduce the path delay and improve the clock running. frequency.
  • the hard decision module in Fig. 3 is used to directly take out the 40-bit information transmitted from the input buffer unit when the FIFO is full, and take out the highest sign bit of each channel information as a direct hard decision result output.
  • the decoder outputs 8 bits per clock. If the iterative decoding also has an output at this time, the decoding control unit uniformly controls the output of the entire decoder.
  • 4 is an update unit structure of a variable node of 4 in an embodiment of the present invention. 4 confidence information plus 1 channel prior information. Different from the traditional random computing variable node implementation, it implements a counter structure based on TFM (Tracking Majority Memory) shared signal. When calculating each output signal, the intermediate calculated Regerative bit and the Hold State or Non-hold state signal are shared, which is different from the traditional random computing architecture and does not cause any performance loss. . This shared structure is derived from Table 1 below. Inside the rectangular box is a signal that can be shared, which saves the child node structure.
  • the probability tracker design of the variable nodes with degrees 4 and 3 is implemented by a TFM-based 7-bit wide counter method, and the counting step is a set exponential decay coefficient ⁇ .
  • FIG. 5 is a probability tracking counter structure used in the present invention.
  • the output of the hard decision uses a memory feedback method, the output of which is omitted from the channel information, and only the information transmitted by each check node is used. Experiments prove that this method is based on the technology adopted by the present invention.
  • Figure 6 is a hard decision structure employed in the present invention.
  • Figure 7 shows the structure of the 2_input_ecl_A (2-inputs Equality Check Logic) module.
  • the internal register (Internal Mem) is implemented by a simple 2-bit register.
  • Figure 8 shows the structure of the 2_input_ecl_B module.
  • the XOR gates at the input are a way to apply the "half flooding" technique.
  • Table 1 degrees are 4 variable node inputs and outputs
  • Figure 9 is an implementation structure of a variable node of degree 3, which is constructed using the same principle as a variable node of degree 4, sharing the updated bit output signal.
  • Figure 10 is an implementation of a variable node of degree 2, the structure of which is consistent with the traditional stochastic computing architecture.
  • 11 is an implementation of a variable node of degree 1. Since there is only one variable node connected thereto, the update bit output is channel prior information, and the decision output is determined by the information bits transmitted by the neighbor check node. Due to the "half flooding" technique, all variable node inputs have matching XOR gates. The implementation structure corresponding to each variable node is designed differently according to the degree of the degree.
  • Each check node outputs only one XOR result, and passes it to a neighboring variable node, and then performs an XOR operation to complete the respective confidence match.
  • the input of the verification module A is from the first output of each variable node update unit, and the first verification is completed, and the input of the verification module B is from each time. Iterate the hard decision output of the variable node and complete the second check. The signal output of the final flag verification success or failure is completed by the OR gate.
  • FIG 14 is a flow chart for implementing TFM attenuation coefficient switching and "re-decoding".
  • the TFM counter inside each variable node is initialized by the probability of channel amplitude conversion. After the initialization is completed, iterative decoding is started, and then the code after each decision is performed. The word is "double-checked", if it is successful, it is directly output. Otherwise, it is checked whether the number of times of the first ⁇ 1 parameter decoding in the first stage is reached. Here, 20 times is set, if the first stage first ⁇ (0.025) has been reached.
  • Parameters then switch to the second beta (0.0625) parameter of the first phase, before reaching the maximum number of iterations of the second beta (0.0625) parameter in the first phase (set here 80 times), if the decoding is successful, then output, otherwise End the first stage (100 times in total) to perform the second stage decoding, that is, "re-decoding".
  • the state of the pseudo-random number does not change, the register inside the variable node is re-initialized, and then the first is repeated. The decoding process of the phase until the decoding is successful or the total number of iterations of the second phase is reached.

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Abstract

本发明属于数字通信技术领域，涉及一种基于随机比特流更新的LDPC译码器。该译码器包括译码控制单元，输入缓存单元，信息转化单元，变量节点更新单元，校验节点更新单元，码字校验单元，串行输出单元。其中，基于随机计算原理使得变量节点和校验节点单元结构简单，降低了布线难度；变量节点更新结构进行信号共享，使得该单元资源占用更少；针对不同度数的变量节点采用不同构造方式，使得译码器的资源更少，译码速度更快；采用"交替参数"和"重译码"的译码优化策略，可以提升译码性能；对两层节点之间的连线使用"半洪泛"技术，可以有效提高LDPC译码器的运行时钟频率和数据吞吐率；"双校验"技术使得译码收敛速度更快。

Description

一种基于随机比特流更新的LDPC译码器 技术领域
本发明属于数字通信技术领域，涉及一种基于随机比特流更新的LDPC译码器。
背景技术
信息在信道传输尤其是无线信道中传输时会经历噪声干扰和衰落，由此造成在接收端接收到的信息错误较多。纠错控制编码是一项可以有效解决这类问题的技术。纠错控制编码通过在发送端按照一定规则向原始信息比特串中加入冗余校验比特，完成编码操作，在接收端通过对应的译码手段进行译码，起到降低误码率的作用。
低密度奇偶校验码(Low Density Parity Check Code，LDPC)是一类纠错性能优良的纠错控制编码。它是由Robert G.Gallager于1962年首次提出。LDPC基于稀疏矩阵进行校验矩阵的构造，根据不同应用场景和构造方式可以分为多类，其主要有规则码和非规则码两类。802.11ad标准中定义的准循环码(Quasi Cyclic Low Density Parity Check Code，QC-LDPC)属于非规则LDPC码，由于其编码简洁，所以便于实现。由于具有逼近香农限的优良性能，LDPC码已经被应用在计算机和数字通信等多个场合。
QC-LDPC的编码比较简单，基于SPA算法形成的译码算法实现较为复杂，关于LDPC编解码硬件实现的研究点主要集中于其译码方面。SPA算法利用根据校验矩阵得到的变量节点和校验节点之间传播更新后置信度信息来达到译码，由于其定义的校验节点更新公式中设计反双曲正切函数，所以其很难在硬件上直接实现。衍生出的最小和(Min-Sum Algorithm，MSA)算法能够解决这一问题。但是在译码时，校验矩阵中有多少个1元素就有多少根连接两类节点的连线，随着码长规模和连线比特宽度的增加，MSA涉及的硬件实现布线会非常困难，无法在较高的时钟频率下维持时序收敛，最终造成实现的译码器吞吐率无法得到提升，同时也造成芯片面积的大量占用，并且其变量节点和校验节点更新单元的实现仍然消耗很大资源，进而造成的功耗较较高。
基于随机比特流更新原理实现的LDPC译码器是一种基于SPA算法但是区别于传统MSA算法的架构。他不同于MSA利用对数域信息而是直接在概率域内进行运算，在进行计算时，他通过随机比较手段将概率转化成伯努利序列，该伯努利序列中1元素的数量表征对应的概率，其后的运算都是基于该伯努利序列进行运算，它利用随机计算算理以及单比特运算的优势，使得在变量节点和校验节点之间连线宽度只需单比特，使得布线难度大大降低，芯片面 积利用率得到有效提升。但是目前基于随机比特流更新的架构，存在着收敛速度慢，占用资源和架构设计存在冗余，变量节点更新模块设计不够优化，译码延时大等问题。
发明内容
本发明的目的是针对上述问题，提出一种基于随机比特流更新的LDPC译码器，能够有效降低硬件设计冗余度，提高随机译码收敛速度，提高译码吞吐率。
本发明的技术方案为：
一种基于随机比特流更新的LDPC译码器；其特征在于译码的思想基于传统的和积译码(Sum-Product Algorithm，SPA)，但是实现架构和置信度的传播信息都在随机比特流的形式下进行设计和实现，其核心原理在于比特流的随机计算。该译码器架构中主要包括：译码控制单元，输入缓存单元，信息转化单元，变量节点更新单元，校验节点更新单元，码字校验单元，串行输出单元。
所述的译码控制单元，是在时钟信号的驱动下，采用有限状态机的方式产生各类控制信号并将其传递给输入缓存单元，信息转化单元，变量节点更新单元，校验节点更新单元，码字校验单元，串行输出单元，以产生如下效果：产生的控制信号使得输入缓存单元能够缓存必要的信道原始信息并给译码过程预留译码时间；产生的控制信号使得信息转化单元能够及时开始和停止转化信息；产生的控制信号使得变量节点更新单元能够完成内部寄存单元的初始化和译码更新以及与校验节点单元、码字校验单元、输出缓存单元的信息交互；产生的控制信号使得校验节点更新单元能够完成自身译码更新以及与变量节点单元的信息交互；产生的控制信号使得码字校验单元能够在译码正确以及在达到设定的最大译码迭代次数时刻产生和传递出终止译码信号；产生的控制信号使得串行输出单元能够及时的输出译得的码字。
所述的输入缓存单元使用一定长度的BRAM或者其他类似于FIFO的内存单元来完成对未得到及时译码的信道信息进行缓存。该缓存内存单元的的深度或大小根据吞吐率和译码延时进行设定，可具体根据所用的LDPC协议标准进行仿真确定。采用时钟控制的方法进行对输入的信道符号进行顺序缓存。当其内部已经存满数据时，直接将输入进来的信息传递给信息转化单元进行相关处理，直到其内存单元有大于1个完整码字信息的存储空余量时才进一步进行缓存。
所述的信息转化单元完成如下功能：将信道的对数域信息(Logarithm Likelihood Ratio，LLR)根据如下公式转化成概率信息；
Figure PCTCN2018096642-appb-000001
Figure PCTCN2018096642-appb-000002
Figure PCTCN2018096642-appb-000003
上面公式中s代表的是接收的符号，P(s＝1)代表的含义是，信道接收到的符号是比特1的先验概率，L′为采用独立噪声放缩算法(Noise Dependent Scale，NDS)得到中间LLR信道值，α为放缩参数，Y为接收到的信道符号的最大幅度值，N 0为信道高斯白噪声的功率谱密度值，L为接收到的信道符号LLR值，y为接收到个码字比特对应的信道符号接收幅度值。
所述的信息转化单元还将码块内各符号转化成的串行概率信息变成并行概率信息串便于同时钟内完成所有码字概率信息转化成随机比特流信息；完成对信道信息的直接硬判决。其内部由16个概率转化查找表(LUT)构成，在同一个时钟内该查找表阵列完成对输入的16个信道LLR信息转化成概率值，并将这些串行672的概率值转换成并行672个概率值；其内部还包括42个线性反馈移位寄存器(LFSR)产生伪随机数，以及672个比较器，用来产生各信道符号对应的随机比特流，并将其传递给变量节点更新单元进行相关处理。
所述的变量节点更新单元根据不同的度数，进行不同的配置。对于度数大于等于3的变量节点采用“组合检验”结构。度为2的变量节点使用普通计数器结构。度为1的变量节点则直接采用硬判决的方式进行更新和输出。以上所述结构输入都是从信息转化单元传递来的单比特随机比特流。变量节点单元根据SPA算法(概率域，非LLR域)中对变量节点更新处理过程的定义进行更新，将更新后的随机单比特形式的置信度信息传递给校验节点更新单元进行更新。同时变量节点更新单元硬判决产生本次迭代译码的码字，并将其传递给码字校验单元进行校验，以及串行输出单元。所述的变量节点更新单元输入端还包括异或预处理模块，以适应本发明所采用的半洪泛连线(Half-Flood Wiring or Routing)，以进一步降低连线复杂度，提高时钟最高运行频率。该预处理模块的输入和输出用于双校验中的第一次校验。变量节点更新单元内部还包括由LFSR构成的伪随机数发生器，用于在输入处于“锁存状态”时产生更可靠的输出。区别于现有随机计算结构，其内部寄存器在高度数时，
所述的校验节点更新单元只有简单的异或门操作。不同度数的校验节点使用和度数对应的输入端口数量的异或门，使用半洪泛技术，所有校验节点更新单元的输出只有单比特数据，该数据传递给变量节点更新单元用以进一步处理。
所述的码字校验单元由不同输入的或门阵列树构成，并采用一级流水的方式降低路径延时；这些或门阵列树完成对变量节点更新单元传递过来的判决码字进行校验，检测器是否是 正确的合法码字，当或门阵列树的输出为0时，表示译得码字正确，否则错误，完成“双校验”的第二次校验；在译码正确的前提下，码字校验单元产生终止译码信号通知译码控制单元，译码器所有单元恢复初始状态；
所述的串行输出单元按大于等于输入缓存单元数据吞吐率的速率对译得的码字进行分时串行输出。其优点是可以省去输出缓存存储器的设置。
所述的基于随机比特流更新的LDPC译码器使用“交替参数”和“重译码”的译码优化策略，可以提升译码性能和降低误码平层。本发明所设计的LDPC译码器中在不同的译码迭代阶段使用不同的连续松弛衰减参数，使得译码速度更快。译码阶段分为两个阶段，两个阶段的译码周期共100(可以针对所采用的的LDPC标准进行仿真确定)，第一阶段采用衰减系数a，迭代20次，第二阶段采用衰减系数b(b<a),迭代80次.当在100次迭代后仍没有正确译码时，则除信息转化单元和变量节点更新单元中的伪随机数发生器维持现有状态不变，译码器中的其他各单元重新恢复初始状态，并继续译码，即“重译码”。利用随机数的的随机状态，可以将译码失败的码字译码在重译码时译码正确。
本发明的有益效果为，基于随机计算原理使得变量节点和校验节点单元结构简单，降低了布线难度；变量节点更新结构进行信号共享，使得该单元资源占用更少；针对不同度数的变量节点采用不同构造方式，使得译码器的资源更少，译码速度更快；采用“交替参数”和“重译码”的译码优化策略，可以提升译码性能；对两层节点之间的连线使用“半洪泛”技术，可以有效提高LDPC译码器的运行时钟频率和数据吞吐率；“双校验”技术使得译码收敛速度更快。
附图说明
图1是本发明的LDPC译码器的逻辑结示意图；
图2是本发明中输入FIFO的控制示意图；
图3是本发明信息转化单元结构示意图；
图4是本发明度为4的变量节点更新单元结构示意图；
图5为本发明中所采用的概率跟踪器结构示意图；
图6为本发明所采用的变量节点更新单元内部硬判决结构示意图；
图7为带内部寄存器2_input_ecl_A的两输入等价判断结构示意图；
图8为不带内部寄存器2_input_ecl_B的两输入等价判断结构示意图；
图9是度为3的变量节点更新的实现结构示意图；
图10是度为2的变量节点更新的实现结构示意图；
图11是度为1的变量节点更新的实现结构示意图；
图12为采用“半洪泛”技术下的校验节点更新单元结构示意图；
图13为本发明中“双校验”码字校验单元单元的一种实现结构示意图；
图14为实现TFM衰减系数切换和“重译码”步骤的流程图。
具体实施方式
下面结合附图对本发明做进一步说明。
图1是本发明所阐述的一种基于随机比特流更新的LDPC译码器的实施例。每个方框代表一个单元，每个单元内部由不同实现部件构成。加粗的箭头表明数据流交互，箭头上面的数字表示了数据流的宽度。
图2为一种输入缓存单元使用异步FIFO的实现方式，深度共为256，宽度5bit，输入输出不同位宽，该输入每个时钟进入40bit，共占用8个FIFO单元。5bit代表一个接收到的信道符号幅值，亦即量化成5bit。FIFO每个时钟输出80bit。这样对于802.11ad中定义的672长度的LDPC码，在84个时钟周期完成输入缓存，42个时钟周期完成一个码块输出，这种设计最大限度降低了FIFO写满的可能性。将256个缓存单元采用16个深度为16，宽度为5bit的分布式FIFO构成，写入时，按照时钟驱动，先写入第一个FIFO块的一个内存单元，再写第二个FIFO块单元的一个内存单元，以此类推，直到第16个FIFO块也写入一个单元。然后再从第一个FIFO块的下一个单元开始写。读出时，在一个时钟驱动下，16个FIFO块同时读使能，输出80bit，对应16个信道符号，传递给信息转化单元。在写满时，新的数据将直接传递给信息转化单元进行相关处理，并同时通知信息转化单元写满。当FIFO已经写满时，将直接向信息转化模块传递信道符号信息，此时80位宽的输出端口每时钟只输出40bit，并同样经过84个时钟周期完整的传递672个符号后，方可恢复正常的读写操作，防止出现码块错位的情况。在读空时，将读空信号传递给信息转化单元。图2旁边的表格列出了该内存单元的输入输出端口说明，斜划线后面的I表示输入端口，O表示输出端口。
图3为一种信息转化单元的实现方式。将信道幅值转化成概率值，采用16个分布式查找表实现，这些查找表在同一个时钟周期内将输入缓存单元传递进来的16个信道幅值信息转化成16个7bit概率信息。经过42个周期完成对672个符号的转化。伪随机数发生器10位LSFR构成，采用42个分布式伪随机发生器，将672个概率值在一个时钟周期内通过和产生的随机数比较转化成672个随机比特。不同于传统的随机计算架构，这里所有分布式伪随机发生器反馈系数和种子均相同，实验证明，这种设计可以有效加快译码收敛速度，采用分布式可以降低路延时，提高时钟最高运行频率。图3中的硬判决模块用于当FIFO写满时直接取出输 入缓存单元传递过来的40bit信息，取出各信道信息的最高符号位作为直接硬判决结果输出。译码器每时钟输出8bit。如果此时迭代译码也有输出，那么由译码控制单元统一协调控制整个译码器的输出。
图4是本发明一种实施例中的变量节点为4的更新单元结构。4个置信度信息加上1个信道先验信息。区别于传统随机计算的变量节点实现方式，它实现了一种基于TFM(Tracking Majority Memory)共享信号的计数器结构。在计算各输出信号时，共享中间计算而得的再生比特(Regerative bit)和锁存状态(Hold State or Non-hold state)信号，这区别于传统随机计算架构，并且不会带来任何性能损失。这种共享结构是根据下面表1得出的。矩形框内的是可以共享的信号，这样可以节省子节点结构。度为4和3的变量节点的概率跟踪器设计采用基于TFM的7比特宽的计数器方式实现，计数步长为设定的指数衰减系数β，图5为本发明中所采用的概率跟踪计数器结构。硬判决的输出采用的是一种记忆反馈的方式，其输出略去了信道信息，而只使用各校验节点传递过来的信息，实验证明，这种做法在本发明所采用的的技术之上没有过多的译码性能损失，图6为本发明所采用的硬判决结构。图7为2_input_ecl_A(2-inputs Equality Check Logic)模块结构，内部寄存器(Internal Mem)由简单的2比特寄存器实现；图8为2_input_ecl_B模块结构。输入端的各异或门是应用“半洪泛”技术的一种方式。
表1 度为4变量节点输入与输出
Figure PCTCN2018096642-appb-000004
图9是度为3的变量节点的实现结构,它采用与度为4的变量节点相同的原理进行构造，共享更新比特输出信号。图10是度为2的变量节点的一种实现方式，其结构实现与传统基于随机计算架构一致。图11是度为1的变量节点的实现方式，因与其相连的变量节点只有1个，所以其更新比特输出就是信道先验信息，判决输出即为由邻近校验节点传递来的信息比特决定。由于采用“半洪泛”技术，所有的变量节点输入端都有匹配异或门。根据度数的大小来 差异化设计各变量节点对应的实现结构。
图12为采用多输入异或门实现的校验节点更新单元，每个校验节点只输出一个异或结果，传递给邻近的变量节点后再进行异或操作完成各自的置信度匹配。
图13为本发明中码字校验单元的一种实现方式，校验模块A的输入来自各变量节点更新单元的第一输出，完成第一次校验，校验模块B的输入来自每次迭代变量节点的硬判决输出，完成第二次校验。采用或门完成最后标志校验成功与否的信号输出。
图14实现TFM衰减系数切换和“重译码”的流程图，利用信道幅值转化的概率初始化各变量节点内部的TFM计数器，初始化完成后开始进行迭代译码，然后对每次判决后的码字进行“双校验”，如果成功则直接输出，否则检查是否达到了第一阶段第一β1参数译码的次数，这里设定的是20次，如果已经达到第一阶段第一β(0.025)参数，那么切换到第一阶段第二β(0.0625)参数，在到达第一阶段第二β(0.0625)参数的最大迭代次数(这里设定80次)之前，如果译码成功则输出，否则结束第一阶段(共100次)进行第二阶段译码，亦即“重译码”，第二阶段开始时，伪随机数的状态不改变，变量节点内部的寄存器重新初始化，然后重复第一阶段的译码过程，直到译码成功或者到达第二阶段的总迭代次数。

Claims (5)

  1. 一种基于随机比特流更新的LDPC译码器，该译码器包括译码控制单元、输入缓存单元、变量节点更新单元、校验节点更新单元、码字校验单元和串行输出单元；
    译码控制单元，用于对译码器各个模块的工作时序进行控制；
    输入缓存单元，用于对未能及时得到译码操作的输入信道信息进行缓存；
    变量节点更新单元，用于对迭代过程中的变量节点信息进行更新运算；
    校验节点更新单元，用于对迭代过程中的校验节点信息进行更新运算；
    码字校验单元，用于对当前迭代译出码字的合法性进行判断，并指示本次译码是否完成；
    串行输出单元，用于对所译得的码字进行分时串行输出；
    其特征在于，还包括信息转化单元，用于将输入的信道信息进行概率转化和比特流转化。
  2. 根据权利要求1所述的一种基于随机比特流更新的LDPC译码器，其特征在于，所述信息转化单元将输入的信道信息进行概率转化和比特流转化的具体方法为：
    将信道的对数域信息转化成概率信息；
    将码块内各符号转化成的串行概率信息变成并行概率信息串，便于同时钟内完成所有码字概率信息转化成随机比特流信息；
    完成对信道信息的直接硬判决；
    所述信息转化单元包括16个概率转化查找表，在同一个时钟内该查找表阵列完成对输入的16个信道LLR信息转化成概率值，并将这些串行672的概率值转换成并行672个概率值；
    所述信息转化单元还包括42个线性反馈移位寄存器产生伪随机数，以及672个比较器，用来产生个信道符号对应的随机比特流，并将其传递给变量节点更新单元。
  3. 根据权利要求2所述的一种基于随机比特流更新的LDPC译码器，其特征在于，所述变量节点更新单元根据信息转化单元传递来的单比特随机比特流，进行如下操作：
    变量节点更新单元根据SPA算法中对变量节点更新处理过程的定义进行更新，将更新后的随机单比特形式的置信度信息传递给校验节点更新单元进行更新；
    同时变量节点更新单元硬判决产生本次迭代译码的码字，并将其传递给码字校验单元进行校验，以及串行输出单元；
    所述的变量节点更新单元输入端还包括异或预处理模块，该预处理模块的输入和输出用于第一次校验。
  4. 根据权利要求3所述的一种基于随机比特流更新的LDPC译码器，其特征在于，所述校验节点更新单元只有异或门操作，不同度数的校验节点使用和度数对应的输入端口数量的异或门，使用半洪泛技术，所有校验节点更新单元的输出只有单比特数据，该数据传递给变量节点更新单元。
  5. 根据权利要求4所述的一种基于随机比特流更新的LDPC译码器，其特征在于，所述码字校验单元由不同输入的或门阵列树构成，并采用一级流水的方式降低路径延时；
    所述或门阵列树完成对变量节点更新单元传递过来的判决码字进行校验，检测器是否是正确的合法码字，当或门阵列树的输出为0时，表示译得码字正确，否则错误，完成第二次校验；在译码正确的前提下，码字校验单元产生终止译码信号通知译码控制单元，译码器所有单元恢复初始状态。
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