WO2019203019A1 - Circuit de stockage non volatil - Google Patents

Circuit de stockage non volatil Download PDF

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Publication number
WO2019203019A1
WO2019203019A1 PCT/JP2019/015073 JP2019015073W WO2019203019A1 WO 2019203019 A1 WO2019203019 A1 WO 2019203019A1 JP 2019015073 W JP2019015073 W JP 2019015073W WO 2019203019 A1 WO2019203019 A1 WO 2019203019A1
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WIPO (PCT)
Prior art keywords
transistor
store
circuit
storage
driver
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PCT/JP2019/015073
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English (en)
Japanese (ja)
Inventor
啓三 平賀
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ソニーセミコンダクタソリューションズ株式会社
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Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Priority to CN201980015138.XA priority Critical patent/CN112020744A/zh
Priority to JP2020514076A priority patent/JP7282749B2/ja
Priority to DE112019002007.2T priority patent/DE112019002007T5/de
Publication of WO2019203019A1 publication Critical patent/WO2019203019A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Definitions

  • the present technology relates to a nonvolatile memory circuit, and more particularly, to a nonvolatile memory circuit that can achieve downsizing and keep power consumption low while maintaining stable writing.
  • PG Power Gating
  • PG Power Gating
  • NVFF Non-VolatileolaFlip-Floplononvolatile flip-flop
  • MTJ Magnetic Tunnel Junction
  • NVM Non Volatile Memory
  • NVFF nonlinear logic circuit
  • two MTJs are provided, and a transistor arranged on the store current path, that is, on the store path is connected to each of the MTJs. Either one of these always becomes a source connection in which the MTJ is connected to the ground side with respect to the transistor.
  • the gate width of the transistor needs to be increased in order to prevent disturbance (latch breakdown) to the latch during storage.
  • the present technology has been made in view of such a situation, and makes it possible to obtain a small nonvolatile memory circuit with low power consumption while maintaining stable writing.
  • a nonvolatile storage circuit includes a volatile storage unit that stores information, the information in the volatile storage unit is written by a store operation, and a store path at the time of the store operation by a restore operation. Includes a non-volatile storage unit from which the information is read out to the volatile storage unit through different restore paths, and all the transistors arranged on the store path are connected to the drain.
  • the nonvolatile storage circuit stores a volatile storage unit that stores information, and the information in the volatile storage unit is written by a store operation.
  • a non-volatile storage unit from which the information is read to the volatile storage unit via a restore path different from the path is provided, and all transistors arranged on the store path are connected to the drain.
  • FIG. 3 is a diagram illustrating a configuration example of an NVDFF circuit of a footer type SSR-NVFF circuit system.
  • NVDFF circuit> ⁇ Configuration example of NVDFF circuit>
  • the source-connected transistors are not arranged on the store path, and all the transistors on the store path are connected to the drain so that the nonvolatile memory is small and has low power consumption while maintaining stable writing.
  • a memory circuit can be obtained.
  • Figure 1 shows the header type SSR-NVFF (Split Store / Restore-Non-Volatile Flip-Flop) circuit type NVDFF ((Non-Volatile D Flip-Flop) non-volatile as a nonvolatile memory circuit to which this technology is applied. It is a figure which shows the structural example of a flip-flop) circuit.
  • SSR-NVFF Split Store / Restore-Non-Volatile Flip-Flop
  • NVDFF Non-Volatile D Flip-Flop
  • the NVDFF circuit 11 shown in FIG. 1 includes a volatile storage unit 21, a store driver 22, a transistor 23, a store driver 24, a transistor 25, a transistor 26, a transistor 27, a nonvolatile storage unit 28, a control driver 29, and an OR circuit 30. And a transistor 31.
  • the transistor 23, the transistor 25, the transistor 26, the transistor 27, and the transistor 31 are nMOS transistors.
  • a pMOS transistor (not shown) is used as a PS (power switch) for PG.
  • PS power switch
  • PG power switch
  • the volatile storage unit 21 includes a flip-flop circuit that temporarily holds storage data that is information supplied from the outside, and more specifically, a storage node state such as a voltage level corresponding to the storage data.
  • the volatile memory unit 21 includes an inverter 41, a transmission gate 42, a master latch 43, a transmission gate 44, a slave latch 45, and an inverter 46.
  • the master latch 43 includes an inverter 51, an inverter 52, and a transmission gate 53.
  • the slave latch 45 includes an inverter 61, an inverter 62, a transmission gate 63, and a transistor 64.
  • the slave latch 45 has a storage node N11 and a storage node N12.
  • the transmission gate 42 and the transmission gate 63 are turned on when the clock signal CLK falls and turned off when the clock signal CLK rises.
  • the transmission gate 53 and the transmission gate 44 are turned off when the clock signal CLK falls and turned on when the clock signal CLK rises.
  • the input side of the inverter 41 is an input terminal of the volatile storage unit 21, and the output side of the inverter 41 is connected to the input side of the inverter 51 via the transmission gate 42.
  • the storage node N11 of the slave latch 45 is connected to the output side of the inverter 51 via the transmission gate 44, and the output terminal of the inverter 51 is also connected to the input side of the inverter 52.
  • the output side of the inverter 52 is connected to the input side of the inverter 51 via the transmission gate 53. That is, the output side of the transmission gate 53 is connected between the inverter 51 and the transmission gate 42 via the transmission gate 53.
  • the slave latch 45 has a storage node N11 and a storage node N12 that temporarily hold a voltage level corresponding to the input storage data, and an inverter 61 is interposed between the storage node N11 and the storage node N12. Is provided.
  • the storage node N12 is connected to input terminals of the inverter 46, the inverter 62, and the store driver 24.
  • the output side of the inverter 46 is an output terminal of the volatile storage unit 21.
  • the output side of the inverter 62 is connected to the storage node N11 via the transmission gate 63.
  • a transistor 64 that is an nMOS transistor is connected to both ends of the transmission gate 63. In other words, one end of the transistor 64 is connected to the input side of the transmission gate 63, and the other end of the transistor 64 is connected to the output side of the transmission gate 63.
  • a control signal R having a predetermined voltage level is supplied to the gate of the transistor 64.
  • the input terminal of the store driver 22 is also connected to the storage node N11.
  • the store driver 22 includes an inverter that is an inverting element. That is, the store driver 22 includes a transistor 71 that is a pMOS transistor and a transistor 72 that is an nMOS transistor.
  • one end of the transistor 71 is connected to the power supply, and the transistor 72 is connected to the other end of the transistor 71.
  • a control signal SR2 is supplied to the gate of the transistor 23.
  • the output side end of the inverter composed of the transistor 71 and the transistor 72 is connected to the non-volatile storage unit 28 via the node N13.
  • the store driver 24 is an inverter that is an inverting element. That is, the store driver 24 includes a transistor 81 that is a pMOS transistor and a transistor 82 that is an nMOS transistor.
  • one end of the transistor 81 is connected to the power source, and the transistor 82 is connected to the other end of the transistor 81.
  • a control signal SR2 is supplied to the gate of the transistor 25.
  • the output side end of the inverter composed of the transistor 81 and the transistor 82 is connected to the nonvolatile storage unit 28 via the node N14.
  • the non-volatile storage unit 28 is a non-volatile storage unit, and at the time of storing (writing), voltage level states at the storage node N11 and the storage node N12, that is, storage data is written into the non-volatile storage unit 28.
  • the storage data held in the nonvolatile storage unit 28 that is, the state of the held voltage level is read to the storage node N11 and the storage node N12 through a path different from the path at the time of storage. It is.
  • the nonvolatile storage unit 28 includes a storage element 91 and a storage element 92.
  • the storage element 91 and the storage element 92 are composed of nonvolatile storage elements such as MTJ which is a magnetoresistive element and ReRAM (Resistive Random Access Memory) which is a resistance change type memory.
  • MTJ magnetoresistive element
  • ReRAM Resistive Random Access Memory
  • MTJ consists of a fixed layer (p layer) and a free layer (f layer) and a barrier layer formed between the fixed layer and the free layer. It is a nonvolatile memory element that can be changed to a state.
  • an H level that is a higher voltage level is associated with a high resistance state, in other words, “1” as stored data
  • an L level that is a lower voltage level is associated with a low resistance state.
  • the low resistance state of the MTJ is referred to as a Parallel state (hereinafter also referred to as a P state), and the high resistance state is referred to as an Anti-Parallel state (hereinafter also referred to as an AP state).
  • a P state Parallel state
  • AP state Anti-Parallel state
  • the free layer of the storage element 91 is connected to the control line L11, and the side opposite to the free layer, that is, the fixed layer of the storage element 91 is connected to the node N14.
  • the node N14 is connected to the output-side end of the store driver 24 and is also connected to the storage node N11 via the transistor 26.
  • the free layer of the storage element 92 is connected to the control line L11, and the fixed layer of the storage element 92 is connected to the node N13.
  • the node N13 is connected to the output-side end of the store driver 22 and is also connected to the storage node N12 via the transistor 27.
  • the control signal SR1 is supplied to the gates of the transistor 26 and the transistor 27.
  • a control driver 29 for controlling a voltage level in the control line L11 is connected to the control line L11 connected to the storage element 91 and the storage element 92.
  • the control driver 29 is an inverter that is an inverting element. That is, the control driver 29 includes a transistor 101 that is a pMOS transistor and a transistor 102 that is an nMOS transistor.
  • one end of the transistor 101 is connected to the power source, and the transistor 102 and the control line L11 are connected to the other end of the transistor 101.
  • the end of the transistor 102 opposite to the end to which the transistor 101 and the control line L11 are connected is connected to the ground via the transistor 31.
  • the control signal CTRL is supplied to the input side end of the control driver 29, that is, the gate of the transistor 101 and the gate of the transistor 102.
  • the output side end of the OR circuit 30 is connected to the gate of the transistor 31, and the control signal SR1 and the control signal SR2 are supplied to the input side end of the OR circuit 30.
  • the transistor 31 in each NVDFF circuit 11 is turned on in the store mode and the restore mode. To be in a state.
  • one OR circuit common to all the plurality of cells that is, all of the plurality of NVDFF circuits 11, may be provided.
  • the NVDFF circuit 11 there are four operation modes, an active mode, a store mode, a sleep mode, and a restore mode.
  • an active mode When the NVDFF circuit 11 is operated, the operation mode transitions from the active mode to the store mode, the sleep mode, and the restore mode in order.
  • PS (not shown) is turned on. Further, the control signal SR1 is set to H level, and the transistors 26 and 27 are turned on. That is, the transistor 26 and the transistor 27 are turned on (conductive state). At this time, the control signal SR2 is set to the L level.
  • the output of the inverter 41 becomes the H level.
  • This H level is input to the inverter 51 at the timing when the clock signal CLK falls, that is, when the transmission gate 42 is turned on.
  • the transmission gate 53 and the transmission gate 44 are turned on, so that the output of the inverter 51 becomes L level by the loop of the inverter 51 and the inverter 52.
  • This L level is supplied as storage data to the storage node N11 via the transmission gate 44.
  • the transmission gate 53 and the transmission gate 44 are turned off, and the transmission gate 42 and the transmission gate 63 are turned on.
  • the loop composed of inverter 61 and inverter 62 holds (stores) the L level indicating the stored data at storage node N11, and holds the H level obtained by inverting the stored data at storage node N12.
  • control signal SR1 is set to L level and the transistors 26 and 27 are turned off, and the control signal SR2 is set to H level and the transistors 23 and 25 are turned on.
  • the transistor 71 is turned on in the store driver 22 connected to the storage node N11, and the output terminal of the store driver 22, that is, the node N13 is H Become a level.
  • the transistor 82 is turned on, and the output terminal of the store driver 24, that is, the node N14 becomes L level.
  • the transistor 101 is turned on in the control driver 29, and the output terminal of the control driver 29, that is, the control line L11 is set to the H level.
  • control driver 29 since the control line L11 is at the H level and the node N14 is at the L level, the control driver 29, the control line L11, the storage element 91, the node N14, the transistor 82, and the power supply connected to the control driver 29 Store current flows through transistor 25 to ground.
  • the state “H level” held in the storage node N12 is inverted by the store driver 24 and held (stored) in the storage element 91.
  • the state “H level” held in the storage node N12 is inverted and written (stored) in the storage element 91.
  • control driver 29 turns off the transistor 101 and turns on the transistor 102.
  • the output terminal of the control driver 29, that is, the control line L11 is connected to the ground and becomes L level.
  • the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor are connected from the power source connected to the store driver 22.
  • Store current flows through 31 to ground.
  • a current flows from the fixed layer connected to the node N13 side to the free layer connected to the control line L11 side, so that the memory element 92 is in a high resistance state, that is, AP It becomes a state.
  • the state “L level” held in the storage node N11 is inverted by the store driver 22 and held in the storage element 92.
  • the state “L level” held in the storage node N11 is inverted and written to the storage element 92.
  • the control signal CTRL is then set to the L level, and the store operation ends.
  • a store current path (hereinafter also referred to as a store path) during the above-described store operation is shown.
  • the broken line L21 indicates a store path when information (state) is stored in the storage element 91 at the timing when the control signal CTRL is set to the L level.
  • the transistor 101, the storage element 91, the transistor 82, and the transistor 25 are arranged on the store path indicated by the broken line L21.
  • the broken line L22 indicates a store path at the time of storing information (state) to the storage element 92 at the timing when the control signal CTRL is set to the H level.
  • the transistor 71, the storage element 92, the transistor 102, and the transistor 31 are arranged on the store path indicated by the broken line L22.
  • the transistor 23, the transistor 25, the transistor 31, and the OR circuit 30 in the NVDFF circuit 11 are not provided.
  • transistors are provided on the store path at a position corresponding to between the store driver 22 and the storage element 92 and at a position corresponding to between the store driver 24 and the storage element 91. .
  • either one of these two transistors will always be a source connection in which the MTJ is connected to the ground side with respect to the transistor.
  • the store current flows through the MTJ through the source-connected transistor, the store current is reduced due to the back bias effect. Therefore, if a sufficiently large store current is to be ensured, the gate width of the transistor must be increased, resulting in an increase in circuit scale.
  • the transistor 23, the transistor 25, and the transistor 31 are provided between the store driver 22, the store driver 24, and the control driver 29 and the ground, respectively.
  • NVDFF circuit 11 it is not necessary to provide a transistor between the store driver 22 and the storage element 92 or between the store driver 24 and the storage element 91.
  • NVDFF circuit 11 no source-connected transistors are arranged in the store path, and all the transistors in the store path are connected to the drain connected to the storage element on the opposite side to the ground side. It has become.
  • the transistor 25 arranged in the store path indicated by the broken line L21 has a drain connection in which the storage element 91 is connected to the drain side (power supply side).
  • the transistor 31 arranged in the store path indicated by the broken line L22 also has a drain connection in which the storage element 92 is connected to the drain side. Further, when a store current flows through the transistor 23 during storage, the store current flows from the storage element 92 through the transistor 23 to the ground. In this case, the transistor 23 is connected to the drain.
  • the store current is not reduced due to the back bias effect, so that a sufficient store current can be ensured even if a transistor having a narrow gate width is used, and the circuit scale of the entire NVDFF circuit 11 is ensured. Can be kept small.
  • the NVDFF circuit 11 has a structure in which the voltage level of the storage node of the slave latch 45 is received by the store driver at the time of store, and the output is written to the storage element through a path that does not affect the voltage level of the storage node. Therefore, latch breakdown does not occur. That is, stable writing can be performed.
  • the NVDFF circuit 11 can provide a small NVDFF circuit 11 with low power consumption while maintaining stable writing.
  • the state transits to the sleep mode at an appropriate timing.
  • the PS (not shown) is turned off, and the power supplied to the NVDFF circuit 11 is shut off. As a result, the voltage level on the output side of the inverter 46 becomes L level.
  • control signal SR1 is set to H level to turn on the transistors 26 and 27, and the control signal SR2 is set to L level to turn off the transistors 23 and 25 (non-conductive state).
  • control signal CTRL is set to H level, the transistor 102 of the control driver 29 is turned on, and the control line L11 is connected to the ground. That is, the control line L11 becomes L level.
  • the storage element 91 is in the low resistance state, that is, the P state
  • the storage element 92 is in the high resistance state, that is, the AP state, as in the above example.
  • a restore current flows through four paths (hereinafter also referred to as a restore path) of broken lines L41 to L44.
  • the restore path indicated by the broken line L41 is a path through which a restore current flows from the power source to the ground through the transistor 81, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
  • the restore path indicated by the broken line L42 is a path through which a restore current flows from the inverter 62 to the ground through the transmission gate 63, the transistor 26, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
  • the restore path indicated by the broken line L43 is a path through which a restore current flows from the power source to the ground through the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
  • the restore path indicated by the broken line L44 is a path through which a restore current flows from the inverter 61 to the ground through the transistor 27, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
  • the transistor 27 has a significantly lower conductance than the transistor 26 due to an increase in the source voltage. Therefore, the current flowing through the transistor 27 is smaller than the current flowing through the transistor 26 more than the difference in resistance between the memory element 91 and the memory element 92.
  • the voltage at the storage node N12 rises higher than the voltage at the storage node N11, positive feedback is applied in the loop composed of the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N12 becomes the power supply voltage (H level).
  • the storage node N11 is at the ground level (L level). That is, the storage node N11 and the storage node N12 are restored to the same voltage level state at the time of storage.
  • the NVDFF circuit described in Document 1 elements corresponding to the transistor 23 and the transistor 25 in the NVDFF circuit 11 are not provided.
  • the NVDFF circuit 11 is provided with the transistor 23 and the transistor 25, so that the restoration time can be shortened without wasteful power consumption during restoration.
  • the transistor 23 is not provided in the NVDFF circuit 11.
  • the input terminal of the store driver 22 becomes an intermediate voltage between the power supply voltage and the ground level. Both transistors 72 are turned on.
  • the NVDFF circuit 11 is provided with the transistor 23, and the transistor 23 is in the off state during the restore operation. For this reason, in the store driver 22, useless current does not flow from the power source to the ground, but current flows from the power source along the path indicated by the broken line L 43, and the current becomes a restore current.
  • the restore current flows only in the path indicated by the polygonal line L 42 and the polygonal line L 44 in the related art so that the restore current also flows in the path indicated by the polygonal line L 41 and the polygonal line L 43 in addition to them.
  • the restore current becomes larger as a whole, the time until the voltage levels of the storage node N11 and the storage node N12 return to the store state can be further shortened.
  • the short circuit at the time of restoration is used for charging the storage node, useless power consumption can be reduced and the restoration time can be shortened.
  • the operations of the active mode, the store mode, the sleep mode, and the restore mode described above are performed according to the input storage data.
  • the NVDFF circuit is configured as shown in FIG. 4, for example.
  • FIG. 4 portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
  • the NVDFF circuit 201 shown in FIG. 4 is an NVDFF circuit of a footer type SSR-NVFF circuit system.
  • an nMOS transistor (not shown) is used for PG. Specifically, for example, when the PS is turned on, each part of the NVDFF circuit 201 is connected to the ground via the nMOS transistor, and when the PS is turned off, each part of the NVDFF circuit 201 is electrically disconnected from the ground and PG Is realized.
  • the NVDFF circuit 201 includes a volatile storage unit 21, a store driver 22, a transistor 23, a store driver 24, a transistor 25, a transistor 211, a transistor 212, a nonvolatile storage unit 213, a control driver 29, an XNOR circuit 214, and a transistor 31. have.
  • the circuit configuration of the NVDFF circuit 201 includes a transistor 211, a transistor 212, a nonvolatile memory unit 213, and an XNOR circuit 214 instead of the transistor 26, the transistor 27, the nonvolatile memory unit 28, and the OR circuit 30 in the NVDFF circuit 11. It becomes the composition.
  • the nonvolatile storage unit 213 includes a storage element 221 and a storage element 222 made of MTJ, ReRAM, or the like.
  • a storage element 221 and a storage element 222 made of MTJ, ReRAM, or the like.
  • the description will be continued assuming that the memory element 221 and the memory element 222 are MTJ.
  • a transistor 211 is provided between the storage node N11 and the node N14, and a transistor 212 is provided between the storage node N12 and the node N13.
  • the transistors 211 and 212 are pMOS transistors, and a control signal SR1 is supplied to the gates of the transistors 211 and 212.
  • the fixed layer (p layer) of the storage element 221 is connected to the control line L11, and the free layer (f layer) of the storage element 221 is connected to the node N14. Further, the fixed layer of the storage element 222 is connected to the control line L11, and the free layer of the storage element 222 is connected to the node N13.
  • NVDFF circuit 201 As in the NVDFF circuit 11, all transistors in the store path are connected to the drain.
  • the transistor 25 and the transistor 23 arranged in the store path have a drain connection in which the storage element 221 and the storage element 222 are connected to the drain side.
  • the transistor 31 arranged in the store path has a drain connection in which the storage element 221 and the storage element 222 are connected to the drain side.
  • control signal SR1 and the control signal SR2 are supplied to the input terminal of the XNOR circuit 214, and the output terminal of the XNOR circuit 214 is connected to the transistor 31.
  • the NVDFF circuit 201 performs the same operation as that of the NVDFF circuit 11 described above in the active mode.
  • control signal SR1 is set to H level to turn off the transistors 211 and 212
  • control signal SR2 is set to H level to turn on the transistors 23 and 25.
  • control signal CTRL is set to H level, and then the control signal CTRL is set to L level, and the state of the storage node is stored in the nonvolatile storage unit 213.
  • the state of the storage node N11 is L level and the state of the storage node N12 is H level.
  • the transistor 71 of the store driver 22 is turned on and the node N13 becomes H level, and the transistor 82 of the store driver 24 is turned on and the node N14 becomes L level.
  • the storage current flows from the control line L11 side to the node N14 side in the storage element 221, and the storage element 221 is in the high resistance state (AP state). It becomes.
  • the state of the voltage level of the storage node N12 is held (stored) in the storage element 221 as it is by the store driver 24.
  • the NVDFF circuit 201 similarly to the case of the NVDFF circuit 11, no source-connected transistors are arranged in the store path, and all the transistors in the store path are drain-connected. That is, the transistor 23, the transistor 25, and the transistor 31 are drain connected.
  • the PS (not shown) is turned off and the PG is realized. After that, when returning from the sleep state, the operation in the restore mode is performed.
  • control signal SR1 is set to the L level and the transistors 211 and 212 are turned on, and the control signal SR2 is set to the L level and the transistors 23 and 25 are turned off.
  • control signal CTRL is set to L level
  • the transistor 101 of the control driver 29 is turned on, and the control line L11 is connected to the power source. That is, the control line L11 becomes H level.
  • the memory element 221 is in the high resistance state (AP state) and the memory element 222 is in the low resistance state (P state) as in the above example.
  • the voltage of the node N14 is set to the node due to the difference in electrical resistance between the memory element 221 and the memory element 222 when the restore current flows. Lower than the voltage of N13.
  • the transistor 211 a decrease in conductance due to a decrease in source voltage appears more significantly than in the transistor 212. Accordingly, the current flowing through the transistor 211 is smaller than the current flowing through the transistor 212 more than the difference between the resistances of the memory element 221 and the memory element 222.
  • the voltage at the storage node N11 is lower than the voltage at the storage node N12, positive feedback is applied in the loop composed of the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N12 becomes the power supply voltage (H level).
  • the storage node N11 is at the ground level (L level). That is, the storage node N11 and the storage node N12 are restored to the same voltage level state at the time of storage.
  • the transistor 23 and the transistor 25 are in an off state, so that a restore current does not flow from the transistor 23 or the transistor 25 to the ground, and wasteful power consumption occurs. It is suppressed.
  • the operation in each of the active mode, the store mode, the sleep mode, and the restore mode is performed according to the input storage data.
  • NVDFF circuit 201 as described above, as in the case of the NVDFF circuit 11, it is possible to achieve downsizing and keep power consumption low while maintaining stable writing.
  • the present technology can be configured as follows.
  • a volatile storage unit for storing information A non-volatile storage unit in which the information in the volatile storage unit is written by a store operation, and the information is read to the volatile storage unit by a restore path different from the store path at the time of the store operation by a restore operation; With A non-volatile memory circuit in which all the transistors arranged on the store path are connected to the drain.
  • the store driver is an inverting element.
  • the volatile storage unit has a first storage node and a second storage node,
  • the nonvolatile storage unit includes a first storage element and a second storage element, The first storage node and the first storage element are connected via a third transistor;
  • the first storage node and the second storage element are connected via the store driver;
  • the nonvolatile memory circuit according to (9), wherein the second storage node and the first storage element are connected via the other store driver.
  • (11) The nonvolatile memory circuit according to (9) or (10), wherein the first memory element and the second memory element are MTJs.
  • NVDFF circuit 21 volatile storage unit, 22 store driver, 23 transistor, 24 store driver, 25 transistor, 28 non-volatile storage unit, 29 control driver, 30 OR circuit, 31 transistor, 91 storage element, 92 storage element

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Abstract

La présente invention concerne un circuit de stockage non volatil qui permet une miniaturisation et une consommation d'énergie réduite tout en maintenant une écriture stable. Ce circuit de stockage non volatil est pourvu d'une unité de stockage volatile qui stocke des informations, et d'une unité de stockage non volatile dans laquelle les informations dans l'unité de stockage volatile sont écrites par une opération de stockage, et à partir desquelles des informations sont lues dans l'unité de stockage volatile par une opération de restauration par l'intermédiaire d'un chemin de restauration qui est différent du chemin de stockage pour l'opération de stockage, tous les transistors disposés le long du chemin de stockage comportant leurs drains connectés ensemble. La présente technique peut être appliquée à des circuits NVDFF.
PCT/JP2019/015073 2018-04-19 2019-04-05 Circuit de stockage non volatil WO2019203019A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201980015138.XA CN112020744A (zh) 2018-04-19 2019-04-05 非易失性存储电路
JP2020514076A JP7282749B2 (ja) 2018-04-19 2019-04-05 不揮発性記憶回路
DE112019002007.2T DE112019002007T5 (de) 2018-04-19 2019-04-05 Nichtflüchtige speicherschaltung

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291929A (ja) * 1992-04-14 1993-11-05 Hitachi Ltd 半導体回路
WO2009060625A1 (fr) * 2007-11-08 2009-05-14 Panasonic Corporation Circuit de verrouillage non volatile et circuit bascule non volatile
JP2011123987A (ja) * 2009-12-09 2011-06-23 Samsung Electronics Co Ltd 不揮発性論理回路、該不揮発性論理回路を備える集積回路、及び該集積回路の動作方法
WO2016185903A1 (fr) * 2015-05-15 2016-11-24 ソニー株式会社 Circuit de mémoire non volatile
WO2017150028A1 (fr) * 2016-02-29 2017-09-08 ソニー株式会社 Circuit à semi-conducteurs, procédé de commande de circuit à semi-conducteurs et dispositif électronique
JP2017208146A (ja) * 2016-05-16 2017-11-24 ソニー株式会社 半導体回路、駆動方法、および電子機器
WO2018088297A1 (fr) * 2016-11-14 2018-05-17 ソニーセミコンダクタソリューションズ株式会社 Circuit à semi-conducteur et système de circuit à semi-conducteur

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151898A (ja) * 1984-01-18 1985-08-09 Nec Corp 不揮発性ランダムアクセスメモリセル
DE60043651D1 (de) * 1999-02-01 2010-02-25 Renesas Tech Corp Integrierte halbleiterschaltung und nichtflüchtiges speicherelement
JP4191355B2 (ja) * 2000-02-10 2008-12-03 株式会社ルネサステクノロジ 半導体集積回路装置
US7369446B2 (en) * 2006-07-13 2008-05-06 Atmel Corporation Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory
US9342259B2 (en) * 2012-09-10 2016-05-17 Texas Instruments Incorporated Nonvolatile logic array and power domain segmentation in processing device
US10607700B2 (en) * 2016-01-15 2020-03-31 Sony Corporation Semiconductor circuit, driving method, and electronic apparatus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291929A (ja) * 1992-04-14 1993-11-05 Hitachi Ltd 半導体回路
WO2009060625A1 (fr) * 2007-11-08 2009-05-14 Panasonic Corporation Circuit de verrouillage non volatile et circuit bascule non volatile
JP2011123987A (ja) * 2009-12-09 2011-06-23 Samsung Electronics Co Ltd 不揮発性論理回路、該不揮発性論理回路を備える集積回路、及び該集積回路の動作方法
WO2016185903A1 (fr) * 2015-05-15 2016-11-24 ソニー株式会社 Circuit de mémoire non volatile
WO2017150028A1 (fr) * 2016-02-29 2017-09-08 ソニー株式会社 Circuit à semi-conducteurs, procédé de commande de circuit à semi-conducteurs et dispositif électronique
JP2017208146A (ja) * 2016-05-16 2017-11-24 ソニー株式会社 半導体回路、駆動方法、および電子機器
WO2018088297A1 (fr) * 2016-11-14 2018-05-17 ソニーセミコンダクタソリューションズ株式会社 Circuit à semi-conducteur et système de circuit à semi-conducteur

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DE112019002007T5 (de) 2021-01-21
CN112020744A (zh) 2020-12-01

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