WO2019201327A1

WO2019201327A1 - Linear constant current drive chip and multi-chip parallel led lighting circuit

Info

Publication number: WO2019201327A1
Application number: PCT/CN2019/083364
Authority: WO
Inventors: 邵蕴奇
Original assignee: 上海路傲电子科技有限公司
Priority date: 2018-04-20
Filing date: 2019-04-19
Publication date: 2019-10-24
Also published as: CN111935874A; CN108366462B; CN111935874B; CN108366462A

Abstract

The present invention relates to LED lighting circuits. Disclosed are a linear constant current drive chip and a multi-chip parallel LED lighting circuit. The linear constant current drive chip comprises a linear constant current drive circuit, a metal base plate, and at least eight pins. The pins are symmetrically distributed on both sides of the metal base plate. Each pin comprises a first power end, a second power end, at least one intermediate power end disposed on one side of the metal base plate, and the same number of additional intermediate power ends disposed on the other side of the metal base plate. The intermediate power ends and the additional intermediate power ends are in one-to-one correspondence according to the same order, and the corresponding intermediate power ends and additional intermediate power ends are connected. The first power end, the intermediate power ends, the second power end, and the additional intermediate power ends are sequentially arranged around the metal base plate. When the linear constant current drive chip is used for forming a multi-chip parallel LED lighting circuit, a line does not need to use a jumper, and the circuit is simple and features high reliability.

Description

Linear constant current driving chip and multi-chip parallel LED lighting circuit

The present application claims priority to Chinese Patent Application No. CN201810360250.4, filed on Apr. 20, 2018. This application cites the entire text of the above-mentioned Chinese patent application.

Technical field

The invention relates to an LED lighting circuit, in particular to a linear constant current driving chip and a multi-chip parallel LED lighting circuit.

Background technique

Existing high-power LED lighting driver circuits, the rated power of a linear constant-current driving chip can not meet the needs of use, often need to use multiple linear constant-current driving chips in parallel to form a multi-chip parallel LED lighting circuit to expand power.

Referring to FIG. 1 , a conventional multi-chip parallel LED lighting circuit including three linear constant current driving chips includes a rectifier circuit, three linear constant current driving chips connected in parallel, and a series lighting group formed by connecting three LEDs in series. The rectifier circuit is a bridge rectifier circuit composed of four diodes. The input end of the rectifier circuit is connected to the mains, the anode of the output of the rectifier circuit is connected to the cathode of the series illumination group, and the cathode of the output end of the rectifier circuit is grounded and connected to the anode of the series illumination group. The grounding ends of the three linear constant current driving chips are grounded; the eight linear constant current driving chips have 8 pins connected to each other, 7 pins are connected to each other, and 6 pins are connected to each other; the linear constant current driving chip has 8 pins and 7 pins. The pin and the 6 pin are respectively connected to the positive electrodes of the three LEDs.

In the existing multi-chip parallel LED lighting circuit, three linear constant current driving chips ensure that the current flowing through each of the light emitting diodes is a constant current. However, considering the heat dissipation of the LED and the linear constant current driving chip, the multi-chip parallel LED lighting circuit is usually soldered on the same single-sided copper-clad aluminum substrate, so that the intersections of the wires in the multi-chip parallel LED lighting circuit are It needs to be realized by jumpers, which increases the cost and the board area, and reduces the reliability of the multi-chip parallel LED lighting circuit, which is prone to short circuit.

Summary of the invention

It is an object of the present invention to provide a linear constant current driving chip and a multi-chip parallel LED lighting circuit to solve the problems set forth in the above background art.

To achieve the above object, the present invention provides a linear constant current driving chip including a linear constant current driving circuit, a metal substrate, and at least 8 pins; the metal substrate is exposed outside the linear constant current driving chip; Pins are symmetrically distributed on both sides of the metal base plate; the pin includes a first power end and a second power end; the pin further includes at least one intermediate power end disposed on one side of the metal base plate, and Having the same number of additional intermediate power terminals on the other side of the metal backplane; the intermediate power end and the additional intermediate power end are in one-to-one correspondence in the same arrangement order, corresponding to the intermediate power end and the The additional intermediate power terminals are connected to each other; the first power terminal, the intermediate power terminal, the second power terminal, and the additional intermediate power terminal are sequentially arranged around the metal base plate.

Further, the metal base plate, at least one pin on a side of the intermediate power end, and at least one pin on a side of the additional intermediate power end serve as first, second, and third ground ends, respectively.

Further, the intermediate power end and the additional intermediate power end are located on the same side of the second ground end and the third ground end connection; the first power end and the second power end are located in the first The two grounding ends and the third grounding end are connected to different sides of the line.

Further, the linear constant current driving circuit includes an enabling unit, a control circuit, and at least one MOS transistor; the MOS transistor includes a first MOS transistor, a second MOS transistor, and at least one intermediate MOS transistor; and the control circuit a resistor and an operational amplifier; the resistor includes a first resistor, a second resistor, a sampling resistor, and at least one intermediate resistor; the operational amplifier includes a first operational amplifier, a second operational amplifier, and at least one intermediate operational amplifier; The first resistor, the intermediate resistor and the second resistor are connected in series to each other to form a resistor series group, and the first resistor and the second resistor are located at two ends of the resistor series group; the first resistor is not One end connected to the intermediate resistor is connected to a common ground; an input terminal of the first operational amplifier is positively connected to an end of the first resistor not connected to the common ground; and an input terminal of the second operational amplifier is positively connected An end of the second resistor that is not connected to the intermediate resistor; a positive terminal of the input terminal of the intermediate operational amplifier sequentially connects one end of the intermediate resistor away from the common ground The input terminal of all of the operational amplifiers and the source of all of the MOS transistors are connected in common via the sampling resistor; the output of the first operational amplifier is connected to the gate of the first MOS transistor; An output end of the second operational amplifier is connected to a gate of the second MOS transistor; an output end of the intermediate operational amplifier is sequentially connected to a gate of the middle | MOS transistor; and an output terminal of the enabling unit is connected The input terminal of the second operational amplifier is positive, the other output is connected to the drain of the first MOS transistor; the drain of the first MOS transistor is connected to the first power terminal; and the drain of the second MOS transistor a pole connected to the second power terminal; a drain of the intermediate MOS transistor is connected to the intermediate power terminal in order; the drain of the middle MOS transistor is connected to the additional intermediate power terminal in the same order; Commonly connected to any one of the first ground terminal, the second ground terminal, and the third ground terminal.

DRAWINGS

1 is a schematic structural view of a conventional multi-chip parallel LED lighting circuit;

2 is a schematic structural view of Embodiment 1 of a linear constant current driving chip of the present invention;

3 is a schematic structural view of a linear constant current driving circuit of a linear constant current driving chip of the present invention;

4 is a schematic structural view of Embodiment 1 of a multi-chip parallel LED lighting circuit of the present invention;

5 is a schematic structural diagram of Embodiment 2 of a linear constant current driving chip of the present invention;

6 is a schematic structural view of a linear constant current driving circuit of a second embodiment of the linear constant current driving chip of the present invention;

7 is a schematic structural view of a second embodiment of a multi-chip parallel LED lighting circuit of the present invention.

In the reference numerals: 11, first pin; 12, second pin; 13, third pin; 14, fourth pin; 15, fifth pin; 16, sixth pin; Seven pins; 18, eighth pin; 19, ninth pin; 10, tenth pin; 2, metal backplane; 3, linear constant current drive circuit; 4, enable unit; 5, printed power ground .

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Example 1

As shown in FIG. 2, the linear constant current driving chip of the present invention comprises eight pins, a metal substrate 2 and a linear constant current driving circuit 308 pins symmetrically distributed on both sides of the metal substrate 2, one side of which is left side. The other side is the right side, and the four pins on the left side of the metal base plate 2 are the first pin 11, the second pin 12, the third pin 13, and the fourth pin 14 from top to bottom. The four pins on the right side of the metal substrate 2 are the fifth pin 15, the sixth pin 16, the seventh pin 17, and the eighth pin 18 from bottom to top. The linear constant current driving circuit 3 is fixed on the metal base plate 2, and the metal base plate 2 is exposed outside the linear constant current driving chip.

As shown in FIG. 3, the linear constant current driving circuit 3 includes a control circuit M1, an enabling unit 4, and three MOS transistors. The three MOS transistors include a first MOS transistor Q1, a second MOS transistor Q2, and an intermediate MOS transistor Q3. The control circuit M1 includes four resistors and three operational amplifiers, and the four resistors include a first resistor R1, a second resistor R2, a sampling resistor RCS, and an intermediate resistor R3. The three operational amplifiers include a first operational amplifier OP1 and a second operational amplifier. OP2 and intermediate operational amplifier OP3. The input terminal of the first operational amplifier OP1, the second operational amplifier OP2, and the intermediate operational amplifier OP3 and the first MOS transistor Q1, the second MOS transistor Q2, and the source of the intermediate MOS transistor are both connected to one end of the sampling resistor RCS, and are sampled. The other end of the resistor RCS is connected to the common ground COM. The output end of the first operational amplifier OP1 is connected to the gate of the first MOS transistor Q1, the output end of the intermediate operational amplifier OP3 is connected to the gate of the intermediate MOS transistor Q3, and the output end of the second operational amplifier OP2 is connected to the gate of the second MOS transistor Q2. pole. One end of the first resistor R1 is connected to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the common ground COM; one end of the intermediate resistor R3 is connected to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the positive terminal of the input terminal of the intermediate operational amplifier OP3; The second resistor R2 has one end connected to the positive terminal of the input terminal of the intermediate operational amplifier OP3, and the other end connected to the positive terminal of the input terminal of the second operational amplifier OP2. One output of the enabling unit 3 is connected to the positive terminal of the input terminal of the second operational amplifier OP2, and the other output terminal is connected to the drain of the first MOS transistor Q1.

As shown in FIG. 2 and FIG. 3, the drain of the first MOS transistor Q1 is connected to the eighth pin 18 as the first power terminal D1; the drain of the intermediate MOS transistor Q3 is connected to the seventh pin 17 as the intermediate power terminal D3B, and The drain of the intermediate MOS transistor Q3 is connected to the first pin 11 as an additional intermediate power terminal D3A; the drain of the second MOS transistor Q2 is connected to the fifth pin 15 as the second power terminal D2; the common ground of the linear constant current driving circuit 3 The COM is connected to the metal backplane 2 as the first ground terminal GND1; the common ground COM of the linear constant current driving circuit 3 is also connected to the sixth pin 16 as the second ground terminal GND2; the common ground COM of the linear constant current driving circuit 3 is also connected to the third Pin 13 serves as a third ground terminal GND3.

The voltage provided by the enabling unit 4 is divided into three voltage signals by the first resistor R1, the intermediate resistor R3 and the second resistor R2 connected in series, and the first operational amplifier OP1, the intermediate operational amplifier OP3 and the second operational amplifier OP2 are received. The voltage signals of different sizes are controlled to sequentially increase the magnitude and priority of the current flowing through the sampling resistor RCS via the first MOS transistor Q1, the intermediate MOS transistor Q3, and the second MOS transistor Q2.

As shown in FIG. 4, the multi-chip parallel LED lighting circuit of the present invention comprises three linear constant current driving chips, and the three linear constant current driving chips are all the linear constant current driving chips proposed by the present invention, including the first driving chip, The second driving chip U2 and the third driving chip mountain. The multi-chip parallel LED lighting circuit of the invention further comprises a bridge rectifier circuit DB and three light-emitting diodes, and the three light-emitting diodes comprise a first light-emitting diode LED1, an intermediate light-emitting diode LED3 and a second light-emitting diode LED2. The bridge rectifier circuit DB is a bridge rectifier circuit composed of four diodes. As a power supply unit, its input terminal is connected to the mains VAC for converting AC power from the commercial VAC into DC power. The positive terminal of the positive electrode bridge rectifier circuit DB of the first light emitting diode LED1 is connected to the anode of the first light emitting diode LED1, and the anode of the second light emitting diode LED2 is connected to the cathode of the intermediate light emitting diode LED3. The first driving chip U1, the second driving chip U2, and the first driving terminal D1 of the third driving chip mountain (ie, the eighth pin 18) are connected to the negative electrode of the first LED 131; the first driving chip U1 and the second driving The second power terminal D2 of the chip U2 and the third driver chip mountain (ie, the fifth pin 15) are connected to the negative pole of the second LED diode 2; the old intermediate power terminal D3B of the first driver chip (ie, the seventh pin 17) An additional intermediate power terminal D3A (ie, the first pin 11) connected to the second driver chip mountain is connected, and an intermediate power terminal D3B (ie, the seventh pin 17) of the second driver chip mountain is connected to the additional intermediate power terminal of the third driver chip mountain. D3A (ie, the first pin 11), and the intermediate power terminal D3B of the third driver chip mountain (ie, the seventh pin 17) is connected to the cathode of the intermediate light emitting diode LED3. The first driving chip U1, the second driving chip U2, and the first grounding terminal GND1 of the third driving chip mountain (ie, the metal substrate 2), the second grounding terminal GND2 (ie, the sixth pin 16), and the third grounding terminal GND3 ( That is, the third pin 13) is connected to each other through the printed power ground 5, and the printed power ground 5 is at the bottom of the metal base plate 2, which is a line printed on the substrate, and is a straight line, reducing the printed power ground 5 and The probability of the other lines crossing, the printed power ground 5 passes through the bottoms of the first driving chip U1, the second driving chip U2, and the third driving chip mountain. The printed power ground 5 is connected to the negative terminal of the output of the bridge rectifier circuit DB and grounded. The lines in the multi-chip parallel LED lighting circuit do not cross each other.

Considering the heat dissipation of the LED and the linear constant current driving chip, the multi-chip parallel LED lighting circuit is usually soldered on the same single-sided copper-clad aluminum substrate, as shown in FIG. 4, the multi-chip parallel LED lighting circuit of the present invention There is no cross between the lines, no jumper is needed for each part of the line connection, the reliability is high, the circuit is simple, the cost is low, and the area is small.

Example 2

As shown in FIG. 5, the linear constant current driving chip of the present invention comprises 10 pins, a metal substrate 2 and a linear constant current driving circuit 3010 pins symmetrically distributed on both sides of the metal substrate 2, one side of which is left side. The other side is the right side, and the five pins on the left side of the metal base plate 2 are the first pin 11, the second pin 12, the third pin 13, the fourth pin 14 and the first from the top to the bottom. Five pins 15, five pins on the right side of the metal substrate 19 are the sixth pin 16, the seventh pin 17, the eighth pin 18, the ninth pin 19 and the tenth pin from bottom to top. 10. The linear constant current driving circuit 3 is fixed on the metal base plate 2, and the metal base plate 2 is exposed outside the linear constant current driving chip.

As shown in FIG. 6, the linear constant current driving circuit 3 includes a control circuit M1, an enabling unit 4, and four MOS transistors, and the four MOS transistors include a first MOS transistor Q1, a second MOS transistor Q2, and a first intermediate MOS transistor Q3. And the second intermediate MOS regulation. The control circuit M1 includes five resistors and four operational amplifiers, and the five resistors include a first resistor R1, a second resistor R2, a sampling resistor RCS, a first intermediate resistor R3, and a second intermediate resistor. The four operational amplifiers include the first The operational amplifier OP1, the second operational amplifier OP2, the first intermediate operational amplifier OP3, and the second intermediate operational amplifier OP4. The input terminal negative electrode of the first operational amplifier OP1, the second operational amplifier OP2, the first intermediate operational amplifier OP3 and the second intermediate operational amplifier OP4 and the first MOS transistor Q1, the second MOS transistor Q2, the first intermediate MOS transistor Q3 and the first The source of the two intermediate MOS control is connected to one end of the sampling resistor RCS, and the other end of the sampling resistor RCS is connected to the common ground COM. The output end of the first operational amplifier OP1 is connected to the gate of the first MOS transistor Q1, the output end of the first intermediate operational amplifier OP3 is connected to the old gate of the first intermediate MOS transistor, and the output end of the second intermediate operational amplifier OP4 is connected to the second The gate of the intermediate MOS regulation, the output of the second operational amplifier OP2 is connected to the gate of the second MOS transistor Q2. The first resistor R1 is connected at one end to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the common ground COM; the first intermediate resistor R3 is connected at one end to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the first intermediate operational amplifier. The input terminal of the P3 is positive; the second intermediate resistor R4 is connected to the positive terminal of the input terminal of the first intermediate operational amplifier OP3, the other terminal is connected to the positive terminal of the input terminal of the second intermediate operational amplifier OP4; and the second resistor R2 is connected to the second intermediate operational amplifier at one end. The input terminal of P4 is positive, and the other end is connected to the positive terminal of the input terminal of the second operational amplifier OP2. One output of the enabling unit 4 is connected to the positive terminal of the input terminal of the second operational amplifier OP3, and the other output terminal is connected to the drain of the first MOS transistor Q1.

As shown in FIG. 5 and FIG. 6, the drain of the first MOS transistor Q1 is connected to the tenth pin 10 as the first power terminal D1; the old drain of the first intermediate MOS transistor is connected to the seventh pin 17 as the first intermediate power. Terminal D3B, and the old drain of the first intermediate MOS transistor is connected to the third pin 13 as the first additional intermediate power terminal D3A; the second intermediate MOS regulated drain is connected to the sixth pin 16 as the second intermediate power terminal D4B, And the second intermediate MOS regulated drain is connected to the fourth pin 14 as the second additional intermediate power terminal D4A; the drain of the second MOS transistor Q2 is connected to the fifth pin 15 as the second power terminal D2; the linear constant current driving circuit The common ground COM of 3 is connected to the metal base plate 2 as the first ground terminal GND1; the common ground COM of the linear constant current drive circuit 3 is also connected to the ninth pin 19 as the second ground terminal GND2; the common ground of the linear constant current drive circuit 3 The second pin 12 is also connected as the third ground GND3.

The voltage provided by the enabling unit 4 is divided into four voltage signals by the first resistor R1, the first intermediate resistor R3, the second intermediate resistor R4 and the second resistor R2 connected in series, and the first operational amplifier OP1 is first intermediately operated. The amplifier OP3, the second intermediate operational amplifier OP4, and the second operational amplifier OP2 receive voltage signals of different magnitudes to flow through the first MOS transistor Q1, the first intermediate MOS transistor Q3, the second intermediate MOS regulator, and the second MOS transistor Q2. The magnitude and priority of the current on the oversampling resistor RCS is incremented.

As shown in FIG. 7, the multi-chip parallel LED lighting circuit of the present invention comprises three linear constant current driving chips, and the three linear constant current driving chips are all the linear constant current driving chips proposed by the present invention, including the first driving chip, The second driving chip U2 and the third driving chip mountain. The multi-chip parallel LED lighting circuit of the invention further comprises a bridge rectifier circuit DB and four light emitting diodes, and the four light emitting diodes comprise a first light emitting diode LED1, a first intermediate light emitting diode LED3, a second intermediate light emitting diode LED4 and a second light emitting diode. LED2. The bridge rectifier circuit DB is a bridge rectifier circuit composed of four diodes. As a power supply unit, its input terminal is connected to a mains VAC for converting alternating current from the commercial VAC into direct current. The positive terminal of the positive electrode bridge rectifier circuit DB of the first light emitting diode LED1 is positive, the positive electrode of the first intermediate light emitting diode LED3 is connected to the negative electrode of the first light emitting diode LED1, and the positive electrode of the second intermediate light emitting diode LED4 is connected to the first intermediate light emitting diode LED3. The anode of the second light emitting diode LED2 is connected to the cathode of the second intermediate light emitting diode LED4. The first driving chip U1, the second driving chip U2, and the first driving terminal D1 of the third driving chip mountain (ie, the tenth pin 10) are connected to the negative electrode of the first light emitting diode LED1; the first driving chip U1 and the second driving The second power terminal D2 of the chip U2 and the third driver chip mountain (ie, the fifth pin 15) are connected to the negative pole of the second LED diode 2; the first first intermediate power terminal D3B of the first driver chip (ie, the seventh pin) 17) connecting the first additional intermediate power terminal D3A (ie, the third pin 13) of the second driver chip mountain, and the first intermediate power terminal D3B (ie, the seventh pin 17) of the second driver chip mountain is connected to the third driver chip a first additional intermediate power terminal D3A of the mountain (ie, the third pin 13), and the first intermediate power terminal D3B of the third driver chip mountain (ie, the seventh pin 17) is connected to the cathode of the first intermediate light emitting diode LED3; The second intermediate power terminal D4B of the driving chip U1 (ie, the sixth pin 16) is connected to the second additional intermediate power terminal D4A (ie, the fourth pin 14) of the second driving chip mountain, and the second driving chip mountain is second. The intermediate power terminal D4B (ie, the sixth pin 16) is connected to the second additional intermediate power terminal D4A of the third driver chip mountain (ie, The fourth pin 14), and the second intermediate power terminal D4B of the third driver chip mountain (ie, the sixth pin 16) is connected to the cathode of the second intermediate light emitting diode LED4. The first driving chip U1, the second driving chip U2, and the first grounding terminal GND1 of the third driving chip mountain (ie, the metal substrate 2), the second grounding terminal GND2 (ie, the ninth pin 19), and the third grounding terminal GND3 ( That is, the second pins 12) are connected to each other through the printed power ground 5, and the printed power ground 5 is at the bottom of the metal base plate 2, which is a line printed on the substrate, and is a straight line, reducing the printed power ground 5 and The probability of the other lines crossing, the printed power ground 5 passes through the bottoms of the first driving chip U1, the second driving chip U2, and the third driving chip mountain. The printed power ground 5 is connected to the negative terminal of the output of the bridge rectifier circuit DB and grounded. The lines in the multi-chip parallel LED lighting circuit do not cross each other.

Considering the heat dissipation of the LED and the linear constant current driving chip, the multi-chip parallel LED lighting circuit is usually soldered on the same single-sided copper-clad aluminum substrate, as shown in FIG. 7, the multi-chip parallel LED lighting circuit of the present invention There is no cross between the lines, no jumper is needed for each part of the line connection, the reliability is high, the circuit is simple, the cost is low, and the area is small.

While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the invention is defined by the appended claims and their equivalents.

Claims

A linear constant current driving chip, comprising: a linear constant current driving circuit, a metal backplane and at least 8 pins;

The metal substrate is exposed outside the linear constant current driving chip;

The pins are symmetrically distributed on both sides of the metal base plate;

The pin includes a first power end and a second power end;

The pin further includes at least one intermediate power terminal disposed on one side of the metal backplane, and an same number of additional intermediate power terminals disposed on the other side of the metal backplane;

The intermediate power terminal and the additional intermediate power terminal are in one-to-one correspondence in the same arrangement order, and the corresponding intermediate power terminal and the additional intermediate power terminal are connected to each other;

The first power end, the intermediate power end, the second power end, and the additional intermediate power end are sequentially arranged around the metal bottom plate.
A linear constant current driving chip according to claim 1, wherein:

The metal base plate, at least one pin on a side of the intermediate power end, and at least one pin on a side of the additional intermediate power end serve as first, second, and third ground ends, respectively.
A linear constant current driving chip according to claim 2, wherein:

The intermediate power end and the additional intermediate power end are located on the same side of the connection between the second ground end and the third ground end;

The first power end and the second power end are located on different sides of the second ground end and the third ground end connection.
A linear constant current driving chip according to claim 1, wherein said linear constant current driving circuit comprises an enabling unit, a control circuit and at least one MOS transistor:

The MOS transistor includes a first MOS transistor, a second MOS transistor, and at least one intermediate MOS transistor;

The control circuit includes a resistor and an operational amplifier;

The resistor includes a first resistor, a second resistor, a sampling resistor, and at least one intermediate resistor;

The operational amplifier includes a first operational amplifier, a second operational amplifier, and at least one intermediate operational amplifier;

The first resistor, the intermediate resistor and the second resistor are connected in series to each other to form a resistor series group, and the first resistor and the second resistor are located at two ends of the resistor series group;

One end of the first resistor not connected to the intermediate resistor is connected to a common ground;

An input terminal of the first operational amplifier is positively connected to an end of the first resistor that is not connected to the common ground;

An input terminal of the second operational amplifier is positively connected to an end of the second resistor that is not connected to the intermediate resistor;

The positive terminal of the input terminal of the intermediate operational amplifier is sequentially connected to one end of the intermediate resistor away from the common ground;

The input negative terminal of all the operational amplifiers and the sources of all of the MOS transistors are connected to the common ground via the sampling resistor;

An output end of the first operational amplifier is connected to a gate of the first MOS transistor;

An output end of the second operational amplifier is connected to a gate of the second MOS transistor;

The output end of the intermediate operational amplifier is sequentially connected to the gate of the middle | MOS transistor;

One output end of the enabling unit is connected to the positive terminal of the input end of the second operational amplifier, and the other output end is connected to the drain of the first MOS transistor;

The drain of the first MOS transistor is connected to the first power end;

The drain of the second MOS transistor is connected to the second power terminal;

The drain of the intermediate MOS transistor is connected to the intermediate power terminal in order;

The drains of the intermediate MOS transistors are connected to the additional intermediate power terminals in the same order;

The common ground is connected to any one of the first ground terminal, the second ground terminal, and the third ground terminal.
A multi-chip parallel LED lighting circuit, comprising: at least two linear constant current driving chips according to any one of claims 1 to 4;

The multi-chip parallel LED lighting circuit further includes a power supply unit and a light emitting diode;

The light emitting diode comprises a first light emitting diode, a second light emitting diode and at least one intermediate light emitting diode, the number of the intermediate light emitting diodes being equal to the number of the intermediate MOS tubes in each of the linear constant current driving chips;

The power supply unit is configured to convert the alternating current from the commercial power into direct current to provide energy for the light emitting of the light emitting diode;

The first light emitting diode, the intermediate diode, and the second light emitting diode are sequentially connected to each other to form a series of light emitting diodes, and the first light emitting diode and the second light emitting diode are located in series with the light emitting diode. a cathode of the first light emitting diode is connected to a positive pole of one of the intermediate light emitting diodes, and a cathode of the second light emitting diode is connected to a cathode of one of the intermediate light emitting diodes;

The anode of the first light emitting diode is connected to the anode of the output end of the power supply unit;

The first power end of the linear constant current driving chip is connected to the negative electrode of the first light emitting diode;

The second power end of the linear constant current driving chip is connected to the negative electrode of the second light emitting diode;

In order, the intermediate power terminals of each of the linear constant current driving chips are sequentially connected to corresponding additional intermediate power terminals on the next linear constant current driving chip;

The anode of the intermediate light emitting diode is sequentially connected to at least one corresponding intermediate power end or the additional intermediate power end of the linear constant current driving chip;

Each of the grounding terminals of each of the linear constant current driving chips is connected to each other by a printed power source, which is a circuit printed on the substrate, and drives the bottom of the chip through the linear constant current;

The printed power source is connected to the output terminal of the power supply circuit.
The multi-chip parallel LED lighting circuit according to claim 5, wherein the negative electrode of the intermediate light-emitting diode is sequentially connected to the corresponding intermediate power terminal or the first linear constant current driving in the last linear constant current driving chip. A corresponding additional intermediate power terminal in the chip.
A multi-chip parallel LED lighting circuit according to claim 5, wherein the power supply unit is a bridge rectifier circuit composed of four diodes, and the input terminal is connected to the mains.