JP3769115B2 - Integrated circuit for closed loop / dimming stability control - Google Patents

Description

【００６５】
が５回分周されるように相互に機能する。この時点で、「イネーブル」は「高値」になり、駆動回路論理に半ブリッジ駆動回路を駆動させさらにはＭＯＳＦＥＴ／ＩＧＢＴ２０および２１を駆動することが出来るようになる。信号「ＣＬＫ１」の次の縁（約２５０Ｈｚ後）で、「Ｓｅｔｄｅｔ」が「高値」になり、バースト論理に「Ｌａｍｐｉｎ」を読み込むように指示する。「Ｌａｍｐｉｎ」が「高値」の場合、ランプ存在が検出されシステムは動作を続ける。「スタート」信号は「高値」になり「Ｓｅｔｄｅｔ」と「イネーブル」信号を両方とも「高値」にラッチしてタイマー・ブロックの予熱インターバルが開始する（タイマー回路については図２０参照）。「Ｓｅｔｄｅｔ」信号が「高値」なる時に「Ｌａｍｐｉｎ」が逆に「低値」であれば、「リセット」信号が高値になってタイマーをリセットする。タイマーがリセットされると「イネーブル」が「低値」になり半ブリッジ駆動回路がオフになるので、ＭＯＳＦＥＴ／ＩＧＢＴ２０および２１をオフにする。「イネーブル」が「低値」になると、「Ｓｅｔｄｅｔ」のラッチも開放するので、これも低値になる。
【００６６】
「Ｓｅｔｄｅｔ」が低値になる場合、「リセット」も低値になり、１６Ｈｚのインターバルがもう一度達成され「Ｌａｍｐｉｎ」を読み込むまでタイマーはカウントをもう一度開始する。この、待機−イネーブル−測定−待機の「バースト」モード処理はランプが挿入されるまで続く。更に、ランプが検出された時には「Ｓｅｔｄｅｔ」が「高値」にラッチされるため、動作中のどの時点でもランプを取り外して「Ｌａｍｐｉｎ」信号が「低値」になると「イネーブル」が「低値」になってＭＯＳＦＥＴ／ＩＧＢＴ２０および２１はオフになり、「バースト」モードが始まる。
【００６７】
ランプ共振回路においてランプ・カソードが直列接続してあるため、カソードのどちらか（または両方）が動作中に断線した場合、ランプ存在検出回路は「Ｌａｍｐｉｎ」信号を「低値」として読み込み、新しいランプが挿入されるまでバーストモードに入る。更に、「整流作用」として知られているランプの寿命現象が発生し、一方のカソードが断線しているが他方のカソードが放射し続けている場合、抵抗「ＲＣＳ」を流れる電流は非対称で「Ｖｔｈ」以下になるので、ＭＯＳＦＥＴ／ＩＧＢＴ２０および２１がオフになりシステムはバーストモードに移行する。
【００６８】
３．多ランプ存在検出回路
多蛍光ランプを駆動するのに適した本発明の安定駆動ＩＣの第１の実施例は有利にも多ランプ存在検出回路を含む。
【００６９】
多ランプ存在検出回路はここのランプ各々の存在を検出してそれらの一つにおけるランプ電力を調整する。調整済みランプが動作中に取り外された場合、回路は次に利用できるランプを探して調整する。取り外されたランプが動作中に再挿入された場合、安定制御回路は半ブリッジ・トランジスタ・スイッチ２０および２１を停止させ、再開する前に予熱シーケンスをリセットする。全てのランプがランプ共振出力回路から取り外された場合（図６〜図９参照）、半ブリッジ駆動回路３０が停止し半ブリッジ・スイッチ２０および２１が両方ともオフになる。
【００７０】
図２２を参照すると（この図は図８の３並列ランプ構成に対応する）、検出抵抗（ＲＣＳ１、ＲＣＳ２、ＲＣＳ３）は各々のランプ・フィラメントとアースの間に配置されて各々のランプ共振回路の総電流を検出する。いずれかのランプ・フィラメントが取り外された場合にはそのパスにある検出抵抗にかかる電圧Ｖ_RCS1、Ｖ_RCS2、Ｖ_RCS3がゼロになる。各々の電流検出入力と低閾値電圧（Ｖ_th1 ）をコンパレータ７０，７１，７２で比較し、Ｄ型フリップフロップ７３，７４，７５をＨＩＮ（図２３の回路図と図２４および図２５のタイミング図を参照）でクロックすることによりゲート駆動信号ＨＯが高位側半ブリッジ・スイッチ２０をオフにする直前に測定することにより、各々のランプ共振回路の回路が完全であり、したがって全てのランプ・カソードが無傷であり回路に挿入されていることを表わす信号が生成される。
【００７１】
上位側半ブリッジ・スイッチ２０がオフになる時に各々の検出抵抗を通って電流が流れる方向がピークにあるので各々の電流検出入力はＨＩＮでクロックされる。これはスイッチング期間の間の他の時刻に存在するかも知れないその他の全ての望ましくない電流スパイクおよび／または雑音を抑圧する。
【００７２】
Ｄ型フリップフロップ７３，７４，７５からのＱ出力は互いに（ＮＯＲゲート７６で）ＮＯＲが取られて信号ＬＭＰＮを形成し、この信号はすべてのランプ共振回路が完全な回路を有していない（すべてのランプが取り外されているか、または、すべてのランプが破損したカソードを有する）場合にのみ「高値」になり、安定制御は半ブリッジ・スイッチ２０および２１をオフにラッチする。単一のランプが取り外されて再挿入された場合、ランプが再挿入された時点で適当なパルス・ジェネレータがリセット・パルスＬＩＤＯ（動作中ランプ挿入：Lamp Inserted During Operation）を与え安定制御は半ブリッジ・スイッチをオフにし、予熱シーケンスをリセットし、安定制御を再起動する。これは挿入されたランプの「ハード点灯」を防止するためと、ランプが再挿入された時に形成されたＱの高い直列ＬＣ回路の共振周波数より動作周波数が低い結果として半ブリッジ・トランジスタ・スイッチ２０および２１が損傷する可能性を防止するためである。
【００７３】
ランプ電力調整として、総負荷電流のゼロ交差（ＺＸ）が良好なランプを挿入したランプ共振回路の一つから要求される。調整しつつあるランプが取り外された場合、ランプの存在を表わす信号によって（即ちＤ型フリップフロップ７３，７４によって）制御される電圧制御スイッチ（Ｓ１およびＳ２）が「ランプ検索回路」を形成し、この回路は排除処理を用いて調整するために次に利用可能なランプを見つけ出す。全てのランプが存在している場合には、ＣＳ１に接続されたランプが調整される。ＣＳ１にランプが接続されていない場合には、ＣＳ２のゼロ交差が調整される。ＣＳ１とＣＳ２の両方にランプが接続されていない場合には、ＣＳ３のゼロ交差を調整する（以下の真理値表を参照）：
【００７４】
【表１】

【００７５】
スイッチＳ１とＳ２を図２６（Ａ）に図示したように３入力ＯＲゲートで置き換えることが可能である。この構造では、半ブリッジ電圧に関して最小限の位相シフトによる共振出力段ランプの位相測定（ゼロ交差検出）は信号ＺＸのパルス幅を判定する（図２６（Ｂ）参照）。これは、もっとも電力を多く消費するランプがマスターとなって調整される一方で、他のランプはスレーブとなってこれに従属することを表わしている。これによってマスター・ランプが取り外された場合に次に利用できるランプへジャンプする必要が排除され回路が簡略化される。
【００７６】
４．予熱電流制御回路
蛍光ランプ寿命を長くする鍵がランプを点灯する前に正しい放射温度までランプ・カソードを正しく予熱することであることが周知になっている。これは通常、回路がランプ・カソードを通って流れる所望の電流に対応する周波数で駆動されるような在来の共振回路（図２７）により実現されている。この電流は、
【００７７】
【外２】

【００７８】
にわたって流れる。この周波数は他の回路コンポーネントたとえば共振インダクタ（Ｌ）または共振キャパシタ（Ｃ）での許容範囲とは無関係に固定されているのが普通である。そのため大量の安定器を製造する場合、コンポーネント許容範囲を考慮するようにまた全ての販売される安定器で長いランプ寿命が得られることを補償するように予熱周波数設定に微調整を行なわなければならない。
【００７９】
微調整の時間のかかる手順を回避するには、予熱周波数を連続的に調整しつつ予熱電流を一定に維持する閉ループ方式を用いることができる。さらに、ループを閉じることで厳しい許容範囲仕様を要求する開ループ回路より大きな許容範囲で簡単な発振回路が出来る。
【００８０】
ループを閉じるには、カソード電流の測定値を「フィードバック」しこれを電流設定または「基準」に対して比較することが必要である。結果は一般に「誤差」と呼ばれ、これを用いて基準がフィードバックと等しくなり誤差がゼロになるまでシステムを調節する。システムは外部的な影響たとえばコンポーネントの許容範囲、電圧変動や温度などに依存しなくなる。
【００８１】
本発明の電子安定器用の閉ループ予熱電流制御回路（本発明の両方の実施例で使用されている）は前述した同一の古典的アプローチを使用しているが、本実施および制御回路は新規かつユニークである。予熱カソード電流はＲＣＳ両端の電圧降下（Ｖ_FB）としてＭＯＳＦＥＴ／ＩＧＢＴ２１のソースで検出される（図２８参照）。この信号は総ランプ共振回路電流（Ｉ_L ）で、共振回路を通って流れる電流（Ｉ_L ）の方向に対する検出抵抗ＲＣＳを通って流れる電流の方向のために９０度だけ位相がシフトしている（図２９）。
【００８２】
電圧Ｖ_FBをコンパレータ「ＣＯＭＰ１」を通る基準電圧「ＲＥＦ」と比較し、出力「ＥＲＲＯＲ」は「Ｖ_FB」と「ＲＥＦ」の間の関連誤差である。得られた関連誤差「パルス」である「ＥＲＲＯＲ」は、定電流源ＣＨＡＲＧＥとＩ_REF ＤＩＳＣＨＡＲＧＥによりキャパシタＣ２を充電または放電する（「Ｖ_FB」が大きいかまたは小さいかによって変化する）でＭＯＳＦＥＴ７８および７９から構成される増幅器を駆動する。キャパシタＣ２に得られた電圧「Ｖ_VCO 」は、一定のデューティ・サイクル(duty cycle)５０％の時に「Ｖ_FB」が「ＲＥＦ」より大きいかまたは小さいかによって、電圧制御発振回路をもっと高いまたはもっと低い周波数に調節する。
【００８３】
得られた信号を用いて所望の周波数で「半ブリッジ駆動回路」を駆動し、この回路がＭＯＳＦＥＴ／ＩＧＢＴ２０および２１を駆動する。得られた高電圧方形波電圧「ＶＳ」（図２９）はランプ共振出力回路への入力となり、この回路は電圧「ＶＳ」の周波数および振幅の関数である電流を出力する。
【００８４】
注意すべき重要なことは、総ランプ共振回路電流（Ｉ_L ）がランプ・カソードおよびキャパシタＣ（図２８）を流れる電流に等しいことである。これは、予熱中に、ランプがまだ点灯しておらず回路は低ダンプ直列ＲＣＬ構成で、ランプ・カソードがＬおよびＣと直列に接続されていることによる。
【００８５】
電流を調整するもっと古典的なアプローチはトランスで負荷における電流を検出し、出力を全波整流し、整流した電圧をローパスフィルタに通して電流の直流電圧表現を得ることであろう。限定されたバンド幅の誤差増幅器および任意の補償ネットワークを介して、この直流電圧を直流基準電圧に加算する。得られた誤差がＶＣＯを調整する。しかしこの方法はコンポーネント点数が多く、トランス電圧の整流（ならびに整流ダイオード両端の電圧降下対温度）が誤差をもたらすことのあるような非線形動作である。本発明の電流制御回路は測定および加算動作を大幅に簡略化し、コンポーネントが少なく、線形である。
【００８６】
要約すると、本発明の予熱電流制御回路は単純に基準誤差への電流を直接時間に変換する。この時間はどの程度長く定電流がキャパシタへまたはキャパシタから流れるかを制御する。キャパシタＣ２で得られた電圧はすでに積分された形を取っており、即ち：
【００８７】
【数１】

【００８８】
この全てが、サンプル・コンパレータと、２個のＭＯＳＦＥＴと、２個の電流供給源で実現され、本発明の集積回路へ容易に実装される。
【００８９】
５．アナログ調光インタフェース回路
調光可能な電子安定器、たとえば本発明の第２の実施例などでは、複数安定器で均一な輝度が達成されるように最小および最大輝度設定を許容可能な許容範囲内にまでトリム（trim）する必要がある。これは、ランプどうしの小さな輝度偏差が人間の目で簡単に検出できる低い輝度レベルで特に必要なことである。
【００９０】
本発明の調光インタフェース回路はアナログ入力制御電圧を微調整のためのプログラム可能なオフセットおよび利得調整でアナログ出力基準電圧へ変換する。ある種の蛍光ランプは用途によっては他の蛍光ランプより低い光量レベルに調光するため、本発明の調光インタフェースではあらゆる最小および最大輝度レベル（またはランプ電力）への汎用微調整を行なって全ての種類のランプに対応できる。
【００９１】
本発明の調光インタフェース回路は有利にも、ＭＩＮおよびＭＡＸ設定の独立制御を提供する。図３０を参照すると、入力電圧はＤＩＭノードにあってオペアンプ８０がＤＩＭ入力電圧へのマイナス（−）端子を調整する。Ｒ_MAX およびＱ１がＤＩＭ電圧を電流Ｉ_DIM ＝Ｖ_DIM ／Ｒ_MAX に変換する。Ｒ_MAX を調節することでＶ_DIM からＩ_DIM への変換の利得を調節することになる。
【００９２】
第２の電圧制御電流源はオペアンプ８１、Ｑ２、Ｒ_MIN およびＶ_REF1で与えられる。ここでＲ_MIN （Ｖ_REF1一定として）がＩ_MIN の利得を制御する。Ｉ_DIM およびＩ_MIN はノードΣで互いに加算されて、数式を得る：
【００９３】
【数２】

【００９４】
したがって利得およびオフセットの独立制御が得られる（図３１）。
【００９５】
得られた電流はＲ３を通って流れる前に
【００９６】
【外３】

【００９７】
集積回路に本発明の回路を実装する際に、Ｒ３が外部抵抗であれば回路は完成し温度の影響による許容範囲は受け入れられるものとなる。プログラム可能な抵抗Ｒ_MAX およびＲ_MIN を除いて電流が全てＩＣに対して内部的なものであるとすれば、Ｒ３の抵抗は温度で劇的に変化する必要がなく、また、たとえば、追加の単位利得バッファ（オペアンプ８３、Ｑ５、Ｒ４）および電流ミラー（Ｒ５、Ｒ６、Ｑ６、Ｑ７、およびＲ７、Ｒ８、Ｑ８、Ｑ９）は更なる変換を実現するように実装できる（図２）。
【００９８】
本発明の回路の新規性は各々が電圧と抵抗によって制御される２つの独立した電流を加算して、次の形の終端アナログ関数を形成することにある：
【００９９】
【数３】
ｙ＝ｍｓ＋ｂ
Ｒ３がＩＣの内部にあれば、ゼロ温度係数を有する必要があり終端基準は温度で変化しないことになる。
【０１００】
本発明はこれの特定の実施例に関連して説明したが、その他多くの変化および変更ならびにその他の用途が当該技術の熟練者には明らかになるであろう。したがって本発明は本明細書の特定の開示によって制限されるべきではなく、むしろ添付の請求項によって制限されるのが望ましい。
【図面の簡単な説明】
【図１】単一ランプ構成における本発明の第１の実施例の安定ＩＣ駆動回路の代表的接続図である。
【図２】単一ランプ構成における本発明の第２の実施例の安定ＩＣ駆動回路の代表的接続図である。
【図３】本発明の第１の実施例のブロック図である。
【図４】本発明の第１の実施例について通常の予熱、点灯、および動作状態の間に、ＶＣＯピンにかかる電圧、ＴＰＨピンにかかる電圧、および負荷電流の包絡線を示すタイミング図である。
【図５】本発明の第１の実施例について非点灯状態の間にＶＣＯピンにかかる電圧、ＴＰＨピンにかかる電圧、および負荷電流の包絡線を示すタイミング波形図である。
【図６】本発明の第１の実施例についての多ランプ・フックアップ構成図である。
【図７】本発明の第１の実施例についての多ランプ・フックアップ構成図である。
【図８】本発明の第１の実施例についての多ランプ・フックアップ構成図である。
【図９】本発明の第１の実施例についての多ランプ・フックアップ構成図である。
【図１０】本発明の第２の実施例のブロック図である。
【図１１】本発明の第２の実施例について通常の予熱、点灯、および調光状態の間に、ＶＣＯピンにかかる電圧、ＴＰＨピンにかかる電圧、および負荷電流の包絡線を示すタイミング図である。
【図１２】本発明の第２の実施例について非点灯状態の間にＶＣＯピンにかかる電圧、ＴＰＨピンにかかる電圧、および負荷電流の包絡線を示すタイミング波形図である。
【図１３】予熱、点灯、および動作運転状態の間の安定器出力段の伝達関数のボード線図である。
【図１４】図１４（Ａ）はランプが点灯しない間の負荷電流（Ｉ_L ）を示す図であり、図１４（Ｂ）は本発明の制御回路の予熱中のタイミング図である。
【図１５】本発明の閉ループ過電流制御回路を示す図である。
【図１６】本発明の過電流制御回路のタイミング図である。
【図１７】本発明のランプ存在検出回路のブロック図である。
【図１８】ランプ存在検出回路のタイミング波形図である。
【図１９】ランプ存在検出回路のバースト論理についての回路図と付随する真理値表である。
【図２０】ランプ存在検出回路のタイマー回路図を示す。
【図２１】ランプ存在検出回路のタイミング図である。
【図２２】３並列ランプ構成と安定駆動回路に関連して多ランプ存在検出回路を示す模式図である。
【図２３】多ランプ検出回路の詳細を示す図である。
【図２４】多ランプ存在検出回路のタイミング図である。
【図２５】多ランプ存在検出回路のタイミング図である（図２４の続き）。
【図２６】図２６（Ａ）および図２６（Ｂ）は２個のスイッチがＯＲゲートで置き換えられている多ランプ存在検出回路についての別の回路図とタイミング図を示す。
【図２７】従来のランプ共振回路を示す図である。
【図２８】本発明の閉ループ予熱電流制御回路を示す図である。
【図２９】本発明の閉ループ予熱電流制御回路のタイミング図を示す。
【図３０】本発明のアナログ調光インタフェース回路を示す図である。
【図３１】本発明の調光インタフェース回路の伝達関数を示す図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to gate drive circuits for MOS gate devices, and more particularly to monolithic gate drive circuits for MOS gate devices, and more particularly to circuits used in lamp stabilization circuits.
[0002]
[Description of related technology]
Electronic ballasts for gas discharge circuits are now widely used due to the availability of power MOSFET switching devices and insulated gate bipolar transistors (IGBTs) that replace the power bipolar switching devices previously used Came to be. Monolithic gate drive circuits, such as IR2155 sold by International Rectifier Corporation and disclosed in US Pat. No. 5,545,955, drive power MOSFETs or IGBTs in electronic ballasts. It has been devised. The IR2155 gate drive IC is packaged in a typical DIP or SOIC package and includes an internal level shift circuit, an undervoltage lockout circuit, a dead time delay circuit, and additional logic circuitry and inputs so that the drive circuit is an external resistor R_T And C_T Provides a significant advantage over conventional circuits in that it can self oscillate at a frequency determined by.
[0003]
IR2155 offers an extensive improvement over conventional stable control circuits, but is an open loop system. In addition, it does not have a programmable preheat or life function, nor does it have a lamp fault, overtemperature protection, or dimming control.
[0004]
SUMMARY OF THE INVENTION
The present invention relates to two MOS gate power semiconductors, such as a power MOSFET or IGBT, in which two switches, one called a “low-side switch” and the other called a “high-side switch”, are connected in a totem pole or half-bridge structure. A novel monolithic electronic stability control IC that can drive the IC is provided. Advantageously, the present invention provides programmable preheat time and current, programmable lifetime protection, lamp fault protection, and overtemperature protection.
[0005]
The first embodiment of the present invention is a closed-loop stability control IC intended for a multi-lamp configuration, comprising three current sensing inputs and programmable lamp power. The stability control IC of this embodiment of the present invention can drive one, two (parallel or series), three (parallel), or four (series-parallel) lamps. Although dimming is possible in this embodiment, it is not recommended to reduce the light level to an extremely low light level (−10%) because of the allowable range in manufacturing the lamp.
[0006]
The closed-loop control in the present invention is realized by phase control, or more specifically, by a phase-locked loop (PLL) near the resonant output stage that drives the fluorescent lamp. When adjusting a large number of lamps, the lamp that consumes more power becomes the master, which makes life detection and ballast shutdown easier.
[0007]
The second embodiment of the present invention has the same architecture as that of the first embodiment, and is modified to some extent so that it can be dimmed and lowered to a low light level. The second embodiment includes a dimming interface for analog control, lamp brightness 0-5VDC, minimum and maximum brightness settings. This makes it possible to change the dimming range of a specific type of lamp, for example, from 10% to 100% brightness, with 0 volts corresponding to 10% and 5V corresponding to 100%. The second embodiment of the present invention has only one current sense input, which can drive one or two (series) lamps.
[0008]
Both the first and second embodiments include a VCO, programmable preheat time, programmable preheat current, overcurrent protection, additional shutdown inputs, and full high and low half bridge drive circuits.
[0009]
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The following is a detailed functional description of the overall architecture of two embodiments of the ballast IC controller of the present invention.
[0011]
The first embodiment is a stable control IC suitable for a multi-lamp configuration. The second embodiment is a stable control IC particularly suitable for low light level control.
[0012]
Referring first to FIG. 1 and FIG. 2, representative connection schematic diagrams are shown for the closed-loop stabilization ICs of the first and second embodiments of the present invention, respectively. In each case, the ballast IC controls two power MOSFETs or IGBTs 20 and 21 connected in a “totem pole” or half-bridge circuit. The power MOSFETs / IGBTs 20 and 21 are driven by the stability control IC of the present invention, and are turned on alternately via gate signals from pins HO and Lo described later.
[0013]
The output circuit driven by the power supplied by MOSFET / IGBTs 20 and 21 includes at least one gas discharge tube, typically a fluorescent lamp 24, which is in parallel with capacitor 26 and in series with inductor 28. To form a normal lamp resonant circuit.
[0014]
A description of the overall architecture of each of the two embodiments of the present invention is provided below, followed by a detailed description of the individual circuit blocks in each embodiment.
[0015]
Overall architecture-first example
The stable drive IC of the first embodiment of the present invention identified by reference numeral 30 in FIG. 1 is built in a 16-pin DIP or SOIC package and has the following pin arrangement:
VCC-Logic and internal gate drive supply voltage. A 15.6V internal zener diode clamps the voltage between VCC and GND. The nominal rising and falling undervoltage lockout thresholds are TBD and TBD, respectively. When the IC enters an undervoltage lockout mode, the total quiescent current is typically less than 150 μA, reducing the power consumption requirements of the high voltage startup resistor. VCC should be bypassed to GND so that it is as close as possible to the IC terminal with a low ESR / ESL capacitor. As a rule of thumb for the value of this bypass capacitor, keep its minimum value at least 2500 times the value of the total input capacitance (Ciss) of the power transistor to be driven.
[0016]
IREF-Reference current setting. An external resistor sets the internal current reference for all programmable inputs of the IC.
[0017]
TPH-Preheat timing pin. The preheating time is determined by charging the external capacitor to an internal reference current of 4V threshold.
[0018]
IPH-Preheat current setting. The internal reference current through the external resistor sets the reference for closed loop peak preheating current adjustment.
[0019]
VCO-Voltage controlled oscillator input. An external capacitor sets the lamp duration and loop compensation for preheat current and lamp power regulation.
[0020]
PLAMP-Lamp power setting. The internal reference current through the external resistor sets the reference for closed-loop lamp power adjustment.
[0021]
EOL-Life setting. An internal reference current through an external resistor sets a maximum VCO frequency shutdown threshold that corresponds to the maximum allowable increment in lamp voltage during lifetime. As the lamp voltage increases with operating time, the regulation loop increases the frequency to maintain constant power in the lamp until the maximum setting is exceeded and the half-bridge circuit stops.
[0022]
COM IC-Power and signal ground. Both the low power control circuit and the low side gate drive circuit output stage ground return to this pin. The COM pin connects to the source of the lower power MOSFET using a single independent wire to avoid the possibility of a high current ground loop that interferes with the sense timing component current. In addition, the timing component and VCC decoupling capacitor ground return paths connect directly to the IC COM pins and do not go through independent wiring or jumpers to other ground wires on the board.
[0023]
VB-High side gate drive floating feed. This is the power supply pin for the high side level shift and gate drive logic. In a normal case, power is supplied to the high-order circuit using a simple charge pump from VCC. A high voltage fast recovery diode (so-called bootstrap diode) is connected between VCC (anode) and VB (cathode), and a capacitor (so-called bootstrap capacitor) is connected between the VB and VS pins. When the low side power MOSFET or IGBT is on, the bootstrap capacitor is charged from the VCC to COM decoupling capacitor using the bootstrap diode. When the high side power MOSFET or IGBT is turned on, the bootstrap diode is reverse biased and the VB node floats above the source potential of the high side power MOSFET or IGBT. VB should be biased to VS so that it is as close as possible to the IC pin with a low ESR / ESL capacitor. As an empirical value for the value of this capacitor, keep its minimum value at least 50 times the total input capacitance (Ciss) of the power transistor to be driven.
[0024]
HO-High side gate drive output. This pin is connected to the gate of the high side power MOSFET or IGBT. If the power transistor mirror current exceeds 0.5A (ie gate to drain current) due to the high dV / dt condition present at the output of the half bridge, the gate resistor is used to buffer the IC from the power stage. It is recommended.
[0025]
VS-High voltage floating supply recovery. The high side gate driver and logic return to this pin. The VS pin should be connected directly to the source of the high side power MOSFET or IGBT. In addition, the half-bridge output transistors should be placed as close as possible to each other to minimize the series inductance between them.
[0026]
LO-Low side gate drive output. This pin is connected to the gate of the low side power MOSFET or IGBT. If the power transistor mirror current exceeds 0.5A (ie, gate to drain current) due to the high dV / dt condition present at the output of the half bridge, the gate resistor is used to buffer the IC from the power stage. It is recommended.
[0027]
CS1-General-purpose current detection input. The voltage generated by the load current flowing through the external sense resistor and being positive during the on time of the HO or LO gate drive output is detected. Also included is a comparator having a low threshold for detecting the presence of the lamp and a high threshold for detecting the current limit. It also performs current detection for preheating current adjustment and lamp power adjustment.
[0028]
CS2-Second current detection input. The voltage generated by the load current flowing through the external detection resistor and being positive during the ON time of the HO gate drive output is detected. A window comparator with a low threshold for detecting the presence of the lamp and a high threshold for detecting the current limit is included.
[0029]
CS3-Third current detection input. The voltage generated by the load current flowing through the external detection resistor and being positive during the ON time of the HO gate drive output is detected. It includes a window comparator with a low threshold for detecting the presence of the lamp and a high threshold for the current limit.
[0030]
SD-Shutdown pin. This pin is used to stop the half-bridge drive circuit and turn off both gate drive outputs HO and LO (active low) and put the ballast IC controller into a power saving mode. The rising shutdown pin threshold voltage is 2.5V and includes about 0.1V of hysteresis to increase noise immunity. Since the shutdown function is not latched and the output of the SD comparator resets the CS latch, the IC resumes the preheat sequence when the SD pin voltage returns below the input threshold.
[0031]
Referring now to FIG. 3, a block diagram of the overall architecture of the ballast IC 30 is shown. In operation, a voltage controlled oscillator (VCO) 32 sets the operating frequency of the half bridge drive circuit. The voltage applied to the input of the VCO 32 is adjusted in an “adjust” block 34, which blocks a capacitor (not shown) at the input of the VCO 32 according to the error between the reference phase and the phase of one inductor current in the resonant lamp output stage. ) To supply or shunt current. The inductor current is one of the current sense inputs (CS1, CS2, or CS3) (as illustrated in the representative connection diagram of FIG. 2), between the lamp filament and ground and / or low. It is detected by a voltage generated by inserting a detection resistor (RCS) 36 between the side half-bridge MOSFET 21 and the ground. The phase is determined at the zero crossing of this voltage, which is fed back to the phase control block 38 where it is subtracted from the reference phase to generate an ERROR pulse for adjustment.
[0032]
During preheating (see FIG. 4 timing diagram showing normal preheating, lighting, and operating conditions), adjustment block 34 is used to adjust the cycle-by-cycle peak load current to programmable preheat current reference input IPH. To do. Preheat logic is included in block 40-preheat time is determined by a linear ramping voltage generated by an internal current charging an external capacitor at pin TPH. If the lamp is not lit, the ballast stops operating as illustrated in the timing diagram of FIG.
[0033]
The lamp power is generated by an internal current that flows through an external resistor at the pin PLAMP and is set by a voltage that sets the reference phase in the phase control block 38. An internal current through an external resistor at pin EOL generates a voltage that programs a maximum frequency shutdown when compared to the VCO voltage. If one or more of the lamps have reached their end of life as detected by protection logic 40, the phase control block 38 will increase the frequency to reach the maximum frequency FMAX and power off until the ballast is safely shut down. Try to keep it constant.
[0034]
The shutdown pin SD provides a logic input external shutdown option. When this pin is pulled above 2 volts, the ballast is held off in an “unlatched” state. If pulled below 2 volts, the preheat sequence is reset via preheat logic 42 and the ballast is started again. This allows the ballast to be automatically restarted after a fault condition has occurred due to the attachment / detachment of the lamp without recycling the input main voltage to the ballast.
[0035]
6-9 show various multi-lamp configurations in the stability control IC of the first embodiment of the present invention--FIG. 6 is a 2-parallel configuration, FIG. 7 is a 2-series configuration, FIG. 8 is a 3-parallel configuration, FIG. Is a series-parallel configuration. The detection resistors RCS1 to RCS3 in the multi-lamp configuration are arranged between the lamp cathode and the ground. Similarly, the RCS 36 in the single lamp configuration of FIG. 1 may be inserted at this other position.
[0036]
In a multiple lamp configuration, if one lamp is removed or the filament breaks, the other lamps will continue to operate. If the lamp is replaced and reinserted during operation, the ballast will shut down and the preheat sequence will be reset, and all lamps will be preheated and re-lighted.
[0037]
The stability control IC of the present invention also includes a power saving start-up, Zener clamp VCC, overtemperature shutdown, undervoltage lockout, as illustrated in circuit block 44. Undervoltage lockout (UVLO) provides noise hysteresis and off-line power supply for turn-on and turn-off thresholds.
[0038]
Overall architecture-second example
The overall architecture of the second embodiment of the stable IC control device of the present invention differs from the first embodiment in that it is specifically designed for business use in which light is dimmed and reduced to an ultra-low light level.
[0039]
The chip of the second embodiment shown in FIG. 2 and identified by reference numeral 50 has many pin arrangements identical to the first embodiment, and is related to the dimming function as follows: It is different in point.
[0040]
VCO-Voltage controlled oscillator input. The external capacitor sets the phase control for dimming as well as the lamp compensation and preheating current adjustment loop compensation.
[0041]
DIM-Dimming control input. 0-5VDC external control voltage corresponding to lamp power setting.
[0042]
MAX-Maximum lamp power. The internal reference current through the external resistor sets the maximum lamp power corresponding to the 5VDC dimming control input voltage.
[0043]
MIN-Minimum lamp power. An internal reference current through the external resistor sets the minimum lamp power corresponding to the 0VDC dimming control input voltage.
[0044]
CS-Current detection input. The voltage generated by the load current flowing through the external detection resistor and being positive during the ON time of the LO gate drive output is detected. Includes comparator with high threshold for current limit. Current detection is performed for preheating current adjustment and phase control (dimming).
[0045]
FB-Loop compensation. External compensation network for stable feedback loop during dimming. The resistance between pin FB and pin VCO has a value between 500Ω and 10KΩ.
[0046]
Referring now to the block diagram of the second embodiment of the present invention illustrated in FIG. 10, a dimming interface 52 is provided that allows 0-5 VDC analog control of lamp brightness with minimum and maximum adjustments. In order to simulate lamp lighting at any luminance setting, the lighting detection block 54 detects the phase change of the inductor current representing the lamp lighting (measured at the source of the lower half bridge MOSFET at pin CS). This tells the adjustment block 16 that the lamp has lit successfully, closing the loop and adjusting the phase of the inductor current relative to the reference phase generated by the dimming interface 52.
[0047]
Since the ionization time of the lamp is constant (-1 ms), the lamp cannot respond as fast as the loop, thus causing an overshoot of the VCO voltage, which can cause the lamp to turn off immediately after it is turned on. To prevent this, an internal switch S1 is provided to connect the DIM input to the TPH pin and ramp up between 4 and 5 volts during lighting.
[0048]
More detailed description will be given with reference to the typical connection diagram of FIG. 2 and the timing diagrams of FIGS. 11 and 12 (respectively showing the normal operation and the operation when the lamp fails to light), and is connected to the pin TPH. Capacitor 58 charges through an internal current supply during preheating. When the voltage applied to the capacitor 58 reaches the internal threshold value of 4V, the preheating is finished. If the reference of FIG. 11 is continued, the capacitor 58 continues to be charged exceeding 4V, the lamp is turned on, and the lighting detection block 54 detects lighting. At this point, the circuit of the chip closes switch S1 (FIG. 10) and the voltage on the DIM pin is discharged at an exponential rate determined by the value of capacitor 58 and resistor 56 to the voltage set by the user. Thus, the time constant formed by capacitor 58 and resistor 56 is programmable, allowing the designer to adjust the “transition” time from lighting to dimming setting for different lamp types. Capacitor 58 typically has a maximum value of 1 μF and resistor 56 has a typical value between 1 KΩ and 100 KΩ depending on the desired transition time.
[0049]
A detailed description of the salient circuit blocks illustrated in the block diagrams of FIGS. 3 and 10 is provided below.
[0050]
1. Overcurrent protection circuit
It is necessary to have some form of current limiting to prevent excessive and dangerous high voltages from appearing in the fluorescent lamp in the electronic ballast lamp resonant output stage. High voltage may be generated by trying to light a lamp that has stopped operating (the cathode is intact but there is no gas or the tube is broken). The currents associated with these voltages are detrimental to the person touching the fluorescent lamp when removing or inserting the lamp from the lamp socket of the fixture, and the absolute maximum voltage of the power component including the ballast lamp resonant output stage And current ratings may be exceeded.
[0051]
Both embodiments of the present invention have overcurrent protection defined by an internal threshold generated within the protection logic block 40. The protection compares the voltage generated at both ends of the low resistance external current detection resistor via the pin CS (pins CS1, CS2, CS3 in the first embodiment) with the internal threshold. The external current sense resistor RCS is placed between the lower half bridge switch and ground (eg, as shown in FIGS. 1 and 2) or (eg, as shown in FIGS. 6 and 8). As between) the lower lamp filament and ground.
[0052]
If the voltage across the sense resistor RCS exceeds the internal threshold, the peak output current will first be brought to the threshold by injecting a current pulse into the VCO capacitor whenever the threshold is exceeded via a signal to the phase control 38. Regulated or restricted. (Note that the direction in which the VCO is designed to operate is arbitrary--ie, the circuit can be designed so that the VCO capacitor is discharged rather than charged by a current pulse). This continues until the pin TPH voltage is charged to 5V and the lamp can be lit. The next time the threshold is exceeded, the ballast IC is latched off and the half-bridge switch is tri-stated, shutting down the ballast.
[0053]
A voltage cycling across the SD pin or VCC resets the IC and starts the preheat sequence again. During operation or dimming, it can occur when the lamp is removed using an overcurrent threshold, and the non-zero voltage at the half bridge is reduced as explained in more detail in the later section of the lamp presence detection circuit. Can be detected.
[0054]
The overcurrent protection circuit of the present invention is responsible for current detection, current adjustment with respect to a reference threshold, and tri-bridge switch tri-state, which is illustrated in FIG. 15 and corresponding timing diagrams. Is shown in FIG. 14 (B) in alignment with the appropriate load current of FIG. 14 (A). The Bode diagram of the transfer function of the resonant output stage (FIG. 13) shows the ballast operating point along with the current limit. As illustrated in FIG. 13, the current is limited to a threshold for a period of time before the half-bridge switch is tri-stated (both off). Maintaining the current for some time before the ballast shuts down gives the lamp time to turn on.
[0055]
Referring again to FIG. 15, the overcurrent protection circuit will now be described in detail. This circuit uses a voltage proportional to the total load current across RCS and a constant threshold V_IMAXCompare V_RCS Is V_IMAXExceeds the value, the output of COMP1 (FB) becomes a high value, and a pulse is sent to the switch S1. As a result, S1 is closed and the current supply source Il supplies the capacitor C._VCO Can be charged with current. Therefore C_VCO Is increased, which also increases the output frequency of the half-bridge signal that drives the lamp resonant stage (VS). This moves the operating point to the right along a high Q transfer function (FIG. 13), reducing the total load current below the maximum limit.
[0056]
When switch S1 is opened again, current source I2 is C_VCO To reduce the frequency and increase the load current (Il) again until the limit is exceeded. This “nudging” effect to limit the current is CPH (V_CPH ) Is the threshold voltage V_OCENThe output of COMP2 (3 state) goes high and the half-bridge drive circuit stops and half-bridge transistor switches 20 and 21 are in 3 states (both off).
[0057]
The same circuit is used to regulate the peak preheat current flowing through the lamp filament. The peak current reference threshold is initially set to V via switch S2._IPH (FIG. 15), the voltage applied to the capacitor CPH is the threshold voltage V_OCP The total peak load current is adjusted to this value until At this point, the preheating period is over (see FIGS. 14A and 14B) and the output of comparator COMP3 moves switch S2 to the “high” position (shown as “1” in S2). , Adjust threshold value to a higher value V_IMAXShift to. The current source I2 is linearly connected to the capacitor C_VCO Until the lamp is well lit or V_IMAXThe frequency is reduced in a ramp shape toward the resonance frequency of the resonance output stage having a high Q (FIG. 13) until either of the above is reached. FIG. 16 is a timing chart of the overcurrent control circuit of FIG.
[0058]
The first embodiment of the present invention includes not only a high threshold value but also a low threshold value of 200 mV, which is used to detect near or below resonance operation and lamp insertion during operation.
[0059]
2. Lamp presence detection circuit
Both embodiments of the present invention detect whether (1) a fluorescent lamp (or group of fluorescent lamps) has been inserted into the lamp resonant circuit prior to startup, and (2) whether the fluorescent lamp has been removed during ballast operation. Including a lamp presence detection circuit. This circuit prevents damage to the ballast, particularly the MOSFET / IGBTs 20 and 21, which can occur if the ballast continues to operate without a lamp. The damage is caused by a large current generated from charging or discharging the snubber capacitor 64 (see FIGS. 1 and 2). Without the lamp, there is no load current that reverses the current direction of the capacitor 64, and a non-zero voltage switching condition occurs in the MOSFET / IGBTs 20 and 21, which causes the final thermal breakdown of the MOSFETs / IGBTs 20 and 21. .
[0060]
The lamp presence detection circuit of the present invention is contained within the protection logic block 40 and is arranged in series with the source of the half-bridge low-side MOSFET / IGBT 21 and is the same detection resistor as previously described in connection with peak current detection. Use RCS. The current flowing through resistor RCS is zero when the half-bridge is operating without a lamp, except for the large current “spikes” that occur when the MOSFET / IGBT 21 is turned on. .
[0061]
If the lamp is inserted while the half-bridge is operating, the current flows through the resistor RCS that exists only when the MOSFET / IGBT 21 is on, and the total lamp circuit current (I_L1) Partly linear part and the total lamp circuit current (I_L1) By 90 degrees (see FIG. 18). The voltage obtained across the resistor RCS is compared with the DC threshold voltage “th” (COMP1) (FIG. 17). If the voltage applied to the RCS is greater than “Vth”, the output becomes a digital “high value” and the voltage applied to the RCS is If it is smaller than “Vth”, it becomes a digital “low value”.
[0062]
Since the rising edge of the slow current is measured, it is conceivable that the comparator output “chatters” when the voltage applied across the resistor RCS begins to exceed “Vth”. In order to prevent this “chattering” or any other undesirable signal, such as an input “spike” or high frequency high current noise that may be present at the measurement point (voltage across RCS), the output of the comparator COMP1 is turned off of the MOSFET / IGBT21. Synchronize with the rim. This is realized by a D-type flip-flop (DFF1, FIG. 17), and a clock circuit (CLK2) of the flip-flop generates an edge in which a positive edge is directed to a negative voltage from the gate to the source of the MOSFET / IGBT 21. A logic control signal (shown in FIG. 18 as signal “LO”) represents the turn-off of MOSFET / IGBT 21. In other words, the measurement is performed immediately before the MOSFET / IGBT 21 is turned off. The propagation delay from the CLK2 signal to the actual MOSFET / IGBT 21 turn-off provides the time required to clock DFF1 (or the output of COMP1) while not being affected by any possible turn-off interference.
[0063]
The output (LAMPIN) of DFF1 becomes a digital “high value” when the lamp is attached and becomes a digital “low value” when the lamp is removed, and becomes an input to the burst logic block (FIG. 17). The burst logic block is illustrated in more detail in FIG. The burst logic block outputs “start” and “reset” signals to the timer block, and the timer block further outputs a signal “Enable” to the driver circuit logic block. Burst logic and timer until an interval of about 16 Hz is achieved
[0064]
[Outside 1]

[0065]
Mutually function so as to be divided five times. At this point, “enable” becomes “high value”, and the drive circuit logic can drive the half-bridge drive circuit and drive the MOSFETs / IGBTs 20 and 21. At the next edge (after about 250 Hz) of the signal “CLK1”, “Setdet” becomes “high value” and instructs the burst logic to read “Lampin”. If “Lampin” is “high”, the presence of the lamp is detected and the system continues to operate. The “start” signal becomes “high”, and both the “Setdet” and “enable” signals are latched to “high” and the timer block preheat interval begins (see FIG. 20 for the timer circuit). If “Lampin” is “low value” when the “Setdet” signal becomes “high value”, the “reset” signal becomes high value and the timer is reset. When the timer is reset, “enable” becomes “low value” and the half-bridge driving circuit is turned off, so that the MOSFETs / IGBTs 20 and 21 are turned off. When “enable” becomes “low value”, the latch of “Setdet” is also released, so this also becomes low value.
[0066]
If “Setdet” goes low, “Reset” goes low, and the timer starts counting again until the 16 Hz interval is again reached and “Lampin” is read. This standby-enable-measure-standby "burst" mode process continues until the lamp is inserted. Furthermore, since “Setdet” is latched to “high value” when the lamp is detected, “enable” is set to “low value” when the lamp is removed at any time during operation and the “Lampin” signal becomes “low value”. MOSFET / IGBTs 20 and 21 are then turned off and the “burst” mode begins.
[0067]
Since the lamp and cathode are connected in series in the lamp resonance circuit, if either (or both) of the cathodes breaks during operation, the lamp presence detection circuit reads the “Lampin” signal as “low value” and a new lamp The burst mode is entered until is inserted. Furthermore, when a lamp life phenomenon known as “rectifying action” occurs and one of the cathodes is disconnected, but the other cathode continues to radiate, the current flowing through the resistor “RCS” is asymmetric and “ Therefore, MOSFET / IGBTs 20 and 21 are turned off and the system shifts to burst mode.
[0068]
3. Multi-lamp presence detection circuit
The first embodiment of the stable drive IC of the present invention suitable for driving a multi-fluorescent lamp advantageously includes a multi-lamp presence detection circuit.
[0069]
The multi-lamp presence detection circuit detects the presence of each of the lamps here and adjusts the lamp power in one of them. If the adjusted lamp is removed during operation, the circuit looks for and adjusts to the next available lamp. If the removed lamp is reinserted during operation, the stability control circuit stops half-bridge transistor switches 20 and 21 and resets the preheat sequence before restarting. When all lamps have been removed from the lamp resonant output circuit (see FIGS. 6-9), the half-bridge drive circuit 30 stops and both half-bridge switches 20 and 21 are turned off.
[0070]
Referring to FIG. 22 (this figure corresponds to the three parallel lamp configuration of FIG. 8), the sense resistors (RCS1, RCS2, RCS3) are placed between each lamp filament and ground to provide each lamp resonant circuit. Detect total current. If any lamp filament is removed, the voltage V across the sense resistor in that path_RCS1, V_RCS2, V_RCS3Becomes zero. Each current detection input and low threshold voltage (V_th1 ) Are compared by the comparators 70, 71, 72, and the D-type flip-flops 73, 74, 75 are clocked by HIN (see the circuit diagram of FIG. 23 and the timing diagrams of FIG. 24 and FIG. 25). Is measured immediately before turning off the high-side half-bridge switch 20, indicating that each lamp resonant circuit is complete, so that all lamp cathodes are intact and inserted into the circuit. A signal is generated.
[0071]
Each current sense input is clocked at HIN because the direction of current flow through each sense resistor is peaked when the upper half bridge switch 20 is turned off. This suppresses all other undesirable current spikes and / or noise that may exist at other times during the switching period.
[0072]
The Q outputs from D-type flip-flops 73, 74, 75 are NORed together (by NOR gate 76) to form signal LMPN, which isAllOnly when the lamp resonant circuit does not have a complete circuit (all lamps have been removed or all lamps have a broken cathode), stable control is a half-bridge switch Latches 20 and 21 off. If a single lamp is removed and reinserted, the appropriate pulse generator will provide a reset pulse LIDO (Lamp Inserted During Operation) when the lamp is reinserted and stability control is half-bridge -Turn off the switch, reset the preheating sequence, and restart the stable control. This is to prevent "hard lighting" of the inserted lamp and as a result of the operating frequency being lower than the resonant frequency of the high Q series LC circuit formed when the lamp is reinserted, the half-bridge transistor switch 20 This is to prevent the possibility of damaging and.
[0073]
As a lamp power adjustment, a zero crossing (ZX) of the total load current is required from one of the lamp resonance circuits in which a good lamp is inserted. When the lamp being adjusted is removed, the voltage control switches (S1 and S2) controlled by a signal indicating the presence of the lamp (ie by D flip-flops 73 and 74) form a “lamp search circuit”; This circuit finds the next available lamp to adjust using the exclusion process. If all lamps are present, the lamp connected to CS1 is adjusted. If no lamp is connected to CS1, the zero crossing of CS2 is adjusted. If no lamps are connected to both CS1 and CS2, adjust the zero crossing of CS3 (see truth table below):
[0074]
[Table 1]

[0075]
The switches S1 and S2 can be replaced with a three-input OR gate as shown in FIG. In this structure, the phase measurement (zero-crossing detection) of the resonant output stage lamp with a minimum phase shift with respect to the half-bridge voltage determines the pulse width of the signal ZX (see FIG. 26B). This means that the lamp that consumes the most power is adjusted as a master while the other lamps are slaves and are subordinate to it. This simplifies the circuit by eliminating the need to jump to the next available lamp if the master lamp is removed.
[0076]
4). Preheating current control circuit
It is well known that the key to extending the life of a fluorescent lamp is to correctly preheat the lamp and cathode to the correct radiation temperature before the lamp is lit. This is typically accomplished by a conventional resonant circuit (FIG. 27) in which the circuit is driven at a frequency corresponding to the desired current flowing through the lamp cathode. This current is
[0077]
[Outside 2]

[0078]
Flowing over. This frequency is usually fixed independently of the tolerances in other circuit components such as the resonant inductor (L) or the resonant capacitor (C). Therefore, when manufacturing a large number of ballasts, the preheating frequency setting must be fine-tuned to account for component tolerances and to compensate for the long lamp life obtained with all sold ballasts. .
[0079]
To avoid time-consuming procedures for fine adjustment, it is possible to use a closed loop system that keeps the preheating current constant while continuously adjusting the preheating frequency. Furthermore, by closing the loop, a simple oscillation circuit can be made with a larger tolerance than an open loop circuit requiring strict tolerance specifications.
[0080]
Closing the loop requires “feedback” the cathode current measurement and compare it against the current setting or “reference”. The result is commonly called “error” and is used to adjust the system until the reference is equal to the feedback and the error is zero. The system is independent of external influences such as component tolerances, voltage fluctuations and temperature.
[0081]
Although the closed loop preheat current control circuit for the electronic ballast of the present invention (used in both embodiments of the present invention) uses the same classic approach described above, the implementation and control circuit are new and unique. It is. The preheating cathode current is the voltage drop across the RCS (V_FB) At the source of the MOSFET / IGBT 21 (see FIG. 28). This signal is the total lamp resonant circuit current (I_L ), The current flowing through the resonant circuit (I_L The phase is shifted by 90 degrees due to the direction of the current flowing through the detection resistor RCS with respect to the direction of) (FIG. 29).
[0082]
Voltage V_FBIs compared with the reference voltage “REF” passing through the comparator “COMP1”, and the output “ERROR” is “V”._FB”And“ REF ”. The obtained related error “pulse”, “ERROR”, is obtained from the constant current sources CHARGE and I_REF The capacitor C2 is charged or discharged by DISCHARGE (“V_FB"Depends on whether" is large or small ") drives the amplifier consisting of MOSFET 78 and 79. The voltage “V” obtained on the capacitor C2_VCO "Is at" V "when the duty cycle is 50%._FB"Is greater or smaller than" REF ", the voltage controlled oscillator circuit is adjusted to a higher or lower frequency.
[0083]
The resulting signal is used to drive a “half-bridge drive circuit” at the desired frequency, which drives MOSFET / IGBTs 20 and 21. The resulting high voltage square wave voltage “VS” (FIG. 29) is input to the lamp resonant output circuit, which outputs a current that is a function of the frequency and amplitude of the voltage “VS”.
[0084]
It is important to note that the total lamp resonant circuit current (I_L ) Is equal to the current through the lamp cathode and capacitor C (FIG. 28). This is because during preheating, the lamp is not yet lit, the circuit is in a low dump series RCL configuration, and the lamp cathode is connected in series with L and C.
[0085]
A more classic approach to adjusting the current would be to detect the current in the load with a transformer, full-wave rectify the output, and pass the rectified voltage through a low-pass filter to obtain a DC voltage representation of the current. This DC voltage is added to the DC reference voltage via a limited bandwidth error amplifier and optional compensation network. The resulting error adjusts the VCO. However, this method is a non-linear operation where the number of components is large and the rectification of the transformer voltage (as well as the voltage drop across the rectifier diode vs. temperature) can introduce errors. The current control circuit of the present invention greatly simplifies the measurement and summing operations, has fewer components and is linear.
[0086]
In summary, the preheat current control circuit of the present invention simply converts the current to reference error directly into time. This time controls how long a constant current flows into or out of the capacitor. The voltage obtained at capacitor C2 is already in an integrated form, ie:
[0087]
[Expression 1]

[0088]
All of this is realized with a sample comparator, two MOSFETs, and two current sources, and is easily implemented in the integrated circuit of the present invention.
[0089]
5. Analog dimming interface circuit
In a dimmable electronic ballast, such as the second embodiment of the present invention, the minimum and maximum brightness settings are trimmed to an acceptable tolerance so that uniform brightness is achieved with multiple ballasts. )There is a need to. This is especially necessary at low brightness levels where small lamp-to-lamp brightness deviations can be easily detected by the human eye.
[0090]
The dimming interface circuit of the present invention converts the analog input control voltage to an analog output reference voltage with programmable offset and gain adjustment for fine adjustment. Some fluorescent lamps are dimmed to lower light levels than other fluorescent lamps in some applications, so the dimming interface of the present invention provides a general fine-tuning to all minimum and maximum brightness levels (or lamp power). It can correspond to the kind of lamp.
[0091]
The dimming interface circuit of the present invention advantageously provides independent control of MIN and MAX settings. Referring to FIG. 30, the input voltage is at the DIM node and the operational amplifier 80 adjusts the minus (−) terminal to the DIM input voltage. R_MAX And Q1 sets the DIM voltage to current I_DIM = V_DIM / R_MAX Convert to R_MAX By adjusting V_DIM To I_DIM Will adjust the gain of conversion to.
[0092]
The second voltage controlled current sources are operational amplifiers 81, Q2, R_MIN And V_REF1Given in. Where R_MIN (V_REF1As constant) I_MIN To control the gain. I_DIM And I_MIN Are added together at the node Σ to get the formula:
[0093]
[Expression 2]

[0094]
Therefore, independent control of gain and offset is obtained (FIG. 31).
[0095]
Before the resulting current flows through R3
[0096]
[Outside 3]

[0097]
When the circuit of the present invention is mounted on an integrated circuit, if R3 is an external resistor, the circuit is completed and an allowable range due to the influence of temperature is acceptable. Programmable resistance R_MAX And R_MIN If the currents are all internal to the IC except for, the resistance of R3 does not need to change dramatically with temperature and, for example, an additional unity gain buffer (opamp 83, Q5, R4) and current mirrors (R5, R6, Q6, Q7, and R7, R8, Q8, Q9) can be implemented to achieve further conversion (FIG. 2).
[0098]
The novelty of the circuit of the present invention is to add two independent currents, each controlled by voltage and resistance, to form a termination analog function of the form:
[0099]
[Equation 3]
y = ms + b
If R3 is inside the IC, it must have a zero temperature coefficient and the termination criterion will not change with temperature.
[0100]
Although the invention has been described with reference to specific embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Accordingly, the invention should not be limited by the specific disclosure herein, but rather by the appended claims.
[Brief description of the drawings]
FIG. 1 is a typical connection diagram of a ballast IC drive circuit of a first embodiment of the present invention in a single lamp configuration.
FIG. 2 is a typical connection diagram of a ballast IC drive circuit of a second embodiment of the present invention in a single lamp configuration.
FIG. 3 is a block diagram of a first embodiment of the present invention.
FIG. 4 is a timing diagram showing the voltage on the VCO pin, the voltage on the TPH pin, and the envelope of the load current during normal preheating, lighting, and operating conditions for the first embodiment of the present invention. .
FIG. 5 is a timing waveform diagram showing an envelope of a voltage applied to a VCO pin, a voltage applied to a TPH pin, and a load current during a non-lighting state in the first embodiment of the present invention.
FIG. 6 is a multi-lamp hookup configuration diagram for the first embodiment of the present invention.
FIG. 7 is a multi-lamp hookup configuration diagram for the first embodiment of the present invention.
FIG. 8 is a multi-lamp hookup configuration diagram for the first embodiment of the present invention.
FIG. 9 is a multi-lamp hookup configuration diagram for the first embodiment of the present invention.
FIG. 10 is a block diagram of a second exemplary embodiment of the present invention.
FIG. 11 is a timing diagram showing envelopes of the voltage on the VCO pin, the voltage on the TPH pin, and the load current during normal preheating, lighting, and dimming states for the second embodiment of the present invention. is there.
FIG. 12 is a timing waveform diagram showing envelopes of the voltage applied to the VCO pin, the voltage applied to the TPH pin, and the load current during the non-lighting state in the second embodiment of the present invention.
FIG. 13 is a Bode plot of the ballast output stage transfer function during preheating, lighting, and operating states of operation.
FIG. 14A shows a load current (I when the lamp is not lit)._L FIG. 14B is a timing chart during preheating of the control circuit of the present invention.
FIG. 15 is a diagram showing a closed loop overcurrent control circuit of the present invention.
FIG. 16 is a timing chart of the overcurrent control circuit of the present invention.
FIG. 17 is a block diagram of a lamp presence detection circuit according to the present invention.
FIG. 18 is a timing waveform diagram of a lamp presence detection circuit.
FIG. 19 is a circuit diagram of burst logic of the lamp presence detection circuit and an accompanying truth table.
FIG. 20 shows a timer circuit diagram of a lamp presence detection circuit.
FIG. 21 is a timing chart of the lamp presence detection circuit.
FIG. 22 is a schematic diagram showing a multi-lamp presence detection circuit in relation to a three-parallel lamp configuration and a stable drive circuit.
FIG. 23 is a diagram showing details of a multi-lamp detection circuit.
FIG. 24 is a timing chart of the multi-lamp presence detection circuit.
FIG. 25 is a timing chart of the multi-lamp presence detection circuit (continuation of FIG. 24).
FIGS. 26A and 26B show another circuit diagram and timing diagram for a multi-lamp presence detection circuit in which two switches are replaced with OR gates.
FIG. 27 is a diagram showing a conventional lamp resonance circuit.
FIG. 28 is a diagram showing a closed-loop preheating current control circuit of the present invention.
FIG. 29 shows a timing diagram of the closed loop preheat current control circuit of the present invention.
FIG. 30 is a diagram showing an analog dimming interface circuit of the present invention.
FIG. 31 is a diagram showing a transfer function of the dimming interface circuit of the present invention.

Claims (1)

An integrated circuit for driving first and second MOS gate power transistors connected to a half-bridge structure for supplying power to a fluorescent lamp to which a lamp resonant circuit is coupled, comprising: A half-bridge structure of the MOS gate power transistor of 2 supplies an oscillation input voltage to the ramp resonance circuit, the oscillation input voltage has a phase, the resonance circuit has a current flowing through the resonance circuit, and the resonance The current flowing through the circuit has a phase, and the integrated circuit is
Means for determining the phase of the current flowing through the lamp resonant circuit;
Means for adjusting the power of the lamp by maintaining a substantially constant phase difference between the phase of the oscillation input voltage and the phase of the current of the lamp resonant circuit;
The integrated circuit includes a programmable dimming control circuit;
The programmable dimming control circuit includes a dimming level input s that is a voltage value for setting a reference y that determines the phase difference between the phase of the oscillation input voltage and the phase of the current of the lamp resonant circuit. And the dimming level of the lamp is set by determining the phase difference,
The programmable dimming control circuit adds two independent currents, each controlled by voltage and resistance, to form a termination analog function of the form y = ms + b , and the programmable dimming control The circuit allows independent adjustment of the resistance R _MIN for setting the minimum fluorescent lamp power and the resistance R _MAX for setting the maximum fluorescent lamp power , m = C ₁ / R _MAX , b = C ₂ V _REF1 / R _MIN , C ₁ and C ₂ are constants, and V _REF1 is a reference voltage value .

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