CN1993006A - Dimming ballast control circuit - Google Patents

Abstract

A dimming ballast control circuit for driving a ballast power switching circuit powering a gas discharge lamp. The circuit includes a driver circuit for driving high and low side switches of the ballast power switching circuit; a control circuit for driving the driver circuit including an oscillator circuit for providing an oscillating signal to control the frequency of operation of the ballast power switching circuit, the ballast power switching circuit outputting lamp powering pulsed signals; and a dimming control circuit having an input, the dimming control circuit receiving an AC lamp current feedback signal at the input, the dimming control circuit further receiving a DC input voltage reference at the input whereby the DC input voltage reference determines a desired dimming level of the lamp and the AC lamp current feedback signal maintains the lamp brightness at the desired dimming level.

Description

Dimming ballast control circuit

The cross reference of related application

[0001] the application based on and required the rights and interests that the interim sequence number of the U.S. on October 24 in 2005 is 60/729586, name is called the application of " dimming ballast control integrated circuit ", required its priority and its full content be incorporated herein by reference at this.

Background technology

[0002] the present invention relates to dimming ballast control, relate more specifically to a kind of dimming ballast control integrated circuit, be used to control the gaseous discharge lamp of ballast driven, for example the ballast of fluorescent lamp or compact fluorescent lamp.

[0003] from utilizing integrated circuit to realize the quantity of the necessary pin of ballast circuit/connection, the frequent unnecessary complexity of ballast control integrated circuit.Usually, these circuit have the pin more than 8, and if comprise and then need independent pin by dimming function, the FEEDBACK CONTROL that is used to set dim level and keeps desirable dim level.

[0004] expectation is the minimum ballast control IC of number of pin and peripheral circuit.

Summary of the invention

[0005] an object of the present invention is to provide a kind of dimming ballast control circuit, the quantity of its pin and element reduces.This circuit comprises drive circuit, be used to drive the control circuit of drive circuit, offer the power switch circuit that lamp applies the pulse signal of electric power, and adjusting control circuit, wherein drive circuit is used to drive the high-pressure side of ballast power switching circuit and the switch of low-pressure side, control circuit comprises pierce circuit, is used to provide the running frequency of oscillator signal with the power controlling switching circuit; Adjusting control circuit has input, and adjusting control circuit is at the AC of input receiving light current feedback signal, adjusting control circuit also receives the DC input reference voltage at input, is used to set the dim level of lamp, and the AC current feedback signal of lamp remains on desirable dim level with lamp.By circuit of the present invention, single input both had been used to set dim level, also was used for the power of lamp is remained on desirable light modulation level.

[0006] therefore, provide a kind of integrated circuit, its element and number of pin reduce.The input that is used for light modulation is also by the feedback from the output stage of lamp, the strength level of the output of the lamp that is used to keep desirable.

[0007] other features of the present invention and advantage will become apparent from following description of the invention by with reference to accompanying drawing.

Description of drawings

[0008] Fig. 1 is the structure chart of dimming ballast control IC of the present invention;

[0009] Fig. 2 is the circuit diagram of the part of Fig. 1 circuit, and it provides common AC and the DC input that is used for dimming ballast control IC of the present invention, is used to set dim level and keeps dim level by the output stage feedback;

[0010] Fig. 3 is the state diagram of dimming ballast control IC of the present invention; And

[0011] Fig. 4 is the circuit diagram that dimming ballast control IC typical case of the present invention uses.

Embodiment

[0012] Fig. 1 shows 8 pin dimming ballast control integrated circuit (IC) 25.Fig. 4 shows to the IC25 in the ballast circuit of lamp 14 power supplies.This IC25 has realized simple, high performance dimming ballast scheme.In the illustrated embodiment, obtain ballast control circuit by the integrated circuit that has only 8 pins.The VCC pin one provides logic and internal gate driving power voltage V _CC, be used for powering to IC.This voltage also provides under voltage maintenance (UVLO) circuit 62 and bootstrapped switch 52.UVLO circuit 62 provides under voltage to keep protection, in order to work as V _CCWhen being lower than threshold level, prevent the out drive stage operation.Boostrap circuit 52 provides the voltage of high-pressure side driving stage, is used at voltage level V _BGreater than voltage V _CCThe time, be the high-pressure side driver power supply.The COM pin two provides IC power supply and the signal ground to UVLO circuit 62.Signal from UVLO circuit 62 provides to fault logic circuit 66.

[0013] DIM pin 3 provides brightness adjustment control and feedback to input to adjusting control circuit 40, and this adjusting control circuit 40 provides signal to input to voltage controlled oscillator 58.Light protective circuit 48 and also receive input, and provide and export adjusting control circuit 40 to from DIM pin 3.The AC feedback current 12 (Fig. 4) of DC DIM input reference voltage 20 (Fig. 4) and lamp couples together, and to allow single pin-DIM pin 3, is used for the light modulation and the FEEDBACK CONTROL of the brightness degree of lamp.

[0014] input of the voltage of VCO pin 4 electric capacity of self-charging in the future provides to voltage-controlled oscillator circuit 58, with the frequency of oscillator in the control light modulation operations necessary.VCO pin 4 also provides the frequency scanning time of preheating/ignition mode to fault logic circuit 66.Internal current source booster circuit 60 is connected to VCO pin 4, is used for to outside capacitor C PH charging (Fig. 4).

[0015] LO pin 5 provides the driving output from low-pressure side half-bridge driver circuit 46, provides this driving output to be used to drive the low-side switch of ballast circuit.During UVLO or fault mode, provide LO pin 5 to input to and restart logical circuit 54.This input is common shutdown function, also is used to detect the existence of lamp in this application.

[0016] VS pin 6 is connected to the switching mode Vs of output half-bridge ballast circuit, and receives the floating power supply (floating supply) of high-pressure side half-bridge driver voltage, and the input that is provided for half-bridge current and voltage sensing circuit 64.This circuit 64 provides and inputs to non-zero voltage switch (ZVS) protective circuit 56 and crest factor protective circuit 50.High pressure VS pin 6 sensing half-bridge current and the voltages that this is single are to carry out necessary ballast protection function.

[0017] HO pin 7 will provide the high side switch to ballast circuit from the driving output of high-pressure side half-bridge driver circuit 44.VB pin 8 provides the high-pressure side half-bridge driven floating power supply by bootstrapped switch 52 controls.

[0018] IC25 comprises the Zener clamp structure (not shown) between VCC pin one and the COM pin two.Zener clamp structure has nominal breakdown voltage, for example 15.6V.This power supply should be by the V greater than appointment in the table 3 _CLAMPLow ESR DC power drives.Enough electric currents are provided for the VCC pin one, to keep the Zener diode clamping voltage of inner 15.6V at this pin place.Simultaneously, should avoid exporting the switch situation, promptly wherein be lower than to VS pin 6 irritability earthed voltage rapidly and surpass 5V.

[0019] IC25 also comprises driver logic circuit 42, and its oscillation output signal that receives VCO58 is as input.It also has the input from fault logic circuit 66.Driver logic circuit 42 control high-pressure side half-bridge driver 44 and low-pressure side half-bridge drivers 46.Fault logic circuit 66 also receives from restarting logical circuit 54 except having the input from UVLO circuit 62, lights testing circuit 48, and the input of crest factor protective circuit 50, in order to ballast protection to be provided.

[0020] as mentioned above, IC25 comprises the closed loop current adjusting control circuit 40 of lamp; Drive the driver logic circuit 42 of high-pressure side half-bridge driver 44 and low-pressure side half-bridge driver 46; Light testing circuit 48; Crest factor protective circuit 50; Bootstrapped switch 52; Lamp is restarted logical circuit 54; Non-ZVS protective circuit 56 is in order to provide non-ZVS protection and V _CCOn the Zener clamping diode, 15.6V for example.IC25 also comprises warm-up time able to programme; Fixing idle time (1.5ustyp.); Little power consumption starts, for example 200 μ A and anti-latching and esd protection.

[0021] Fig. 2 shows the circuit 40 that IC25 is connected internally to DIM pin 3, and how the single input that is used to represent DIM pin 3 places is used for light modulation and how is used to keep from the feedback of lamp output stage the desirable output intensity grade of lamp.This circuit 40 is positioned at IC25 inside, comprises the comparator 200 that is used for receiving from DIM pin 3 input.The output of comparator 200 is connected to the switch 210 of pair of series connection and 212 grid, and wherein first switch 210 is PMOS, is connected to current source 208, and second switch 212 is NMOS, is connected to current absorption device 206.Usually use absorption (discharge) electric current of about 625 μ A and source (charging) electric current of 160 μ A.Here providing for the ratio of stablizing very important absorption current of light modulation and source electric current, approximately is 4: 1.

[0022] provide the explanation of relevant adjusting control circuit 40 operations now, wherein adjusting control circuit is via the feedback of lamp, sets and keeps desirable dim level.

[0023] the DIM pin 3 of IC25 receives two signals, i.e. DC level V _DIMWith AC signal Ilamp, wherein DC level V _DIMProvided from the light modulation input by non-essential resistance RD 1M1, be set at 1-10V usually to set dim level, AC signal Ilamp connects capacitor C FB by AC and separates from the voltage at current limliting sensing resistor RCS two ends.

[0024] voltage of pin 3 is represented dimmer voltage V _DIMThe combination of (DC level) and AC signal Ilamp, wherein the AC signal is represented the electric current of lamp, and the voltage of pin 3 is sine curves 204.Comparator 200 compares the trough 202 of the sine curve 204 at DIM pin 3 places with COM (zero).Be lower than COM if trough 202 drops to, the output of comparator 200 becomes " height " so, and with the NMOS FET212 conducting of bottom, wherein NMOS FET 212 is connected to VCO pin 4 with absorption current 206.This absorption current is discharged a little to the capacitor C VCO voltage at VCO pin 4 places, to increase frequency.The increase of this frequency makes sinusoidal amplitude (electric current of lamp) descend a little, to such an extent as to sinusoidal trough increases to the position greater than COM.

[0025] if sinusoidal trough 202 greater than zero, comparator output " low " so, and with PMOS FET 210 conductings on top, wherein PMOS FET 210 is connected to VCO pin 4 with current source 208.This current source increases the voltage of the capacitor C VCO at VCO pin place, with slight reduction frequency.This will increase the electric current of lamp, and therefore increase sinusoidal amplitude, make trough finally drop to the position of COM level thus.Therefore, circuit 40 is always attempted change frequency, so that sinusoidal trough 202 is forced to COM.But as long as trough 202 reaches COM, absorb pulse and just be passed to VCO, be used for increasing once more frequency, so that trough is increased to greater than COM.By such circulation each time, trough will be finally be adjusted to COM just, and VCO voltage will reach steady-state value and thus the dim level of lamp remained on by V _DIMThe value of determining, wherein VCO voltage is determined by absorption current and source electric current.

[0026] VCO voltage setpoint frequency, wherein this frequency provides the current amplitude of correct lamp.The ballast half-bridge (referring to Fig. 4 30) always operate in 50% duty ratio and fixing idle time, and only have frequency controlled, to be used for that the electric current of lamp is continued to be adjusted to correct level.Resonance output stage (LRESA connects with the R and the CRES of parallel connection) (Fig. 4) has transfer function, i.e. gain and frequency contrast, and it increases the electric current of lamp when frequency reduces, and when frequency increases, reduces the electric current of lamp.

[0027] Fig. 3 shows the state table 100 of IC25.When in step 102, at first applying power supply, the i.e. V of VCC pin one _CCGreater than 0 o'clock, IC25 entered the UVLO pattern in step 104.In the UVLO pattern, set up following setting: half-bridge 30 (Fig. 1) turn-offs, I _QCC≌ 200 μ A; VCO pin 4 equals 0V; HO pin 7 turn-offs, and LO pin 5 is open circuits.

[0028] become greater than 12.5V (UVLO+) when the VCC pin one, LO pin 5 is during less than 4.7V, and this indication lamp is access in, and then in step 106, IC25 enters preheating/ignition mode.When IC25 is in preheating/ignition mode, and lamp will not have the AC component at the DIM pin when not lighting, and DIM voltage will remain on the DC level.VCO will finally charge to greater than 4.6V like this, enter fault mode and shutdown then.Fault logic circuit 66 has the input that is connected to VCO.If lamp is lighted, then IC25 light the electric current that testing circuit 48 will detect lamp, this is because the trough 202 at DIM pin 3 places will be reduced to about 30 times of COM down.When this situation took place, IC entered the DIM pattern.

[0029] in preheating/ignition mode, the setting below setting up: the half-bridge frequency of oscillation is from f _MAXOblique line drops to f _MIN4 chargings (1uA) of VCO pin; Crest factor and non-ZVS are that fault is stopped using.And when DIM pin 3 remained on following 30 times of 0V, IC25 entered the DIM pattern in step 108, otherwise IC25 is back to the UVLO pattern.

[0030] in case detect and light, IC25 enters the DIM pattern, and the absorption of circuit 40/source adjusting control circuit (Fig. 2) is activated.If during the DIM pattern, lamp is removed, frequency can be adjusted to resonance saturated up to inductance for brightness adjustment control circulation or non-ZVS so.This inductance is saturated will to make the crest factor CF ratio of mean value (peak value with) of inductive current surpass 5, and in step 110, this will make IC25 enter fault mode so, and shutdown.

[0031] in the DIM pattern, the setting below setting up: the half-bridge frequency of oscillation is set at f _DIMThe light modulation loop start; Crest factor and non-ZVS protection start.

[0032] if the voltage of VCC pin one less than 10.5V (UVLO-), then IC25 is back to the UVLO pattern from any state, shown in 107 or 109.For non-ZVS, IC enters the ZVS pattern in step 112, and wherein the value of VCO pin 4 reduces, i.e. VCO=VCO-dV, and the half-bridge frequency of oscillation increases, i.e. and freq=freq.+df, and IC25 is back to the DIM pattern.Like this, switch is urged to zero voltage switch by the ZVS circulation.

[0033] or, if crest factor greater than 5 (do not light when lamp, for example are removed), perhaps VCO is less than 0.85V (non-ZVS), in step 110, IC25 enters fault mode so.In fault mode, failure locking is set, and half-bridge is closed; I _QCC≌ 200 μ A; 7 outputs of HO pin are closed; The LO pin two is an open circuit.

[0034] from fault mode, when the voltage of VCC pin one less than 10.5V (UVLO-) or LO pin 5 during greater than 5V, when promptly lamp was removed, IC25 was back to the UVLO pattern.

[0035] Fig. 4 shows the typical application graph of utilizing IC25 of the present invention in dimming ballast circuit 10.Ballast circuit 10 will be connected to the DC DIM signal of pin 3 from the AC feedback signal 12 of lamp 14.As mentioned above, this allows to utilize single IC pin to come light modulation and feedback.The IC current sensing resistor of lamp is RCS16.The AC current signal 12 of lamp is connected to light modulation input 20 by feedback resistance RFB and capacitor C FB 18.Provide DC DIM signal at DIM input 20, this signal comprises 1 to 10 volt of variable DC level.DIM input 20 is provided the bleeder circuit that forms to by resistance R DIM2 and RDIM1.Provide additional capacitor CDIM to be used for noise filtering, this electric capacity is less than connecting capacitor C FB18.Usually, capacitor C FB18 equals 470nF, and capacitor C DIM equals 1nF.

[0036] capacitor C FB18 is superimposed to the AC current feedback signal 12 of lamp the DC dimmer voltage at 22 places.The current peak of DIM level 20 control lamps, and feedback signal 12 remains on desirable value with the light modulation level.Correspondingly, has only a pin in the control IC 25, i.e. pin 3 dim level (DC) that is used to provide desirable and light modulation or gray scale are remained on desirable rank by AC feedback signal 12.

[0037] the dimming ballast circuit 10 of Fig. 4 utilizes single 8 pin chip light modulation schemes, and the electric current dimming controlling method of simple lamp is provided.10 single resistance of needs of ballast circuit are used for the current sense of lamp.And, do not need current sensing resistor to connect with half-bridge.Do not need outer protection circuit and external cathode loading-diode.And the parts number of circuit 10 reduces in a large number, and has increased manufacturability and stability.It also is easy to be used for the quick design cycle.

[0038] table 1 shows the absolute maximum rating of control IC 25.Its expression continues the limit, surpasses this limit, control IC 25 will occur and damage.All voltage parameters are to be the absolute voltage of reference with COM.All electric currents are defined as and enter lead for just.Thermal resistance and power loss rated value are being installed circuit board and are also being measured under atmospheric conditions.

Table 1

Parameter		Minimum value	Maximum	Unit
					Symbol	Definition
V B	High-pressure side floating power supply voltage						-0.3	625	V
		V S	High-pressure side floating power supply offset voltage	V B-25	V B+0.3	V
V HO	Output voltage floats in the high-pressure side						V S-0.3	V B+0.3	V
		V LO	The low-pressure side output voltage	-0.3	V CC+0.3	V
V VCO	The VCO input voltage						-0.3	6	V
		V DIM	The DIM input voltage	-0.3	V CC+0.3	V
I CC	Source current (note 1)						---	20	mA
		IOMAX	Since the transistorized the Miller effect of external power, the maximum permissible current at LO, HO and PFC place	-500	500
dV S/dt	The VS pin voltage rate of change (voltage stew rate) that allows					-50	50	V/ns
		P
D	8 pin DIP, maximum power loss during in TA≤+ 25 ℃		---	1.0	W
		P
D	8 pin SOIC, maximum power loss during in TA≤+ 25 ℃		---	0.625	W
		R θJA				8 pin DIP, environment links the thermal resistance of (Junction to Ambient)	---	85	℃/W
R
	θJA	8 pin SOIC, environment links the thermal resistance of (Junction to Ambient)	---	128	℃/W
T J						Junction temperature	-55	150	℃
	T S	Storing temperature	-55	150
T L					Conductor temperature (welding, 10 seconds)	---	300

[0039], use the recommendation condition of control IC 25 in table 2, to provide for proper operation.

Table 2

Parameter		Minimum value	Maximum	Unit
					Symbol	Definition
V BS	High-pressure side floating power supply voltage						V CC-0.7	V CLAMP	V
		V S	Floating power supply offset voltage in high-pressure side under the stable state	-3.0 (note 2s)	600	V
V CC	Supply voltage						V CCUV++0.1V	V CC CLAMP	V
		I CC	Source current	(note 3)	5	mA
T J	Junction temperature						-40	125	℃

The electrical characteristics of IC25 are provided in table 3 below [0040], wherein unless otherwise outside, VCC=VBS=14V, VS=0V and TA=25 ℃.Output voltage and electric current (V ₀And I ₀) parameter with COM as a reference, and be applied to each HO and LO output lead.

Table 3

Symbol	Definition	Minimum value	Representative value	Maximum	Unit	Test condition
							The LVPS characteristic
V CLAMP	V CCThe Zener clamping voltage	14.6	15.4	16.6	V	I CC＝10Ma
							V CCUV+	The V that rises CCUnder voltage keeps	11.5	12.5	13.5
V CCUV-	The V that descends CCUnder voltage keeps	9.5	10.5	11.5
							V CCUVHYS	V CCUnder voltage keeps lagging behind	1.5	2.0	3.0
I CCUV	Little power consumption starts V CCSource current	---	200	---	μA	V CC＝8V
							I CCDIM	Operational mode V CCSource current	---	2.5	---	mA	Pattern=DIM
I CCFLT	Fault mode V CCSource current	---	300	---	μA	Pattern=fault
							The floating power supply characteristic
I QBS	Static V BSSource current	---	60	80	μA
							V BSUV+	The V that rises BSPower supply under voltage threshold value	8.5	9.0	9.5	V
V BSUV-	The V that descends BSPower supply under voltage threshold value	7.6	8.0	9.0
						I LK	The offset power source leakage current	---	---	50	mA		V B＝V S＝600V
The ballast control characteristic
							f MIN	Minimum output frequency	33	35	37	kHz	VCO＝6V
f MAX	Maximum output frequency	---	100	---	VCO＝0V
						d	Duty ratio	---	50	---	％
DT	Export idle time (HO or LO)	---	2.0	---	usec							Pattern=ALL
						I VCO	VCO pin charging current	---	1	---	uA		Pattern=preheating/light
V RSRT	The LO pin inserts lamp restarts threshold value	---	5.0	---	V							Pattern=fault
						V RSRTIIYS	The LO pin is restarted threshold value and is lagged behind	---	300	---	mV		Pattern=fault
n EVENTSIGN	Light the detection event number	---	30	---	N/A							Pattern=preheating/light DIM=-0.5V
						V ZVSTH	The non-ZVS detection threshold of VS	---	5.0	---	V		Pattern=DIM LO=height
V VCOFLT+	VCO fault rising threshold value	---	4.6	---	V							Pattern=preheating/light

C SCF	Crest factor fault factor	---	5.0	-- -	N/A	Pattern=DIM VS skew=0.5V
							VS -ODDSET-MAX	Maximum crest factor ratio deviation voltage	---	3.0	---	V
The brightness adjustment control characteristic
							V DIMREG	DIM regulates threshold value	---	0.0	---	V	Pattern=DIM
I VCO+	VCO light modulation source electric current	---	160	---	μA	Pattern=DIM
							V VCO-	VCO light modulation absorption current	---	625	---	μA	Pattern=DIM
Gate driving output characteristic (HO and LO)
							V OH	High-level output voltage	---	V CC	---		I 0＝0A
V OL	Low-level output voltage	---	COM	---		I 0＝0A
							VOL_UV	UV pattern output voltage	---	COM	---		I 0＝0A， VCC≤VCCUV.
t R	The output rise time	---	120	220	nsec
							t F	Export fall time	---	50	80
t SD	The shutdown propagation delay	---	350	---
							I O+	The output source electric current	---	180	mA	mA
I O-	The output absorption current	---	260	---
						Cathode load FET characteristic
VB_ON	VB during cathode load FET conducting		13.7		V
						IB_CAP	VB source electric current during the cathode load conducting	5	55		mA	CBS＝0.1uF
IB_10V	VB source electric current during the cathode load conducting	8	12		VB＝10V

[0041] circuit 10 of Fig. 4 comprises AC main power source and DC bus capacitor CBUS, and wherein this AC main power source comprises bridge rectifier R and input filter EMF.In addition, also comprise VCO charging capacitor CVCO, be used for providing good stable, wherein this charging capacitor CVCO and RVCO that connects and capacitor C PH parallel connection at other dimming period of low luminance level.Resistance R VCO enough little (about 1 kilo-ohm), oblique line rises to such an extent as to the voltage of VCO pin 4 rises along with capacitor C PH oblique line.Frequency is lighted up to lamp along with the voltage oblique line of VCO pin 4 rises and descends.Like this, the CPH electric capacity programmed settings preheating of charging/light regularly via internal current source.The combination of CPH and RVCO also provides additional compensating network, is used for the light modulation feedback cycle that light modulation is stablized in the low luminance level other places.

[0042] circuit 10 also comprises VCC filter capacitor CVCC, bootstrapping charging capacitor CBS, dropping resistor RVCC, gate driving resistance R HO and RLO, buffer capacitor CSNUB, charge pump diode DCP1 and DCP2 also are provided, it has voltage sensing resistance R LMP1 and RLMP2, is used for the voltage (being used to restart circuit 54) of sense light.

[0043] if remove lamp during fault or UVLO pattern, the filament of bottom connects will become open circuit, and voltage sensing resistance R LMP2 is pulled to LO pin 5 by RLMP1 the internal threshold 5V of setting.This can remain on the UVLO pattern with IC25.Therefore when filament inserted again, the filament of bottom was pulled to the level that approaches COM with the node between voltage sensing resistance R LMP1 and the RLMP2, and LO pin 5 was pulled to and is lower than internal threshold 4.7V, and IC25 is restarted in preheating/ignition mode.

[0044] in addition, the output circuit of lamp comprises output resonance inductor LRESA, LRESB and LRESC, and resonant capacitor CRES, DC hinder (blocking) capacitor C DC and capacitor C H1 and CH2.During filament pre-heating, filament F1 and F2 are preheated the voltage heating during preassigned pattern.In case lamp is triggered and lights, then use as a lamp when bright, the resonant circuit that comprises LRESB and CH1 and LRESC and CH2 is by low lamp impedance bypass.

[0045] though the present invention has described its certain embodiments, many variations and distortion and other application will become apparent to those skilled in the art.Therefore, preferably, the present invention is not limited to concrete disclosure here.

Claims (23)

1, a kind of dimming ballast control circuit is used to drive the ballast power switching circuit to the gaseous discharge lamp power supply, comprising:

Drive circuit is used to drive the high-pressure side and the low-side switch of described ballast power switching circuit;

Control circuit is used to drive drive circuit, and this control circuit comprises the oscillator that is used to provide the running frequency of oscillator signal to control the ballast power switching circuit, and the ballast power switching circuit is exported to the pulse signal of lamp power supply; And

Adjusting control circuit, has input, described adjusting control circuit is at the AC of input receiving light current feedback signal, this adjusting control circuit also receives the DC input reference voltage at input, the DC input reference voltage is determined the desirable dim level of lamp thus, and the AC current feedback signal of lamp remains on desirable dim level with the brightness of lamp.

2, circuit according to claim 1, the AC current signal of wherein said lamp is superimposed upon on the described DC input reference voltage at input, so that the time varying signal with DC level to be provided, wherein said adjusting control circuit compares the feature and the reference level of described time varying signal, if the feature of time varying signal is different with reference level, adjust the control input of described oscillating circuit so, the frequency that changes described oscillating circuit makes it have the level identical with reference level to be used to drive the described feature of described time varying signal.

3, circuit according to claim 2, wherein said feature are the troughs of described time varying signal, and reference level is the earth level of circuit.

4, circuit according to claim 2, wherein said pierce circuit is a voltage controlled oscillator, and it has charging capacitor at input, and described adjusting control circuit is to described charging capacitor charging and discharge, to change the frequency of described oscillator signal.

5, circuit according to claim 4, wherein said adjusting control circuit comprises:

First and second switches that are connected in series;

Comparator receives input and the grid that exports first and second switches to is provided; And

Be connected to the current source of the end in each first and second switch and absorb circuit, the points of common connection between the described switch is connected to described charging capacitor.

6, circuit according to claim 5, wherein said first switch is PMOS, and second switch is NMOS, and first switch is connected to current source, and second switch is connected to the current absorption circuit.

7, circuit according to claim 6, wherein the ratio of absorption current and source electric current is 4: 1 approximately, and absorption current is used for the charging capacitor discharge, and the source electric current is used for the charging capacitor charging, and wherein said charging capacitor is connected to the voltage controlled oscillator control input end.

8, circuit according to claim 5, wherein said feature comprises the voltage level of the trough of input end time varying signal, if described trough is lower than reference level, comparator output is high so, if trough is greater than reference level, comparator output is low so.

9, circuit according to claim 8, wherein

High comparator output conducting second switch makes the charging capacitor discharge, and the frequency that this has increased drive circuit descends the amplitude of time varying signal and lamp current, and the trough voltage level of time varying signal is increased to position greater than reference level; And

Low comparator output conducting first switch, make the charging capacitor charging, this has reduced the frequency of drive circuit, the amplitude of time varying signal and lamp current is increased, and the trough voltage level of time varying signal is dropped to position less than reference level, and described ballast switching circuit moves with fixed duty cycle.

10, circuit according to claim 9, wherein said duty ratio is 50%, fix idle time.

11, circuit according to claim 1 also comprises the bootstrapped switch circuit, and it receives supply voltage from described circuit, and control provides the voltage floating voltage power supply (VB) to high pressure side driver circuit.

12, circuit according to claim 1, wherein said circuit is included in the integrated circuit.

13, circuit according to claim 12, wherein said integrated circuit have 8 pins at the most.

14, circuit according to claim 1 also comprises the feedback comparator, is used for being connected to described input with the proportional voltage of the electric current of flowing through lamps;

Wherein be superimposed to described DC input reference voltage with the proportional AC voltage of the electric current of described lamp, wherein said DC input reference voltage is set desirable dim level.

15, circuit according to claim 14 also comprises the electric resistance partial pressure level that is connected to described public input, so that described DC input reference voltage to be provided.

16, circuit according to claim 14, wherein said feedback capacity are used to receive and the proportional AC voltage of the electric current of lamp, and this AC voltage is positioned at the two ends of the sensing resistor of connecting with lamp.

17, circuit according to claim 16, drive circuit wherein, pierce circuit and adjusting control circuit are included in the integrated circuit bag, described input is the single pin of described integrated circuit bag, wherein said single pin is as the input that receives described DC input voltage, setting the dim level of desirable lamp, and described single pin receives described feedback signal, described lamp is remained on the desirable dim level of being determined by described DC input voltage.

18, circuit according to claim 1; also comprise electric current and voltage sensing circuit and crest factor protective circuit; wherein said electric current and voltage detecting circuit are used to detect the electric current and the voltage of the ballast power switching circuit at the switching mode place between high-pressure side and the low-side switch; and provide and export the zero voltage switch protective circuit to, be used to provide the non-zero voltage switch protection.

19, circuit according to claim 18 also comprises:

Restart logical circuit, be used for the signal that codan lamp exists, and if lamp do not exist, shutdown signal is provided;

The under voltage latch cicuit; And

From the fault logic circuit of restarting logical circuit, light testing circuit, crest factor testing circuit and under-voltage latch cicuit receiving input, this fault logic circuit provides and exports described drive circuit to,

Wherein said pierce circuit comprises the voltage controlled oscillator that is used to receive input control signal (VCO), be used to set the frequency of oscillator, described pierce circuit receives input from lighting testing circuit and adjusting control circuit, and provides oscillator signal to drive drive circuit.

20, circuit according to claim 19 also comprises the internal current source booster circuit, is used for external capacitive is charged.

21, circuit according to claim 20, wherein said fault logic circuit also receives the frequency scanning time that is used for preheating/ignition mode.

22, circuit according to claim 21 wherein provides input control signal, frequency scanning time and electric charge at single pin to external capacitive.

23, circuit according to claim 19, wherein said drive circuit is connected to the signal low-side switch, describedly restarts logical circuit is connected to drive circuit at identical single pin output.

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