WO2019200900A1 - 一种环路稳定的电源系统 - Google Patents

一种环路稳定的电源系统 Download PDF

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Publication number
WO2019200900A1
WO2019200900A1 PCT/CN2018/115061 CN2018115061W WO2019200900A1 WO 2019200900 A1 WO2019200900 A1 WO 2019200900A1 CN 2018115061 W CN2018115061 W CN 2018115061W WO 2019200900 A1 WO2019200900 A1 WO 2019200900A1
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Prior art keywords
signal
control
resistor
output
voltage
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PCT/CN2018/115061
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English (en)
French (fr)
Inventor
樊茂
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晶晨半导体(上海)股份有限公司
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Priority claimed from CN201810360664.7A external-priority patent/CN108429464B/zh
Priority claimed from CN201810361828.8A external-priority patent/CN108471236B/zh
Application filed by 晶晨半导体(上海)股份有限公司 filed Critical 晶晨半导体(上海)股份有限公司
Priority to US16/342,051 priority Critical patent/US11239758B2/en
Publication of WO2019200900A1 publication Critical patent/WO2019200900A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of power electronics, and in particular, to a loop-stabilized power system.
  • the step-down switching regulator has wide application in buck mode due to its simple circuit structure, convenient adjustment and high reliability. According to different control mechanisms, the step-down switching regulator The advantages of the working mode and the conversion efficiency of the converter are increasingly applied to the switching power supply.
  • the traditional switching regulator is affected by the large range of load variation, and the variation range of the secondary pole is large.
  • the loop stability is poor under the prior art control mode.
  • a loop-stabilized power system that includes:
  • a pulse width modulation driver comprising a control input, a first pulse output and a second pulse output
  • the pulse width modulation driver receives a control signal through the control input, and outputs a first pulse signal from the first pulse output terminal according to the control signal, and outputs a second pulse from the second pulse output terminal signal;
  • a gate of the PMOS transistor is connected to the first pulse output terminal
  • An NMOS transistor the gate of the NMOS transistor is connected to the second pulse output terminal;
  • the drain of the NMOS transistor is connected to the source of the PMOS transistor to form an output node for outputting an electrical signal
  • the first phase input of the first comparator receives a reference signal
  • the inverting input end of the first comparator is connected to the output node through a voltage dividing unit to receive an electrical signal at the output node and compare the stepped down signal according to a preset;
  • the first comparator compares the reference signal and the signal input by the inverting input terminal to generate a comparison result voltage signal, and outputs the comparison result voltage signal through a comparison output terminal;
  • the current limiting protection circuit comprises a current limiting input port, a current limiting collecting port and a current limiting control output port;
  • the current limiting input port is connected to the comparison output end, and the current limiting control output port is connected to the control input end of the pulse modulation driver;
  • the current limiting collection port is configured to collect an on current of the PMOS tube; and the current limiting protection circuit delivers the comparison result voltage when an on current of the PMOS tube is lower than a preset current value
  • the signal is used as the control signal of the pulse modulation driver to output a turn-off signal for turning off the pulse width modulation driver when the on current of the PMOS transistor is higher than a preset current value.
  • the control signal is used as the control signal of the pulse modulation driver to output a turn-off signal for turning off the pulse width modulation driver when the on current of the PMOS transistor is higher than a preset current value.
  • the loop-stabilized power system further includes:
  • the voltage control resistor comprising a first connection end, a second connection end, and a center tap control end;
  • the first connection end is connected to the comparison output end;
  • the second connection end is connected to a first capacitor;
  • the center tap control end is connected to the comparison output end;
  • the voltage control resistor adjusts a resistance value between the first connection end and the second connection end according to the comparison result voltage signal received by the center tap control end, and the resistance value is compared with the comparison As a result, the voltage value of the voltage signal is negatively correlated; or
  • the loop-stabilized power system further includes:
  • the anode of the first diode is connected to the comparison output
  • one end of the first resistor is connected to a cathode of the first diode
  • an anode of the second diode is connected to a cathode of the first diode
  • a first capacitor one end connected to the first resistor is not connected to the first diode.
  • the maximum voltage value of the comparison result voltage signal is k
  • the resolution of the voltage control resistor is k/64 to k/16.
  • the maximum value of the resistance value is 10 M ⁇ .
  • the resistance value of the second resistor is greater than the resistance value of the first resistor.
  • one end of the first capacitor not connected to the first resistor is grounded.
  • an inductance is connected to the output node
  • a second capacitor is connected to one end of the inductor away from the output node.
  • the drain of the PMOS transistor is connected to a power source
  • the source of the NMOS transistor is grounded.
  • the pulse width modulation driver further includes a clock input terminal for receiving an external clock signal.
  • the technical solution of the present invention has the beneficial effects of disclosing a loop-stabilized power supply system, which can ensure high loop stability and high reliability.
  • FIG. 1 is a schematic structural diagram of a loop-stabilized power supply system according to an embodiment of the present invention
  • FIG. 2 is a structural schematic diagram of another type of loop-stabilized power supply system according to an embodiment of the present invention.
  • FIG. 3 is a waveform diagram of an output voltage of a power supply system in the prior art
  • FIG. 4 is a waveform diagram of signals of respective nodes in a loop-stabilized power supply system according to an embodiment of the present invention
  • FIG. 5 is a waveform diagram of an output voltage in a loop-stabilized power supply system according to an embodiment of the present invention.
  • the invention discloses a loop stable power supply system, which comprises:
  • a pulse width modulation driver 10 comprising a control input terminal, a first pulse output terminal and a second pulse output terminal;
  • the pulse width modulation driver 10 receives a control signal Vcomp through the control input, and outputs a first pulse signal PWM1 from the first pulse output terminal according to the control signal Vcomp, and outputs a second pulse signal PWM2 from the second pulse output terminal;
  • the gate of the PMOS transistor PM1 is connected to the first pulse output terminal;
  • An NMOS transistor NM1 the gate of the NMOS transistor NM1 is connected to the second pulse output terminal;
  • the drain of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM1 to form an output node Lx for outputting an electrical signal;
  • the first phase input of the first comparator 20 receives a reference signal Vref;
  • the inverting input terminal of the first comparator 20 is connected to the output node Lx through a voltage dividing unit 30 to receive the electrical signal at the output node Lx to compare the stepped down signal, that is, the signal VFB;
  • the first comparator 20 compares the reference signal Vref with the signal input by the inverting input terminal (signal VFB) to generate a comparison result voltage signal Veao, and outputs the comparison result voltage signal Veao through a comparison output;
  • a voltage control circuit is connected between the comparison output Veao and the ground;
  • the current limiting protection circuit 40 includes a current limiting input port, a current limiting collecting port, and a current limiting control output port;
  • the current limiting input port is connected to the comparison output end, and the current limiting control output port is connected to the control input end of the pulse modulation driver 10;
  • the current limiting collection port is configured to collect the conduction current of the PMOS tube PM1; and the current limiting protection circuit 40 delivers the comparison result voltage signal Veao as the pulse modulation driver 10 when the conduction current of the PMOS tube is lower than a preset current value.
  • the control signal Vcomp outputs a turn-off signal for turning off the pulse width modulation driver 10 as the control signal Vcomp when the on current of the PMOS transistor PM1 is higher than a predetermined current value.
  • the voltage control circuit includes a voltage control resistor P including a first connection end, a second connection end, and a center tap control end;
  • the first connection end is connected to the comparison output end;
  • the second connection end is connected to a first capacitor;
  • the center tap control end is connected to the comparison output end;
  • the voltage control resistor P adjusts the resistance value between the first connection end and the second connection end according to the comparison result voltage signal Veao received by the center tap control terminal, and the resistance value is negatively correlated with the voltage value of the comparison result voltage signal Veao;
  • the voltage control circuit includes:
  • one end of the first resistor R1 is connected to the cathode of the first diode D1;
  • the anode of the second diode D2 is connected to the cathode of the first diode D1;
  • the two ends of the second resistor R2 are respectively connected to the cathode of the second diode D2 and the comparison output;
  • a first capacitor C1 is connected at one end to the first resistor R1 and is not connected to the first diode D1.
  • the current limiting protection circuit 40 may specifically include a second comparator 41 and a third comparator 42; the positive phase input terminal of the second comparator 41 serves as The current limiting input port of the current limiting protection circuit 40, the inverting input end of the second comparator 41 is connected to the output end of the third comparator 42, and the output end of the second comparator 41 is used as the current limiting protection circuit 40.
  • the current control input terminal of the third comparator 42 receives the power supply Vdd, and the inverting input terminal of the third comparator 42 is connected to the output node Lx, wherein the positive phase input terminal of the third comparator 42 and the inverting phase
  • the input terminals together constitute a current limiting collection port of the current limiting protection circuit 40;
  • the third comparator 42 delivers the result of the comparison, that is, the signal VCS to the inverting input terminal of the second comparator 41;
  • the output of the current limiting control output port is The control signal;
  • the output node Lx can also be connected with an inductor L and a second capacitor C2, and the final output voltage is Vout;
  • a first pre-driver KN1 can be connected between the first pulse output terminal and the PMOS transistor PM1.
  • the maximum voltage value of the comparison result voltage signal Veao is k
  • the resolution of the voltage control resistor P may be k/64 to k/16, for example, k/64, or k/48, or k/32, or k/24, etc.;
  • the maximum value of the resistance value of the voltage control resistor P may be 10 M ⁇ (mega ohms).
  • the maximum voltage value k can be set according to actual conditions, and is not limited herein.
  • the current limiting protection circuit 40 may specifically include a second comparator 41 and a third comparator 42; a positive phase input terminal of the second comparator 41 As the current limiting input port of the current limiting protection circuit 40, the inverting input end of the second comparator 41 is connected to the output end of the third comparator 42, and the output end of the second comparator 41 is used as the current limiting protection circuit 40.
  • the current limiting control terminal of the third comparator 42 receives the power supply Vdd, and the inverting input terminal of the third comparator 42 is connected to the output node Lx, wherein the positive phase input terminal of the third comparator 42 and the opposite phase
  • the phase input terminals together constitute a current limiting collection port of the current limiting protection circuit 40;
  • the third comparator 42 delivers the result of the comparison, that is, the signal VCS to the inverting input terminal of the second comparator 41; the output of the current limiting control output port
  • an inductor L and a capacitor may be connected to the output node Lx; a first pre-driver KN1 and a second pulse output terminal and the PMOS transistor PM2 may be connected between the first pulse output terminal and the PMOS transistor PM1.
  • a second pre-driver KN2 can be connected; Referring to FIG. 4, after using the technical solution of the present invention, the comparison voltage signal Veao and the current at the inductance L are obviously stable; comparing FIG. 3 and FIG. 5, after using the technical solution of the present invention, the output voltage Vout fluctuates more. small.
  • the resistance value of the second resistor R2 may be greater than the resistance value of the first resistor R1; one end of the first capacitor C1 not connected to the first resistor R1 may be grounded.
  • such a design is such that the charging process of the first capacitor C1 is fast and the discharging speed is slow.
  • an output L is connected to the output node Lx;
  • a second capacitor C2 is connected to one end of the inductor L away from the output node Lx.
  • the drain of the PMOS transistor PM1 is connected to a power supply Vdd;
  • the source of the NMOS transistor NM1 can be grounded.
  • the pulse width modulation driver 10 further includes a clock input for receiving an external clock signal clk.
  • the present invention discloses a loop-stabilized power supply system including: a pulse width modulation driver including a control input terminal, a first pulse output terminal, and a second pulse output terminal; the pulse width modulation driver passes through the control input terminal Receiving a control signal, and outputting a first pulse signal from the first pulse output end according to the control signal, and outputting a second pulse signal from the second pulse output end; a PMOS transistor, the gate of the PMOS tube is connected to the first pulse output end; An NMOS transistor, the gate of the NMOS transistor is connected to the second pulse output terminal; the drain of the NMOS transistor is connected to the source of the PMOS transistor to form an output node for outputting an electrical signal; a first comparator, the positive of the first comparator The phase input terminal receives a reference signal; the inverting input end of the first comparator is connected to the output node through a voltage dividing unit to receive the electrical signal at the output node to compare the stepped down signal according to a preset; the first comparator

Abstract

一种环路稳定的电源系统，包括：一脉宽调制驱动器（10）；一PMOS管（PM1）；一NMOS管（NM1）；一第一比较器（20）；一电压控制电路连接于比较输出端与接地端之间；限流采集口用于采集PMOS管（PM1）的导通电流；限流保护电路（40）于采集到PMOS管（PM1）的导通电流低于预设电流值时，输送比较结果电压信号（Veao）作为脉宽调制驱动器（10）的控制信号（Vcomp），于采集到PMOS管（PM1）的导通电流高于预设电流值时，输出用于关断脉宽调制驱动器（10）的关断信号作为控制信号（Vcomp）。有益效果在于：能够保证较高的环路稳定性，可靠性高。

Description

一种环路稳定的电源系统 技术领域
本发明涉及电力电子技术领域，尤其涉及一种环路稳定的电源系统。
背景技术
随着微电子技术的迅猛发展，降压型开关稳压器由于电路结构简单、调整方便、可靠性高等优点，在降压式场合有着广泛应用；根据控制机制不同，降压型开关稳压器工作方式的优点，提高转换器的转换效率，被越来越多地应用到开关电源中。
但是，传统的开关稳压器在应用过程中，受负载变化范围大的影响，次极点的变化范围很大，现有技术控制方式下环路稳定性较差。
发明内容
针对目前存在不足的问题，现提供一种环路稳定的电源系统。
具体技术方案如下：
一种环路稳定的电源系统，其中包括：
一脉宽调制驱动器，包括控制输入端、第一脉冲输出端和第二脉冲输出端；
所述脉宽调制驱动器通过所述控制输入端接收一控制信号，并根据所述 控制信号从所述第一脉冲输出端输出第一脉冲信号，以及从所述第二脉冲输出端输出第二脉冲信号；
一PMOS管，所述PMOS管的栅极连接所述第一脉冲输出端；
一NMOS管，所述NMOS管的栅极连接所述第二脉冲输出端；
所述NMOS管的漏极连接所述PMOS管的源极形成用于输出电信号的一输出节点；
一第一比较器，所述第一比较器的正相输入端接收一参考信号；
所述第一比较器的反相输入端通过一分压单元与所述输出节点连接，以接收所述输出节点处的电信号按预设比较降压后的信号；
所述第一比较器将所述参考信号和反相输入端输入的信号进行比较生成一比较结果电压信号，并通过一比较输出端将所述比较结果电压信号输出；
一电压控制电路，连接于所述比较输出端与接地端之间；
限流保护电路，包括一限流输入口、一限流采集口和一限流控制输出口；
所述限流输入口连接所述比较输出端，且所述限流控制输出口与所述脉冲调制驱动器的所述控制输入端连接；
所述限流采集口用于采集所述PMOS管的导通电流；所述限流保护电路于采集到所述PMOS管的导通电流低于一预设电流值时，输送所述比较结果电压信号作为所述脉冲调制驱动器的所述控制信号，于采集到所述PMOS管的导通电流高于一预设电流值时，输出用于关断所述脉宽调制驱动器的一关断信号作为所述控制信号。
优选的，所述环路稳定的电源系统还包括：
一电压控制电阻器，所述电压控制电阻器包括第一连接端、第二连接端 和中心抽头控制端；
所述第一连接端连接所述比较输出端；所述第二连接端连接一第一电容；所述中心抽头控制端连接所述比较输出端；
所述电压控制电阻器根据所述中心抽头控制端接收的所述比较结果电压信号调节所述第一连接端和所述第二连接端之间的电阻值，且所述电阻值与所述比较结果电压信号的电压值呈负相关；或
所述环路稳定的电源系统还包括：
一第一二极管，所述第一二极管的正极连接所述比较输出端；
一第一电阻，所述第一电阻的一端连接所述第一二极管的负极；
一第二二极管，所述第二二极管的正极连接所述第一二极管的负极；
一第二电阻，所述第二电阻的两端分别连接所述第二二极管的负极和所述比较输出端；
一第一电容，一端连接所述第一电阻未连接所述第一二极管。
优选的，所述比较结果电压信号的最大电压值为k；
所述电压控制电阻器的分辨率为k/64～k/16。
优选的，所述电阻值的最大值为10MΩ。
优选的，所述第二电阻的电阻值大于所述第一电阻的电阻值。
优选的，所述第一电容未连接所述第一电阻的一端接地。
优选的，所述输出节点处连接有一电感；
所述电感远离所述输出节点的一端连接有一第二电容。
优选的，所述PMOS管的漏极连接一电源；
所述NMOS管的源极接地。
优选的，所述脉宽调制驱动器还包括一时钟输入端，所述时钟输入端用于接收外部的时钟信号。
本发明的技术方案有益效果在于：公开一种环路稳定的电源系统，能够保证较高的环路稳定性，可靠性高。
附图说明
图1为本发明的实施例中环路稳定的电源系统的结构原理图；
图2为本发明的实施例中环路稳定的电源系统的另一种的结构原理图；
图3为现有技术中电源系统的输出电压的波形图；
图4为本发明一上实施例中环路稳定的电源系统中各节点的信号的波形图；
图5为本发明一上实施例中环路稳定的电源系统中输出电压的波形图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。
下面结合附图和具体实施例对本发明作进一步说明，但不作为本发明的限定。
本发明公开一种环路稳定的电源系统，其中包括：
一脉宽调制驱动器10，包括控制输入端、第一脉冲输出端和第二脉冲输出端；
脉宽调制驱动器10通过控制输入端接收一控制信号Vcomp，并根据控制信号Vcomp从第一脉冲输出端输出第一脉冲信号PWM1，以及从第二脉冲输出端输出第二脉冲信号PWM2；
一PMOS管PM1，PMOS管PM1的栅极连接第一脉冲输出端；
一NMOS管NM1，NMOS管NM1的栅极连接第二脉冲输出端；
NMOS管NM1的漏极连接PMOS管PM1的源极形成用于输出电信号的一输出节点Lx；
一第一比较器20，第一比较器20的正相输入端接收一参考信号Vref；
第一比较器20的反相输入端通过一分压单元30与输出节点Lx连接，以接收输出节点Lx处的电信号按预设比较降压后的信号，即信号VFB；
第一比较器20将参考信号Vref和反相输入端输入的信号(信号VFB)进行比较生成一比较结果电压信号Veao，并通过一比较输出端将比较结果电压信号Veao输出；
一电压控制电路，连接于比较输出端Veao与接地端之间；
限流保护电路40，包括一限流输入口、一限流采集口和一限流控制输出口；
限流输入口连接比较输出端，且限流控制输出口与脉冲调制驱动器10的控制输入端连接；
限流采集口用于采集PMOS管PM1的导通电流；限流保护电路40于采 集到PMOS管的导通电流低于一预设电流值时，输送比较结果电压信号Veao作为脉冲调制驱动器10的控制信号Vcomp，于采集到PMOS管PM1的导通电流高于一预设电流值时，输出用于关断脉宽调制驱动器10的一关断信号作为控制信号Vcomp。
在一种较优的实施例中，电压控制电路包括电压控制电阻器P，包括第一连接端、第二连接端和中心抽头控制端；
第一连接端连接比较输出端；第二连接端连接一第一电容；中心抽头控制端连接比较输出端；
电压控制电阻器P根据中心抽头控制端接收的比较结果电压信号Veao调节第一连接端和第二连接端之间的电阻值，且电阻值与比较结果电压信号Veao的电压值呈负相关；或
电压控制电路包括：
一第一二极管D1，第一二极管D1的正极连接比较输出端；
一第一电阻R1，第一电阻R1的一端连接第一二极管D1的负极；
一第二二极管D2，第二二极管D2的正极连接第一二极管D1的负极；
一第二电阻R2，第二电阻R2的两端分别连接第二二极管D2的负极和比较输出端；
一第一电容C1，一端连接第一电阻R1未连接第一二极管D1。
在一种较优的实施例中，如图1所示，限流保护电路40具体可以包括一第二比较器41和一第三比较器42；该第二比较器41的正相输入端作为限流保护电路40的限流输入口，该第二比较器41的反相输入端与第三比较器42的输出端连接，该第二比较器41的输出端作为限流保护电路40的限流控 制输出端，该第三比较器42的正相输入端接收电源Vdd，该第三比较器42的反相输入端连接输出节点Lx，其中第三比较器42的正相输入端和反相输入端共同组成限流保护电路40的限流采集口；该第三比较器42将比较的结果，即信号VCS输送至第二比较器41的反相输入端；限流控制输出口输出的为控制信号；输出节点Lx处还可以连接有一电感L和一第二电容C2，此时最终的输出电压为Vout；第一脉冲输出端与PMOS管PM1之间可以连接有一第一前级驱动器KN1，以及第二脉冲输出端与PMOS管PM2之间可以连接有一第二前级驱动器KN2；利用与比较结果电压信号的电压值呈负相关的电压控制电阻器P的电阻值，能够使得向第一电容C1充电的过程保持快速，而从第一电容C1放电的速度保持平缓，从而提高环路的稳定性；参见图4可知，采用本发明中的技术方案后，比较结果电压信号Veao以及电感L处的电流明显稳定；比较图3和图5可知，采用本发明中的技术方案后，输出电压Vout波动更小。
上述实施例中，比较结果电压信号Veao的最大电压值为k；
电压控制电阻器P的分辨率可以为k/64～k/16，例如为k/64，或，k/48，或k/32，或k/24等；
电压控制电阻器P的电阻值的最大值可以为10MΩ(兆欧姆)。
具体地，最大电压值k可以根据实际情况进行设定，在此不做限制。
在另一种较优的实施例中，如图2所示，限流保护电路40具体可以包括一第二比较器41和一第三比较器42；该第二比较器41的正相输入端作为限流保护电路40的限流输入口，该第二比较器41的反相输入端与第三比较器42的输出端连接，该第二比较器41的输出端作为限流保护电路40的限流控 制输出端，该第三比较器42的正相输入端接收电源Vdd，该第三比较器42的反相输入端连接输出节点Lx，其中第三比较器42的正相输入端和反相输入端共同组成限流保护电路40的限流采集口；该第三比较器42将比较的结果，即信号VCS输送至第二比较器41的反相输入端；限流控制输出口输出的为控制信号；输出节点Lx处还可以连接有一电感L和一电容；第一脉冲输出端与PMOS管PM1之间可以连接有一第一前级驱动器KN1，以及第二脉冲输出端与PMOS管PM2之间可以连接有一第二前级驱动器KN2；参考图4可知，采用本发明中的技术方案后，比较结果电压信号Veao以及电感L处的电流明显稳定；比较图3和图5可知，采用本发明中的技术方案后，输出电压Vout波动更小。
在一种较优的实施例中，第二电阻R2的电阻值可以大于第一电阻R1的电阻值；第一电容C1未连接第一电阻R1的一端可以接地。
具体地，这样的设计以使得第一电容C1的充电过程快速，而放电速度缓慢。
在一种较优的实施例中，输出节点Lx处连接有一电感L；
电感L远离输出节点Lx的一端连接有一第二电容C2。
在一种较优的实施例中，PMOS管PM1的漏极连接一电源Vdd；
NMOS管NM1的源极可以接地。
在一种较优的实施例中，脉宽调制驱动器10还包括一时钟输入端，时钟输入端用于接收外部的时钟信号clk。
综上所述，本发明公开一种环路稳定的电源系统，包括：一脉宽调制驱动器，包括控制输入端、第一脉冲输出端和第二脉冲输出端；脉宽调制驱动 器通过控制输入端接收一控制信号，并根据控制信号从第一脉冲输出端输出第一脉冲信号，以及从第二脉冲输出端输出第二脉冲信号；一PMOS管，PMOS管的栅极连接第一脉冲输出端；一NMOS管，NMOS管的栅极连接第二脉冲输出端；NMOS管的漏极连接PMOS管的源极形成用于输出电信号的一输出节点；一第一比较器，第一比较器的正相输入端接收一参考信号；第一比较器的反相输入端通过一分压单元与输出节点连接，以接收输出节点处的电信号按预设比较降压后的信号；第一比较器将参考信号和反相输入端输入的信号进行比较生成一比较结果信号，并通过一比较输出端将比较结果信号输出；限流保护电路，包括一限流输入口、一限流采集口和一限流控制输出口；限流输入口连接比较输出端，且限流控制输出口与脉冲调制驱动器的控制输入端连接；限流采集口用于采集PMOS管的导通电流；限流保护电路于采集到PMOS管的导通电流低于一预设电流值时，输送比较结果信号作为脉冲调制驱动器的控制信号，于采集到PMOS管的导通电流高于一预设电流值时，输出用于关断脉宽调制驱动器的一关断信号作为控制信号；能够保证较高的环路稳定性，可靠性高。
以上所述仅为本发明较佳的实施例，并非因此限制本发明的实施方式及保护范围，对于本领域技术人员而言，应当能够意识到凡运用本发明说明书及图示内容所作出的等同替换和显而易见的变化所得到的方案，均应当包含在本发明的保护范围内。

Claims (9)

  1. 一种环路稳定的电源系统，其特征在于，包括：
    一脉宽调制驱动器，包括控制输入端、第一脉冲输出端和第二脉冲输出端；
    所述脉宽调制驱动器通过所述控制输入端接收一控制信号，并根据所述控制信号从所述第一脉冲输出端输出第一脉冲信号，以及从所述第二脉冲输出端输出第二脉冲信号；
    一PMOS管，所述PMOS管的栅极连接所述第一脉冲输出端；
    一NMOS管，所述NMOS管的栅极连接所述第二脉冲输出端；
    所述NMOS管的漏极连接所述PMOS管的源极形成用于输出电信号的一输出节点；
    一第一比较器，所述第一比较器的正相输入端接收一参考信号；
    所述第一比较器的反相输入端通过一分压单元与所述输出节点连接，以接收所述输出节点处的电信号按预设比较降压后的信号；
    所述第一比较器将所述参考信号和反相输入端输入的信号进行比较生成一比较结果电压信号，并通过一比较输出端将所述比较结果电压信号输出；
    一电压控制电路，连接于所述比较输出端与接地端之间；
    限流保护电路，包括一限流输入口、一限流采集口和一限流控制输出口；
    所述限流输入口连接所述比较输出端，且所述限流控制输出口与所述脉冲调制驱动器的所述控制输入端连接；
    所述限流采集口用于采集所述PMOS管的导通电流；所述限流保护电路于采集到所述PMOS管的导通电流低于一预设电流值时，输送所述比较结果 电压信号作为所述脉冲调制驱动器的所述控制信号，于采集到所述PMOS管的导通电流高于一预设电流值时，输出用于关断所述脉宽调制驱动器的一关断信号作为所述控制信号。
  2. 根据权利要求1所述的环路稳定的电源系统，其特征在于，所述电压控制电路包括：
    一电压控制电阻器，所述电压控制电阻器包括第一连接端、第二连接端和中心抽头控制端；
    所述第一连接端连接所述比较输出端；所述第二连接端连接一第一电容；所述中心抽头控制端连接所述比较输出端；
    所述电压控制电阻器根据所述中心抽头控制端接收的所述比较结果电压信号调节所述第一连接端和所述第二连接端之间的电阻值，且所述电阻值与所述比较结果电压信号的电压值呈负相关；或
    所述电压控制电路包括：
    一第一二极管，所述第一二极管的正极连接所述比较输出端；
    一第一电阻，所述第一电阻的一端连接所述第一二极管的负极；
    一第二二极管，所述第二二极管的正极连接所述第一二极管的负极；
    一第二电阻，所述第二电阻的两端分别连接所述第二二极管的负极和所述比较输出端；
    一第一电容，一端连接所述第一电阻未连接所述第一二极管。
  3. 根据权利要求2所述的环路稳定的电源系统，其特征在于，所述比较结果电压信号的最大电压值为k；
    所述电压控制电阻器的分辨率为k/64～k/16。
  4. 根据权利要求2所述的环路稳定的电源系统，其特征在于，所述电阻值的最大值为10MΩ。
  5. 根据权利要求2所述的环路稳定的电源系统，其特征在于，所述第二电阻的电阻值大于所述第一电阻的电阻值。
  6. 根据权利要求2所述的环路稳定的电源系统，其特征在于，所述第一电容未连接所述第一电阻的一端接地。
  7. 根据权利要求1所述的环路稳定的电源系统，其特征在于，所述输出节点处连接有一电感；
    所述电感远离所述输出节点的一端连接有一第二电容。
  8. 根据权利要求1所述的环路稳定的电源系统，其特征在于，所述PMOS管的漏极连接一电源；
    所述NMOS管的源极接地。
  9. 根据权利要求1所述的环路稳定的电源系统，其特征在于，所述脉宽调制驱动器还包括一时钟输入端，所述时钟输入端用于接收外部的时钟信号。
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CN108566077A (zh) * 2017-12-19 2018-09-21 晶晨半导体(上海)股份有限公司 一种具有自学习功能的电源系统
CN108429464A (zh) * 2018-04-20 2018-08-21 晶晨半导体(上海)股份有限公司 一种环路稳定的电源系统
CN108471236A (zh) * 2018-04-20 2018-08-31 晶晨半导体(上海)股份有限公司 一种环路稳定的电源系统

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