WO2019200667A1 - 一种像素补偿电路及像素补偿方法 - Google Patents

一种像素补偿电路及像素补偿方法 Download PDF

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Publication number
WO2019200667A1
WO2019200667A1 PCT/CN2018/089413 CN2018089413W WO2019200667A1 WO 2019200667 A1 WO2019200667 A1 WO 2019200667A1 CN 2018089413 W CN2018089413 W CN 2018089413W WO 2019200667 A1 WO2019200667 A1 WO 2019200667A1
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Prior art keywords
thin film
film transistor
signal
turned
storage capacitor
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English (en)
French (fr)
Inventor
王一伊
王少波
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/234,187 priority Critical patent/US10665159B2/en
Publication of WO2019200667A1 publication Critical patent/WO2019200667A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel compensation circuit and a pixel compensation method.
  • pixels are arranged in a matrix including a plurality of rows and columns, and each pixel is usually composed of two films.
  • the transistor is composed of a capacitor, commonly known as a 2T1C circuit.
  • This 2T1C design is sensitive to the following factors: threshold voltage (Vth) and channel mobility (Mobility) of TFT (thin film transistor), startup voltage and quantum of OLED (organic light emitting diode) Efficiency and transients in the power supply. These factors can cause uneven brightness in different OLEDs. Therefore, it is generally necessary to use a compensation circuit to reduce the influence of these factors, such as a 7T1C circuit composed of seven thin film transistors and one capacitor, a 6T2C circuit composed of 6 thin film transistors and 2 capacitors, and the like.
  • the present invention provides a pixel compensation circuit and a pixel compensation method, which can reduce the influence of factors such as the threshold voltage of a thin film transistor on a light emitting device, and make the brightness of the light emitting device more uniform when illuminated.
  • a pixel compensation circuit provided by the present invention includes:
  • a source of the first thin film transistor is connected to a constant DC voltage signal
  • a second thin film transistor having a first end connected to a gate of the first thin film transistor, a second end connected to a drain of the first thin film transistor, and a second thin film transistor Three-terminal access to the nth-level scan signal;
  • a third thin film transistor a first end of the third thin film transistor is connected to a drain of the first thin film transistor, and a second end of the third thin film transistor is connected to a common ground through the light emitting device, The third end of the third thin film transistor is connected to an enable signal;
  • a storage capacitor a first end of the storage capacitor being connected to a gate of the first thin film transistor and a second end of the fourth thin film transistor;
  • a fifth thin film transistor a first end of the fifth thin film transistor is connected to a second end of the storage capacitor, a second end of the fifth thin film transistor is connected to a data signal, and a third end of the fifth thin film transistor is The terminal accesses the nth-level scan signal;
  • a sixth thin film transistor a first end of the sixth thin film transistor is connected to a second end of the storage capacitor, a second end of the sixth thin film transistor is connected to a common ground end, and the sixth thin film transistor is Three-terminal access to the enable signal;
  • the second thin film transistor and the fifth thin film transistor are controlled to be turned on or off by the nth stage scan signal, and the fourth thin film transistor is controlled to be turned on or off by the n-1th stage scan signal. And controlling, by the enable signal, the third thin film transistor and the sixth thin film transistor to be turned on or off.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all P-type thin film transistors .
  • the light emitting device is an OLED device.
  • a current passing through the light emitting device is according to a hole mobility of the first thin film transistor, a capacitance of a gate insulating layer per unit area in the first thin film transistor, The channel width and channel length of the first thin film transistor and the voltage value of the data signal are calculated.
  • the present invention also provides a pixel compensation method, which is applied to a pixel compensation circuit, and the pixel compensation circuit includes:
  • a source of the first thin film transistor is connected to a constant DC voltage signal
  • a second thin film transistor having a first end connected to a gate of the first thin film transistor, a second end connected to a drain of the first thin film transistor, and a second thin film transistor Three-terminal access to the nth-level scan signal;
  • a third thin film transistor a first end of the third thin film transistor is connected to a drain of the first thin film transistor, and a second end of the third thin film transistor is connected to a common ground through the light emitting device, The third end of the third thin film transistor is connected to an enable signal;
  • a storage capacitor a first end of the storage capacitor being connected to a gate of the first thin film transistor and a second end of the fourth thin film transistor;
  • a fifth thin film transistor a first end of the fifth thin film transistor is connected to a second end of the storage capacitor, a second end of the fifth thin film transistor is connected to a data signal, and a third end of the fifth thin film transistor is The terminal accesses the nth-level scan signal;
  • a sixth thin film transistor a first end of the sixth thin film transistor is connected to a second end of the storage capacitor, a second end of the sixth thin film transistor is connected to a common ground end, and the sixth thin film transistor is Three-terminal access to the enable signal;
  • the pixel compensation method includes the following steps:
  • Vdd is connected to the source of the first thin film transistor a voltage value of the constant DC voltage signal
  • Vth1 is a threshold voltage of the first thin film transistor
  • Vdata is a voltage value of a data signal accessed by the fifth thin film transistor
  • the sixth thin film transistor is turned on, the potential of the gate of the first thin film transistor is pulled to a third potential value, the first thin film transistor is controlled to be turned on, and the third thin film transistor is further turned on to drive the light emitting device to emit light.
  • the third potential value is Vdd-
  • the fourth thin film transistor is turned on by the n-1th scan signal
  • the second thin film transistor and the fifth thin film transistor are turned on by the nth scan signal
  • the third thin film is turned on by an enable signal.
  • a transistor and the sixth thin film transistor are turned on by the n-1th scan signal
  • the second thin film transistor and the fifth thin film transistor are turned on by the nth scan signal
  • the third thin film is turned on by an enable signal.
  • the n-1th stage scan signal is a low potential signal
  • the nth stage scan signal is a low potential signal
  • the enable signal is a low potential signal.
  • a current passing through the light emitting device is according to a hole mobility of the first thin film transistor, a capacitance of a gate insulating layer per unit area in the first thin film transistor, the first film
  • the channel width and channel length of the transistor and the voltage value of the data signal are calculated.
  • the present invention also provides a pixel compensation method, which is applied to a pixel compensation circuit, and the pixel compensation circuit includes:
  • a source of the first thin film transistor is connected to a constant DC voltage signal
  • a second thin film transistor having a first end connected to a gate of the first thin film transistor, a second end connected to a drain of the first thin film transistor, and a second thin film transistor Three-terminal access to the nth-level scan signal;
  • a third thin film transistor a first end of the third thin film transistor is connected to a drain of the first thin film transistor, and a second end of the third thin film transistor is connected to a common ground through the light emitting device, The third end of the third thin film transistor is connected to an enable signal;
  • a storage capacitor a first end of the storage capacitor being connected to a gate of the first thin film transistor and a second end of the fourth thin film transistor;
  • a fifth thin film transistor a first end of the fifth thin film transistor is connected to a second end of the storage capacitor, a second end of the fifth thin film transistor is connected to a data signal, and a third end of the fifth thin film transistor is The terminal accesses the nth-level scan signal;
  • a sixth thin film transistor a first end of the sixth thin film transistor is connected to a second end of the storage capacitor, a second end of the sixth thin film transistor is connected to a common ground end, and the sixth thin film transistor is Three-terminal access to the enable signal;
  • the pixel compensation method includes the following steps:
  • Vdd is connected to the source of the first thin film transistor a voltage value of the constant DC voltage signal
  • Vth1 is a threshold voltage of the first thin film transistor
  • Vdata is a voltage value of a data signal accessed by the fifth thin film transistor
  • the sixth thin film transistor is turned on, the potential of the gate of the first thin film transistor is pulled to a third potential value, the first thin film transistor is controlled to be turned on, and the third thin film transistor is further turned on to drive the light emitting device to emit light.
  • the third potential value is Vdd-
  • the fourth thin film transistor is turned on by the n-1th scan signal
  • the second thin film transistor and the fifth thin film transistor are turned on by the nth scan signal
  • the third thin film transistor is turned on by an enable signal.
  • a current passing through the light emitting device is according to a hole mobility of the first thin film transistor, a capacitance of a gate insulating layer per unit area in the first thin film transistor, the first film
  • the channel width and channel length of the transistor and the voltage value of the data signal are calculated.
  • the n-1th stage scan signal is a low potential signal
  • the nth stage scan signal is a low potential signal
  • the enable signal is a low potential signal.
  • the present invention has the following beneficial effects: since the threshold voltage of the first thin film transistor is liable to drift, the magnitude of the current flowing through the different light emitting devices is different, thereby causing uneven brightness when the light emitting device emits light.
  • the threshold voltage of the first thin film transistor can be compensated by the second thin film transistor, so that when the light emitting device emits light, the current flowing through the light emitting device is independent of the threshold voltage of the first thin film transistor.
  • the influence of factors such as electrons, hole transport efficiency, and quantum efficiency of the light-emitting device in the light-emitting device is reduced. Therefore, in the present invention, the influence of the first thin film transistor on the light emitting device can be ignored, so that the luminance of the different light emitting devices at the time of light emission is uniform.
  • FIG. 1 is a circuit diagram of a pixel compensation circuit provided by the present invention.
  • FIG. 2 is a timing diagram of signals when the pixel compensation circuit provided by the present invention operates.
  • the present invention provides a pixel compensation circuit.
  • the pixel compensation circuit includes a storage capacitor Cst, a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, and a fifth.
  • Thin film transistor T5, sixth thin film transistor T6, and light emitting device is composed of a pixel electrode and a common electrode line.
  • the source of the first thin film transistor T1 is connected to a constant DC voltage signal VDD.
  • the first end of the second thin film transistor T2 is connected to the gate of the first thin film transistor T1, the second end of the second thin film transistor T2 is connected to the drain of the first thin film transistor T1, and the third end of the second thin film transistor T2 is connected.
  • the first end of the third thin film transistor T3 is connected to the drain of the first thin film transistor T1, the second end of the third thin film transistor T3 is connected to the common ground terminal Vss through the light emitting device, and the third end of the third thin film transistor T3 is connected.
  • Enable signal EM
  • the first end and the third end of the fourth thin film transistor T4 are both connected to the n-1th-th scan signal S[n-1] outputted by the n-1th stage GOA unit in the GOA circuit.
  • the first end of the storage capacitor Cst is connected to the gate of the first thin film transistor T1 and the second end of the fourth thin film transistor T4 to the node A.
  • the first end of the fifth thin film transistor T5 and the second end of the storage capacitor Cst are connected to the Node B, the second end of the fifth thin film transistor T5 is connected to the data signal DS, and the third end of the fifth thin film transistor T5 is connected to the nth The level scan signal S[n].
  • the first end of the sixth thin film transistor T6 is connected to the second end of the storage capacitor Cst to the node B, the second end of the sixth thin film transistor T6 is connected to the common ground terminal Vss, and the third end of the sixth thin film transistor T6 is connected.
  • Can signal EM is connected to the second end of the storage capacitor Cst to the node B, the second end of the sixth thin film transistor T6 is connected to the common ground terminal Vss, and the third end of the sixth thin film transistor T6 is connected.
  • the second thin film transistor T2 and the fifth thin film transistor T5 are controlled to be turned on or off by the nth scanning signal S[n] and the fourth thin film transistor T4 is controlled to be turned on by the n-1th scanning signal S[n-1]. Or turned off, the third thin film transistor T3 and the sixth thin film transistor T6 are controlled to be turned on or off by the enable signal EM.
  • the first end of the thin film transistor is one of a source and a drain
  • the second end of the thin film transistor is the other of the source and the drain
  • the third end of the thin film transistor is a gate.
  • first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are all P-type thin film transistors.
  • the light emitting device is an OLED device, and the anode of the OLED device is connected to the drain of the first thin film transistor T1, and the cathode of the OLED device is connected to the common ground terminal Vss.
  • the current passing through the light emitting device is based on the hole mobility of the first thin film transistor T1, the capacitance of the gate insulating layer per unit area in the first thin film transistor T1, and the channel of the first thin film transistor T1.
  • the width and channel length and the voltage value of the data signal are calculated.
  • the current through the light emitting device is Id, and Id satisfies:
  • ⁇ p is the hole mobility of the first thin film transistor T1 (which may also be referred to as channel mobility)
  • Cox is the capacitance of the gate insulating layer per unit area of the first thin film transistor T1
  • W is the first thin film transistor T1.
  • the channel width, L is the channel length of the first thin film transistor T1
  • Vdata is the voltage value of the data signal DS
  • Vsg is the voltage between the source and the gate of the first thin film transistor T1
  • Vth1 is the first thin film transistor.
  • Vdd is the voltage value of the constant DC voltage signal VDD to which the first thin film transistor T1 is connected.
  • the invention also provides a pixel compensation method, which is applied to the above pixel compensation circuit, and the pixel compensation method comprises the following steps:
  • the second thin film transistor T2 is turned on, the gate potential of the first thin film transistor T1 and the potential of the first end of the storage capacitor Cst (ie, the potential of the node A) are pulled to the first potential value, and the fifth thin film transistor T5 is turned on.
  • Vdd is the first thin film transistor T1
  • Vth1 is the threshold voltage of the first thin film transistor T1
  • Vdata is the voltage value of the data signal DS to which the fifth thin film transistor T5 is connected.
  • the sixth thin film transistor T6 is turned on, and the gate and the drain of the first thin film transistor T1 are shorted.
  • the first thin film transistor T1 is equivalent to a diode, and the potential of the gate of the first thin film transistor T1 can be pulled to the third potential value.
  • the first thin film transistor T1 is controlled to be turned on, and the third thin film transistor T3 is also turned on to drive the light emitting device to emit light.
  • the third potential value is Vdd-
  • the fourth thin film transistor T4 is turned on by the n-1th scanning signal S[n-1], and the second thin film transistor T2 and the fifth thin film transistor T5 are turned on by the nth scanning signal S[n], by enabling The signal EM turns on the third thin film transistor T3 and the sixth thin film transistor T6.
  • the fourth thin film transistor T4 is turned on by the n-1th scanning signal S[n-1]
  • the n-1th scanning signal S[n-1] is a low potential signal.
  • the nth scanning signal S[n] is a low potential signal.
  • the enable signal EM is a low potential signal.
  • Steps S1, S2, and S3 correspond to the t1 time period, the t2 time period, and the t3 time period in FIG. 2, respectively.
  • the n-1th scanning signal S[n-1] is the low potential VGL
  • the nth scanning signal S[n] and the enable signal EM are at the high potential VGH.
  • the n-1th scanning signal S[n-1] and the enable signal EM are at the high potential VGH
  • the nth scanning signal S[n] is at the low potential VGL.
  • the n-1th scanning signal S[n-1] and the nth scanning signal S[n] are both high potential VGH
  • the enable signal EM is low potential VGL.
  • the current passing through the light emitting device is based on the hole mobility of the first thin film transistor T1, the capacitance of the gate insulating layer per unit area in the first thin film transistor T1, and the channel of the first thin film transistor T1.
  • the width and channel length and the voltage value of the data signal are calculated.
  • the current through the light emitting device is Id, and Id satisfies:
  • ⁇ p is the hole mobility of the first thin film transistor T1
  • Cox is the capacitance of the gate insulating layer per unit area of the first thin film transistor T1
  • W is the channel width of the first thin film transistor T1
  • L is the first film. The channel length of transistor T1.
  • the fourth thin film transistor T4 in the first stage, can be controlled to be turned on to clear the charge stored by the storage capacitor Cst; in the second stage, the second control is performed.
  • the thin film transistor T2 and the fifth thin film transistor T5 are turned on, and controlling the opening of the second thin film transistor T2 can short the gate and the drain of the first thin film transistor T1.
  • the first thin film transistor T1 is equivalent to a diode and can be first.
  • the potential of the gate of the thin film transistor T1 is pulled to Vdd-
  • the threshold voltage of the first thin film transistor T1 is likely to drift, the magnitude of the current flowing through the different light emitting devices is different, thereby causing uneven brightness when the light emitting device emits light.
  • the threshold voltage of the first thin film transistor T1 can be compensated by the second thin film transistor T2, so that the current flowing through the light emitting device and the threshold of the first thin film transistor T1 when the light emitting device emits light The voltage is irrelevant.
  • the electron and hole transmission efficiency (ie, channel mobility) of the light-emitting device is affected, thereby affecting the light-emitting stability of the light-emitting device and affecting the quantum of the light-emitting device.
  • Efficiency that is, the threshold voltage of the first thin film transistor T1 affects electrons, hole transport efficiency, and quantum efficiency of the light emitting device in the light emitting device. Therefore, the present invention reduces the influence of the threshold voltage of the first thin film transistor T1 on the light emitting device, and also reduces the influence of factors such as electrons, hole transport efficiency, and quantum efficiency of the light emitting device in the light emitting device.
  • the influence of the first thin film transistor T1 on the light emitting device can be reduced, so that the brightness of the different light emitting devices at the time of light emission is uniform.
  • the present invention has one thin film transistor or one capacitor compared to a pixel compensation circuit such as 7T1C or 6T2C, which reduces the design difficulty of the pixel compensation circuit.

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Abstract

本发明提供一种像素补偿电路及像素补偿方法，补偿电路中：第二薄膜晶体管与第一薄膜晶体管的栅极和漏极连接，第一薄膜晶体管的源极接入恒定直流电压信号，第二薄膜晶体管还接入第n级扫描信号；第三薄膜晶体管与第一薄膜晶体管的漏极连接，还通过发光器件与公共接地端连接以及接入使能信号；第四薄膜晶体管接入第n-1级扫描信号，还与存储电容的第一端和第一薄膜晶体管的栅极连接，存储电容的第二端与第五薄膜晶体管以及第六薄膜晶体管连接；第五薄膜晶体管还分别接入数据信号以及第n级扫描信号；第六薄膜晶体管还分别与公共接地端连接以及接入使能信号。本发明可以降低薄膜晶体管阈值电压对发光器件的影响，使得发光器件在发光时的亮度更均匀。

Description

一种像素补偿电路及像素补偿方法
本申请要求于2018年4月18日提交中国专利局、申请号为201810350263.3、发明名称为“一种像素补偿电路及像素补偿方法”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种像素补偿电路及像素补偿方法。
背景技术
在AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体)显示装置的显示区域内，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个薄膜晶体管与一个电容构成，俗称2T1C电路。这种2T1C的设计对下列因素都很敏感：TFT(薄膜晶体管)的阈值电压(Vth)和沟道迁移率(Mobility)、OLED(organic light emitting diode，有机发光二极体)的启动电压和量子效率以及供电电源的瞬变过程。这些因素会导致不同的OLED发光时亮度不均匀。因此一般需要采用补偿电路，来降低这些因素影响，例如七个薄膜晶体管和一个电容构成的7T1C电路，6个薄膜晶体管和2个电容构成的6T2C电路等。
发明内容
为解决上述技术问题，本发明提供一种像素补偿电路及像素补偿方法，可以降低薄膜晶体管阈值电压等因素对发光器件的影响，使得发光器件在发光时的亮度更均匀。
本发明提供的一种像素补偿电路，包括：
第一薄膜晶体管，所述第一薄膜晶体管的源极接入恒定直流电压信号；
第二薄膜晶体管，所述第二薄膜晶体管的第一端与所述第一薄膜晶体管的栅极连接，第二端与所述第一薄膜晶体管的漏极连接，所述第二薄膜晶体管的第三端接入第n级扫描信号；
第三薄膜晶体管，所述第三薄膜晶体管的第一端与所述第一薄膜晶体管的漏极连接，所述第三薄膜晶体管的第二端通过所述发光器件与公共接地端连接，所述第三薄膜晶体管的第三端接入使能信号；
第四薄膜晶体管，所述第四薄膜晶体管的第一端和第三端均接入第n-1级扫描信号；
存储电容，所述存储电容的第一端与所述第一薄膜晶体管的栅极以及所述第四薄膜晶体管的第二端连接；
第五薄膜晶体管，所述第五薄膜晶体管的第一端与所述存储电容的第二端连接，所述第五薄膜晶体管的第二端接入数据信号，所述第五薄膜晶体管的第三端接入所述第n级扫描信号；
第六薄膜晶体管，所述第六薄膜晶体管的第一端与所述存储电容的第二端连接，所述第六薄膜晶体管的第二端与公共接地端连接，所述第六薄膜晶体管的第三端接入所述使能信号；
其中，通过所述第n级扫描信号控制所述第二薄膜晶体管以及所述第五薄膜晶体管打开或关断，通过所述第n-1级扫描信号控制所述第四薄膜晶体管打开或关断，通过所述使能信号控制所述第三薄膜晶体管和所述第六薄膜晶体管打开或关断。
优选地，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为P型薄膜晶体管。
优选地，所述发光器件为OLED器件。
优选地，当所述发光器件工作时，通过所述发光器件的电流根据所述第一薄膜晶体管的空穴迁移率、所述第一薄膜晶体管中单位面积的栅极绝缘层的电容、所述第一薄膜晶体管的沟道宽度和沟道长度以及所述数据信号的电压值计算得到。
本发明还提供一种像素补偿方法，应用于像素补偿电路中，所述像素补偿电路包括：
第一薄膜晶体管，所述第一薄膜晶体管的源极接入恒定直流电压信号；
第二薄膜晶体管，所述第二薄膜晶体管的第一端与所述第一薄膜晶体管的栅极连接，第二端与所述第一薄膜晶体管的漏极连接，所述第二薄膜晶体管的第三端接入第n级扫描信号；
第三薄膜晶体管，所述第三薄膜晶体管的第一端与所述第一薄膜晶体管的漏极连接，所述第三薄膜晶体管的第二端通过所述发光器件与公共接地端连接，所述第三薄膜晶体管的第三端接入使能信号；
第四薄膜晶体管，所述第四薄膜晶体管的第一端和第三端均接入第n-1级扫描信号；
存储电容，所述存储电容的第一端与所述第一薄膜晶体管的栅极以及所述第四薄膜晶体管的第二端连接；
第五薄膜晶体管，所述第五薄膜晶体管的第一端与所述存储电容的第二端连接，所述第五薄膜晶体管的第二端接入数据信号，所述第五薄膜晶体管的第三端接入所述第n级扫描信号；
第六薄膜晶体管，所述第六薄膜晶体管的第一端与所述存储电容的第二端连接，所述第六薄膜晶体管的第二端与公共接地端连接，所述第六薄膜晶体管的第三端接入所述使能信号；
像素补偿方法包括下述步骤：
S1、开启所述第四薄膜晶体管，清空所述存储电容的电荷；
S2、开启所述第二薄膜晶体管，将所述第一薄膜晶体管的栅极电位以及所述存储电容第一端的电位拉至第一电位值，且开启所述第五薄膜晶体管，将所述存储电容第二端的电位拉至第二电位值，所述第一电位值为Vdd-|Vth1|，所述第二电位值为Vdata，其中，Vdd为所述第一薄膜晶体管的源极所接入的恒定直流电压信号的电压值，Vth1为所述第一薄膜晶体管的阈值电压，Vdata为所述第五薄膜晶体管接入的数据信号的电压值；
S3、开启所述第六薄膜晶体管，将所述第一薄膜晶体管栅极的电位拉至第三电位值，控制所述第一薄膜晶体管开启，还开启所述第三薄膜晶体管，驱动发光器件发光，所述第三电位值为Vdd-|Vth1|-Vdata。
优选地，通过第n-1级扫描信号开启所述第四薄膜晶体管，通过第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管，通过使能信号开 启所述第三薄膜晶体管和所述第六薄膜晶体管。
优选地，通过所述第n-1级扫描信号开启所述第四薄膜晶体管时，所述第n-1级扫描信号为低电位信号；
通过所述第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管时，所述第n级扫描信号为低电位信号；
通过所述使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管时，所述使能信号为低电位信号。
优选地，
当所述发光器件工作时，通过所述发光器件的电流根据所述第一薄膜晶体管的空穴迁移率、所述第一薄膜晶体管中单位面积的栅极绝缘层的电容、所述第一薄膜晶体管的沟道宽度和沟道长度以及所述数据信号的电压值计算得到。
本发明还提供一种像素补偿方法，应用于像素补偿电路中，所述像素补偿电路包括：
第一薄膜晶体管，所述第一薄膜晶体管的源极接入恒定直流电压信号；
第二薄膜晶体管，所述第二薄膜晶体管的第一端与所述第一薄膜晶体管的栅极连接，第二端与所述第一薄膜晶体管的漏极连接，所述第二薄膜晶体管的第三端接入第n级扫描信号；
第三薄膜晶体管，所述第三薄膜晶体管的第一端与所述第一薄膜晶体管的漏极连接，所述第三薄膜晶体管的第二端通过所述发光器件与公共接地端连接，所述第三薄膜晶体管的第三端接入使能信号；
第四薄膜晶体管，所述第四薄膜晶体管的第一端和第三端均接入第n-1级扫描信号；
存储电容，所述存储电容的第一端与所述第一薄膜晶体管的栅极以及所述第四薄膜晶体管的第二端连接；
第五薄膜晶体管，所述第五薄膜晶体管的第一端与所述存储电容的第二端连接，所述第五薄膜晶体管的第二端接入数据信号，所述第五薄膜晶体管的第三端接入所述第n级扫描信号；
第六薄膜晶体管，所述第六薄膜晶体管的第一端与所述存储电容的第二 端连接，所述第六薄膜晶体管的第二端与公共接地端连接，所述第六薄膜晶体管的第三端接入所述使能信号；
像素补偿方法包括下述步骤：
S1、开启所述第四薄膜晶体管，清空所述存储电容的电荷；
S2、开启所述第二薄膜晶体管，将所述第一薄膜晶体管的栅极电位以及所述存储电容第一端的电位拉至第一电位值，且开启所述第五薄膜晶体管，将所述存储电容第二端的电位拉至第二电位值，所述第一电位值为Vdd-|Vth1|，所述第二电位值为Vdata，其中，Vdd为所述第一薄膜晶体管的源极所接入的恒定直流电压信号的电压值，Vth1为所述第一薄膜晶体管的阈值电压，Vdata为所述第五薄膜晶体管接入的数据信号的电压值；
S3、开启所述第六薄膜晶体管，将所述第一薄膜晶体管栅极的电位拉至第三电位值，控制所述第一薄膜晶体管开启，还开启所述第三薄膜晶体管，驱动发光器件发光，所述第三电位值为Vdd-|Vth1|-Vdata；
其中，通过第n-1级扫描信号开启所述第四薄膜晶体管，通过第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管，通过使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管；
当所述发光器件工作时，通过所述发光器件的电流根据所述第一薄膜晶体管的空穴迁移率、所述第一薄膜晶体管中单位面积的栅极绝缘层的电容、所述第一薄膜晶体管的沟道宽度和沟道长度以及所述数据信号的电压值计算得到。
优选地，通过所述第n-1级扫描信号开启所述第四薄膜晶体管时，所述第n-1级扫描信号为低电位信号；
通过所述第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管时，所述第n级扫描信号为低电位信号；
通过所述使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管时，所述使能信号为低电位信号。
实施本发明，具有如下有益效果：由于第一薄膜晶体管的阈值电压容易发生漂移，导致流过不同发光器件的电流大小不同，进而造成发光器件发光时亮度不均。本发明中的像素补偿电路中可以通过第二薄膜晶体管实现对 第一薄膜晶体管阈值电压的补偿，使得在发光器件进行发光时，流过发光器件的电流大小与第一薄膜晶体管的阈值电压无关还降低了发光器件中的电子、空穴传输效率以及发光器件的量子效率等因素的影响。因而，本发明中，可以忽略第一薄膜晶体管对发光器件的影响，使得不同的发光器件在发光时的亮度均匀。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的像素补偿电路的电路图。
图2是本发明提供的像素补偿电路工作时的信号时序图。
具体实施方式
本发明提供一种像素补偿电路，如图1所示，该像素补偿电路包括存储电容Cst、第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6以及发光器件。一般地，存储电容Cst由像素电极和公共电极线构成。
第一薄膜晶体管T1的源极接入恒定直流电压信号VDD。
第二薄膜晶体管T2的第一端与第一薄膜晶体管T1的栅极连接，第二薄膜晶体管T2的第二端与第一薄膜晶体管T1的漏极连接，第二薄膜晶体管T2的第三端接入GOA(Gate Driver on Array，阵列基板行驱动技术)电路中第n级GOA单元输出的第n级扫描信号S[n]，n>1。
第三薄膜晶体管T3的第一端与第一薄膜晶体管T1的漏极连接，第三薄膜晶体管T3的第二端通过发光器件与公共接地端Vss连接，第三薄膜晶体管T3的第三端接入使能信号EM。
第四薄膜晶体管T4的第一端和第三端均接入GOA电路中第n-1级GOA单元输出的第n-1级扫描信号S[n-1]。
存储电容Cst的第一端与第一薄膜晶体管T1的栅极以及第四薄膜晶体管T4的第二端连接于A节点。
第五薄膜晶体管T5的第一端与存储电容Cst的第二端连接于B节点，第五薄膜晶体管T5的第二端接入数据信号DS，第五薄膜晶体管T5的第三端接入第n级扫描信号S[n]。
第六薄膜晶体管T6的第一端与存储电容Cst的第二端连接于B节点，第六薄膜晶体管T6的第二端与公共接地端Vss连接，第六薄膜晶体管T6的第三端接入使能信号EM。
其中，通过第n级扫描信号S[n]控制第二薄膜晶体管T2以及第五薄膜晶体管T5打开或关断，通过第n-1级扫描信号S[n-1]控制第四薄膜晶体管T4打开或关断，通过使能信号EM控制第三薄膜晶体管T3和第六薄膜晶体管T6打开或关断。薄膜晶体管的第一端为源极和漏极中的一个，薄膜晶体管的第二端为源极和漏极中的另一个，薄膜晶体管的第三端为栅极。当第一薄膜晶体管T1和第三薄膜晶体管T3都打开时，发光器件开始工作。
进一步地，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5以及第六薄膜晶体管T6均为P型薄膜晶体管。
进一步地，发光器件为OLED器件，该OLED器件的正极与第一薄膜晶体管T1的漏极连接，该OLED器件的负极与公共接地端Vss连接。
进一步地，当发光器件工作时，通过发光器件的电流根据第一薄膜晶体管T1的空穴迁移率、第一薄膜晶体管T1中单位面积的栅极绝缘层的电容、第一薄膜晶体管T1的沟道宽度和沟道长度以及数据信号的电压值计算得到。
通过发光器件的电流为Id，且Id满足：
Figure PCTCN2018089413-appb-000001
进一步得到：
Figure PCTCN2018089413-appb-000002
又进一步得到：
Figure PCTCN2018089413-appb-000003
可以知道的是，Id的最终结果与第一薄膜晶体管T1的阈值电压不相关。
其中，μp为第一薄膜晶体管T1的空穴迁移率(也可以称为沟道迁移率)，Cox为第一薄膜晶体管T1中单位面积的栅极绝缘层的电容，W为第一薄膜晶体管T1的沟道宽度，L为第一薄膜晶体管T1的沟道长度，Vdata为数据信号DS的电压值，Vsg为第一薄膜晶体管T1的源极和栅极之间的电压，Vth1为第一薄膜晶体管T1的阈值电压，Vdd为第一薄膜晶体管T1接入的恒定直流电压信号VDD的电压值。
本发明还提供一种像素补偿方法，应用于上述的像素补偿电路中，该像素补偿方法包括下述步骤：
S1、开启第四薄膜晶体管T4，清空存储电容Cst的电荷；一般地，存储电容Cst的电荷可以传导至与第四薄膜晶体管T4连接的第n-1级GOA单元。
S2、开启第二薄膜晶体管T2，将第一薄膜晶体管T1的栅极电位以及存储电容Cst第一端的电位(即A节点的电位)拉至第一电位值，且开启第五薄膜晶体管T5，将存储电容Cst第二端的电位(即B节点的电位)拉至第二电位值；第一电位值为Vdd-|Vth1|，第二电位值为Vdata，其中，Vdd为第一薄膜晶体管T1的源极所接入的恒定直流电压信号VDD的电压值，Vth1为第一薄膜晶体管T1的阈值电压，Vdata为第五薄膜晶体管T5接入的数据信号DS的电压值。
S3、开启第六薄膜晶体管T6，将第一薄膜晶体管T1的栅极和漏极短接，第一薄膜晶体管T1相当于二极管，可以将第一薄膜晶体管T1栅极的电位拉至第三电位值，控制第一薄膜晶体管T1开启，还开启第三薄膜晶体管T3，驱动发光器件发光。第三电位值为Vdd-|Vth1|-Vdata。
进一步地，通过第n-1级扫描信号S[n-1]开启第四薄膜晶体管T4，通过第n级扫描信号S[n]开启第二薄膜晶体管T2和第五薄膜晶体管T5，通过使能信号EM开启第三薄膜晶体管T3和第六薄膜晶体管T6。
进一步地，通过第n-1级扫描信号S[n-1]开启第四薄膜晶体管T4时，第n-1级扫描信号S[n-1]为低电位信号。
通过第n级扫描信号S[n]开启第二薄膜晶体管T2和第五薄膜晶体管T5时，第n级扫描信号S[n]为低电位信号。
通过使能信号EM开启第三薄膜晶体管T3和第六薄膜晶体管T6时，使能信号EM为低电位信号。
步骤S1、S2、S3分别对应图2中的t1时间段、t2时间段、t3时间段。在t1时间段，第n-1级扫描信号S[n-1]为低电位VGL，第n级扫描信号S[n]和使能信号EM为高电位VGH。在t2时间段，第n-1级扫描信号S[n-1]和使能信号EM为高电位VGH，第n级扫描信号S[n]为低电位VGL。在t3时间段，第n-1级扫描信号S[n-1]和第n级扫描信号S[n]均为高电位VGH，使能信号EM为低电位VGL。
进一步地，当发光器件工作时，通过发光器件的电流根据第一薄膜晶体管T1的空穴迁移率、第一薄膜晶体管T1中单位面积的栅极绝缘层的电容、第一薄膜晶体管T1的沟道宽度和沟道长度以及数据信号的电压值计算得到。
通过发光器件的电流为Id，且Id满足：
Figure PCTCN2018089413-appb-000004
其中，μp为第一薄膜晶体管T1的空穴迁移率，Cox为第一薄膜晶体管T1中单位面积的栅极绝缘层的电容，W为第一薄膜晶体管T1的沟道宽度，L为第一薄膜晶体管T1的沟道长度。
综上所述，本发明提供的像素补偿电路及像素补偿方法中，在第一阶段，可以控制第四薄膜晶体管T4打开，将存储电容Cst所存储的电荷清空；在第二阶段，控制第二薄膜晶体管T2和第五薄膜晶体管T5开启，控制第二薄膜晶体管T2开启可以将第一薄膜晶体管T1的栅极和漏极短接，此时，第一薄膜晶体管T1相当于二极管，可以将第一薄膜晶体管T1栅极的电位拉至Vdd-|Vth1|；控制第五薄膜晶体管T5开启，可以将存储电容Cst第二端的电 位拉至Vdata，此时存储电容Cst的压降为Vdd-|Vth1|-Vdata；在第三阶段，控制第三薄膜晶体管T3和第六薄膜晶体管T6开启；第六薄膜晶体管T6开启时，由于存储电容Cst的电容特性，可以将第一薄膜晶体管T1的栅极电位拉至Vdd-|Vth1|-Vdata，可以控制第一薄膜晶体管T1开启；同时，第三薄膜晶体管T3也开启了，第一薄膜晶体管T1的电流通过第三薄膜晶体管T3流向发光器件，驱动发光器件发光。
由于第一薄膜晶体管T1的阈值电压容易发生漂移，导致流过不同发光器件的电流大小不同，进而造成发光器件发光时亮度不均。本发明中的像素补偿电路中可以通过第二薄膜晶体管T2实现对第一薄膜晶体管T1阈值电压的补偿，使得在发光器件进行发光时，流过发光器件的电流大小与第一薄膜晶体管T1的阈值电压无关。
当像素补偿电路为OLED器件等发光器件提供的电压漂移不定时，会影响发光器件的电子、空穴传输效率(即沟道迁移率)，进而影响发光器件的发光稳定性，影响发光器件的量子效率；也即是，第一薄膜晶体管T1的阈值电压会影响发光器件中的电子、空穴传输效率以及发光器件的量子效率。因此，本发明降低第一薄膜晶体管T1的阈值电压对发光器件影响的同时，还降低了发光器件中的电子、空穴传输效率以及发光器件的量子效率等因素的影响。
因而，本发明中，可以降低第一薄膜晶体管T1对发光器件的影响，使得不同的发光器件在发光时的亮度均匀。而且，本发明相对于7T1C或6T2C等像素补偿电路，少了一个薄膜晶体管或一个电容，减少了像素补偿电路的设计难度。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种像素补偿电路，其中，包括：
    第一薄膜晶体管，所述第一薄膜晶体管的源极接入恒定直流电压信号；
    第二薄膜晶体管，所述第二薄膜晶体管的第一端与所述第一薄膜晶体管的栅极连接，第二端与所述第一薄膜晶体管的漏极连接，所述第二薄膜晶体管的第三端接入第n级扫描信号；
    第三薄膜晶体管，所述第三薄膜晶体管的第一端与所述第一薄膜晶体管的漏极连接，所述第三薄膜晶体管的第二端通过所述发光器件与公共接地端连接，所述第三薄膜晶体管的第三端接入使能信号；
    第四薄膜晶体管，所述第四薄膜晶体管的第一端和第三端均接入第n-1级扫描信号；
    存储电容，所述存储电容的第一端与所述第一薄膜晶体管的栅极以及所述第四薄膜晶体管的第二端连接；
    第五薄膜晶体管，所述第五薄膜晶体管的第一端与所述存储电容的第二端连接，所述第五薄膜晶体管的第二端接入数据信号，所述第五薄膜晶体管的第三端接入所述第n级扫描信号；
    第六薄膜晶体管，所述第六薄膜晶体管的第一端与所述存储电容的第二端连接，所述第六薄膜晶体管的第二端与公共接地端连接，所述第六薄膜晶体管的第三端接入所述使能信号；
    其中，通过所述第n级扫描信号控制所述第二薄膜晶体管以及所述第五薄膜晶体管打开或关断，通过所述第n-1级扫描信号控制所述第四薄膜晶体管打开或关断，通过所述使能信号控制所述第三薄膜晶体管和所述第六薄膜晶体管打开或关断。
  2. 根据权利要求1所述的像素补偿电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为P型薄膜晶体管。
  3. 根据权利要求2所述的像素补偿电路，其中，所述发光器件为OLED器件。
  4. 根据权利要求3所述的像素补偿电路，其中，当所述发光器件工作时，通过所述发光器件的电流根据所述第一薄膜晶体管的空穴迁移率、所述第一薄膜晶体管中单位面积的栅极绝缘层的电容、所述第一薄膜晶体管的沟道宽度和沟道长度以及所述数据信号的电压值计算得到。
  5. 一种像素补偿方法，其中，应用于像素补偿电路中，所述像素补偿电路包括：
    第一薄膜晶体管，所述第一薄膜晶体管的源极接入恒定直流电压信号；
    第二薄膜晶体管，所述第二薄膜晶体管的第一端与所述第一薄膜晶体管的栅极连接，第二端与所述第一薄膜晶体管的漏极连接，所述第二薄膜晶体管的第三端接入第n级扫描信号；
    第三薄膜晶体管，所述第三薄膜晶体管的第一端与所述第一薄膜晶体管的漏极连接，所述第三薄膜晶体管的第二端通过所述发光器件与公共接地端连接，所述第三薄膜晶体管的第三端接入使能信号；
    第四薄膜晶体管，所述第四薄膜晶体管的第一端和第三端均接入第n-1级扫描信号；
    存储电容，所述存储电容的第一端与所述第一薄膜晶体管的栅极以及所述第四薄膜晶体管的第二端连接；
    第五薄膜晶体管，所述第五薄膜晶体管的第一端与所述存储电容的第二端连接，所述第五薄膜晶体管的第二端接入数据信号，所述第五薄膜晶体管的第三端接入所述第n级扫描信号；
    第六薄膜晶体管，所述第六薄膜晶体管的第一端与所述存储电容的第二端连接，所述第六薄膜晶体管的第二端与公共接地端连接，所述第六薄膜晶体管的第三端接入所述使能信号；
    像素补偿方法包括下述步骤：
    S1、开启所述第四薄膜晶体管，清空所述存储电容的电荷；
    S2、开启所述第二薄膜晶体管，将所述第一薄膜晶体管的栅极电位以及所述存储电容第一端的电位拉至第一电位值，且开启所述第五薄膜晶体管，将所述存储电容第二端的电位拉至第二电位值，所述第一电位值为 Vdd-|Vth1|，所述第二电位值为Vdata，其中，Vdd为所述第一薄膜晶体管的源极所接入的恒定直流电压信号的电压值，Vth1为所述第一薄膜晶体管的阈值电压，Vdata为所述第五薄膜晶体管接入的数据信号的电压值；
    S3、开启所述第六薄膜晶体管，将所述第一薄膜晶体管栅极的电位拉至第三电位值，控制所述第一薄膜晶体管开启，还开启所述第三薄膜晶体管，驱动发光器件发光，所述第三电位值为Vdd-|Vth1|-Vdata。
  6. 根据权利要求5所述的像素补偿方法，其中，通过第n-1级扫描信号开启所述第四薄膜晶体管，通过第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管，通过使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管。
  7. 根据权利要求6所述的像素补偿方法，其中，通过所述第n-1级扫描信号开启所述第四薄膜晶体管时，所述第n-1级扫描信号为低电位信号；
    通过所述第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管时，所述第n级扫描信号为低电位信号；
    通过所述使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管时，所述使能信号为低电位信号。
  8. 根据权利要求5所述的像素补偿方法，其中，
    当所述发光器件工作时，通过所述发光器件的电流根据所述第一薄膜晶体管的空穴迁移率、所述第一薄膜晶体管中单位面积的栅极绝缘层的电容、所述第一薄膜晶体管的沟道宽度和沟道长度以及所述数据信号的电压值计算得到。
  9. 一种像素补偿方法，其中，应用于像素补偿电路中，所述像素补偿电路包括：
    第一薄膜晶体管，所述第一薄膜晶体管的源极接入恒定直流电压信号；
    第二薄膜晶体管，所述第二薄膜晶体管的第一端与所述第一薄膜晶体管的栅极连接，第二端与所述第一薄膜晶体管的漏极连接，所述第二薄膜晶体管的第三端接入第n级扫描信号；
    第三薄膜晶体管，所述第三薄膜晶体管的第一端与所述第一薄膜晶体管的漏极连接，所述第三薄膜晶体管的第二端通过所述发光器件与公共接地端 连接，所述第三薄膜晶体管的第三端接入使能信号；
    第四薄膜晶体管，所述第四薄膜晶体管的第一端和第三端均接入第n-1级扫描信号；
    存储电容，所述存储电容的第一端与所述第一薄膜晶体管的栅极以及所述第四薄膜晶体管的第二端连接；
    第五薄膜晶体管，所述第五薄膜晶体管的第一端与所述存储电容的第二端连接，所述第五薄膜晶体管的第二端接入数据信号，所述第五薄膜晶体管的第三端接入所述第n级扫描信号；
    第六薄膜晶体管，所述第六薄膜晶体管的第一端与所述存储电容的第二端连接，所述第六薄膜晶体管的第二端与公共接地端连接，所述第六薄膜晶体管的第三端接入所述使能信号；
    像素补偿方法包括下述步骤：
    S1、开启所述第四薄膜晶体管，清空所述存储电容的电荷；
    S2、开启所述第二薄膜晶体管，将所述第一薄膜晶体管的栅极电位以及所述存储电容第一端的电位拉至第一电位值，且开启所述第五薄膜晶体管，将所述存储电容第二端的电位拉至第二电位值，所述第一电位值为Vdd-|Vth1|，所述第二电位值为Vdata，其中，Vdd为所述第一薄膜晶体管的源极所接入的恒定直流电压信号的电压值，Vth1为所述第一薄膜晶体管的阈值电压，Vdata为所述第五薄膜晶体管接入的数据信号的电压值；
    S3、开启所述第六薄膜晶体管，将所述第一薄膜晶体管栅极的电位拉至第三电位值，控制所述第一薄膜晶体管开启，还开启所述第三薄膜晶体管，驱动发光器件发光，所述第三电位值为Vdd-|Vth1|-Vdata；
    其中，通过第n-1级扫描信号开启所述第四薄膜晶体管，通过第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管，通过使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管；
    当所述发光器件工作时，通过所述发光器件的电流根据所述第一薄膜晶体管的空穴迁移率、所述第一薄膜晶体管中单位面积的栅极绝缘层的电容、所述第一薄膜晶体管的沟道宽度和沟道长度以及所述数据信号的电压值计算得到。
  10. 根据权利要求9所述的像素补偿方法，其中，通过所述第n-1级扫描信号开启所述第四薄膜晶体管时，所述第n-1级扫描信号为低电位信号；
    通过所述第n级扫描信号开启所述第二薄膜晶体管和所述第五薄膜晶体管时，所述第n级扫描信号为低电位信号；
    通过所述使能信号开启所述第三薄膜晶体管和所述第六薄膜晶体管时，所述使能信号为低电位信号。
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