WO2019196600A1

WO2019196600A1 - Chip and communication device

Info

Publication number: WO2019196600A1
Application number: PCT/CN2019/078567
Authority: WO
Inventors: 刘宁; 陈钊
Original assignee: 华为技术有限公司
Priority date: 2018-04-09
Filing date: 2019-03-18
Publication date: 2019-10-17
Also published as: CN110364510A; CN110364510B

Abstract

Provided is a chip, comprising a substrate, a bare chip, and a solder ball set soldered between the substrate and the bare chip. The solder ball set comprises a first solder ball and a second solder ball spaced apart from each other; a first conductive portion connecting the first solder ball to the second solder ball is arranged on the bare chip; a second conductive portion connecting the first solder ball to the second solder ball is arranged on the substrate; the first solder ball, the first conductive portion, the second solder ball and the second conductive portion form a closed loop; and the bare chip further comprises two inductors distributed at two sides of the closed loop. The chip can ameliorate the crosstalk phenomenon between adjacent inductors. A communication device is further provided.

Description

Chip and communication equipment

Technical field

The present application relates to the field of integrated circuits, and in particular, to a chip and communication device for preventing crosstalk.

Background technique

At present, with the development of communication devices, integrated circuits (ICs, also known as integrated circuits) are also moving toward miniaturization and multi-functionality. Due to the limited space of the devices on the chip, in order to arrange more functional IP (intellectual property) modules, the spacing between the functional IP modules is getting smaller and smaller, resulting in crosstalk between the functional IP modules. A key issue affecting chip performance. Wherein, the coupling between two adjacent inductor coils is mainly magnetic field coupling: when one of the coils (exciting coils) passes an alternating current, the coil forms an alternating magnetic field around the excitation coil, and the magnetic field of the alternating magnetic field When the wire passes through the other coil (the disturbed coil), the induced current is formed in the disturbed coil due to the change of the magnetic flux surrounded by the disturbed coil, which is crosstalk. Crosstalk is particularly noticeable due to the small spacing between the excitation coil and the victim coil.

Summary of the invention

The application provides a chip and a communication device.

In a first aspect, the present application provides a chip. The chip includes a substrate, a bare chip, and a solder ball group soldered between the substrate and the bare chip. The set of solder balls includes a first solder ball and a second solder ball that are spaced apart. There is a gap between the first solder ball and the second solder ball, and the gap may be filled with a colloid or other adhesive. The bare chip is provided with a first conductive portion connected to the first solder ball and the second solder ball. A second conductive portion connected to the first solder ball and the second solder ball is disposed on the substrate. The first solder ball, the first conductive portion, the second solder ball, and the second conductive portion form a closed loop. The bare chip further includes two inductors distributed on both sides of the closed loop.

In this embodiment, when one of the two inductors is an excitation coil, the other inductor is a victim coil, and the excitation coil and the victim coil are respectively located on both sides of the closed loop, and utilize Faraday's law of electromagnetic induction, when the magnetic field lines of the excitation coil pass through the closed loop, an induced current is induced in the closed loop, thereby canceling the magnetic lines of force passing through the closed loop, so that the disturbed coil passes through The magnetic field lines are reduced, so that the degree of coupling between the excitation coil and the victim coil is reduced, and the isolation is improved. In other words, since the two inductors are distributed on both sides of the closed loop, the closed loop can effectively isolate the two inductors, so the two inductors can be lowered by the closed loop The degree of coupling, thereby improving the crosstalk between the two inductors.

Wherein, the chip forms the first conductive portion by using a metal trace in the bare chip, and forms the first solder ball and the second solder ball by using the solder ball group in a chip package structure, and utilizes The encapsulating metal layer on the substrate forms the second conductive portion, so the closed loop can fully utilize the package structure of the chip, improve utilization of the chip package structure, and thereby reduce the isolation ring the cost of.

The first conductive portion is formed because the closed loop of the chip is formed by sequentially connecting the first solder ball, the first conductive portion, the second solder ball, and the second conductive portion. Formed on the bare chip, the second conductive portion is formed on the substrate, and the first solder ball and the second solder ball are connected between the bare chip and the substrate, so The closed loop is a three-dimensional closed loop with respect to the bare chip. Since the two inductors are respectively located on two sides of the closed loop, that is, the closed loop is only disposed on a necessary path in which the magnetic lines of the two inductors are coupled to each other, the closed loop does not The lines of magnetic force in other orientations of the two inductors produce a weakening effect, so the inductance and Q value of the closed loop to the two inductors (also called the quality factor of the inductor) refers to the exchange of the inductor at a certain frequency. The effect of the inductive reactance and its equivalent loss resistance when operating at voltage is very small. In short, the closed loop can reduce the degree of coupling between the two inductors without reducing the inductance and Q of the two inductors to improve the relationship between the two inductors. Crosstalk.

Wherein the closed loop is grounded. Of course, in other embodiments, the closed loop can also be left floating, that is, the closed loop is not connected to other circuits.

In one embodiment, the bare chip has a connection surface toward the substrate. The line connecting the center points of the two inductors is the first connection. A line connecting the center point of the first solder ball and the center point of the second solder ball is a second line. An orthographic projection of the first line on the connecting surface intersects an orthographic projection of the second line on the connecting surface. At this time, the closed loop is located in a middle area between the first inductor and the second inductor, and the closed loop can cancel more magnetic lines of force, and the isolation is higher.

Wherein, the first connection may pass through the closed loop to better isolate the closed loop.

Wherein the orthographic projection of the first line on the connecting surface passes through the center of the orthographic projection of the second line on the connecting surface. At this time, the closed loop is located in a middle area between the first inductor and the second inductor, and the closed loop has better isolation effect.

In one embodiment, the orthographic projection of the first line on the connecting surface is perpendicular to the orthographic projection of the second line on the connecting surface. At this time, the first inductor and the second inductor are arranged substantially symmetrically on both sides of the closed loop, so that the closed loop can cancel more magnetic lines of force, the isolation is higher, and The inductance of the first inductance and the second inductance and the Q value are less affected.

In one embodiment, the first solder ball and the second solder ball are arranged in a first direction. The distance between the first solder ball and the second solder ball is a first length. The spacing between the first solder ball and the second solder ball is a minimum distance between an outer contour of the first solder ball and an outer contour of the second solder ball. The two inductors are a first inductor and a second inductor. The length of the first inductor in the first direction is a second length. The length of the second inductor in the first direction is a third length. The second length is greater than or equal to the third length. The ratio of the first length to the second length is in the range of 0.75 to 1.25.

In this embodiment, when the ratio of the first length to the second length is in the range of 0.75 to 1.25, that is, the length of the closed loop and the longer length of the two inductors When the length is similar, the closed loop has better isolation effect, and can effectively isolate the two inductors.

In one embodiment, the first length is equal to the second length. At this time, the length of the closed loop is equal to the length of the longer length of the two inductors, and the closed loop can better reduce the relationship between the first inductor and the second inductor The degree of coupling, the isolation of the closed loop is good.

In one embodiment, the first conductive portion has a strip shape, and the extending direction of the first conductive portion is consistent with the first direction. At this time, the first conductive portion may be a metal trace formed in the bare chip. Since the extending direction of the first conductive portion is consistent with the first direction, the length of the first conductive portion is short, and the resistance of the first conductive portion is small, which is favorable for improving the sensitivity of the closed loop. The isolation effect of the closed loop is better.

In one embodiment, the first solder ball has a first width in a second direction, the second direction being parallel to the bare chip and perpendicular to the first direction. The width of the second solder ball in the second direction is equal to the first width. The first conductive portion has a second width in the second direction. The ratio of the second width to the first width is greater than or equal to 0.75. Wherein, the outer contour of the first solder ball is the same as or very similar to the outer contour of the second solder ball. The width of the second solder ball in the second direction is also considered when the width of the second solder ball in the second direction is slightly different from the first width due to an error in manufacturing process. Equal to the first width.

In this embodiment, when the ratio of the second width to the first width is greater than or equal to 0.75, that is, the width of the first conductive portion and the width of the first solder ball, the second solder ball When the width is similar, the closed loop has better isolation effect, and can effectively isolate the two inductors.

In one embodiment, the second width is equal to the first width. At this time, the width of the first conductive portion is the same as the width of the first solder ball and the width of the second solder ball, which can save the material of the first conductive portion, and the closed loop is also The degree of coupling between the first inductance and the second inductance can be well reduced, and the isolation effect of the closed loop is good.

In one embodiment, the second conductive portion has a strip shape. The extending direction of the second conductive portion is consistent with the first direction. At this time, the second conductive portion may be a metal trace formed in the substrate. Since the extending direction of the second conductive portion is consistent with the first direction, the second conductive portion has a short length, and the second conductive portion has a small resistance, which is also advantageous for improving the sensitivity of the closed loop. The degree of isolation of the closed loop is better.

The second conductive portion has a third width in the second direction, and the third width is greater than or equal to the second width. For example, the third width is equal to the second width. At this time, the closed loop has a better isolation effect, and can effectively isolate the two inductors.

In one embodiment, the solder ball set further includes a third solder ball. The third solder ball is arranged in the same direction as the first solder ball and the second solder ball, and the third solder ball is located between the first solder ball and the second solder ball . The third solder ball connects the first conductive portion and the second conductive portion.

In this embodiment, the first solder ball, the second solder ball, and the third solder ball are connected between the first conductive portion and the second conductive portion, so the closed loop A plurality of parallel small loops are formed in the road, so that the isolation effect of the closed loop is better.

In one embodiment, the first inductor includes an upper layer inductor, a lower layer inductor, and a plurality of conductive pillars. The upper layer inductor is stacked and spaced apart from the lower layer inductor, and the plurality of conductive pillars are connected between the upper layer inductor and the lower layer inductor. At this time, the first inductor has a large thickness, thereby increasing the Q value of the first inductor.

The upper layer inductor or the lower layer inductor is disposed in the same layer as the first conductive portion. At this time, the preparation process of the first inductor and the first conductive portion is integrated in the molding process of the bare chip, and the first conductive portion can be synchronously formed in the manufacturing process of the first inductor. Thereby, the manufacturing process of the bare chip is simplified, and the cost of the bare chip is reduced.

In a second aspect, the present application provides a communication device. The communication device includes a housing, a circuit board, and a chip. The chip employs the chip described in the above embodiments. The circuit board is housed inside the housing. The chip is fixed to the circuit board and electrically connected to the circuit board. Since the chip can improve the crosstalk problem between adjacent inductors, the chip can process and transmit signals with higher quality, and thus the performance of the communication device to which the chip is applied is better.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings to be used in the embodiments of the present application or the background art will be described below.

1 is a schematic structural diagram of an optional chip provided by an embodiment of the present application;

Figure 2 is an enlarged schematic view showing the structure of the chip A of Figure 1;

3 is a schematic perspective view showing an embodiment of two inductors and a closed loop of the chip shown in FIG. 1;

4 is a graph showing the relationship between the isolation of a possible chip and the existing chip based on the solution of the present application;

FIG. 5 is a graph showing the relationship between the inductance and the frequency of a possible chip and the existing chip obtained based on the solution of the present application.

6 is a graph showing a relationship between a possible chip and a Q value and a frequency of a conventional chip obtained based on the solution of the present application;

Figure 7 is a partial structural view of the structure shown in Figure 2 taken along line B-B;

8 is a schematic perspective view showing another embodiment of two inductors and a closed loop of the chip shown in FIG. 1;

9 is a schematic structural view of the first inductor of FIG. 2;

FIG. 10 is a schematic structural diagram of a communication device according to an embodiment of the present disclosure;

11 is a schematic view showing a positional relationship of a partial projection of a portion of the chip shown in FIG. 1 on a connection surface of a bare chip;

FIG. 12 is another schematic diagram showing the positional relationship of the partial structure of the chip shown in FIG. 1 on the connection surface of the bare chip. FIG.

detailed description

The embodiments of the present application are described below in conjunction with the accompanying drawings in the embodiments of the present application.

Referring to FIG. 1 and FIG. 2 together, the present application provides a chip 100. The chip 100 includes a substrate 1 , a bare chip 2 , and a solder ball group 3 soldered between the substrate 1 and the bare chip 2 .

Referring to FIG. 2 and FIG. 3 together, the solder ball set 3 includes a first solder ball 31 and a second solder ball 32 which are spaced apart. There is a gap between the first solder ball 31 and the second solder ball 32, and the gap may be filled with a colloid or other adhesive. The bare chip 2 is provided with a first conductive portion 21 connecting the first solder ball 31 and the second solder ball 32. A second conductive portion 11 connecting the first solder ball 31 and the second solder ball 32 is disposed on the substrate 1 . The first solder ball 31, the first conductive portion 21, the second solder ball 32, and the second conductive portion 11 form a closed loop 10. The bare chip 2 further includes two inductors (22, 23) distributed on both sides of the closed loop 10.

In this embodiment, when one of the two inductors (22, 23) is an excitation coil, the other inductor is a victim coil, and the excitation coil and the victim coil are respectively located in the closed loop On both sides of 10, using Faraday's law of electromagnetic induction, when the magnetic field lines of the excitation coil pass through the closed loop 10, an induced current is induced in the closed loop 10, thereby canceling through the closed loop 10 The magnetic lines of force, so that the lines of magnetic force passing through the disturbed coil are reduced, so that the degree of coupling between the exciting coil and the disturbed coil is reduced, and the isolation is improved. In other words, since the two inductors (22, 23) are distributed on both sides of the closed loop 10, the closed loop 10 can effectively isolate the two inductors (22, 23), thus the two The inductors (22, 23) can utilize the closed loop 10 to reduce the degree of coupling between each other, thereby improving crosstalk between the two inductors (22, 23).

Referring to FIG. 2 and FIG. 3 together, the chip 100 forms the first conductive portion 21 by using metal traces in the bare chip 2, and is formed by using the solder ball group 3 in the package structure of the chip 100. The first solder ball 31 and the second solder ball 32 form the second conductive portion 11 by using a package metal layer on the substrate 1 , so the closed loop 10 can fully utilize the chip 100 The package structure improves the utilization of the package structure of the chip 100, thereby reducing the cost of the closed loop 10 as an isolation ring. Of course, in other embodiments, an advanced micro-electro-mechanical system (MEMS) processing technology can also be used to construct a three-dimensional isolation ring with a closed loop, which can also improve the inductance. The effect of isolation between the two.

Referring to FIG. 2 and FIG. 3 together, since the closed loop 10 of the chip 100 is composed of the first solder ball 31, the first conductive portion 21, the second solder ball 32, and the The second conductive portion 11 is formed by sequentially connecting, the first conductive portion 21 is formed on the bare chip 2, the second conductive portion 11 is formed on the substrate 1, the first solder ball 31 and The second solder ball 32 is connected between the bare chip 2 and the substrate 1 , so the closed loop 10 is a three-dimensional closed loop with respect to the bare chip 2 . Since the two inductors (22, 23) are respectively located on both sides of the closed loop 10, that is, the closed loop 10 is only required to be coupled to the magnetic lines of the two inductors (22, 23). The closed loop 10 does not attenuate magnetic lines of force in other orientations of the two inductors (22, 23) over the path, so the closed loop 10 pairs the two inductors (22, 23) The inductance and Q value (also called the quality factor of the inductor, which is the ratio of the inductive reactance to its equivalent loss resistance when the inductor operates at an AC voltage of a certain frequency) has very little effect.

As shown in FIG. 4, FIG. 4 is a graph showing the relationship between isolation and frequency of a possible chip 100 obtained according to the solution of the present application in comparison with the existing chip. In FIG. 4, the abscissa indicates the frequency (Frequency), and the unit is GHz (gih); the ordinate indicates the isolation (Isolation), and the unit is dB. The curve C1 represents the relationship between the isolation and the frequency between the two inductors in the existing chip without the isolation structure. The m1 point of the curve C1 represents the isolation between the two inductors at a frequency of 10 GHz of 59.68 dB. The curve C2 represents the relationship between the isolation and the frequency between the two inductors (22, 23) disposed on both sides of the closed loop 10 in the chip 100 of the present application, and the m2 point of the curve C2 represents a frequency of 10 GHz. The isolation between the two inductors (22, 23) is 70.53 dB. From the comparison of the m2 value and the m1 value (the numerical difference is large), the comparison of the curve C2 and the curve C1 (the curve is clearly separated and the spacing is large), the present application is provided on both sides of the closed loop 10 The isolation between the two inductors (22, 23) is significantly higher than the isolation between the two inductors without the isolation structure.

As shown in FIG. 5, FIG. 5 is a graph showing the relationship between the inductance and the frequency of a possible chip and an existing chip based on the solution of the present application. In FIG. 5, the abscissa indicates the frequency (Frequency), and the unit is GHz (gih); the ordinate indicates the inductance (Inductance), and the unit is nH (nahen). The curve D1 represents the relationship between the inductance and the frequency of the two inductors in the existing chip in which the isolation structure is not provided. In the curve D1, the m1 point represents a frequency of 10 GHz, and the inductance of the two inductors is 0.1882 nH. The curve D2 represents the relationship between the inductance and the frequency of the two inductors (22, 23) disposed on both sides of the closed loop 10 in the chip 100 of the present application, and the m2 point in the curve D2 represents a frequency of 10 GHz. The inductance of the two inductors (22, 23) is 0.1875 nH. From the comparison of the m2 value and the m1 value (the numerical value is similar), the comparison of the curve D2 and the curve D1 (the curves are almost overlapped), it is known that the present application sets the two inductances on both sides of the closed loop 10 (22, The inductance of 23) is not much different from the inductance of the two inductors in which the isolation structure is not provided, and the closed loop 10 described in the present application has almost no influence on the inductance.

As shown in FIG. 6, FIG. 6 is a graph showing the relationship between the Q value and the frequency of a possible chip 100 and a conventional chip obtained based on the solution of the present application. In FIG. 6, the abscissa indicates the frequency (Frequency), and the unit is GHz (gih); the ordinate indicates the Q value (Q factor). The curve E1 represents the relationship between the inductance and the frequency of the two inductors in the existing chip without the isolation structure. When the m1 point in the curve E1 represents the frequency of 10 GHz, the Q value of the two inductors is 28.28. The curve E2 represents the relationship between the inductance and the frequency of the two inductors (22, 23) disposed on both sides of the closed loop 10 in the chip 100 of the present application, and the m2 point in the curve E2 represents a frequency of 10 GHz. The Q of the two inductors (22, 23) is 28.15. From the comparison of the m2 value and the m1 value (the numerical value is similar), the comparison of the curve E2 and the curve E1 (the curves almost overlap), the present application sets the two inductances on both sides of the closed loop 10 (22, The Q value of 23) is not much different from the Q value of the two inductors in which the isolation structure is not provided, and the closed loop 10 described in the present application has almost no influence on the Q value.

In short, the closed loop 10 is capable of reducing the degree of coupling between the two inductors (22, 23) without reducing the inductance and Q of the two inductors (22, 23). To improve the crosstalk between the two inductors (22, 23).

Referring to FIG. 3 together, the closed loop 10 is grounded. Of course, in other embodiments, the closed loop 10 can also be suspended, that is, the closed loop 10 is not connected to other circuits.

Referring to FIG. 3 together, the two inductors (22, 23) are the first inductor 22 and the second inductor 23. It can be understood that when the first inductor 22 is an excitation coil, the second inductor 23 passively becomes a victim coil; when the second inductor 23 is an excitation coil, the first inductor 22 Passively become a victim coil. When the first inductor 22 and the second inductor 23 are both in an active state, the first inductor 22 is both an excitation coil and a victim coil that may be interfered by the second inductor 23; the second inductor 23 is both an excitation coil and a victim coil that may be interfered by the first inductance 22.

In one embodiment, the chip 100 can be used as a networking processor. At this point, the chip 100 is a microprocessor that provides for transmitting and receiving data logic (including sound and video) in a communication network. The chip 100 can be used in an Industrial Communication Device (ICD). The communication device includes, but is not limited to, a mobile phone, a tablet computer, a communication base station, and the like.

The two inductors (22, 23) can be applied to a circuit for configuring a radio frequency signal. The radio frequency signal may include, but is not limited to, a Wireless-Fidelity (Wi-Fi) signal, a Bluetooth signal, a Global Navigation Satellite System (GNSS) signal, and 2G (2-Generation wireless telephone technology, 2nd). Generation of wireless communication technology) signal, 3G (3-Generation wireless telephone technology) signal, 4G (4-Generation wireless telephone technology) signal or 5G (5-Generation wireless telephone) Technology, the fifth generation of wireless communication technology) signals. The circuit can be a tank circuit, an oscillator circuit, a resonant circuit, or any other type of circuit in which signal coupling is a concern. The first inductor 22 and the second inductor 23 can be applied to different positions in the same circuit, and can also be applied to different circuits. The signal configured by the circuit including the first inductor 22 and the signal configured by the circuit including the second inductor 23 may be the same or different, may cooperate with each other, or may be independent of each other. work.

In one embodiment, referring to FIG. 1 together, the chip 100 further includes a cover 4 . The cover 4 is disposed on a side of the bare chip 2 away from the substrate 1 . The cover 4 is covered with the substrate 1 to surround the receiving space 40. The bare chip is received in the receiving space 40. The cover 4 may be made of a metal material to achieve electromagnetic shielding. The cover 4 and the bare chip 3 are fixed by the first colloid 5 . A second colloid 6 is further disposed between the bare chip 3 and the substrate 1. The second colloid 6 is formed by an underfill method such as a "non-contact jet type" dispensing method. The second colloid 6 surrounds the solder ball set 3. The chip 100 also includes a Ball Grid Array (BGA) 7. The ball grid array 7 is formed on a side of the substrate 1 away from the bare chip.

Referring to FIG. 2 and FIG. 3 together, the bare chip 2 includes a substrate and a circuit trace layer formed on the substrate. The first inductor 22, the second inductor 23, and the first conductive portion 21 are formed in the circuit trace layer. A solder resist layer is laid on a side of the circuit trace layer toward the substrate 1. In one embodiment, the first conductive portion 21 is formed in a surface trace layer closest to the solder resist layer, and the solder resist layer is fenestrated to a portion of the first conductive portion 21, Forming a partial region of the first conductor portion 21 through the fenestration to form a pad, and the first solder ball 31 and the second solder ball 32 are connected to the corresponding pad, thereby being connected to the first conductive portion 21 connections. In another embodiment, the first conductive portion 21 is formed in an inner wiring layer away from the solder resist layer, and a pad is disposed in a surface trace layer adjacent to the solder resist layer, and the pad is The first conductor portions 21 are connected by a plurality of connection holes (with a conductive material), and the solder resist layer is disposed to be hollowed out to the area of the pads, so that the first solder balls 31 and the second solder are The ball 32 can be connected to the first conductor portion 21 by connecting corresponding pads.

The substrate 1 is a circuit board. The substrate 1 includes a laminated multilayer conductor layer. The substrate 1 is coated with an insulating protective layer on one side of the bare chip 2 . In one embodiment, the second conductive portion 11 is formed in a surface conductor layer closest to the protective layer, and the protective layer is fenestrated to a partial region of the second conductive portion 11 such that the A portion of the second conductive portion 11 is exposed through the fenestration to form a pad, and the first solder ball 31 and the second solder ball 32 are connected to the corresponding pad to be connected to the second conductive portion 11. In another embodiment, the second conductive portion 11 is formed in an inner conductor layer away from the protective layer, and a pad, a pad and the second are disposed in a surface conductor layer adjacent to the protective layer. The conductive portions 11 are connected by a plurality of through holes (with a conductive material), and the protective layer is hollowed out to the area of the pads so that the first solder balls 31 and the second solder balls 32 can be connected A corresponding pad is connected to the second conductive portion 11.

Wherein, the solder ball group 3 can be made of tin material. For example, the solder ball group 3 may employ a tin alloy including at least one of a copper element or an aluminum element.

In one embodiment, referring to FIG. 2, FIG. 3 and FIG. 11, the bare chip 2 has a connection surface 24 facing the substrate 1. The line connecting the center points of the two inductors (22, 23) is the first line 20. A line connecting the center point of the first solder ball 31 and the center point of the second solder ball 32 is a second connection line 30. As shown in FIG. 11, the orthographic projection of the first line 20 on the attachment surface 24 intersects the orthographic projection of the second line 30 on the attachment surface 24. At this time, the closed loop 10 is located in a middle area between the first inductor 22 and the second inductor 23, and the closed loop 10 can cancel more magnetic lines of force, and the isolation is higher.

Wherein, the first connection 20 can pass through the closed loop 10 to better isolate the closed loop 10.

Therein, as shown in FIGS. 3 and 11, the orthographic projection of the first wire 20 on the attachment surface 24 passes through the center of the orthographic projection of the second wire 30 on the attachment surface 24. At this time, the closed loop 10 is located in a middle area between the first inductor 22 and the second inductor 23, and the closed loop 10 has a better isolation effect.

Of course, in other embodiments, as shown in FIG. 12, the orthographic projection of the first connection 20 on the connecting surface 24 and the orthographic projection of the second connection 30 on the connecting surface 24 are not intersect. At this time, the closed loop 10 is located at a region between the first inductor 22 and the second inductor 23, and the closed loop 10 can cancel the magnetic lines of force of the magnetic lines of force and the isolation effect is poor.

In one embodiment, referring to FIG. 3 and FIG. 11 , the orthographic projection of the first connection 20 on the connecting surface 24 is perpendicular to the second connection 30 on the connecting surface 24 . Orthographic projection. At this time, the first inductor 22 and the second inductor 23 are arranged substantially symmetrically on both sides of the closed loop 10, so that the closed loop 10 can cancel more magnetic lines of force and have higher isolation. Moreover, the inductance and the Q value of the first inductor 22 and the second inductor 23 are less affected.

In one embodiment, referring to FIG. 3 and FIG. 7, the first solder ball 31 and the second solder ball 32 are arranged along the first direction X. The distance between the first solder ball 31 and the second solder ball 32 is a first length L1. The spacing between the first solder ball 31 and the second solder ball 32 is the minimum distance between the outer contour of the first solder ball 31 and the outer contour of the second solder ball 32. The two inductors (22, 23) are a first inductor 22 and a second inductor 23. The length of the first inductor 22 in the first direction X is a second length L2. The length of the second inductor 23 in the first direction X is a third length L3. The second length L2 is greater than or equal to the third length L3. The ratio of the first length L1 to the second length L2 is in the range of 0.75 to 1.25.

In this embodiment, when the ratio of the first length L1 to the second length L2 is in the range of 0.75 to 1.25, that is, the length of the closed loop 10 and the two inductors (22, 23) When the length of the long-length inductor is about the same, the closed loop 10 has a better isolation effect, and can effectively isolate the two inductors (22, 23).

In one embodiment, please refer to FIG. 3 and FIG. 7 together, the first length L1 is equal to the second length L2. At this time, the length of the closed loop 10 is equal to the length of the longer length of the two inductors (22, 23), and the closed loop 10 can better reduce the first inductance 22 The degree of coupling between the second inductor 23 and the closed loop 10 is good.

For example, the second length L2 is 0.23 mm (mm), and the first length L1 is in the range of 0.17 mm to 0.29 mm. It can be seen from experiments that at a frequency of 10 GHz, when the first length L1 is in the range of 0.17 mm to 0.23 mm, the isolation increases with the increase of the first length L1; when the first length L1 is 0.23 mm When the range is up to 0.29mm, the isolation decreases with the increase of the first length L1; when the first length L1 is in the range of 0.17mm to 0.29mm, the isolation is approximately in the range of 69 to 70.5, and the isolation value is higher. high.

It can be understood that the position of the first inductor 22 and the position of the second inductor 23 are not strictly defined in the present application, and the positions of the first inductor 22 and the second inductor 23 are mutually interchangeable. .

In one embodiment, referring to FIG. 3 and FIG. 7 , the first conductive portion 21 has a strip shape, and the extending direction of the first conductive portion 21 is consistent with the first direction X. At this time, the first conductive portion 21 may be a metal trace formed in the bare chip 2 . Since the extending direction of the first conductive portion 21 is consistent with the first direction X, the length of the first conductive portion 21 is short, and the resistance of the first conductive portion 21 is small, which is advantageous for improving the closed loop. The sensitivity of the road 10 makes the isolation of the closed loop 10 better.

In one embodiment, referring to FIG. 3 and FIG. 7, the first solder ball 31 has a first width W1 in the second direction Y, and the second direction Y is parallel to the bare chip 2 and vertical. In the first direction X. The largest dimension of the outer contour of the first solder ball 31 in the second direction Y is the first width W1. When the first solder ball 31 is substantially spherical, the first width W1 is the diameter of the first solder ball 31. The width of the second solder ball 32 in the second direction Y is equal to the first width W1. The first conductive portion 21 has a second width W2 in the second direction Y. The ratio of the second width W2 to the first width W1 is greater than or equal to 0.75. The outer contour of the first solder ball 31 is the same as or very similar to the outer contour of the second solder ball 32. The second solder ball 32 is also considered to be in the second when the width of the second solder ball 32 in the second direction Y is slightly different from the first width W1 due to an error in manufacturing process. The width in the direction Y is equal to the first width W1.

In this embodiment, when the ratio of the second width W2 to the first width W1 is greater than or equal to 0.75, that is, the width of the first conductive portion 21 and the width of the first solder ball 31, When the width of the second solder ball 32 is similar, the closed loop 10 has a better isolation effect, and can effectively isolate the two inductors (22, 23).

In one embodiment, please refer to FIG. 3 and FIG. 7 together, the second width W2 is equal to the first width W1. At this time, the width of the first conductive portion 21 is the same as the width of the first solder ball 31 and the width of the second solder ball 32, which can save the material of the first conductive portion 21, and the The closed loop 10 can also well reduce the degree of coupling between the first inductor 22 and the second inductor 23, and the closed loop 10 has a good isolation effect.

For example, the first width W1 of the first solder ball 31 is 80 um, and the second width W2 is 60 um or more. It can be seen from experiments that when the frequency is 10 GHz, when the second width W2 is greater than or equal to 60 um, the isolation is greater than or equal to 70.1; as the second width W2 increases, the isolation can be increased from 70.1 to 70.5, and the isolation value is In the higher range; when the second width W2 is equal to 80um, the isolation is increased to 70.5; after the second width W2 is greater than 80um, the isolation is no longer changed as the second width W2 increases.

In one embodiment, the height of the first solder ball 31 and the second solder ball 32 is 85 um. The lengths of the first solder ball 31 and the second solder ball 32 are not specifically limited in the present application. The spacing between the first inductor 22 and the second inductor 23 is also not specifically defined in the present application.

In one embodiment, referring to FIG. 3 and FIG. 7 together, the second conductive portion 11 has a strip shape. The extending direction of the second conductive portion 11 coincides with the first direction X. At this time, the second conductive portion 11 may be a metal trace formed in the substrate 1. Since the extending direction of the second conductive portion 11 is consistent with the first direction X, the second conductive portion 11 has a short length, and the second conductive portion 11 has a small resistance, which is advantageous for improving the closed loop. The sensitivity of the road 10 makes the isolation of the closed loop 10 better.

Referring to FIG. 3 and FIG. 7 together, the second conductive portion 11 has a third width W3 in the second direction Y, and the third width W3 is greater than or equal to the second width W2. For example, the third width W3 is equal to the second width W2. At this time, the isolation loop 10 has a better isolation effect, and can effectively isolate the two inductors (22, 23).

Of course, in other embodiments, the second conductive portion 11 may also have other shapes, such as a square shape, a circular shape, or the like.

In one embodiment, referring to FIG. 8 together, the solder ball set 3 further includes a third solder ball 33. The third solder ball 33 is arranged in the same direction as the first solder ball 31 and the second solder ball 32 (for example, the first direction X), and the third solder ball 33 is located in the The first solder ball 31 is between the second solder ball 32. The third solder ball 33 connects the first conductive portion 21 and the second conductive portion 11 .

In the embodiment, the first solder ball 31, the second solder ball 32, and the third solder ball 33 are connected between the first conductive portion 21 and the second conductive portion 11 . Therefore, a plurality of parallel small loops are formed in the closed loop 10, so that the isolation effect of the closed loop 10 on the first inductor 22 and the second inductor 23 is better.

Of course, in other embodiments, the number of the third solder balls 33 may be plural. A plurality of the third solder balls 33 are arranged between the first solder balls 31 and the second solder balls 32. In the present application, "a plurality" means at least two.

In one embodiment, referring to FIG. 9 , the first inductor 22 includes an upper layer inductor 221 , a lower layer inductor 222 , and a plurality of conductive pillars 223 . The upper layer inductor 221 is stacked and spaced apart from the lower layer inductor 222 , and the plurality of conductive pillars 223 are connected between the upper layer inductor 221 and the lower layer inductor 222 . At this time, the first inductor 22 has a large thickness, thereby increasing the Q value of the first inductor 22.

Referring to FIG. 2 and FIG. 9 together, the upper layer inductor 221 or the lower layer inductor 222 is disposed in the same layer as the first conductive portion 21. At this time, the preparation process of the first inductor 22 and the first conductive portion 21 is integrated in the molding process of the bare chip 2, and the first conductive portion 21 can be fabricated in the first inductor 22. Synchronous molding in the process simplifies the manufacturing process of the bare chip 2 and reduces the cost of the bare chip 2.

Of course, in other embodiments, the first inductor 22 may further include other inductor layers, and the other inductor layers are connected to the upper layer inductor 221 or the lower layer inductor 222 through the conductive pillars. The first conductive portion 21 may also include multiple layers of conductive traces. The molding process of the multilayer conductive layer is integrated in the preparation process of the first inductor 22. Of course, the molding process of the first conductive portion 21 can also be independent of the preparation process of the first inductor 22.

In one embodiment, as shown in FIG. 7 , the first inductor 22 adopts a differential structure, and the first inductor 22 is bilaterally symmetric. The lower left corner and the lower right corner of the first inductor 22 are respectively input/output ports, and the middle position is a ground port (can be grounded as needed or suspended).

In one embodiment, please refer to FIG. 2 and FIG. 9 together, and the second inductor 23 adopts the same or similar structure as the first inductor 22. In other words, the second inductor 23 also includes a plurality of layers of inductance, and the multilayer inductors are electrically connected through the conductive columns. The second inductor 23 is disposed in the same layer as the first inductor 22, so that the second inductor 23 and the first inductor 22 are formed in the same process, and the cost of the bare chip 2 is reduced. Of course, in other embodiments, the second inductor 23 and the first inductor 22 may also be arranged in different routing layers.

It can be understood that, due to the overall thickness of the circuit trace layer of the bare chip 2 (the dimension in the thickness direction Z, the thickness direction Z is as shown in FIGS. 2 and 3, the thickness direction Z is perpendicular to the first direction X and the second direction Y) are very thin (micron level), when the first inductance 22 and the second inductance 23 are located on both sides of the closed loop 10, the closed loop 10 The first inductor 22 and the second inductor 23 in any of the trace layers can be well insulated. Therefore, the first conductive layer 21 and the first inductor 22 are not strictly defined in the present application. The second inductor 23 is arranged in a positional relationship between the trace layers, and the trace layers in which the three are located may be arranged in the same layer or in different layers.

Referring to FIG. 10 together, the embodiment of the present application further provides a communication device 200. The communication device 200 includes a housing 300, a circuit board 400, and a chip 100. The chip 100 employs the chip described in the above embodiments. The circuit board 400 is housed inside the housing 300. The chip 100 is fixed to the circuit board 400 and electrically connected to the circuit board 400. Since the chip 100 can improve the crosstalk problem between adjacent inductors, the chip 100 can process and transmit signals with higher quality, and thus the performance of the communication device 200 to which the chip 100 is applied is better. The communication device 200 includes, but is not limited to, a mobile phone, a tablet, a communication base station, and the like.

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

A chip, comprising: a substrate, a bare chip, and a solder ball group soldered between the substrate and the bare chip, the solder ball group comprising a first solder ball and a second solder ball arranged at intervals a first conductive portion connecting the first solder ball and the second solder ball is disposed on the bare chip, and the substrate is provided with a first electrode connecting the first solder ball and the second solder ball a second conductive portion, the first solder ball, the first conductive portion, the second solder ball, and the second conductive portion form a closed loop, and the bare chip further includes two inductors, the two The inductance is distributed on both sides of the closed loop.
The chip according to claim 1, wherein the bare chip has a connection surface facing the substrate, and a line connecting the center points of the two inductors is a first connection, the first solder ball a line connecting the center point to a center point of the second solder ball is a second line, an orthographic projection of the first line on the connecting surface and the second line on the connecting surface The orthographic projections intersect.
The chip of claim 2 wherein an orthographic projection of said first line on said connecting surface is perpendicular to an orthographic projection of said second line on said connecting surface.
The chip according to any one of claims 1 to 3, wherein the first solder ball and the second solder ball are arranged in a first direction, the first solder ball and the second solder The distance between the balls is a first length, the two inductors are a first inductor and a second inductor, the length of the first inductor in the first direction is a second length, and the second inductor is in the The length of the first direction is a third length, the second length is greater than or equal to the third length, and a ratio of the first length to the second length is in a range of 0.75 to 1.25.
The chip of claim 4 wherein said first length is equal to said second length.
The chip according to claim 4, wherein the first conductive portion has a strip shape, and the extending direction of the first conductive portion coincides with the first direction.
The chip according to claim 6, wherein said first solder ball has a first width in a second direction, said second direction being parallel to said bare chip and perpendicular to said first direction The width of the second solder ball in the second direction is equal to the first width, the first conductive portion has a second width in the second direction, and the second width is different from the first width The ratio is greater than or equal to 0.75.
The chip of claim 7 wherein said second width is equal to said first width.
The chip according to claim 7 or 8, wherein the second conductive portion has a strip shape, the extending direction of the second conductive portion is consistent with the first direction, and the second conductive portion is The second direction has a third width, and the third width is greater than or equal to the second width.
The chip according to claim 4, wherein the solder ball set further comprises a third solder ball, the third solder ball being arranged in the same direction as the first solder ball and the second solder ball And the third solder ball is located between the first solder ball and the second solder ball, and the third solder ball connects the first conductive portion and the second conductive portion.
The chip according to any one of claims 1 to 10, wherein the first inductor comprises an upper layer inductor, a lower layer inductor and a plurality of conductive pillars, and the upper layer inductor is stacked and spaced apart from the lower layer inductor. The plurality of conductive pillars are connected between the upper layer inductor and the lower layer inductor, and the upper layer inductor or the lower layer inductor is disposed in the same layer as the first conductive portion.
A communication device, comprising: a housing, a circuit board, and the chip according to any one of claims 1 to 11, wherein the circuit board is housed inside the housing, and the chip is fixed to the circuit The board is electrically connected to the circuit board.