CN1938850A - Optimized power delivery to high speed, high pin-count devices - Google Patents
Optimized power delivery to high speed, high pin-count devices Download PDFInfo
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- CN1938850A CN1938850A CN 200580009948 CN200580009948A CN1938850A CN 1938850 A CN1938850 A CN 1938850A CN 200580009948 CN200580009948 CN 200580009948 CN 200580009948 A CN200580009948 A CN 200580009948A CN 1938850 A CN1938850 A CN 1938850A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
A high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and the lower substrate surfaces, the substrate further having an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via; an array of solder balls attached to the lower substrate surface, the array of solder balls including a plurality of ground solder balls disposed at the periphery and electrically connected to the substrate ground via.
Description
The right that No. the 60/547th, 756, the U.S. Provisional Patent Application case of the application's case opinion application on February 24th, 2004.
Technical field
The application's case is usually directed to high-speed integrated circuit (IC) apparatus, and more specifically, relates to a kind of method and system that optimization is counted semiconductor device to high-speed, high pin that are used for.
Background technology
In recent years, wireless telecommunication system quantitatively reaches on the complexity and all is improved.This complexity has forced wireless telecommunication system, and especially the utilization of hand held wireless device has the multiple field substrate of the component package density of increase.The use of multiple field substrate makes people can arrange segmented electric power and ground plane on the inner foundation layer.These configurations can for example cause long path between a high speed device and a corresponding decoupling capacitance device.Therefore, when using high speed device on the multiple field substrate with the electric power that is designed to a plurality of segmenteds zone and ground plane, the electromagnetic interference (EMI) problem may appear.
Can use extremely short electric current burst operation such as high speed device such as microprocessors.Under height running speed, signal propagation delays, the conversion noise that between bonding wire, causes because of mutual inductance and self-induction and crosstalk and can cause signal to be lowered one's standard or status.Described mutual inductance may be due on (for example) substrate the signal code in the described bonding wire between the chip and trace and produces reciprocation between magnetic field, and described self-induction may be due to the reciprocation in the opposed magnetic field that is produced by the antiparallel electric current.Along with continuing to increase to the input of chip and the quantity of output, outside connection becomes more and more and becomes increasingly complex, and in some cases, can cause the bonding wire lead-in wire and the conductivity substrate trace of non-desired length.Therefore, faster and signal frequency continuous increase has caused the signal propagation effect of non-expectation because of the inductance of package lead or trace.
As seen, people need a kind of configurable in order to holding and to overcome the defective relevant with inductance, EMI problem, and the semiconductor packages of problem with grounding substantially, so as can one relatively simply and the cost-efficient mode of tool realize encapsulating whole advantages of the favourable aspect of notion.
Summary of the invention
In an embodiment, the semiconductor device comprises: a substrate, it has a upper substrate surface, a bottom substrate surface, an and periphery that defines described top and lower substrate surface, described upper substrate surface further has at least one substrate top ground connection trace, with provide via at least one substrate grounding through hole one to the described lower substrate surface the power path of at least one substrate bottom ground connection trace; One solder ball array, it is attached to described lower substrate surface, and comprises a plurality of ground connection solder ball that are arranged on described periphery place and are electrically connected at least one substrate grounding through hole.
In another embodiment, one high-speed semiconductor device comprises: a substrate, and it has a upper substrate surface, a bottom substrate surface, one provides a upper substrate ground connection trace to the power path on described lower substrate surface, and one can provide a upper substrate power traces to the power path on described lower substrate surface via a substrate electric power through hole via a substrate grounding through hole; One system printed circuit board, it comprises that a power supply conductivity path and has the upper board surface of a ground plane; One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises a plurality of ground connection solder ball and a plurality of electric power solder ball that are electrically connected to described ground plane, each all relative one adjacent ground connection solder ball in the described electric power solder ball is provided with, and is right to form one electric power/ground connection solder ball; An and chip that is mounted to described upper substrate surface.
In an embodiment again, the semiconductor device comprises: a substrate, it has a upper substrate surface, a bottom substrate surface, an and periphery that defines described upper substrate surface and lower substrate surface, described substrate further have one via a substrate grounding through hole provide one to the described lower substrate surface the power path of a bottom substrate ground connection trace upper substrate ground connection trace and one via a substrate electric power through hole provide one to the described lower substrate surface the upper substrate power traces of the power path of a bottom substrate power traces; One system printed circuit board, it comprises a upper board surface with a ground plane, and the power plane that is provided with of a contiguous described ground plane, described upper board surface comprises that one is electrically connected to the plate earthing trace of described ground plane, and described power ground plane further comprises the plate power trace that a described relatively plate earthing trace is provided with; One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises in a plurality of outermost skiddings in the periphery place that is arranged on described substrate and is attached to a plurality of ground connection solder ball of described ground plane, described solder ball array further comprises a plurality of electric power solder ball and is electrically connected to described power plane, described a plurality of electric power solder ball is arranged in a plurality of adjacent outer row, and each outermost skidding is arranged between a described periphery and the corresponding adjacent outer row; One is mounted to the chip of described upper face; One is connected to the bonding wire of described upper substrate ground connection trace with described chip; Reaching one is arranged on the described upper board surface and the electric decoupling capacitance device that is attached to described substrate ground connection trace.
In a further embodiment, a uncoupling branch that supplies to be attached to a high-speed chip comprises: a decoupling capacitance device; One is electrically connected to first conductive path of described decoupling capacitance device with a chip earth terminal, and described first conductive path comprises a ground connection bonding wire, a substrate top ground connection trace, a substrate grounding through hole, a substrate bottom ground connection trace, a ground connection solder ball, an and plate earthing trace; And one be electrically connected to second conductive path of described decoupling capacitance device with a chip power terminal, and described second conductive path comprises a plate power trace, an electric power solder ball, a substrate bottom power traces, a substrate electric power through hole, a substrate top power traces and an electric power bonding wire.
Among the further embodiment of Yu Zaiyi, the semiconductor device comprises: a substrate, it has a upper substrate surface, a bottom substrate surface, an and periphery that defines described top and lower substrate surface, described upper substrate surface further have at least one substrate top power traces with provide via at least one substrate electric power through hole one to the described lower substrate surface the substrate of the power path of at least one substrate bottom power traces; One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises in the outermost skidding that is arranged on described array and is electrically connected to a plurality of electric power solder ball of at least one substrate electric power through hole that described solder ball array further comprises in the adjacent outer row that is arranged on described array and is electrically connected to a plurality of ground connection solder ball of a substrate grounding through hole in the described substrate; One system printed circuit board, it comprises a upper board surface, described upper board surface has at least one a power plane that is electrically connected in described a plurality of electric power solder ball; An and chip that is mounted to described upper substrate surface.
In another embodiment, one has a wireless communication apparatus high-speed, that high pin is counted semiconductor device comprises: a decoupling capacitance device, can be electrically connected to semiconductor device earth terminal first conductive path of described decoupling capacitance device, described first conductive path comprises a ground connection bonding wire, a substrate top ground connection trace, a substrate grounding through hole, a substrate bottom ground connection trace, a ground connection solder ball, and a plate earthing trace, wherein said plate earthing trace has about one a millimeter length; And one be electrically connected to second conductive path of described decoupling capacitance device with semiconductor device power terminal, described second conductive path comprises a plate power trace, an electric power solder ball, a substrate bottom power traces, a substrate electric power through hole, a substrate top power traces, and an electric power bonding wire.
In a further embodiment, the semiconductor device comprises: the solder ball array apparatus, and it is used for a substrate is attached to a system printed circuit board with a ground plane and a power trace, and described solder ball array apparatus is arranged in the substrate perimeter; The uncoupling member, it is connected between described ground plane and the described power trace; Reach electric power/ground connection solder ball to device, it is arranged on described substrate perimeter and sentences for described substrate electricity is attached to described uncoupling member.
In another further embodiment, disclose a kind of method that is used to the semiconductor device power supply, described semiconductor device has one and is attached to the substrate of a upper face of a system printed circuit board with a solder ball array, said method comprising the steps of: (1) utilizes a solder ball that is arranged on the periphery place of a substrate to reduce the path of an electric power signal as a ground connection solder ball, with the minimum signal parasitics; And (2) to utilize the solder ball of a contiguous described ground connection solder ball to be used for the electric power/ground connection solder ball of described electric power signal right, to minimize electromagnetic emission.
In an embodiment again, a kind of method with semiconductor device power supply of a ball grid matrix that is used to comprises: (1) one utilize one be arranged on a substrate the periphery place solder ball as a ground connection solder ball reduce the path of an electric power signal, with the step of minimum signal parasitics; And (2) one utilize the solder ball of a contiguous described ground connection solder ball form an electric power/ground connection solder ball that is used for described electric power signal to, to minimize step from the electromagnetic emission of described electric power signal.
With reference to hereinafter graphic, explanation and claim, with easier understanding these and other feature of the present invention, aspect and advantage.
Description of drawings
Fig. 1 one is installed in the partial sectional view of the chip on the substrate according to an embodiment one, and wherein said substrate is to be connected to a system printed circuit board by a solder ball array;
Fig. 2 is a plane graph according to the solder ball array on the embodiment substrate lower surface shown in Figure 1;
Fig. 3 is the schematic isometric drawing that the interconnection configuration of semiconductor device constitutes, and wherein said semiconductor device comprises that chip bonding wire, top and lower substrate conductive trace, are positioned at the plate power traces of power plane, reach a plate earthing trace that is positioned at the ground plane of system shown in Figure 1 printed circuit board (PCB);
Fig. 4 one is used for the plane graph of alternative solder ball array of the lower surface of substrate shown in Figure 1;
Fig. 5 is the schematic isometric drawing that the alternative interconnection configuration of semiconductor device constitutes, and wherein said semiconductor device comprises chip bonding wire, top and lower substrate conductive trace, a plate earthing trace, reaches a plate power traces; And
Fig. 6 is a flow chart, and its graphic extension can be according to a kind of method that electric power and ground connection connection are provided for semiconductor device shown in Figure 3 of embodiment regulation.
Embodiment
Below describing in detail is the current optimal mode of containing that is used to implement the embodiment of the invention.Because scope of the present invention is defined by claims the best of enclosing, therefore, this explanation should not be considered as having limiting meaning, and only is used for the purpose of the General Principle of the graphic extension embodiment of the invention.
Put it briefly, a kind of high speed device is provided, it has the signal path of low inductance characteristic, and compared with prior art, described characteristic tolerable higher frequency signal and electric power transmit and has an electromagnetic emission of minimum voltage drop and minimizing.Described embodiment can comprise electric power/ground connection pin of being positioned at described device periphery place to so that voltage drop minimize.Comparatively speaking, traditional high speed device then may provide the electric power pin so that outside pin is used for signal near described device center or center.
With comparing than long through-hole seen in the conventional substrate, described embodiment can comprise further that one has the substrate of through hole of a minimum length to minimize voltage drop.Compare with traditional multiple field substrate, can comprise that also one has the substrate of near be positioned at the substrate surface electric power and ground plane to reduce electromagnetic emission with internal power and ground plane.One example of electronic installation that can benefit from the application of described embodiment is such as hand held wireless communication apparatus such as mobile phones.Yet, should be appreciated that the application of the embodiment that discloses is not limited in communication device.
Generally speaking, if reduce the interior parasitics of the used power-supply system of high-speed semiconductor device, can improve the performance of described power-supply system.Printed circuit board (PCB) during tradition is used can provide electric power continuous, that be subjected to good control and ground plane to reduce this type of parasitics.Yet,, therefore electric power and ground plane design must be become multiple segmented zone because mobile electronic system need use highdensity printed circuit board (PCB) usually.This type of configuration can hinder the minimized target of path that realizes making between encapsulation pin and the decoupling capacitance device.
Reduce the EMI except that a upper circuit flaggy is defined as a ground plane, described embodiment also can use circuit board routing resource to reduce parasitics, but not only relies on the configuration of electric power and ground plane.For example, can use minimum wire length or flip-chip to connect and design Electronic Packaging, realize the routing of best pin layout and printed circuit board (PCB) simultaneously to coupling capacitor so that package inductance minimizes.In addition, can electric power-ground connection solder ball be set by the periphery place in Electronic Packaging to minimizing loop inductance.Thus, can be with described electric power-ground connection solder ball to being connected to corresponding electric power and the earth lead that is electrically connected to local decoupling capacitance device on the adjacent upper layer printed circuit board.By with ground connection and electric power solder ball to being connected to the adjacent printed circuit boards layer, can reduce mutual inductance, and, can minimize through hole length by the connection that is connected to the upper print board layer is provided.
One embodiment is configurable in a microprocessor package, for example is disposed in BGA, the PGA or chip size packages (CSP) who is applicable in the hand held wireless communication apparatus for example.Use BGA or PGA encapsulation can make a complicated integrated circuit be positioned on the system board of wireless communication apparatus a relatively little area.CSP can provide the more dingus that a pin count is less than BGA or PGA encapsulation, but can utilize an electric power/ground connection pin as mentioned below to configuration.For high-speed application, the BGA configuration can provide one to dispose the encapsulation with lower inductance such as lead type such as PGA.
With reference to Fig. 1,2 and 3, according to an embodiment, semiconductor device 10 can comprise that one is mounted to the upper substrate surface 12 of a substrate 13 and is encapsulated in chip 11 in the Chip Packaging 15.Described semiconductor device 10 can further comprise a system printed circuit board 20, described system printed circuit board 20 has plate earthing trace 21, a power supply conductivity path that is positioned at 23 places, upper board surface, a plate power trace 25 that is positioned at the one deck below the plate earthing trace 21 for example reaches a dielectric layer 27 between plate earthing trace 21 and plate power trace 25.Another is chosen as, and described plate earthing trace 21 can constitute the part on the plate earthing plane 63 on part or all upper board surface 23 of covering.
Can provide one or more from chip 11 to substrate the ground connection bonding wire 31 of the upper substrate ground connection trace 33 on 13.Can between the ground connection trace 33 and the substrate bottom ground connection trace 37 on the bottom substrate surface 14 of upper substrate, provide a substrate grounding through hole 35, to be electrically connected to plate earthing trace 21 by a ground connection solder ball 39.Similarly, can provide one or more from chip 11 to substrate the electric power bonding wire 41 of the substrate top power traces 43 on 13.Can between a substrate top power traces 43 and a substrate bottom power traces 47, provide a substrate electric power through hole 45, to be electrically connected to plate power trace 25 by an electric power solder ball 49 and a plate electric power through hole 29.
Described semiconductor device 10 can comprise further that one is positioned at the decoupling capacitance device 51 on the upper board surface 23.One end of decoupling capacitance device 51 can be connected directly to plate earthing trace 21 as shown in the figure, and the other end of decoupling capacitance device 51 can be connected to plate power trace 25 by one second plate electric power through hole 53.Ground connection solder ball 39 can be positioned at peripheral 19 places of substrate 13.Described peripheral 19 define upper substrate surface 12 and lower substrate surface 14.This can allow decoupling capacitance device 51 is arranged in ground connection solder ball 39 1 distances " D ", and its middle distance " D " can reach 1 millimeter for a short time.
In shown in configuration in, one substantially by plate earthing trace 21, plate power trace 25, plate electric power through hole 29, and the area of section (being called " A ") that defines of the second plate electric power through hole 53 can be less than the respective cross-sectional areas seen in the traditional design.Therefore, more elaborate as mentioned, can be by the EMI that electric current produced in the plate power trace 25 (for example separating) less than the EMI that electric current produced in the conventional power source trace by configuration institute example shown in Figure 1.
Solder ball configuration shown in Figure 2 can be used for semiconductor device 10.One solder ball array 55 can be attached to the lower substrate surface 14 of substrate 13.Array 55 can comprise a plurality of electric power solder ball 49 (promptly, be decorated with the circle of the crossing shade of parallel lines), each electric power solder ball 49 is all via corresponding one group of substrate bottom power traces 47, substrate electric power through hole 45, and substrate top power traces 43, be electrically connected to a corresponding electric power bonding wire 41 (referring to Fig. 1).Array 55 can comprise a plurality of ground connection solder ball 39 (promptly, solid circles), each ground connection solder ball 39 is all via corresponding one group of substrate bottom ground connection trace 37, substrate grounding through hole 35, and substrate top ground connection trace 33, is electrically connected to a corresponding ground connection bonding wire 31 (referring to Fig. 1).Ground connection solder ball 39 can be positioned at periphery 19 places of substrate 13.In shown in the configuration in, ground connection solder ball 39 is positioned at one or more outermost skidding 57a, 57b, 57c and 57d.
In addition, each electric power solder ball 49 all can be matched with an adjacent ground connection solder ball 39, to reduce the electromagnetic emission from a conduct power signal.For example, a ground connection solder ball 39a and an electric power solder ball 49a can be connected to same power supply (not shown).Correspondingly, ground connection solder ball 39a is positioned at the then close ground connection solder ball 39a of the peripheral 19 electric power solder ball 49a of place location to form one electric power/ground connection solder ball to 50 (representing with a frame of broken lines).When an electric power signal flows out (or inflow) via ground connection solder ball 39a inflow (or outflow) and via electric power solder ball 49a, can make 50 electromagnetic emission being minimized of being produced because of the entity proximity of ground connection solder ball 39a and electric power solder ball 49a from electric power/ground connection solder ball.Correspondingly, in shown in the configuration in, described electric power solder ball 49 is positioned in one or more adjacent outer row 59a, 59b, 59c and the 59d.Plurality of solder balls 61 (that is empty circles) can be electrically connected use for signal and other.
It will be understood by one of ordinary skill in the art that, though the pin on the conventional substrate periphery can remain for high-speed signal path usually in advance, but can be with 100MHz or following signal routing to inboard pin, for example signal ball 61, and this can not cause timing problems because of signal path lengths increases.
As shown in Figure 3, a uncoupling branch 40 can comprise first a conductive path 40a from chip earth terminal 16 to decoupling capacitance device 51, and second a conductive path 40b from decoupling capacitance device 51 to chip power terminal 17.The described first conductive path 40a can comprise ground connection bonding wire 31, substrate top ground connection trace 33, substrate grounding through hole 35, substrate bottom ground connection trace 37, ground connection solder ball 39, reach plate earthing trace 21.The length of plate earthing trace 21 is approximately 1 millimeter.The described second conductive path 40b can comprise plate power trace 25, electric power solder ball 49, substrate bottom power traces 47, substrate electric power through hole 45, substrate top power traces 43, reach electric power bonding wire 41.As described shown in the legend, the width of plate earthing trace 21, shape and position basically with the width of plate power trace 25, shape, and position consistency, and provide isolation by dielectric layer 27.
Configuration shown in Fig. 1 and 3 can further provide electromagnetic shielding in the following manner: the ground plane 63 at 23 places, upper board surface as an external ground, and is provided with one and realizes the coupling routing of electric power signal such as power supply conductivity paths such as power plane 65 at next internal layer place.In addition, connect a ground connection solder ball 39 that for example is positioned at one or more outermost skidding 57a, 57b, 57c and 57d by the outer row pin being used for ground connection, can make one to be minimized than conventional arrangement such as the physical distance between the corresponding ground connection solder ball 39 such as decoupling capacitance device 51 devices such as decoupling capacitance such as grade with one at periphery 19 places of substrate 13.
As be appreciated by one of skill in the art that, high-speed signal is that thereby routing can produce EMI on the substrate surface of printed circuit board (PCB), thereby needs a metal can or metal plastic shielding reaching shielding on chip and the substrate on adjacent high-speed circuits (if having) usually.As disclosed herein, by making electric power and ground connection be positioned at the surface and make plate earthing trace 21 and plate power trace 25 opposite disposed (that is, crossover and isolate) by dielectric layer 27, meeting " built-in " electromagnetic shielding, thus reduction is to the needs of exterior shield.In a conventional arrangement, can come electrical power distribution by internal power plane.When using this type of configuration, a chip with a plurality of electric power rail that are used for power collapse may need one to reach 18 layers system board.On a plate superficial layer or plate superficial layer place (for example in the embodiment shown) provide electric power can reduce needs to the electric power through hole, and also can eliminate needs to power plane.This can make the plate routing easier and can realize the minimizing of the substrate number of plies, thereby saves cost.
In addition, by reducing the described parasitics that discloses among the embodiment, the feasible performance that is improved to the power supply of semiconductor device 10 power supplies becomes possibility.For example, can reduce or minimize loop inductance to 50 by one or more electric power-ground connection solder ball that use is arranged on periphery 19 places of semiconductor device 10.Electric power solder ball 49 and ground connection solder ball 39 can preferably be connected to respective plate power trace 25 and the plate earthing trace 21 that causes local decoupling capacitance device 51 on the adjacent upper layer on the system printed circuit board 20.As be appreciated by one of skill in the art that, use the effect of adjacent layer to provide mutual inductance in this way, and upper layer is used for the length that ground connection and electric power can minimize ground connection and electric power through hole.In addition, by a top flaggy is designated as a ground plane, can further reduce EMI.
In an alternate embodiment, solder ball configuration shown in Figure 4 can be used jointly with semiconductor device 10.One solder ball array 70 can be attached to the lower substrate surface 14 of substrate 13.Array 70 comprises a plurality of ground connection solder ball 71 (promptly, solid circles), each ground connection solder ball 71 all can via corresponding one group of substrate bottom ground connection trace 37, substrate grounding through hole 35, and substrate top ground connection trace 33 be electrically connected to a corresponding ground connection bonding wire 31 (referring to Fig. 1).Array 70 can comprise a plurality of electric power solder ball 73 (promptly, be decorated with the circle of section line), each electric power solder ball 73 all via corresponding one group of substrate bottom power traces 47, substrate electric power through hole 45, and substrate top power traces 43 be electrically connected to a corresponding electric power bonding wire 41 (referring to Fig. 1).
Electric power solder ball 73 can be positioned at periphery 19 places of substrate 13.In shown in the configuration, electric power solder ball 73 can be positioned at one or more outermost skiddings, for example in the outermost skidding 79a, and ground connection solder ball 71 can be positioned at one or more adjacent outer row, in for example adjacent outer row 79b.Each electric power solder ball 73 all can be matched with an adjacent ground connection solder ball 71, forms one electric power/ground connection solder ball to 77 (representing with a frame of broken lines).
In another alternate embodiment, as shown in Figure 5, a uncoupling branch 80 can comprise the first conductive path 80a, and second a conductive path 80b from decoupling capacitance device 51 to one chip power terminal (not shown)s from a chip earth terminal (not shown) to decoupling capacitance device 51.The described first conductive path 80a can comprise a ground connection bonding wire 81, a substrate top ground connection trace 83, a substrate grounding through hole 85, a substrate bottom ground connection trace 87, ground connection solder ball 71, reach a plate earthing trace 89.The described second conductive path 80b can comprise a plate power trace 99, electric power solder ball 73, a substrate bottom power traces 97, a substrate electric power through hole 95, a substrate top power traces 93, reach an electric power bonding wire 91.Decoupling capacitance device 51 can be electrically connected to plate earthing trace 89 and plate power trace 99.As shown in Figure 4, electric power solder ball 73 can be positioned at periphery 19 places of substrate 13.
Flow process Figure 100 among Fig. 6 shows a kind of method that is used to semiconductor device power supply, and wherein said semiconductor device has one and is attached to the substrate of the upper face of a system printed circuit board by a solder ball array.In step 101, a ground connection solder ball (for example the ground connection solder ball 39) can be arranged in the peripheral solder ball array of locating of substrate (for example substrate 13).In step 103, can in solder ball array (for example the solder ball array 55), be close to described ground connection solder ball one electric power solder ball (for example the electric power solder ball 49) is set, to form one electric power/ground connection solder ball to (for example electric power/ground connection solder ball is to 50).In step 105, a ground plane (for example ground plane 63) can be arranged in the upper face of described system printed circuit board.In step 107, described ground connection solder ball can be attached to described ground plane.In step 109, a power trace (for example the plate power trace 25) can be arranged at the upper face below of described system printed circuit board.In step 111, a dielectric layer (for example dielectric layer 27) can be arranged between described power trace and the described ground plane.In step 113, described electric power solder ball can be attached to described power trace.In step 115, can be close to described ground connection solder ball one decoupling capacitance device (for example the decoupling capacitance device 51) is set, and can be in step 117, described decoupling capacitance device is positioned at apart from described ground connection solder ball locates less than five millimeters and preferable being positioned in one millimeter of described ground connection solder ball.In a conventional arrangement, the distance between described ground connection solder ball and the described decoupling capacitance device can be five millimeters or bigger.As be appreciated by one of skill in the art that said method also is used to voltage drop be minimized and also reduce electromagnetic emission.
Certainly, should be appreciated that above explanation relates to each exemplary embodiment and can modify, this does not deviate from hereinafter spirit and the scope of the described embodiment of claim.
Claims (32)
1, a kind of semiconductor device, it comprises:
One substrate, it has a upper substrate surface, a bottom substrate surface, an and periphery that defines described top and lower substrate surface, described upper substrate surface further has at least one substrate top ground connection trace, described at least one substrate top ground connection trace via at least one substrate grounding through hole provide one to the described lower substrate surface the power path of at least one substrate bottom ground connection trace;
One is attached to the solder ball array on described lower substrate surface, and described solder ball array comprises a plurality of ground connection solder ball that are arranged on described periphery place and are electrically connected to described at least one substrate grounding through hole.
2, semiconductor device as claimed in claim 1, wherein said solder ball array further comprises an electric power solder ball, described electric power solder ball be arranged to contiguous described a plurality of ground connection solder ball one of them and be electrically connected to a substrate electric power through hole in the described substrate.
3, semiconductor device as claimed in claim 1, it further comprises:
One system printed circuit board, it comprises that one has a upper board surface that is electrically connected to the ground plane of described a plurality of ground connection solder ball;
One is mounted to the chip on described upper substrate surface; And
One is electrically connected to the bonding wire of described substrate top ground connection trace with described chip.
4, semiconductor device as claimed in claim 3, it further comprises the power supply conductivity path of being arranged to contiguous described ground plane.
5, semiconductor device as claimed in claim 4, wherein said system printed circuit board further comprise a dielectric layer between described power supply conductivity path and described ground plane.
6, semiconductor device as claimed in claim 1, wherein said a plurality of ground connection solder ball are arranged at least one outermost skidding in the described solder ball array.
7, semiconductor device as claimed in claim 6, it further comprises a plurality of electric power solder ball that are arranged at least one adjacent outer row in the described solder ball array, and described at least one outermost skidding is arranged between described at least one adjacent outer row and the described periphery.
8, semiconductor device as claimed in claim 6, it further comprises a plurality of electric power solder ball, each described electric power solder ball all is arranged to the corresponding ground connection solder ball in contiguous described a plurality of ground connection solder ball, and is right to form one electric power/ground connection solder ball.
9, semiconductor device as claimed in claim 3, wherein said system printed circuit board comprise at least one decoupling capacitance device.
10, semiconductor device as claimed in claim 9, wherein said at least one decoupling capacitance device is electrically connected to described ground plane.
11, a kind of semiconductor device, it comprises:
One substrate, it has a upper substrate surface, a bottom substrate surface, one provides a upper substrate ground connection trace to the power path on described lower substrate surface via a substrate grounding through hole, and one provides a upper substrate power traces to the power path on described lower substrate surface via a substrate electric power through hole;
One system printed circuit board, it comprises that a power supply conductivity path and has the upper board surface of a ground plane;
One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises a plurality of ground connection solder ball and a plurality of electric power solder ball that are electrically connected to described ground plane, each described a plurality of ground connection solder ball all is arranged to the corresponding electric power solder ball in contiguous described a plurality of electric power solder ball, and is right to form one electric power/ground connection solder ball; And;
One is mounted to the chip on described upper substrate surface.
12, semiconductor device as claimed in claim 11, wherein said a plurality of ground connection solder ball are arranged in the outermost skidding of described solder ball array.
13, semiconductor device as claimed in claim 11, wherein said a plurality of electric power solder ball are arranged in the adjacent outer row of described solder ball array.
14, a kind of semiconductor device, it comprises:
One substrate, it has a upper substrate surface, a bottom substrate surface, an and periphery that defines described upper substrate surface and described lower substrate surface, described substrate further has one provides a upper substrate ground connection trace to the power path of the lip-deep bottom substrate ground connection trace of described lower substrate via a substrate grounding through hole, and one provides a upper substrate power traces to the power path of the lip-deep bottom substrate power traces of described lower substrate via a substrate electric power through hole;
One system printed circuit board, it comprises that one has the upper board surface that a ground plane and is arranged to the power plane of contiguous described ground plane, described upper board surface comprises that one is electrically connected to the plate earthing trace of described ground plane, and described power ground plane further comprises a plate power trace that is oppositely arranged with described plate earthing trace;
One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises in the peripheral a plurality of outermost skiddings of locating that are arranged on described substrate and is attached to a plurality of ground connection solder ball of described ground plane, described solder ball array further comprises a plurality of electric power solder ball and is electrically connected to described power plane, described a plurality of electric power solder ball is arranged in a plurality of adjacent outer row, and each described outermost skidding all is arranged between a described periphery and the corresponding adjacent outer row;
One is mounted to the chip of described upper face;
One is connected to the bonding wire of described upper substrate ground connection trace with described chip; And
One decoupling capacitance device, it is arranged on the described upper board surface, and electricity is attached to described lower substrate ground connection trace.
15, semiconductor device as claimed in claim 14, wherein said solder ball array further comprise a plurality of electric power solder ball in the adjacent outer row that is arranged on described solder ball array.
16, semiconductor device as claimed in claim 14, wherein said decoupling capacitance device electricity is attached to described power plane.
17, a kind of uncoupling branch that is suitable for being attached to a high-speed chip, described uncoupling branch comprises:
One decoupling capacitance device;
One first conductive path, it is electrically connected to described decoupling capacitance device with a chip earth terminal, described first conductive path comprises a ground connection bonding wire, a substrate top ground connection trace, a substrate grounding through hole, a substrate bottom ground connection trace, a ground connection solder ball, and a plate earthing trace; And
One second conductive path, it is electrically connected to described decoupling capacitance device with a chip power terminal, described second conductive path comprises a plate power trace, an electric power solder ball, a substrate bottom power traces, a substrate electric power through hole, a substrate top power traces, and an electric power bonding wire.
18, uncoupling as claimed in claim 17 branch, wherein said plate earthing trace comprises about one a millimeter length.
19, uncoupling as claimed in claim 17 branch comprises that further one is arranged on the dielectric layer between described plate earthing trace and the described plate power trace.
20, a kind of semiconductor device, it comprises:
One substrate, it has a upper substrate surface, one bottom substrate surface, an and periphery that defines described top and lower substrate surface, described upper substrate surface further has at least one substrate top power traces, and described at least one substrate top power traces provides a power path to lip-deep at least one the substrate bottom power traces of described lower substrate via at least one substrate electric power through hole;
One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises in the outermost skidding that is arranged on described array and is electrically connected to a plurality of electric power solder ball of described at least one substrate electric power through hole that described solder ball array further comprises in the adjacent outer row that is arranged on described array and is electrically connected to a plurality of ground connection solder ball of a substrate grounding through hole in the described substrate;
One system printed circuit board, it comprises a upper board surface, described upper board surface has at least one a power plane that is electrically connected in described a plurality of electric power solder ball; And
One is mounted to the chip on described upper substrate surface.
21, semiconductor device as claimed in claim 20, wherein each described ground connection solder ball all is arranged to an electric power solder ball of the correspondence in contiguous described a plurality of electric power solder ball, and is right to form one ground connection/electric power solder ball.
22, a kind of have a wireless communication apparatus one high-speed, that high pin is counted semiconductor device, and described wireless communication apparatus comprises:
One decoupling capacitance device;
One first conductive path, it is electrically connected to described decoupling capacitance device with semiconductor device earth terminal, described first conductive path comprises a ground connection bonding wire, a substrate top ground connection trace, a substrate grounding through hole, a substrate bottom ground connection trace, a ground connection solder ball, and a plate earthing trace, wherein said plate earthing trace comprises about one a millimeter length; And
One second conductive path, it is electrically connected to described decoupling capacitance device with semiconductor device power terminal, described second conductive path comprises a plate power trace, an electric power solder ball, a substrate bottom power traces, a substrate electric power through hole, a substrate top power traces, and an electric power bonding wire.
23, wireless communication apparatus as claimed in claim 22, electric power/ground connection solder ball that wherein said ground connection solder ball and described electric power solder ball form an approaching described plate earthing trace is right.
24, wireless communication apparatus as claimed in claim 22 further comprises a substrate, and described substrate has a lower substrate surface by a periphery definition.
25, wireless communication apparatus as claimed in claim 24, comprise that further one is attached to the solder ball array on described lower substrate surface, described solder ball array comprises that one is arranged on the ground connection solder ball that described plate earthing trace was located and be attached to described periphery, described solder ball array further comprises the electric power solder ball of being arranged to contiguous described ground connection solder ball and being electrically connected to described power plane, and it is right that described ground connection solder ball and described electric power solder ball form one electric power/ground connection solder ball.
26, wireless communication apparatus as claimed in claim 25, wherein said plate earthing trace comprise one less than five millimeters length.
27, wireless communication apparatus as claimed in claim 24 further comprises being used for dielectric devices that described ground plane and described power trace are kept apart.
28, a kind of semiconductor device, it comprises:
The solder ball array apparatus, it is used for a substrate is attached to a system printed circuit board with a ground plane and a power trace, and described solder ball array apparatus is arranged in the substrate perimeter;
The uncoupling device, it is connected between described ground plane and the described power trace; And
Electric power/ground connection solder ball is to device, and it is arranged on described substrate perimeter place, to be used for that described substrate electricity is attached to described uncoupling device.
29, a kind of method that is used to semiconductor device power supply, described semiconductor device have one and are attached to the substrate of a upper face of a system printed circuit board by a solder ball array, and described method comprises the steps:
By utilizing a solder ball that is arranged on a periphery place of a substrate to reduce the path of an electric power signal, so that the signal parasitics minimizes as a ground connection solder ball; And
By the solder ball of utilizing a contiguous described ground connection solder ball be used for described electric power signal electric power/the ground connection solder ball is right so that electromagnetic emission minimizes.
30, method as claimed in claim 29, further comprising the steps: increases the electromagnetism shade by in the described upper face of described system printed circuit board a ground plane being set, so that electromagnetic emission minimizes.
31, a kind of method that is used to a semiconductor device with a ball grid array to power, described method comprises:
One utilizes a solder ball that is arranged on a periphery place of a substrate to reduce the path of an electric power signal as a ground connection solder ball, with the step of minimum signal parasitics; And
One to utilize the solder ball of a contiguous described ground connection solder ball to be used for the electric power/ground connection solder ball of described electric power signal right, so that from the minimized step of the electromagnetic emission of described electric power signal.
32, method as claimed in claim 31, a upper face that further comprises the steps: a system printed circuit board is set to a ground plane, and contiguous described ground plane is provided with a power supply conductivity path, minimize so that be connected to the length of the through hole in described power supply conductivity path, make one thus by described ground plane, described power supply conductivity path reaches the area of section that described through hole defined and minimizes, to reduce the electromagnetic emission from described electric power signal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US54775604P | 2004-02-24 | 2004-02-24 | |
| US60/547,756 | 2004-02-24 | ||
| US11/025,486 | 2004-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1938850A true CN1938850A (en) | 2007-03-28 |
| CN100539112C CN100539112C (en) | 2009-09-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580009948 Active CN100539112C (en) | 2004-02-24 | 2005-02-16 | Optimization is to electric power transfer high-speed, the high pin counting apparatus |
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| Country | Link |
|---|---|
| CN (1) | CN100539112C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102792439A (en) * | 2010-02-23 | 2012-11-21 | 高通股份有限公司 | Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits |
| CN102859685A (en) * | 2010-02-09 | 2013-01-02 | 阿尔特拉公司 | Interconnect pattern for transceiver package |
| CN105101638A (en) * | 2015-07-16 | 2015-11-25 | 浪潮电子信息产业股份有限公司 | Circuit board and method for decoupling chip on circuit board |
| WO2019196600A1 (en) * | 2018-04-09 | 2019-10-17 | 华为技术有限公司 | Chip and communication device |
-
2005
- 2005-02-16 CN CN 200580009948 patent/CN100539112C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102859685A (en) * | 2010-02-09 | 2013-01-02 | 阿尔特拉公司 | Interconnect pattern for transceiver package |
| CN102859685B (en) * | 2010-02-09 | 2016-04-27 | 阿尔特拉公司 | For the interconnection pattern of transceiver package |
| CN102792439A (en) * | 2010-02-23 | 2012-11-21 | 高通股份有限公司 | Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits |
| CN102792439B (en) * | 2010-02-23 | 2014-11-05 | 高通股份有限公司 | Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits |
| CN105101638A (en) * | 2015-07-16 | 2015-11-25 | 浪潮电子信息产业股份有限公司 | Circuit board and method for decoupling chip on circuit board |
| WO2019196600A1 (en) * | 2018-04-09 | 2019-10-17 | 华为技术有限公司 | Chip and communication device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100539112C (en) | 2009-09-09 |
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