WO2019161655A1 - 一种功率放大器的反馈控制电路 - Google Patents

一种功率放大器的反馈控制电路 Download PDF

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Publication number
WO2019161655A1
WO2019161655A1 PCT/CN2018/104472 CN2018104472W WO2019161655A1 WO 2019161655 A1 WO2019161655 A1 WO 2019161655A1 CN 2018104472 W CN2018104472 W CN 2018104472W WO 2019161655 A1 WO2019161655 A1 WO 2019161655A1
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Prior art keywords
circuit
voltage
signal
current
ldo
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PCT/CN2018/104472
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English (en)
French (fr)
Inventor
周永峰
朱波
梁绪亮
郭嘉帅
宣凯
龙华
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深圳飞骧科技有限公司
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Publication of WO2019161655A1 publication Critical patent/WO2019161655A1/zh

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3036Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3036Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H03G3/3042Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G2201/00Indexing scheme relating to subclass H03G
    • H03G2201/40Combined gain and bias control

Definitions

  • the present invention relates to the field of mobile phone communication technologies, and in particular, to a feedback control circuit for a power amplifier.
  • the power control method of the power amplifier is divided into current control and voltage control.
  • the current control technology also known as the base control technology, is a closed-loop control that detects the output power by detecting the current of the output stage of the power amplifier.
  • the sampling resistor By connecting a small sampling resistor in series with the power supply of the output stage of the power amplifier, the sampling resistor converts the current signal into The voltage signal, which is combined with the Vramp voltage, is controlled by adjusting the bias current of the power amplifier.
  • Voltage control technology also known as collector control technology, feeds the output voltage of the power amplifier back to the peak detector.
  • the output voltage of the peak detector is combined with Vramp to control the LDO.
  • the LDO supplies power to the power amplifier.
  • the present application is to provide a feedback control circuit for a power amplifier, which avoids the use of a sampling resistor to increase the cost of the chip and the test cost, and avoids the use of a large PMOS tube. This causes problems such as increased costs.
  • the invention provides a feedback control circuit of a power amplifier, the circuit comprising a feedback acquisition circuit, a VLDO control circuit, a radio frequency signal amplifier circuit, a choke inductor and a matching circuit;
  • the feedback acquisition circuit is configured to collect a voltage signal through the collection tube, and convert the output current signal to the V LDO control circuit;
  • the V LDO control circuit is configured to receive the output current signal, and jointly control the output V LDO voltage signal together with the Vramp voltage;
  • the RF signal amplifier circuit is configured to receive the V LDO voltage signal, and adjust the voltage and power of the output voltage signal together with the choke inductor and the matching circuit.
  • the method further includes a bias circuit and a DC blocking capacitor, wherein the bias circuit and the DC blocking capacitor are used to adjust the power of the output voltage signal, wherein:
  • One end of the bias circuit is connected to the VLDO voltage output end of the VLDO control circuit, and the other end is connected to the radio frequency signal amplifier circuit;
  • One end of the DC blocking capacitor is connected to the collecting tube, and the other end is connected to the RF signal amplifier circuit.
  • the feedback acquisition circuit includes a current sampling circuit and a voltage to current circuit, wherein:
  • the current sampling circuit is configured to collect a voltage signal through the collecting tube and send the voltage to the voltage to current circuit;
  • the voltage to current circuit is configured to convert the received voltage signal into an output current signal to the VLDO control circuit.
  • the current sampling circuit includes a first stage low pass filter circuit, wherein:
  • the first stage low pass filter circuit is configured to filter the collected voltage signal, filter a part of the radio frequency signal, and adjust to a suitable ratio to the voltage to current circuit.
  • the voltage to current circuit includes a second stage low pass filter circuit, wherein:
  • the second stage low pass filter circuit is configured to filter out a majority of the radio frequency signals from the converted current signal, and send the obtained output current signal to the V LDO control circuit.
  • the radio frequency signal amplifier circuit includes three electrically connected N-type amplifiers or an N-type switching tube for receiving the V LDO voltage signal, and adjusting the output together with the choke inductor and the matching circuit. Voltage and power of the voltage signal.
  • the voltage-to-current circuit includes a resistor R1
  • the current sampling circuit includes a resistor R2. Adjusting a proportional relationship between R1 and R2 can adjust a value of the output current signal.
  • the feedback acquisition circuit includes an amplifier 1 including an amplifier 2, and the proportional relationship of the amplifier 1 and the amplifier 2 can adjust the value of the output current signal.
  • the VLDO control circuit includes an electrically connected amplifier, a P-type adjustment tube, a first feedback resistor R4, a second feedback resistor R5, and a voltage stabilizing capacitor, and adjusting a ratio of R4 to R5 can adjust a voltage of the VIDO . .
  • the current output signal and the Vramp voltage jointly control the V LDO manner: when the Vramp voltage is low, the current output signal Ifb has a small current, mainly Vramp to control the output of the V LDO ; and the Vramp voltage is further increased.
  • the Ifb current gradually becomes larger and plays a main feedback role.
  • the power control circuit of the power amplifier provided by the invention further improves the filtering effect on the radio frequency signal, avoids the influence of the radio frequency signal on the working state of the feedback circuit, and avoids the current control on the basis of realizing the power amplifier power control.
  • the use of sampling resistors in the technology leads to an increase in chip cost and test cost; it also avoids the cost increase caused by the use of large PMOS transistors in voltage control technology.
  • FIG. 1 is a schematic diagram of a feedback control circuit of a power amplifier according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of a feedback control circuit of a power amplifier according to a second embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a feedback control circuit of a power amplifier according to a third embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a feedback control circuit of a power amplifier according to a fourth embodiment of the present invention.
  • the invention provides a feedback control circuit for a power amplifier, the circuit comprising a feedback acquisition circuit, a VLDO control circuit, a radio frequency signal amplifier circuit, a choke inductor and a matching circuit;
  • the feedback acquisition circuit is configured to collect through a collection tube And converting a voltage signal to an output current signal to the V LDO control circuit;
  • the V LDO control circuit is configured to receive the output current signal, and jointly control an output V LDO voltage signal with a Vramp voltage; And receiving the V LDO voltage signal, and adjusting the voltage and power of the output voltage signal together with the choke inductor and the matching circuit.
  • reference numeral VBAT is the positive pole of the power supply
  • RF_IN is the input terminal
  • RF_OUT is the output terminal.
  • the feedback acquisition circuit includes a current sampling circuit and a voltage-to-current circuit, wherein: the current sampling circuit is configured to collect a voltage signal through a collecting tube and send the voltage to a current-to-current circuit; the voltage-to-current circuit is configured to receive The resulting voltage signal is converted to an output current signal that is sent to the VLDO control circuit.
  • the current sampling circuit includes a first stage low pass filter circuit, wherein: the first stage low pass filter circuit is configured to filter the collected voltage signal, filter part of the radio frequency signal, and adjust to a suitable ratio to send the voltage to Current circuit.
  • the voltage-to-current circuit includes a second-stage low-pass filter circuit, wherein: the second-stage low-pass filter circuit is configured to filter out most of the RF signals from the converted current signal, and send the obtained output current to the Said V LDO control circuit.
  • the RF signal amplifier circuit includes three electrically connected N-type amplifiers or an N-type switching tube for receiving the V LDO voltage signal, and adjusting the output voltage signal together with the choke inductor and the matching circuit. Voltage and power.
  • the voltage-to-current circuit includes a resistor R1.
  • the current sampling circuit includes a resistor R2. Adjusting a proportional relationship between R1 and R2 can adjust a value of the output current signal.
  • the feedback acquisition circuit includes an amplifier 1 that includes an amplifier 2 that adjusts the magnitude of the current output signal by adjusting the proportional relationship of the amplifier 1 to the amplifier 2.
  • the VLDO control circuit includes an electrically connected amplifier, a P-type adjustment tube, a first feedback resistor R4, a second feedback resistor R5, and a voltage stabilizing capacitor.
  • the ratio of R4 to R5 can be adjusted to adjust the voltage of VLDO .
  • the current output signal Ifb has a small current, mainly Vramp to control the output of V LDO .
  • the Ifb current gradually becomes larger, acting as a main feedback.
  • the feedback control circuit of the power amplifier further includes a bias circuit and a DC blocking capacitor, wherein the bias circuit and the DC blocking capacitor are used to adjust the power of the output voltage signal, wherein: the bias circuit is connected to the V LDO control at one end The V LDO voltage output end of the circuit is connected to the RF signal amplifier circuit at the other end; the DC blocking capacitor is connected to the collector tube at one end and the RF signal amplifier circuit is connected to the other end.
  • the current sampling circuit is composed of N1, R2, R3, and C2, and is connected to the gate of the amplification stage N2, and the voltage signal is collected through the collection tube N1.
  • the source of the N-type MOS transistor N1 is grounded, the drain is connected to the resistor R3, one end of the resistor R2 is connected to R3 and the capacitor C2, and the other end is connected to the power source.
  • the capacitor C2 is connected to the power supply at one end and the other end is connected to the next stage.
  • the resistor R2, the resistor R3, and the capacitor C2 constitute a first-stage low-pass filter circuit, and the first-stage low-pass filter circuit is configured to filter the collected voltage signal, filter part of the radio frequency signal, and adjust to a proper ratio to the The voltage to current circuit.
  • the cutoff frequency is:
  • the voltage-to-current circuit is composed of an amplifier OP1, a P-type adjustment tube P1, a resistor R1, and a filter capacitor C1 for converting the received voltage signal into an output current signal and sent to the VLDO control circuit.
  • the positive terminal of the amplifier OP1 is connected to the current sampling resistor, and the negative terminal of the amplifier is connected to the source of the regulating tube P1.
  • the resistor R1 is connected to the power supply at one end, and the other end is connected to the source stage of the P-type adjustment tube P1.
  • the filter capacitor C1 is connected to the power supply at one end, and the other end is connected to the gate of the adjustment tube P1 and the output stage of the amplifier OP1.
  • the capacitor C1 and the output resistor Rout of the amplifier OP1 constitute a second-stage low-pass filter circuit, and the second-stage low-pass filter circuit is configured to filter out most of the RF signals from the converted current signal, and the obtained output is obtained.
  • Current is supplied to the VLDO control circuit.
  • the cutoff frequency is:
  • the RF signal amplifier circuit includes three electrically connected N-type amplifiers N2, N3, and N4 for receiving the V LDO voltage signal, and adjusting the output voltage signal together with the choke inductor L1 and the matching circuit. Voltage and power.
  • the drain of the amplifier tube N4 is connected to the choke inductor and the matching circuit, and the other end of the choke inductor is connected to the power source.
  • the Vramp control V IDO circuit comprises an electrically connected amplifier OP2, a P-type adjustment tube P2, a first feedback resistor R4, a second feedback resistor R5, a voltage stabilizing capacitor C3, and a Vramp voltage connected to the negative terminal of the amplifier OP2, the feedback The current is connected to the positive terminal of the amplifier OP2.
  • Vldo The formula for Vldo can be obtained by Ifb and Vramp as follows:
  • Vldo (1+R 4 /R 5 ) ⁇ Vramp-R 4 ⁇ I fb
  • Adjusting the proportional relationship between R4 and R5 can adjust the voltage of V LDO through the Vramp voltage to further control the output power.
  • Adjusting the proportional relationship between the resistor R1 and the resistor R2 can adjust the value of the output current signal; adjusting the proportional relationship between the amplifier N1 and the amplifier N2 can adjust the value of the output current signal.
  • the current sampling circuit is composed of Q1, R2, R3, and C2, and is connected to the base stage of the amplification stage Q2, and the voltage signal is collected through the collection tube Q1.
  • the emitter stage of the N-type amplifying tube Q1 is grounded, the collector is connected to the resistor R3, one end of the resistor R2 is connected to the R3 and the capacitor C2, the other end is connected to the power source, the capacitor C2 is connected to the power source at one end, and the other end is connected to the next stage.
  • the resistor R2, the resistor R3, and the capacitor C2 constitute a first-stage low-pass filter circuit, and the first-stage low-pass filter circuit is configured to filter the collected voltage signal, filter part of the radio frequency signal, and adjust to a proper ratio to the The voltage to current circuit.
  • the cutoff frequency is:
  • the voltage-to-current circuit is composed of an amplifier OP1, a P-type adjustment tube P1, a resistor R1, and a filter capacitor C1 for converting the received voltage signal into an output current signal and sent to the VLDO control circuit.
  • the positive terminal of the amplifier OP1 is connected to the current sampling resistor, and the negative terminal of the amplifier is connected to the source of the regulating tube P1.
  • the resistor R1 is connected to the power supply at one end, and the other end is connected to the source stage of the P-type adjustment tube P1.
  • the filter capacitor C1 is connected to the power supply at one end, and the other end is connected to the gate of the adjustment tube P1 and the output stage of the amplifier OP1.
  • the capacitor C1 and the output resistor Rout of the amplifier OP1 constitute a second-stage low-pass filter circuit, and the second-stage low-pass filter circuit is configured to filter out most of the RF signals from the converted current signal, and the obtained output is obtained.
  • Current is supplied to the VLDO control circuit.
  • the cutoff frequency is:
  • the radio frequency signal amplifier circuit includes three electrically connected N-type amplifying tubes Q2 for receiving the V LDO voltage signal, and adjusting the voltage and power of the output voltage signal together with the choke inductor L1 and the matching circuit. .
  • the collector stage of the amplifying tube Q2 is connected to the choke inductor and the matching circuit, and the other end of the choke inductor is connected to the power source.
  • the Vramp control V IDO circuit comprises an electrically connected amplifier OP2, a P-type adjustment tube P2, a first feedback resistor R4, a second feedback resistor R5, a voltage stabilizing capacitor C3, and a Vramp voltage connected to the negative terminal of the amplifier OP2, the feedback The current is connected to the positive terminal of the amplifier OP2.
  • V LDO The formula for V LDO can be obtained by Ifb and Vramp as follows:
  • Vldo (1+R 4 /R 5 ) ⁇ Vramp-R 4 ⁇ I fb
  • Adjusting the proportional relationship between R4 and R5 can adjust the voltage of V LDO through the Vramp voltage to further control the output power.
  • Adjusting the proportional relationship between the resistor R1 and the resistor R2 can adjust the value of the output current signal; adjusting the proportional relationship between the amplifier Q1 and the amplifier Q2 can adjust the value of the output current signal.
  • the current sampling circuit is composed of N1, R2, R3, and C2, and is connected to the gate of the amplification stage N2, and the voltage signal is collected through the collection tube N1.
  • the source of the N-type MOS transistor N1 is grounded, the drain is connected to the resistor R3, one end of the resistor R2 is connected to R3 and the capacitor C2, and the other end is connected to the power source.
  • the capacitor C2 is connected to the power supply at one end and the other end is connected to the next stage.
  • the resistor R2, the resistor R3, and the capacitor C2 constitute a first-stage low-pass filter circuit, and the first-stage low-pass filter circuit is configured to filter the collected voltage signal, filter part of the radio frequency signal, and adjust to a proper ratio to the The voltage to current circuit.
  • the cutoff frequency is:
  • the voltage-to-current circuit is composed of an amplifier OP1, a P-type adjustment tube P1, a resistor R1, and a filter capacitor C1 for converting the received voltage signal into an output current signal and sent to the VLDO control circuit.
  • the positive terminal of the amplifier OP1 is connected to the current sampling resistor, and the negative terminal of the amplifier is connected to the source of the regulating tube P1.
  • the resistor R1 is connected to the power supply at one end, and the other end is connected to the source stage of the P-type adjustment tube P1.
  • the filter capacitor C1 is connected to the power supply at one end, and the other end is connected to the gate of the adjustment tube P1 and the output stage of the amplifier OP1.
  • the capacitor C1 and the output resistor Rout of the amplifier OP1 constitute a second-stage low-pass filter circuit, and the second-stage low-pass filter circuit is configured to filter out most of the RF signals from the converted current signal, and the obtained output is obtained.
  • Current is supplied to the VLDO control circuit.
  • the cutoff frequency is:
  • the RF signal amplifier circuit includes three electrically connected N-type amplifiers N2, N3, and N4 for receiving the V LDO voltage signal, and adjusting the output voltage signal together with the choke inductor L1 and the matching circuit. Voltage and power.
  • the drain of the amplifier tube N4 is connected to the choke inductor and the matching circuit, and the other end of the choke inductor is connected to the power source.
  • the Vramp control V IDO circuit comprises an electrically connected amplifier OP2, a P-type adjustment tube P2, a first feedback resistor R4, a second feedback resistor R5, a voltage stabilizing capacitor C3, and a Vramp voltage connected to the negative terminal of the amplifier OP2, the feedback The current is connected to the positive terminal of the amplifier OP2.
  • Vldo The formula for Vldo can be obtained by Ifb and Vramp as follows:
  • Vldo (1+R 4 /R 5 ) ⁇ Vramp-R 4 ⁇ I fb
  • Adjusting the proportional relationship between R4 and R5 can adjust the voltage of V LDO through the Vramp voltage to further control the output power.
  • Adjusting the proportional relationship between the resistor R1 and the resistor R2 can adjust the value of the output current signal; adjusting the proportional relationship between the amplifier N1 and the amplifier N2 can adjust the value of the output current signal.
  • the feedback control circuit of the power amplifier further includes a bias circuit and a DC blocking capacitor C4, wherein the bias circuit and the DC blocking capacitor are used to adjust the power of the output voltage signal, wherein: the bias circuit is connected to the V LDO at one end a V LDO voltage output end of the control circuit, the other end is connected to the gate of N2 of the RF signal amplifier circuit; the DC blocking capacitor is connected to the collecting tube at one end, and the N 2 gate of the RF signal amplifier circuit is connected to the other end .
  • the current sampling circuit is composed of Q1, R2, R3, and C2, and is connected to the base stage of the amplification stage Q2, and the voltage signal is collected through the collection tube Q1.
  • the emitter stage of the N-type amplifying tube Q1 is grounded, the collector is connected to the resistor R3, one end of the resistor R2 is connected to the R3 and the capacitor C2, the other end is connected to the power source, the capacitor C2 is connected to the power source at one end, and the other end is connected to the next stage.
  • the resistor R2, the resistor R3, and the capacitor C2 constitute a first-stage low-pass filter circuit, and the first-stage low-pass filter circuit is configured to filter the collected voltage signal, filter part of the radio frequency signal, and adjust to a proper ratio to the The voltage to current circuit.
  • the cutoff frequency is:
  • the voltage-to-current circuit is composed of an amplifier OP1, a P-type adjustment tube P1, a resistor R1, and a filter capacitor C1 for converting the received voltage signal into an output current signal and sent to the VLDO control circuit.
  • the positive terminal of the amplifier OP1 is connected to the current sampling resistor, and the negative terminal of the amplifier is connected to the source of the regulating tube P1.
  • the resistor R1 is connected to the power supply at one end, and the other end is connected to the source stage of the P-type adjustment tube P1.
  • the filter capacitor C1 is connected to the power supply at one end, and the other end is connected to the gate of the adjustment tube P1 and the output stage of the amplifier OP1.
  • the capacitor C1 and the output resistor Rout of the amplifier OP1 constitute a second-stage low-pass filter circuit, and the second-stage low-pass filter circuit is configured to filter out most of the RF signals from the converted current signal, and the obtained output is obtained.
  • Current is supplied to the VLDO control circuit.
  • the cutoff frequency is:
  • the radio frequency signal amplifier circuit includes three electrically connected N-type amplifying tubes Q2 for receiving the V LDO voltage signal, and adjusting the voltage and power of the output voltage signal together with the choke inductor L1 and the matching circuit. .
  • the collector of the amplifying tube Q2 is connected to the choke inductor and the matching circuit, and the other end of the choke inductor is connected to the power source.
  • the Vramp control V IDO circuit comprises an electrically connected amplifier OP2, a P-type adjustment tube P2, a first feedback resistor R4, a second feedback resistor R5, a voltage stabilizing capacitor C3, and a Vramp voltage connected to the negative terminal of the amplifier OP2, the feedback The current is connected to the positive terminal of the amplifier OP2.
  • Vldo The formula for Vldo can be obtained by Ifb and Vramp as follows:
  • Vldo (1+R 4 /R 5 ) ⁇ Vramp-R 4 ⁇ I fb
  • Adjusting the proportional relationship between R4 and R5 can adjust the voltage of V LDO through the Vramp voltage to further control the output power.
  • Adjusting the proportional relationship between the resistor R1 and the resistor R2 can adjust the value of the output current signal; adjusting the proportional relationship between the amplifier Q1 and the amplifier Q2 can adjust the value of the output current signal.
  • the feedback control circuit of the power amplifier further includes a bias circuit and a DC blocking capacitor C4, wherein the bias circuit and the DC blocking capacitor are used to adjust the power of the output voltage signal, wherein: the bias circuit is connected to the V LDO at one end a V LDO voltage output end of the control circuit, the other end is connected to the collector of Q2 of the RF signal amplifier circuit; the DC blocking capacitor is connected to the collecting tube at one end, and the collector of Q2 is connected to the RF signal amplifier circuit at the other end .

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Abstract

一种功率放大器的反馈控制电路,所述电路包括反馈采集电路,VLDO控制电路(LDO)、射频信号放大电路、扼流电感(L1)以及匹配电路;所述反馈采集电路用于通过采集管(N1)采集电压信号,转换为输出电流信号(Ifb)送到所述VLDO控制电路(LDO);所述VLDO控制电路(LDO)用于接收所述输出电流信号(Ifb),同Vramp电压共同控制输出VLDO电压信号;所述射频信号放大电路用于接收所述VLDO电压信号,与所述扼流电感(L1)和匹配电路共同调节输出电压信号的电压和功率。该反馈控制电路能够提高对射频信号的滤波效果,避免了电流控制技术中由于使用采样电阻导致芯片成本和测试成本的提高,也避免了电压控制技术中采用大PMOS管导致成本的提高。

Description

一种功率放大器的反馈控制电路 技术领域
本发明涉及手机通信技术领域,尤其涉及一种功率放大器的反馈控制电路。
背景技术
目前,功率放大器的功率控制方法分为电流控制和电压控制。
电流控制技术又称为基极控制技术,为闭环控制,通过检测功率放大器输出级的电流来反映输出功率,通过在功率放大器输出级的电源上串联一个小采样电阻,采样电阻将电流信号转化为电压信号,此电压信号同Vramp电压合成后通过调整功率放大器的偏置电流来实现功率控制。
电压控制技术又称为集电极控制技术,将功率放大器的输出电压反馈到峰值检波器中,峰值检波器的输出电压同Vramp合成后共同控制LDO,LDO为功率放大器提供电源。
然而,由于电流控制技术需要精确的采样电阻,导致芯片集成成本高和测试成本高(需要Fuse电路对电阻进行校准);而电压控制技术由于控制器LDO需要PMOS管供电,其尺寸很大,成本较高,二者都有自己的缺点。
发明内容
为了解决上述背景技术的缺点,本申请拟提供一种功率放大器的反馈控制电路,在实现功率放大器功率控制的基础上,避免由于使用采样 电阻导致芯片成本和测试成本提高,也避免采用大PMOS管导致成本提高等的问题的发生。
本发明提供一种功率放大器的反馈控制电路,所述电路包括反馈采集电路,V LDO控制电路、射频信号放大器电路、扼流电感以及匹配电路;
所述反馈采集电路用于通过采集管采集电压信号,转换为输出电流信号送到所述V LDO控制电路;
所述V LDO控制电路用于接收所述输出电流信号,同Vramp电压共同控制输出V LDO电压信号;
所述射频信号放大器电路用于接收所述V LDO电压信号,与所述扼流电感和匹配电路共同调节所述输出电压信号的电压和功率。
进一步地,还包括偏置电路、隔直电容,所述偏置电路和隔直电容用于调节所述输出电压信号的功率,其中:
所述偏置电路一端连接V LDO控制电路的V LDO电压输出端,另一端连接所述射频信号放大器电路;
所述隔直电容一端连接所述采集管,另一端连接所述射频信号放大器电路。
进一步地,所述反馈采集电路包括电流采样电路、电压转电流电路,其中:
所述电流采样电路用于通过采集管采集电压信号,送到所述电压转电流电路;
所述电压转电流电路用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。
进一步地,所述电流采样电路包括第一级低通滤波电路,其中:
所述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。
进一步地,所述电压转电流电路包括第二级低通滤波电路,其中:
所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将得到的输出电流信号送到所述V LDO控制电路。
进一步地,所述射频信号放大器电路包括三个电性连接的N型放大器或一个N型开关管,用于接收所述V LDO电压信号,与所述扼流电感和匹配电路共同调节所述输出电压信号的电压和功率。
进一步地,所述电压转电流电路包括电阻R1,所述电流采样电路包括电阻R2,调整R1与R2的比例关系可以调整所述输出电流信号的数值。
进一步地,所述反馈采集电路包含放大器1,所述射频信号放大器电路包含放大器2,调整放大器1与放大器2的比例关系可以调整所述输出电流信号的数值。
进一步地,所述V LDO控制电路包含电性连接的放大器、P型调整管、第一反馈电阻R4、第二反馈电阻R5、稳压电容,调整R4与R5的比例关系可以调整V IDO的电压。
进一步地,所述电流输出信号同Vramp电压共同控制V LDO的方式为:在Vramp电压较低时,电流输出信号Ifb电流很小,主要是Vramp来控制V LDO的输出;随着Vramp电压进一步提高,Ifb电流逐渐变大,起到主反馈作用。
本发明取得了以下有益效果:
本发明提供的一种功率放大器的功率控制电路,进一步提高了对射频信号的滤波效果,避免射频信号的强弱影响反馈电路的工作状态;在实现功率放大器功率控制的基础上,避免了电流控制技术中由于使用采样电阻导致芯片成本和测试成本的提高;也避免了电压控制技术中采用大PMOS管导致成本的提高。
附图说明
图1是本发明实施例一的功率放大器的反馈控制电路的原理图。
图2是本发明实施例二的功率放大器的反馈控制电路的原理图。
图3是本发明实施例三的功率放大器的反馈控制电路的原理图。
图4是本发明实施例四的功率放大器的反馈控制电路的原理图。
具体实施方式
以下结合附图和实施例,对本发明的具体实施方式进行更加详细的说明,以便能够更好地理解本发明的方案以及其各个方面的优点。然而,以下描述的具体实施方式和实施例仅是说明的目的,而不是对本发明的限制。
本发明提供一种一种功率放大器的反馈控制电路,所述电路包括反馈采集电路,V LDO控制电路、射频信号放大器电路、扼流电感以及匹配电路;所述反馈采集电路用于通过采集管采集电压信号,转换为输出电流信号送到所述V LDO控制电路;所述V LDO控制电路用于接收所述输出电流信号,同Vramp电压共同控制输出V LDO电压信号;所述射频信号放大器电路用于接收所述V LDO电压信号,与所述扼流电感和匹配电路共同调节所述输出电压信号的电压和功率。所述电路中附图标记VBAT为电源正极,RF_IN为输入端,RF_OUT为输出端。
所述反馈采集电路包括电流采样电路、电压转电流电路,其中:所述电流采样电路用于通过采集管采集电压信号,送到所述电压转电流电路;所述电压转电流电路用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。
所述电流采样电路包括第一级低通滤波电路,其中:所述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。
所述电压转电流电路包括第二级低通滤波电路,其中:所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将 得到的输出电流送到所述V LDO控制电路。
所述射频信号放大器电路包括三个电性连接的N型放大器或一个N型开关管,用于接收所述V LDO电压信号,与所述扼流电感和匹配电路共同调节所述输出电压信号的电压和功率。
所述电压转电流电路包括电阻R1,所述电流采样电路包括电阻R2,调整R1与R2的比例关系可以调整所述输出电流信号的数值。所述反馈采集电路包含放大器1,所述射频信号放大器电路包含放大器2,调整放大器1与放大器2的比例关系可以调整所述电流输出信号的数值。
所述V LDO控制电路包含电性连接的放大器、P型调整管、第一反馈电阻R4、第二反馈电阻R5、稳压电容,调整R4与R5的比例关系可以调整V LDO的电压。
所述电流输出信号作为反馈电流Ifb输入到V LDO的反馈电阻节点,同Vramp电压共同控制V LDO的输出。在Vramp电压较低时,电流输出信号Ifb电流很小,主要是Vramp来控制V LDO的输出。随着Vramp电压进一步提高,Ifb电流逐渐变大,起到主反馈作用。
所述功率放大器的反馈控制电路还包括偏置电路、隔直电容,所述偏置电路和隔直电容用于调节所述输出电压信号的功率,其中:所述偏置电路一端连接V LDO控制电路的V LDO电压输出端,另一端连接所述射频信号放大器电路;所述隔直电容一端连接所述采集管,另一端连接所述射频信号放大器电路。
实施例1
如图1第一实施例原理图所示,所述电流采样电路由N1、R2、R3、C2组成,同放大级N2的栅级相连接,通过采集管N1采集电压信号。N型MOS管N1的源级接地,漏极接电阻R3,电阻R2的一端接R3和电容C2,另一端接电源,电容C2一端接电源,另一端同下一级相接。
其中,电阻R2、电阻R3、电容C2组成第一级低通滤波电路,所 述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。截止频率为:
ω 1=1/(C 1×(R 2//R 3))
所述电压转电流电路由放大器OP1,P型调整管P1,电阻R1,滤波电容C1组成,用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。放大器OP1的正端同电流采样电阻相连接,放大器的负端同调整管P1的源级相连。电阻R1一端接电源,另一端同P型调整管P1的源级相连。滤波电容C1一端连接电源,另一端连接调整管P1的栅极和放大器OP1的输出级。
其中,电容C1,以及放大器OP1的输出电阻Rout组成第二级低通滤波电路,所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将得到的输出电流送到所述V LDO控制电路。截止频率为:
ω 2=1/(C 1×R out)
所述射频信号放大器电路包括三个电性连接的N型放大器N2、N3、N4,用于接收所述V LDO电压信号,与所述扼流电感L1和匹配电路共同调节所述输出电压信号的电压和功率。放大管N4的漏级同扼流电感以及匹配电路相连,扼流电感另一端接电源。
所述Vramp控制V IDO电路包含电性连接的放大器OP2、P型调整管P2、第一反馈电阻R4、第二反馈电阻R5、稳压电容C3,Vramp电压连接放大器OP2的负端,所述反馈电流连接到放大器OP2的正端。
通过Ifb和Vramp可以得到Vldo的公式如下:
Vldo=(1+R 4/R 5)×Vramp-R 4×I fb
调整R4与R5的比例关系可以通过Vramp电压调整V LDO的电压,进一步可以控制输出的功率。
调整电阻R1与电阻R2的比例关系可以调整所述输出电流信号的数值;调整放大器N1与放大器N2的比例关系可以调整所述输出电流 信号的数值。
实施例2
如图2第二实施例原理图所示,所述电流采样电路由Q1、R2、R3、C2组成,同放大级Q2的基级相连接,通过采集管Q1采集电压信号。N型放大管Q1的发射级接地,集电极接电阻R3,电阻R2的一端接R3和电容C2,另一端接电源,电容C2一端接电源,另一端同下一级相接。
其中,电阻R2、电阻R3、电容C2组成第一级低通滤波电路,所述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。截止频率为:
ω 1=1/(C 1×(R 2//R 3))
所述电压转电流电路由放大器OP1,P型调整管P1,电阻R1,滤波电容C1组成,用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。放大器OP1的正端同电流采样电阻相连接,放大器的负端同调整管P1的源级相连。电阻R1一端接电源,另一端同P型调整管P1的源级相连。滤波电容C1一端连接电源,另一端连接调整管P1的栅极和放大器OP1的输出级。
其中,电容C1,以及放大器OP1的输出电阻Rout组成第二级低通滤波电路,所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将得到的输出电流送到所述V LDO控制电路。截止频率为:
ω 2=1/(C 1×R out)
所述射频信号放大器电路包括三个电性连接的N型放大管Q2,用于接收所述V LDO电压信号,与所述扼流电感L1和匹配电路共同调节所述输出电压信号的电压和功率。放大管Q2的集电级同扼流电感以及匹配电路相连,扼流电感另一端接电源。
所述Vramp控制V IDO电路包含电性连接的放大器OP2、P型调整管P2、第一反馈电阻R4、第二反馈电阻R5、稳压电容C3,Vramp电压连接放大器OP2的负端,所述反馈电流连接到放大器OP2的正端。
通过Ifb和Vramp可以得到V LDO的公式如下:
Vldo=(1+R 4/R 5)×Vramp-R 4×I fb
调整R4与R5的比例关系可以通过Vramp电压调整V LDO的电压,进一步可以控制输出的功率。
调整电阻R1与电阻R2的比例关系可以调整所述输出电流信号的数值;调整放大器Q1与放大器Q2的比例关系可以调整所述输出电流信号的数值。
实施例3
如图3第三实施例原理图所示,所述电流采样电路由N1、R2、R3、C2组成,同放大级N2的栅级相连接,通过采集管N1采集电压信号。N型MOS管N1的源级接地,漏极接电阻R3,电阻R2的一端接R3和电容C2,另一端接电源,电容C2一端接电源,另一端同下一级相接。
其中,电阻R2、电阻R3、电容C2组成第一级低通滤波电路,所述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。截止频率为:
ω 1=1/(C 1×(R 2//R 3))
所述电压转电流电路由放大器OP1,P型调整管P1,电阻R1,滤波电容C1组成,用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。放大器OP1的正端同电流采样电阻相连接,放大器的负端同调整管P1的源级相连。电阻R1一端接电源,另一端同P型调整管P1的源级相连。滤波电容C1一端连接电源,另一端连接调整管P1的栅极和放大器OP1的输出级。
其中,电容C1,以及放大器OP1的输出电阻Rout组成第二级低通滤波电路,所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将得到的输出电流送到所述V LDO控制电路。截止频率为:
ω 2=1/(C 1×R out)
所述射频信号放大器电路包括三个电性连接的N型放大器N2、N3、N4,用于接收所述V LDO电压信号,与所述扼流电感L1和匹配电路共同调节所述输出电压信号的电压和功率。放大管N4的漏级同扼流电感以及匹配电路相连,扼流电感另一端接电源。
所述Vramp控制V IDO电路包含电性连接的放大器OP2、P型调整管P2、第一反馈电阻R4、第二反馈电阻R5、稳压电容C3,Vramp电压连接放大器OP2的负端,所述反馈电流连接到放大器OP2的正端。
通过Ifb和Vramp可以得到Vldo的公式如下:
Vldo=(1+R 4/R 5)×Vramp-R 4×I fb
调整R4与R5的比例关系可以通过Vramp电压调整V LDO的电压,进一步可以控制输出的功率。
调整电阻R1与电阻R2的比例关系可以调整所述输出电流信号的数值;调整放大器N1与放大器N2的比例关系可以调整所述输出电流信号的数值。
所述功率放大器的反馈控制电路还包括偏置电路、隔直电容C4,所述偏置电路和隔直电容用于调节所述输出电压信号的功率,其中:所述偏置电路一端连接V LDO控制电路的V LDO电压输出端,另一端连接所述射频信号放大器电路的N2的栅极;所述隔直电容一端连接所述采集管,另一端连接所述射频信号放大器电路的N2的栅极。
实施例4
如图4第四实施例原理图所示,所述电流采样电路由Q1、R2、R3、C2组成,同放大级Q2的基级相连接,通过采集管Q1采集电压信号。N型放大管Q1的发射级接地,集电极接电阻R3,电阻R2的一端接R3和电容C2,另一端接电源,电容C2一端接电源,另一端同下一级相接。
其中,电阻R2、电阻R3、电容C2组成第一级低通滤波电路,所述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。截止频率为:
ω 1=1/(C 1×(R 2//R 3))
所述电压转电流电路由放大器OP1,P型调整管P1,电阻R1,滤波电容C1组成,用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。放大器OP1的正端同电流采样电阻相连接,放大器的负端同调整管P1的源级相连。电阻R1一端接电源,另一端同P型调整管P1的源级相连。滤波电容C1一端连接电源,另一端连接调整管P1的栅极和放大器OP1的输出级。
其中,电容C1,以及放大器OP1的输出电阻Rout组成第二级低通滤波电路,所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将得到的输出电流送到所述V LDO控制电路。截止频率为:
ω 2=1/(C 1×R out)
所述射频信号放大器电路包括三个电性连接的N型放大管Q2,用于接收所述V LDO电压信号,与所述扼流电感L1和匹配电路共同调节所述输出电压信号的电压和功率。放大管Q2的集电极同扼流电感以及匹配电路相连,扼流电感另一端接电源。
所述Vramp控制V IDO电路包含电性连接的放大器OP2、P型调整管P2、第一反馈电阻R4、第二反馈电阻R5、稳压电容C3,Vramp电压连接放大器OP2的负端,所述反馈电流连接到放大器OP2的正端。
通过Ifb和Vramp可以得到Vldo的公式如下:
Vldo=(1+R 4/R 5)×Vramp-R 4×I fb
调整R4与R5的比例关系可以通过Vramp电压调整V LDO的电压,进一步可以控制输出的功率。
调整电阻R1与电阻R2的比例关系可以调整所述输出电流信号的数值;调整放大器Q1与放大器Q2的比例关系可以调整所述输出电流信号的数值。
所述功率放大器的反馈控制电路还包括偏置电路、隔直电容C4,所述偏置电路和隔直电容用于调节所述输出电压信号的功率,其中:所述偏置电路一端连接V LDO控制电路的V LDO电压输出端,另一端连接所述射频信号放大器电路的Q2的集电极;所述隔直电容一端连接所述采集管,另一端连接所述射频信号放大器电路的Q2的集电极。
需要说明的是,以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围,本领域的普通技术人员应当理解,在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换,均应涵盖在本发明的范围之内。此外,除上下文另有所指外,以单数形式出现的词包括复数形式,反之亦然。另外,除非特别说明,那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (10)

  1. 一种功率放大器的反馈控制电路,所述电路包括反馈采集电路,V LDO控制电路、射频信号放大器电路、扼流电感以及匹配电路;
    所述反馈采集电路用于通过采集管采集电压信号,转换为输出电流信号送到所述V LDO控制电路;
    所述V LDO控制电路用于接收所述输出电流信号,同Vramp电压共同控制输出V LDO电压信号;
    所述射频信号放大器电路用于接收所述V LDO电压信号,与所述扼流电感和匹配电路共同调节所述输出电压信号的电压和功率。
  2. 如权利要求1所述的功率放大器的反馈控制电路,其特征在于,还包括偏置电路、隔直电容,所述偏置电路和隔直电容用于调节所述输出电压信号的功率,其中:
    所述偏置电路一端连接所述V LDO控制电路的V LDO电压输出端,另一端连接所述射频信号放大器电路;
    所述隔直电容一端连接所述采集管,另一端连接所述射频信号放大器电路。
  3. 如权利要求1所述的功率放大器的反馈控制电路,其特征在于,所述反馈采集电路包括电流采样电路、电压转电流电路,其中:
    所述电流采样电路用于通过采集管采集电压信号,送到所述电压转电流电路;
    所述电压转电流电路用于将接收到的电压信号转换为输出电流信号送到所述V LDO控制电路。
  4. 如权利要求3所述的功率放大器的反馈控制电路,其特征在于, 所述电流采样电路包括第一级低通滤波电路,其中:
    所述第一级低通滤波电路用于将采集的电压信号,过滤掉部分射频信号,调节到合适的比例送到所述电压转电流电路。
  5. 如权利要求3所述的功率放大器的反馈控制电路,其特征在于,所述电压转电流电路包括第二级低通滤波电路,其中:
    所述第二级低通滤波电路用于对转换后的电流信号过滤掉其中大部分射频信号,将得到的输出电流送到所述V LDO控制电路。
  6. 如权利要求1所述的功率放大器的反馈控制电路,其特征在于,所述射频信号放大器电路包括三个电性连接的N型放大器或一个N型开关管,用于接收所述V LDO电压信号,与所述扼流电感和匹配电路共同调节所述输出电压信号的电压和功率。
  7. 如权利要求3所述的功率放大器的反馈控制电路,其特征在于,所述电压转电流电路包括电阻R1,所述电流采样电路包括电阻R2,调整R1与R2的比例关系可以调整所述输出电流信号的数值。
  8. 如权利要求5所述的功率放大器的反馈控制电路,其特征在于,所述反馈采集电路包含放大器1,所述射频信号放大器电路包含放大器2,调整放大器1与放大器2的比例关系可以调整所述输出电流信号的数值。
  9. 如权利要求1所述的功率放大器的反馈控制电路,其特征在于,所述V LDO控制电路包含电性连接的放大器、P型调整管、第一反馈电阻R4、第二反馈电阻R5、稳压电容,调整R4与R5的比例关系可以调整V LDO的电压。
  10. 如权利要求1所述的功率放大器的反馈控制电路,其特征在于,所述电流输出信号同Vramp电压共同控制V LDO的方式为:在Vramp电压较低时,电流输出信号Ifb电流很小,主要是Vramp来控制V LDO的输出;随着Vramp电压进一步提高,Ifb电流逐渐变大作为主反馈来控制V LDO的输出。
PCT/CN2018/104472 2018-02-23 2018-09-07 一种功率放大器的反馈控制电路 WO2019161655A1 (zh)

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