WO2019154385A1 - 一种高密度三维纳米线沟道阵列及其制备方法 - Google Patents

一种高密度三维纳米线沟道阵列及其制备方法 Download PDF

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WO2019154385A1
WO2019154385A1 PCT/CN2019/074660 CN2019074660W WO2019154385A1 WO 2019154385 A1 WO2019154385 A1 WO 2019154385A1 CN 2019074660 W CN2019074660 W CN 2019074660W WO 2019154385 A1 WO2019154385 A1 WO 2019154385A1
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slope
density
etching
amorphous
layer
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French (fr)
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余林蔚
马海光
雷亚奎
吴小祥
尹涵
王军转
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Nanjing University
Nanjing Tech University
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Nanjing Tech University
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B3/0009—Forming specific nanostructures
    • B82B3/0014—Array or network of similar nanostructural elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs

Definitions

  • the invention relates to a method for growing a planar nanowire three-dimensional slope array, in particular to a method for forming a high-density slope parallel nanowire array by cyclic etching of a mask layer and a substrate to form a slope nano-guide step.
  • the present invention provides a reliable method for obtaining a high-density three-dimensional nanowire channel array, which can be widely applied to semiconductor micro/nanoelectronic devices, especially for large-area electrons (flat-panel display TFT applications), 3D logic, flexible/wearable electronics, and Field effect biochemical sensor device.
  • Crystalline silicon or related semiconductor nanowires are key building blocks for the development of next-generation high-performance micro-nano electronic logic, sensing and display applications.
  • EBL electron beam direct writing
  • the excellent properties of various new nanowire functional devices have been verified, but their preparation costs are extremely expensive and yields are low. Factors have long been difficult to get scaled applications.
  • crystalline silicon, germanium and various alloy semiconductor nanowires with diameters below 100 nm can be prepared in large quantities.
  • the nanowires prepared by the commonly used gas-liquid-solid (VLS) growth mode are mostly vertical random arrays, and it is difficult to achieve reliable and low-cost positioning integration directly in the current planar electronic process.
  • planar solid-liquid-solid (IPSLS) growth mode in which amorphous silicon is used as a precursor, and low-melting-point metal indium, The tin nanoparticles absorb amorphous silicon to grow a crystalline silicon nanowire structure.
  • IPSLS planar solid-liquid-solid
  • a simple single-sided step defined on a planar substrate can be used as a guide, and the metal droplets are attracted by the amorphous silicon covered by the edge of the step, and the edge of the step is moved to grow the nanowire on the edge of the step. Realize the positioning and shape growth of planar nanowires.
  • lithography is still required to define the guiding steps, and the pitch between the steps is determined by the precision of the lithography process.
  • lithography accuracy is above ⁇ 1 ⁇ m on small-area substrates, and for large-area substrates (such as flat-panel display applications with dimensions of several square meters), lithography accuracy can only reach 2 ⁇ 5 microns.
  • each step can generally only guide one nanowire growth, the density of the planar nanowire array (the reciprocal of the spacing) that can be achieved is limited.
  • the highest density can only reach a 2 micron pitch, which is 0.5 plane density of nanochannels/micron.
  • an object of the present invention is to provide a high-density three-dimensional nanowire channel array and a method of fabricating the same.
  • the present invention proposes to use a silicon wafer, glass, metal, compound or other substrate as a basis to define the step position by photolithography, electron beam etching and mask technology, and then use wet or dry vapor engraving.
  • the eclipse forms a tightly-spaced nano-step on the slope surface.
  • the nanowires can be directly guided onto the 3D slope to prepare a high-density nanowire channel with a spacing of up to 100 nanometers.
  • the high-density three-dimensional nanowire channel array prepared by the invention comprises as a base substrate material, a multi-stage slope step structure on the surface of the substrate, and high-density nanowires arranged in parallel on the sidewall of the three-dimensional slope A channel array having a pitch between a few nanometers and a few hundred nanometers.
  • the obtained multi-stage slope step structure comprises at least two steps structure, each step height is in the range of 1 to 1000 nm, and the step series ranges from 2 to 100.
  • the spacing of the nanowire channels is less than 2 microns.
  • the substrate forming the multi-step is a crystalline silicon wafer, amorphous silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, glass, polymer, aluminum foil or other metal, and an intrinsic or doped silicon wafer, Amorphous silicon, amorphous germanium, amorphous germanium silicon.
  • the present invention adopts the following technical solution: a method for cyclically etching a homogenous multi-stage slope step-guided growth (three-dimensional slope) nanowire array, that is, using a cyclic alternating etching to obtain a multi-stage slope surface nanometer Steps for guiding the growth of high density three-dimensional slope nanowire arrays.
  • a metal film covered by a crystalline silicon, glass, polymer or dielectric layer is prepared as a substrate, or an amorphous film is deposited as a substrate by a thin film deposition technique;
  • a stepped edge pattern is defined on an aluminum foil or other metal substrate; the predetermined slope position of the guiding step is defined to transfer the step edge pattern onto the substrate; and the etch is performed by an ICP or RIE alternating cycle etching method.
  • SF 6 (or mixtures thereof) a first gas Etching the pattern is transferred as an edge of the substrate; then oxygen gas (O 2) or chlorine gas (Cl 2) gas like an etching mask layer (photoresist and may be a variety of materials relative to the substrate etching selectivity A thin film, such as an oxide mask, a metal mask, or the like, is etched in a second step to retract the edge of the mask layer a certain distance.
  • the two-step cycle is alternately performed to prepare a two-stage or multi-stage step-shaped slope structure;
  • a catalytic layer including indium or tin metal is prepared by a photolithography process and a metal deposition process such as evaporation or sputtering, and the thickness is in the range of 1 to 500 nm, and the end point can be used as a nanowire.
  • the starting point of growth subsequently, under the action of a plasma of a reducing gas such as hydrogen, the temperature is higher than the melting point of the metal, so that the catalytic metal layer covering the guiding channel of the sidewall slope is transformed into a separated indium or tin metal.
  • the remaining amorphous precursor layer can be removed by hydrogen plasma or a corresponding ICP, RIE etching process.
  • the multi-stage slope step structure obtained in the step 2) comprises at least two step structures (multiple stages), each step height is in the range of 1 to 1000 nm, and the step series ranges from 2 to 100.
  • step 3 the diameter of the metal particles on the slope surface is controlled within a range of 10 to 1000 nm by controlling parameters such as treatment time, temperature, power, and gas pressure.
  • step 4 by using PECVD, CVD or PVD deposition techniques, the surface is covered with one or more layers, and an amorphous thin film precursor layer (covering the amorphous semiconductor layer as a precursor) corresponding to the required nanowire composition to be grown;
  • the precursor layer is amorphous silicon a-Si, amorphous ⁇ a-Ge, amorphous carbon aC or an amorphous alloy layer therein, and a heterogeneous laminated (e.g., a-Ge/a-Si) structure.
  • the nanowires will grow parallel to the high-density nanowire array above the sidewall of the three-dimensional slope; the growth direction is determined by the overall orientation of the guiding slope; the spacing of adjacent nanowires is determined by the step spacing, and the thickness is precisely controlled by the step thickness. Between a few nanometers and a few hundred nanometers.
  • step 2) according to different reaction gas ratios and alternating processes, inclined slopes with different inclination degrees can be obtained; that is, homogenous multi-stage slope step structure.
  • the substrate forming the multi-step is a crystalline silicon wafer, amorphous silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, glass, polymer, aluminum foil or other metal, and an intrinsic or doped silicon wafer, Amorphous silicon, amorphous germanium, amorphous germanium silicon and other semiconductor materials; substrate preparation process can be by chemical vapor deposition (CVD), plasma enhanced PECVD, atomic layer deposition (ALD), thermal evaporation and various sputtering One or more of physical vapor deposition (PVD) techniques are performed; the thickness of the substrate ranges from greater than 5 nm and the cycle period can range from 1 to 100.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • step 2) the wetted or vapor phase dry etching technique containing C 4 F 8 , CF 4 , SF 6 , Ar (or a mixed gas thereof) or an etching component corresponding to the substrate is used to form the slope formed by exposure.
  • the surface structure is processed, and the photoresist is processed by O 2 , Cl 2 or a wet or vapor phase dry etching technique corresponding to the etching composition of the mask layer, so that the photoresist layer is formed between the mask layer and the substrate.
  • Different etching responses to the etching atmosphere form a multi-step inclined slope step structure on the slope surface.
  • the pattern is defined by photolithography, electron beam etching or mask technology, and a layer is formed on the slope by a thickness of 1 to 500 nm by thermal evaporation, CVD, PECVD or various PVD techniques.
  • a metal catalyst layer such as indium, tin, gallium, germanium, gold, copper, nickel, titanium, silver, lead, and alloys thereof; and then, at a temperature above the melting point of the metal, using a reducing gas atmosphere (for example, in PECVD)
  • the hydrogen or ammonia plasma is treated between 200 and 500 ° C to convert the metal catalyst layer into separate nanoparticles and control the processing time and temperature (or plasma power and pressure in the PECVD system).
  • the diameter of the metal particles on the slope surface is controlled in the range of 10 to 1000 nm; in the PECVD system, the treatment power density is between 1 mW/cm 2 and 10 W/cm 2 , and the gas pressure is between 1 Pa and 100 Torr.
  • a layer of one or more layers covered by a PECVD, CVD or PVD deposition technique corresponding to the desired nanowire composition, an amorphous thin film precursor layer; precursor The layer is amorphous silicon a-Si, amorphous ⁇ a-Ge, amorphous carbon aC or an amorphous alloy layer thereof, and a heterogeneous laminate (such as a-Ge/a-Si) structure; on the slope surface, Each layer of film covers a thickness between 2 and 500 nm.
  • the gist of the present invention is: 1) by using an alternate cycle etching technique, a single lithography process is required to form a multi-layered slope step structure on a homogeneous planar substrate.
  • the process is simple and fast, does not require wet etching, or pre-deposited multi-layer heterostructures to form a high-density slope step with good morphology and precise control, which is directly used to guide the nanowires on this slope.
  • the step spacing can be in the range of 5 to 1000 nanometers, and a parallel and separated slope nanowire array structure can be grown; 3) the three-dimensional slope or sidewall nanometer thus arranged A line array architecture that grows high-density nanowire channels on a limited planar projected area, thereby greatly increasing the current load and drive capability of the nanowire array (as a transistor device channel); 4) due to this heterogeneous step 3D
  • the guiding technology can be realized by the traditional lithography and etching technology, and the substrate only needs one material, the process is simple, inherits and maintains the large-area process characteristics of the traditional thin film process, and can be widely applied to the flat panel display TFT, the biological Sensing, flexible wearable electronics and related new electronic logic devices.
  • the invention has the following beneficial effects: 1) solving the key problem that the planar solid-liquid-solid (IPSLS) step-guided growth semiconductor nanowire channel integration density is not high (and the driving current is limited in the device application); 2) adopting Cyclic etching enables high-density nanosteps formed on the slope surface, which can greatly increase the integration density of nanowires, and this technology is fully compatible with the basic process of large-area thin-film electronic devices, without introducing additional high-precision lithography technology; 3) At the same time, because nanowires can be integrated and positioned in parallel on three-dimensional slopes, it provides a key nanochannel implementation technology for the development of a new generation of three-dimensional integrated micro-nanoelectronic devices, and realizes process scalability and low cost.
  • IPSLS planar solid-liquid-solid
  • Programmable three-dimensional nanowire morphology can be used to control growth; 4) Since the slope angle of nanowire growth can be controlled by an etching process, a very high channel current driving capability can be obtained, which is required for realizing flat panel display.
  • High performance thin film transistors (TFTs) are especially important. Based on this technology, nanowire channel arrays are expected to meet the drive currents required to implement new AMOLED displays in a smaller TFT device space. This is particularly important for establishing a new generation of planar nanowire TFT flat panel display technology that achieves high performance (mobility, stability characteristics, aperture ratio, etc.) drive current based on high-generation amorphous silicon technology. 5) In addition, this technology is expected to help achieve more integrated large-area logic circuits, develop or optimize next-generation display, sensing and information device applications.
  • FIG. 1 is a schematic diagram of a preparation process of a method for cyclically etching a homogenous multi-stage step-guided growth three-dimensional slope nanowire array provided by the present invention. a) substrate preparation, b) overlying photoresist, c) photolithography, d) cyclic etching, e) overlying photoresist, f) second lithography, g) deposition of catalyst, h) nanowire growth .
  • FIG. 2 is a schematic structural view of a method for cyclically etching a homogenous multi-stage step-guided growth three-dimensional slope nanowire array according to the present invention.
  • FIG. 3 is a schematic diagram of a slope step and a silicon nanowire growth example structure prepared by the method of cyclic etching etched homogenous multi-stage step-guided growth three-dimensional slope nanowire array provided by the present invention.
  • (a) is a side view of a nano-concave-guided channel scanning electron microscope (SEM) formed on a homogenous multi-stage slope;
  • (b) is a partial enlarged view of (a);
  • (c) is a homogenous multi-stage slope
  • (d) provides a corresponding high-density slope step-guided nanowire array SEM side view.
  • the high-density three-dimensional nanowire channel array prepared by the present invention is as shown in FIGS. 2 and 3.
  • the nanowire channel array includes a substrate material as a foundation, a multi-stage slope step structure on the surface of the substrate, and a parallel row.
  • a high density nanowire channel array disposed over the sidewalls of the three-dimensional slope, the adjacent nanowires having a pitch between a few nanometers and a few hundred nanometers.
  • the obtained multi-stage slope step structure comprises at least two steps structure, each step height is in the range of 1 to 1000 nm, and the step series ranges from 2 to 100.
  • the spacing of the nanowire channels is less than 2 microns.
  • the substrate forming the multi-step is a crystalline silicon wafer, amorphous silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, glass, polymer, aluminum foil or other metal, and an intrinsic or doped silicon wafer, Amorphous silicon, amorphous germanium, amorphous germanium silicon.
  • the preparation process of the high-density three-dimensional nanowire channel array is as shown in FIG. 1 , and the specific implementation is as follows:
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a metal film covered by a crystalline silicon, glass, polymer or dielectric layer is prepared as a substrate (the substrate forming the multi-step can be a crystalline silicon wafer, an amorphous silicon nitride, a silicon oxide, a silicon oxynitride, Alumina, glass, polymer, aluminum foil or other metals, and different intrinsic or different doping components of silicon wafers, amorphous silicon, amorphous germanium, amorphous germanium silicon and other semiconductor materials.
  • the substrate can be purchased directly or The preparation process can be performed by one or more of chemical vapor deposition (CVD), plasma enhanced PECVD, atomic layer deposition (ALD), thermal evaporation, and various sputtering physical vapor deposition (PVD) techniques.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced PECVD
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the thickness of the substrate is greater than 5 nm, the cycle period can be in the range of 1 to 100) or by one or more thin film deposition techniques such as chemical vapor deposition (CVD), plasma enhanced PECVD, atomic layer deposition (ALD) , one or more techniques of thermal evaporation and various sputtering physical vapor deposition (PVD) techniques to deposit non-silicon films (eg, amorphous silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, amorphous) Silicon, amorphous germanium, amorphous germanium silicon, etc.) As a substrate.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced PECVD
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the etching process may be performed by using a reaction gas having different steep characteristics and surface passivation characteristics such as C 4 F 8 , CF 4 , SF6, Ar (or a mixed gas thereof) in the etching process (or alternately circulating different etching atmospheres). Then, the mask layer is etched with a reactive gas having different etching rates in the lateral direction and the longitudinal direction by using O 2 , Cl 2 , etc., and the etching is alternately cycled until the mask layer is finished to form a stepped step. According to different reaction gas ratios and alternating processes, inclined slopes with different inclination degrees can be obtained;
  • the homogenous multi-stage slope step structure comprises at least two stages (multiple stages) step structure, each step height is in the range of 1 to 1000 nm, and the cycle period may be 2 to 100;
  • a catalytic layer comprising indium or tin metal is prepared at one end of the slope step, and the thickness is in the range of 1 to 500 nm, and the end point can be used as a nanowire.
  • the starting point of growth then, under the action of a plasma of a reducing gas, treatment at a temperature higher than the melting point of the metal, so that the catalytic metal layer covering the guiding channel of the sidewall slope is transformed into separated indium or tin metal nanoparticles
  • the parameters such as treatment time, temperature, power and pressure, the diameter of the metal particles on the slope is controlled within the range of 10 to 1000 nm.
  • the crystalline semiconductor layer acts as a precursor).
  • the precursor layer may be amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or an amorphous alloy layer therein, and a heterogeneous laminate (e.g., a-Ge/a-Si) structure.
  • High-density nanowire arrays arranged in parallel on the sidewalls of the three-dimensional slope can be obtained by the guiding channel action of the multi-stage nanosteps formed on the sidewalls of the slope; the nanowires will grow parallel to the sidewalls of the three-dimensional slope High-density nanowire arrays on the upper; the growth direction is determined by the overall orientation of the guiding slope.
  • the spacing of adjacent nanowires is determined by the step spacing and can be precisely controlled between a few nanometers and a few hundred nanometers using the thickness of the laminated film.
  • the remaining amorphous precursor layer can be removed by hydrogen plasma or a corresponding ICP, RIE etching process.
  • a method for preparing a multi-dimensional slope step guided growth three-dimensional nanowire array can be used for growing a parallel silicon nanowire structure on a multi-step slope surface, and the preparation process can include the following steps:
  • a layer of one or more layers covered by a PECVD, CVD or PVD deposition technique corresponding to the desired nanowire composition, an amorphous thin film precursor layer; precursor
  • the layer may be amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon aC or an amorphous alloy layer therein, and a heterogeneous laminate (e.g., a-Ge/a-Si) structure.
  • each layer of the film covers a thickness of between 2 and 500 nm.
  • the method for cyclically etching a homogenous multi-stage slope step to guide and grow a three-dimensional slope nanowire array wherein the diameter of the nanowires grown on the slope surface is larger than the residual amorphous film precursor layer on the slope surface, and the diameter is usually the thickness of the film. 2 to 3 times, and in the same etching process such as ICP, RIE, etc., the etching rate of the amorphous layer is generally higher than that of the crystalline nanowire channel, and the amorphous layer on the slope surface can be selectively (or sacrifice a small amount of crystalline silicon channel thickness) to remove.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the step position is defined by techniques such as photolithography and electron beam etching;
  • a multi-stage slope nano-step is obtained by alternating cyclic etching, and is used for guiding a method for growing a high-density three-dimensional slope nanowire array.
  • ICP inductively coupled plasma etching
  • RIE reactive ion etching
  • the ICP etching method is used to circulate C4F 8 (or SF 6 ) and O 2 to etch the substrate and the photoresist, respectively, until the photoresist is etched, thereby forming a multi-stage slope step structure.
  • the etching process uses C 4 F 8 and SF 6 mixed (1:1) gas, and the ratio can be adjusted to obtain different slope angles;
  • a metal indium catalytic layer (thickness 20-60 nm) is deposited on one end of the slope step as a growth starting point of the nanowire.
  • the sample is loaded into a PECVD chamber, and a hydrogen plasma treatment is performed at 250 degrees to convert the catalytic metal layer covering the channel guiding surface of the sidewall into separated indium nanoparticles having a diameter of about 200 nm.
  • the pattern is defined by photolithography, electron beam etching or mask technology, and by thermal evaporation, CVD or various PVD techniques can also be used to prepare a layer having a thickness in the range of 1 to 500 nm on the slope.
  • a metal catalyst layer such as indium, tin, gallium, germanium, gold, copper, nickel, titanium, silver, lead, and alloys thereof; and then, at a temperature above the melting point of the metal, using a reducing gas atmosphere (for example, in PECVD)
  • the hydrogen or ammonia plasma is treated between 200 and 500 ° C to convert the metal catalyst layer into separate nanoparticles and control the processing time and temperature (or plasma power and pressure in the PECVD system).
  • the diameter of the metal particles on the slope surface is controlled in the range of 10 to 1000 nm; in the PECVD system, the treatment power density is between 1 mW/cm 2 and 10 W/cm 2 , and the gas pressure is between 1 Pa and 100 Torr.
  • the temperature is lowered to 100-160 degrees, and the surface of the PECVD system is covered with an amorphous silicon film (20-100 nm) precursor layer;
  • the shape of the nanowires can be precisely programmed by designing the guiding steps, which is not only a simple linear array of growth, but a programmable planar linear nanowire structure.
  • the spacing of adjacent nanowires is determined by the step spacing, which can be precisely controlled between several nanometers and several hundred nanometers by using the thickness of the laminated film.
  • the steepness of the slope can be controlled by adjusting the etching conditions to obtain a high-density 3D parallel slope nanowire array.
  • the remaining amorphous precursor layer can be selectively etched in the PECVD cavity by hydrogen plasma to remove the remaining amorphous silicon layer.

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Abstract

一种高密度三维纳米线沟道阵列及其制备方法，其制备的高密度三维纳米线沟道阵列，包括作为基础的衬底材料，衬底表面上的多级坡面台阶结构，以及平行排布于三维坡面侧壁之上的高密度纳米线沟道阵列，相邻纳米线的间距由台阶间隔决定，利用台阶厚度精确调控在几纳米到几百纳米之间；该制备方法提出了一种利用硅片、玻璃、金属、化合物或其他衬底作为基础，通过光刻、电子束刻蚀和掩模板技术定义台阶位置，在坡面上形成间距可控的密排引导纳米台阶；如此，可以将纳米线直接引导到3D坡面上生长，从而制备间隔可达到百纳米以下的高密度纳米线沟道。

Description

一种高密度三维纳米线沟道阵列及其制备方法
优先权声明
本申请是2018年2月8日提交的CN201810127391.1(公开号CN108557758A)的延续申请，且要求其优先权，其全部内容特此通过引用方式并入本文。
技术领域
本发明涉及一种平面纳米线三维坡面阵列生长方法，特别是通过对掩模层与衬底进行循环刻蚀形成坡面纳米引导台阶，从而实现高密度坡面平行纳米线阵列的方法。本发明提供了一种获得高密度三维纳米线沟道阵列的可靠方法，可广泛应用于半导体微纳电子器件，尤其针对大面积电子(平板显示TFT应用)、3D逻辑、柔性/可穿戴电子和场效应生物化学传感器件。
背景技术
晶硅或相关半导体纳米线(Nanowire)是开发新一代高性能微纳电子逻辑、传感和显示应用的关键构建单元。基于自上而下的电子束直写(EBL)技术制备直径在10～100nm范围的纳米线结构，已经验证各种新型纳米线功能器件的优异特性，但由于其制备成本极其昂贵、产量低等因素，一直以来都难以得到规模化应用。相比之下，通过纳米金属液滴催化的自下而上的自组装(Self-assembly)纳米线生长，可以大批量制备直径在百纳米以下的晶态硅、锗和各种合金半导体纳米线。然而，通常采用的气-液-固(VLS)生长模式所制备的纳米线多为竖直随机阵列，难以直接在目前的平面电子工艺中实现可靠且低成本的定位集成。
为了更好地与平面电子工艺相兼容，并实现定位集成，本申请人最早提出了一种平面固液固(IPSLS)生长模式：其中，采用非晶硅作为前驱体，由低熔点金属铟、锡纳米颗粒吸收非晶硅而生长出晶硅纳米线结构。同时，基于此方法，可利用平面衬底上定义的简单的单边台阶作为引导，金属液滴在台阶边缘覆盖的非晶硅吸引下，顺延台阶边缘运动，从而将纳米线生长在台阶边缘，实现平面纳米线的定位、定形生长。然而，基于此前方法，仍然需要光刻来定义引导台阶，台阶之间的间距由光刻工艺的精度决定。对于常规光刻技术，在小面积衬底上，光刻精度在～1微米以上，而对于大面积衬底(如尺寸在若干平方米的平板显示应用中)，光刻精度仅能达到2～5微米。由于每个台阶一般只能引导一条纳米线生长，所以所能实现的平面纳米线阵列密度(间距的倒数)受到限制。目前，最高密度只能达到2微米间距，既0.5根纳米沟道/微米的平面密度。对于面向平板显示的纳米线TFT应用，这也就限制了纳米线阵列的单位沟道宽度的电流承载和驱动能力(难以满足新型AMOLED显示所需要的较大驱动电流)。
发明内容
针对上述问题，本发明的目的是，提供一种高密度三维纳米线沟道阵列及其制备方法。具体地，本发明提出了一种利用硅片、玻璃、金属、化合物或其他衬底作为基础，通过光刻、电子束刻蚀和掩模板技术定义台阶位置，再利用湿法或者干法气相刻蚀，在坡面上形成间距可控的密排引导纳米台阶；如此，可以将纳米线直接引导到3D坡面上生长，从而制备高密度(间隔可达到百纳米以下)的纳米线沟道。基于此方法，不需要引入昂贵的超高精度光刻技术(如电子束曝光刻蚀EBL)，既能在现有大面积衬底上，在指定的位置和方向，可靠地制备高密度3D坡面纳米线阵列沟道。将纳米线沟道的间距由原来的2微米缩小到至少0.2微米以下，从而实现一个纳米沟道至少一个数量级的提高。
本发明制备的高密度三维纳米线沟道阵列，包括作为基础的衬底材料，衬底表面上的多级坡面台阶结构，以及平行排布于三维坡面侧壁之上的高密度纳米线沟道阵列，所述相邻纳米线的间距在几纳米到几百纳米之间。
所获得多级坡面台阶结构包括至少两级台阶结构，每级台阶高度在1～1000纳米范围，台阶级数范围为2～100。所述纳米线沟道的间距至小于2微米。
形成多级台阶的衬底为晶硅片、非晶氮化硅、氧化硅、氮氧化硅、氧化铝、玻璃、聚合物、铝箔或其它金属，以及本征或具有掺杂成分的硅片、非晶硅、非晶锗、非晶锗硅组成。
为了实现上述目的，本发明采取以下技术方案：一种循环交替刻蚀同质多级坡面台阶引导生长(三维坡面)纳米线阵列的方法，即利用循环交替刻蚀获得多级坡面纳米台阶，以用于引导生长高密度三维坡面纳米线阵列的方法。
1)首先，准备好晶硅、玻璃、聚合物或者介质层覆盖的金属薄膜作为衬底，或者利用薄膜淀积技术，淀积非晶薄膜作为衬底；
2)其次，利用光刻、电子束刻蚀或者掩模板技术在硅片衬底，化合物衬底(如氮化硅、氧化硅、氮氧化硅、氧化铝)，玻璃衬底，柔性衬底(多为聚合物)，铝箔或其它金属衬底上定义台阶边缘图案；定义引导台阶预定的坡面位置即将台阶边缘图案转移到衬底上；再用ICP或者RIE交替循环刻蚀方法刻蚀出坡面多级台阶结构直到衬底表面；刻蚀过程中先使用C 4F 8、CF 4、SF 6或其混合气体等具有不同陡直特性和表面钝化特性的反应气体进行刻蚀或者交替循环使用上述C 4F 8、CF 4、SF 6不同刻蚀气氛；再用包括O 2、Cl 2等在横向和纵向具有不同刻蚀速率的反应气体刻蚀掩模层，如此交替循环刻蚀，直至掩模层被刻完，形成多级坡面台阶；利用电感耦合等离子体刻蚀(ICP)或者反应离子体刻蚀(RIE)等气相刻蚀技术时，首先采用C 4F 8、CF 4、SF 6(或其混合)气体进行第一步刻蚀，将边缘图案转移如衬底；再用氧气(O 2)或氯气(Cl 2) 等刻蚀气体对掩模层(可为光刻胶及各种相对于衬底材料有刻蚀选择性的薄膜，如氧化物掩模、金属掩模等)进行第二步刻蚀，使掩膜层的边缘往内缩进一定距离。如此两步循环交替进行，从而制备两级或多级台阶形状坡面结构；
3)随后，在坡面台阶之一端，利用光刻工艺和蒸发或者溅射等金属淀积工艺，制备包括铟或锡金属的催化层，厚度在1～500nm范围内，此端点可作为纳米线的生长起点位置；随后在氢气等还原性气体的等离子体作用下，在高于金属熔点的温度进行处理，使覆盖在侧壁坡面引导沟道上的催化金属层转变成为分离的铟或锡金属纳米颗粒；
4)通过PECVD，CVD或者PVD沉积技术，在铟或锡金属纳米颗粒样品表面覆盖与所需生长纳米线相应的非晶半导体前驱体薄膜层；即降低温度到金属催化颗粒熔点以下，覆盖非晶半导体层作为前驱体；
5)生长纳米线：当温度提高到适当温度以上，以使得纳米金属颗粒重新融化，并开始在前端吸收非晶层前驱体，而在后端生长淀积出晶态的纳米线结构；借助坡面侧壁上形成的多级纳米台阶的引导沟道作用，获得平行排布于三维坡面侧壁之上的高密度纳米线阵列；
6)最后，剩余非晶前驱体层可通过氢气等离子体或者相应的ICP、RIE刻蚀工艺清除。
步骤2)中所获得多级坡面台阶结构包括至少两级台阶结构(可以多级)，每级台阶高度在1～1000纳米范围，台阶级数范围为2～100。
步骤3)中通过控制其处理时间、温度、功率和气压等参数，将坡面上的金属颗粒的直径控制在10～1000nm范围内。
步骤4)中通过PECVD，CVD或者PVD沉积技术，在表面覆盖一层或多层，与所需要生长纳米线成分相对应的，非晶薄膜前驱体层(覆盖非晶半导体层作为前驱体)；前驱体层为非晶硅a-Si、非晶锗a-Ge、非晶碳a-C或者其中的非晶合金层，以及异质叠层(如a-Ge/a-Si)结构。
步骤5)中纳米线将平行生长于三维坡面侧壁之上的高密度纳米线阵列；生长方向由引导坡面整体走向决定；相邻纳米线的间距由台阶间隔决定，利用台阶厚度精确调控在几纳米到几百纳米之间。
步骤2)中根据不同的反应气体配比和交替工艺，能够获得不同倾斜程度的倾斜坡面；即同质多级坡面台阶结构。形成多级台阶的衬底为晶硅片、非晶氮化硅、氧化硅、氮氧化硅、氧化铝、玻璃、聚合物、铝箔或其它金属，以及本征或具有掺杂成分的硅片、非晶硅、非晶锗、非晶锗硅等半导体材料组成；衬底制备工艺可以由化学气相沉积(CVD)，等离子体增强PECVD，原子层淀积(ALD)、热蒸发和各种溅射物理气相沉积(PVD)技术的一种或者多种来完成； 衬底的厚度范围大于5nm，循环周期可以为1～100范围之内。
步骤2)中利用含有C 4F 8、CF 4、SF 6、Ar(或其混合气体)或者与衬底对应的刻蚀成分的湿法或气相干法刻蚀技术，对所暴露形成的坡面结构进行处理，利用O 2、Cl 2或与掩模层相对应刻蚀成分的湿法或气相干法刻蚀技术对光刻胶进行处理，使其产生由于掩模层与衬底之间对刻蚀氛围的不同刻蚀响应，在坡面上形成多级倾斜坡面台阶结构。利用C 4F 8刻蚀硅衬底，利用O 2刻蚀光刻胶；同时，根据台阶数目的需求，调节光刻胶的厚度，以便提高循环交替刻蚀的周期数，从而获得更多的坡面台阶。
在引导坡面台阶的一端，通过光刻、电子束刻蚀或者掩模板技术，定义图案并通过热蒸发，CVD，PECVD或者各种PVD技术制备一层在坡面上厚度在1～500nm范围内的金属催化层，例如铟、锡、镓、铋、金、铜、镍、钛、银、铅以及其合金等；然后，在高于金属熔点的温度，利用还原性气体氛围(例如在PECVD中的氢气或氨气等离子体在200～500℃之间)处理金属催化层，使之转变成为分离的纳米颗粒，并通过控制其处理时间、温度(或对于PECVD系统中的等离子体功率和气压等)，将坡面上的金属颗粒的直径控制在10～1000nm范围内；在PECVD系统中，处理功率密度为1mW/cm2～10W/cm2之间，气压在1Pa～100Torr之间。
在低于催化金属液滴熔点的温度下，通过PECVD，CVD或者PVD沉积技术，在表面覆盖一层或多层，与所需要生长纳米线成分相对应的，非晶薄膜前驱体层；前驱体层为非晶硅a-Si、非晶锗a-Ge、非晶碳a-C或者其中的非晶合金层，以及异质叠层(如a-Ge/a-Si)结构；在坡面上，每层薄膜覆盖厚度在2～500nm之间。
本发明的要点为：1)利用交替循环刻蚀技术，仅需要一次光刻工艺，即可在同质平面衬底上形成多层坡面台阶结构。工艺简单快捷，不需要湿法刻蚀，或者预先淀积的多层异质结构，即可形成形貌良好、可精确调控的高密度坡面台阶，直接用于引导纳米线在此坡面上平行生长，获得高密度三维坡面纳米线阵列；2)通过此方法获得的坡面台阶间隔及台阶数多少由刻蚀周期和一个周期内C 4F 8、CF 4、SF 6、Ar(或其混合气体)和O 2、Cl 2或其混合气体的刻蚀时间来决定。可以不受平面光刻空间分辨率的限制，实现的台阶间距可为5～1000纳米范围，并生长出平行且分离的坡面纳米线阵列结构；3)如此排列的三维坡面或侧壁纳米线阵列构架，可在有限的平面投影面积上生长排布高密度纳米线沟道，从而大幅提高纳米线阵列(作为晶体管器件沟道)的电流负载和驱动能力；4)由于此异质台阶三维引导技术可通过传统的光刻和刻蚀技术得以实现，且衬底只需要一种材料，工艺简单，继承保持了传统薄膜工艺的在大面积工艺特性，可广泛地应用于平板显示TFT，生物传感，柔性可穿戴电子以及相关的新型电子逻辑器件。
本发明的有益效果：1)解决了平面固液固(IPSLS)台阶引导生长半导体纳米线沟道集成密度不高(及其带来的器件应用中驱动电流受限)的关键问题；2)采用循环刻蚀使坡面上形成的高密度纳米台阶，可以将纳米线的集成密度大幅提高，并且此技术完全兼容大面积薄膜电子器件的基本工艺，不必引入额外的高精度光刻技术；3)与此同时，由于纳米线可以平行集成定位于三维坡面上，为开拓新一代的三维集成微纳电子器件提供了一种关键的纳米沟道实现技术，并且实现工艺可扩展、低成本，并可以实现可编程的三维纳米线形貌调控生长能力；4)由于纳米线生长的坡面角度可以通过刻蚀工艺调控，可以获得非常高的沟道电流驱动能力，这对于实现平板显示所需要的高性能薄膜晶体管(TFT)尤为重要。基于此技术，纳米线沟道阵列有望在更小的TFT器件空间内满足实现新型AMOLED显示所需要的驱动电流。这对于建立新一代平面纳米线TFT平板显示技术，既以高世代非晶硅技术为基础实现高性能(迁移率、稳定特性和开口率等)驱动电流，意义尤其重大。5)另外，此技术还有望帮助实现集成度更高的大面积逻辑电路，开发或优化新一代显示、传感和信息器件应用。
附图说明
图1是本发明提供的一种循环刻蚀同质多级台阶引导生长三维坡面纳米线阵列方法的制备流程示意图。a)衬底准备、b)覆盖光刻胶、c)光刻、d)循环刻蚀、e)覆盖光刻胶、f)第二次光刻、g)淀积催化剂、h)纳米线生长。
图2是本发明提供的一种循环刻蚀同质多级台阶引导生长三维坡面纳米线阵列方法的结构示意图。
图3是本发明提供的一种循环刻蚀同质多级台阶引导生长三维坡面纳米线阵列方法的制备的坡面台阶以及硅纳米线生长范例结构。(a)为在同质多级坡面上所形成的纳米凹凸引导沟道扫描电镜(SEM)侧视图；(b)为(a)的局部放大图；(c)为在同质多级坡面上所形成的纳米凹凸引导沟道扫描电镜(SEM)俯视图；(d)提供相应的高密度坡面台阶引导纳米线阵列SEM侧视图。
具体实施方式
为使本发明的技术方案和优点更加清楚明白，以下结合具体实施范例，并参照附图1和图2和图3，对本发明进一步阐述说明。
本发明制备的高密度三维纳米线沟道阵列如图2、3所示，所述纳米线沟道阵列包括作为基础的衬底材料，衬底表面上的多级坡面台阶结构，以及平行排布于三维坡面侧壁之上的高密度纳米线沟道阵列，所述相邻纳米线的间距在几纳米到几百纳米之间。
所获得多级坡面台阶结构包括至少两级台阶结构，每级台阶高度在1～1000纳米范围， 台阶级数范围为2～100。所述纳米线沟道的间距至小于2微米。
形成多级台阶的衬底为晶硅片、非晶氮化硅、氧化硅、氮氧化硅、氧化铝、玻璃、聚合物、铝箔或其它金属，以及本征或具有掺杂成分的硅片、非晶硅、非晶锗、非晶锗硅组成。
所述高密度三维纳米线沟道阵列的制备工艺如图1所示，具体实施方式如下：
实施例一：
1、首先，准备好晶硅、玻璃、聚合物或者介质层覆盖的金属薄膜作为衬底(形成多级台阶的衬底可为晶硅片、非晶氮化硅、氧化硅、氮氧化硅、氧化铝、玻璃、聚合物、铝箔或其它金属等以及不同本征或具有不同掺杂成分的硅片、非晶硅、非晶锗、非晶锗硅等半导体材料组成。衬底可以直接购买或自行制备，制备工艺可以由化学气相沉积(CVD)，等离子体增强PECVD，原子层淀积(ALD)、热蒸发和各种溅射物理气相沉积(PVD)技术的一种或者多种来完成。衬底的厚度范围大于5nm，循环周期可以为1～100范围之内)或者利用一种或多种薄膜淀积技术，例如化学气相沉积(CVD)，等离子体增强PECVD，原子层淀积(ALD)、热蒸发和各种溅射物理气相沉积(PVD)技术的一种或者多种技术，淀积非硅薄膜(例如：非晶氮化硅、氧化硅、氮氧化硅、氧化铝、非晶硅、非晶锗、非晶锗硅等)作为衬底。
2、其次，利用光刻、电子束刻蚀或者掩模板技术，定义引导台阶预定的坡面位置；再用ICP或者RIE交替循环刻蚀方法刻蚀出坡面多级台阶结构直到衬底表面；刻蚀过程中可先使用C 4F 8、CF 4、SF6、Ar(或其混合气体)等具有不同陡直特性和表面钝化特性的反应气体进行刻蚀(或者交替循环使用不同刻蚀气氛)，再用O 2、Cl 2等在横向和纵向具有不同刻蚀速率的反应气体刻蚀掩模层，如此交替循环刻蚀，直至掩模层被刻完，形成坡面多级台阶。根据不同的反应气体配比和交替工艺，可以获得不同倾斜程度的倾斜坡面；
同质多级坡面台阶结构包括至少两级(可以多级)台阶结构，每级台阶高度在1～1000纳米范围，循环周期可为2～100；
3、随后，利用光刻工艺和蒸发或者溅射等金属淀积工艺，在坡面台阶之一端，制备包括铟或锡金属的催化层，厚度在1～500nm范围内，此端点可作为纳米线的生长起点位置；随后在还原性气体的等离子体作用下，在高于金属熔点的温度进行处理，使覆盖在侧壁坡面引导沟道上的催化金属层转变成为分离的铟或锡金属纳米颗粒；通过控制其处理时间、温度、功率和气压等参数，将坡面上的金属颗粒的直径控制在10～1000nm范围内。
4、将温度降低到金属催化颗粒熔点以下，通过PECVD，CVD或者PVD沉积技术，在表面 覆盖一层或多层，与所需要生长纳米线成分相对应的，非晶薄膜前驱体层(覆盖非晶半导体层作为前驱体)。前驱体层可以为非晶硅a-Si、非晶锗a-Ge、非晶碳a-C或者其中的非晶合金层，以及异质叠层(如a-Ge/a-Si)结构。
5、当温度提高到适当温度以上，以使得纳米金属颗粒重新融化，并开始在前端吸收非晶层前驱体，而在后端生长淀积出晶态的纳米线结构。借助坡面侧壁上形成的多级纳米台阶的引导沟道作用，可以获得平行排布于三维坡面侧壁之上的高密度纳米线阵列；纳米线将平行生长于三维坡面侧壁之上的高密度纳米线阵列；生长方向由引导坡面整体走向决定。相邻纳米线的间距由台阶间隔决定，可利用叠层膜厚精确调控在几纳米到几百纳米之间。
6、最后，剩余非晶前驱体层可通过氢气等离子体或者相应的ICP、RIE刻蚀工艺清除。
如图1所示，一种同质多级坡面台阶引导生长三维纳米线阵列的制备方法，可用于在多级台阶坡面上生长平行硅纳米线结构，其制备过程可包括以下步骤：
在低于催化金属液滴熔点的温度下，通过PECVD，CVD或者PVD沉积技术，在表面覆盖一层或多层，与所需要生长纳米线成分相对应的，非晶薄膜前驱体层；前驱体层可以为非晶硅a-Si、非晶锗a-Ge、非晶碳a-C或者其中的非晶合金层，以及异质叠层(如a-Ge/a-Si)结构。在坡面上，每层薄膜覆盖厚度在2～500nm之间。
所述的循环刻蚀同质多级坡面台阶引导生长三维坡面纳米线阵列的方法，由于坡面生长的纳米线直径大于坡面上剩余非晶薄膜前驱体层，通常直径是薄膜厚度的2～3倍，且在相同的ICP，RIE等刻蚀工艺中，非晶层的刻蚀速率通常高于对晶态纳米线沟道的刻蚀，坡面上的非晶层可被选择性(或牺牲少量晶硅沟道厚度)地清除。
实施例二：
1、首先，以晶硅或玻璃作为衬底，利用光刻、电子束刻蚀等技术定义台阶位置；
2、利用交替循环刻蚀获得多级坡面纳米台阶，用于引导生长高密度三维坡面纳米线阵列的方法。先利用光刻、电子束直写或掩模板技术在硅片衬底，化合物衬底(如氮化硅、氧化硅、氮氧化硅、氧化铝)，玻璃衬底，柔性衬底(多为聚合物)，铝箔或其它金属衬底上定义台阶边缘图案；然后，利用电感耦合等离子体刻蚀(ICP)或者反应离子体刻蚀(RIE)等气相刻蚀技术，首先采用C 4F 8、CF 4、SF 6、(或其混合)气体进行第一步刻蚀，将边缘图案转移如衬底；再用氧气(O 2)或氯气(Cl 2)等刻蚀气体对掩模层(为光刻胶及各种相对于衬底材料有刻蚀选择性的薄膜材料，如氧化物掩模、金属掩模等)进行第二步刻蚀，使掩膜层的边缘往内缩进一定距离； 如此两步交替循环进行，从而制备两级或多级台阶形状坡面结构；
利用ICP刻蚀方法循环通入C4F 8(或SF 6)和O 2分别刻蚀衬底和光刻胶直到光刻胶被刻蚀完，即可形成多级坡面台阶结构。刻蚀过程使用C 4F 8和SF 6混合(1：1)气体，比例可以调节以获得不同的坡面角度；
3、利用光刻定位以及热蒸发技术，在坡面台阶一端淀积金属铟催化层(厚度20～60nm)，作为纳米线的生长起点位置。样品装入PECVD腔体，在在250度进行氢气等离子体处理，使覆盖在侧壁坡面引导沟道上的催化金属层转变成为分离铟纳米颗粒，直径在200nm左右。
在引导坡面台阶的一端，通过光刻、电子束刻蚀或者掩模板技术，定义图案并通过热蒸发，也可以CVD或者各种PVD技术制备一层在坡面上厚度在1～500nm范围内的金属催化层，例如铟、锡、镓、铋、金、铜、镍、钛、银、铅以及其合金等；然后，在高于金属熔点的温度，利用还原性气体氛围(例如在PECVD中的氢气或氨气等离子体在200～500℃之间)处理金属催化层，使之转变成为分离的纳米颗粒，并通过控制其处理时间、温度(或对于PECVD系统中的等离子体功率和气压等)，将坡面上的金属颗粒的直径控制在10～1000nm范围内；在PECVD系统中，处理功率密度为1mW/cm 2～10W/cm 2之间，气压在1Pa～100Torr之间。
4、将温度降低到100～160度，在PECVD系统中表面覆盖一层非晶硅薄膜(20～100nm)前驱体层；
5、当温度提高到350度，以使得纳米铟颗粒重新融化，并开始在前端吸收非晶硅，而在后端生长淀积出晶态的硅纳米线结构。借助坡面纳米台阶的引导作用，纳米线将平行生长与坡面之上，顺延引导坡面整体走向。如图2示意结构，以及图3b-3d中SEM图像所示；
需要在真空或者惰性气体保护的环境中，将温度升高到金属熔点(或金属与薄膜前驱体和合金eutectic温度)以上，坡面上的金属颗粒将重新变为液滴，并开始在前端不断吸收非晶前驱体，而在后端界面淀积出晶态的纳米线结构。由于坡面纳米台阶的引导作用，纳米线将平行生长与坡面之上，生长方向由引导坡面整体走向决定。故而，纳米线的线形可以通过对引导台阶的设计而精确编程设计，既不仅仅是生长简单直线阵列，而是可以生长出可编程的平面线形纳米线结构。同时，相邻纳米线的间距由台阶间隔决定，可利用叠层膜厚精确调控在几纳米到几百纳米之间。通过调节刻蚀条件可控制坡面陡直度，从而获得高密度3D平行坡面纳米线阵列。
6、最后，剩余非晶前驱体层可通过氢气等离子体在PECVD腔体中进行选择性刻蚀去除剩 余的非晶硅层。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种高密度三维纳米线沟道阵列，其特征在于：所述纳米线沟道阵列包括作为基础的衬底材料，衬底表面上的多级坡面台阶结构，以及平行排布于三维坡面侧壁之上的高密度纳米线沟道阵列，相邻纳米线的间距在几纳米到几百纳米之间。
  2. 根据权利要求1所述的高密度三维纳米线沟道阵列，其特征在于：所获得多级坡面台阶结构包括至少两级台阶结构，每级台阶高度在1～1000纳米范围，台阶级数范围为2～100。
  3. 根据权利要求2所述的高密度三维纳米线沟道阵列，其特征在于：所述纳米线沟道的间距至小于2微米。
  4. 根据权利要求1-3任一项所述的高密度三维纳米线沟道阵列，其特征在于：形成多级台阶的衬底为晶硅片、非晶氮化硅、氧化硅、氮氧化硅、氧化铝、玻璃、聚合物、铝箔或其它金属；以及本征或具有掺杂成分的硅片、非晶硅、非晶锗、非晶锗硅材料组成。
  5. 一种根据权利要求1-4所述的高密度三维纳米线沟道阵列的制备方法，其特征在于，包括如下制备步骤：
    1)首先，准备好晶硅、玻璃、聚合物或者介质层覆盖的金属薄膜作为衬底，或者利用薄膜淀积技术淀积非晶薄膜作为衬底；
    2)其次，利用光刻、电子束刻蚀或者掩模板技术，定义引导台阶预定的坡面位置即将台阶边缘图案转移到衬底上；再用ICP或者RIE交替循环刻蚀方法刻蚀出坡面多级台阶结构直到衬底表面；刻蚀过程中先使用C 4F 8、CF 4、SF 6或其混合气体等具有不同陡直特性和表面钝化特性的反应气体进行刻蚀或者交替循环使用上述C 4F 8、CF 4、SF 6不同刻蚀气氛；再用包括O 2、Cl 2等在横向和纵向具有不同刻蚀速率的反应气体刻蚀掩模层，如此交替循环刻蚀，直至掩模层被刻完，形成坡面多级台阶；
    3)随后，利用光刻工艺和蒸发或者溅射等金属淀积工艺，在坡面台阶之一端，制备包括铟或锡金属的催化层，厚度在1～500nm范围内，此端点可作为纳米线的生长起点位置；随后在还原性气体的等离子体作用下，在高于金属熔点的温度进行处理，使覆盖在侧壁坡面引导沟道上的催化金属层转变成为分离的铟或锡金属纳米颗粒；
    4)通过PECVD，CVD或者PVD沉积技术，在样品表面覆盖与所需生长纳米线相应的非晶半导体前驱体薄膜层；
    5)生长纳米线：当温度提高到适当温度以上，以使得纳米金属颗粒重新融化，并开始在前端吸收非晶层前驱体，而在后端生长淀积出晶态的纳米线结构；借助坡面侧壁上形成的多级纳米台阶的引导沟道作用，获得平行排布于三维坡面侧壁之上的高密度纳米线阵列；
    6)最后，剩余非晶前驱体层可通过氢气等离子体或者相应的ICP、RIE刻蚀工艺清除。
  6. 根据权利要求5所述的高密度三维纳米线沟道阵列的制备方法，其特征在于：步骤3)中通过控制其处理时间、温度、功率和气压等参数，将坡面上的金属颗粒的直径控制在10～1000nm范围内。
  7. 根据权利要求5所述的高密度三维纳米线沟道阵列的制备方法，其特征在于，步骤4)中通过PECVD，CVD或者PVD沉积技术，在表面覆盖一层或多层，与所需要生长纳米线成分相对应的，非晶薄膜前驱体层；前驱体层为非晶硅a-Si、非晶锗a-Ge、非晶碳a-C或者其中的非晶合金层，以及异质叠层结构。
  8. 根据权利要求5所述的高密度三维纳米线沟道阵列的制备方法，其特征在于，步骤2)中根据不同的反应气体配比和交替工艺，能够获得不同倾斜程度的倾斜坡面；即同质多级坡面台阶结构。
  9. 根据权利要求5所述的高密度三维纳米线沟道阵列的制备方法，其特征是，利用含有C 4F 8、CF 4、SF 6或其混合气体或者与衬底对应的刻蚀成分的湿法或气相干法刻蚀技术，对所暴露形成的坡面结构进行处理；利用O 2、Cl 2或与掩模层相对应刻蚀成分的湿法或气相干法刻蚀技术对光刻胶进行处理，使其产生由于掩模层与衬底之间对刻蚀氛围的不同刻蚀响应，在坡面上形成多级倾斜坡面台阶结构。
  10. 根据权利要求5所述的高密度三维纳米线沟道阵列的制备方法，其特征是：在引导坡面台阶的一端，通过光刻、电子束刻蚀或者掩模板技术，定义图案并通过热蒸发，CVD，PECVD或者各种PVD技术制备一层在坡面上厚度在1～500nm范围内的金属催化层；然后，在高于金属熔点的温度，利用还原性气体氛围处理金属催化层，使之转变成为分离的纳米颗粒，并通过控制其处理时间、温度，将坡面上的金属颗粒的直径控制在10～1000nm范围内；在PECVD系统中，处理功率密度为1mW/cm 2～10W/cm 2之间，气压在1Pa～100Torr之间。
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