WO2019153299A1 - 一种显示屏及终端设备 - Google Patents

一种显示屏及终端设备 Download PDF

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Publication number
WO2019153299A1
WO2019153299A1 PCT/CN2018/076269 CN2018076269W WO2019153299A1 WO 2019153299 A1 WO2019153299 A1 WO 2019153299A1 CN 2018076269 W CN2018076269 W CN 2018076269W WO 2019153299 A1 WO2019153299 A1 WO 2019153299A1
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WIPO (PCT)
Prior art keywords
insulating layer
display screen
layer
opening
array substrate
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PCT/CN2018/076269
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English (en)
French (fr)
Inventor
李文兵
马磊
张峰
王振伟
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华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/076269 priority Critical patent/WO2019153299A1/zh
Priority to CN201880061419.4A priority patent/CN111108432A/zh
Publication of WO2019153299A1 publication Critical patent/WO2019153299A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display screen and a terminal device.
  • an opening 10 is usually formed on the display screen, thereby Components such as the above-described camera, receiver, and photosensor may be disposed in the opening 10.
  • the portions of the above display screen located on both sides of the opening 10 can still be displayed without using a light-shielding material for shielding, thereby achieving the purpose of increasing the proportion of the display screen.
  • the sub-pixels ie, the same row of sub-pixels driven by the same row of gate lines on both sides of the opening 10 in FIG. 1a need to be disposed around the opening 10 and are disposed on both sides of the opening 10, so that the entire row cannot be realized.
  • the cloth, and the same row of sub-pixels below the opening 10 are not affected by the opening 10, so that the entire row can be arranged. Therefore, the number of sub-pixels in the same row on both sides of the opening 10 is smaller than the number of sub-pixels in the same row below the opening 10.
  • the charging time of one row of sub-pixels on both sides of the opening 10 and the charging time of one row of sub-pixels below the opening 10 are different, so that the deflection speed of the liquid crystal molecules on both sides of the opening 10 is different.
  • the deflection speed of the liquid crystal molecules below the opening 10 is different, which causes an abnormal phenomenon such as horizontal stripes or flicker in the display screen during display.
  • Embodiments of the present invention provide a display screen and a terminal device.
  • the display screen is provided with a slotted area, the probability of occurrence of an abnormal phenomenon such as horizontal stripes or flicker during display display can be reduced.
  • the embodiment adopts the following technical solutions:
  • a display screen having an opening.
  • the display screen includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer is disposed between the array substrate and the counter substrate.
  • the array substrate comprises a first insulating layer. Between the opening and the effective display area of the display screen, a gate line is provided on the lower surface of the first insulating layer.
  • the array substrate is further included between the opening and the effective display area of the display screen, and an auxiliary conductive layer is disposed above the first insulating layer.
  • a capacitance called a first capacitance, can be formed between the auxiliary conductive layer and the gate line between the opening and the effective display area of the display screen.
  • the auxiliary conductive layer may be supplied with the same voltage as the common electrode layer.
  • the voltage across the gate line between the opening and the effective display area of the display screen needs to be charged to the first capacitor, so that the gate line between the opening and the effective display area of the display screen can be increased.
  • the load reaches a charging time of at least one row of sub-pixels in the display area on both sides of the opening such that a row of sub-pixels on either side of the opening and a row of sub-pixels below the opening have the same or substantially the same charging time.
  • the deflection speed of the liquid crystal molecules corresponding to the position of the display area on both sides of the opening is approximately the same as the deflection speed of the liquid crystal molecules corresponding to the position of the display area below the opening, thereby reducing the occurrence of horizontal stripes or flicker, and the like.
  • the probability of an anomaly is approximately the same as the deflection speed of the liquid crystal molecules corresponding to the position of the display area below the opening, thereby reducing the occurrence of horizontal stripes or flicker, and the like.
  • the array substrate further includes a common electrode layer, the common electrode layer being located above the first insulating layer.
  • an auxiliary conductive layer in the same layer as the common electrode layer may be formed by a masking and exposure process.
  • the auxiliary conductive layer and the common electrode layer are integrated.
  • the auxiliary conductive layer can also receive the above-mentioned common voltage.
  • the first insulating layer is a gate insulating layer; the array substrate further includes a data line contacting the upper surface of the gate insulating layer, and covering the surface of the data line. a second insulating layer, a pixel electrode on an upper surface of the second insulating layer, and a third insulating layer on an upper surface of the pixel electrode.
  • the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the third insulating layer.
  • the first insulating layer is a gate insulating layer; the array substrate further includes a data line contacting the upper surface of the gate insulating layer, and covering the surface of the data line The second insulating layer.
  • the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the second insulating layer.
  • the array substrate further includes a gate insulating layer; the gate line is located on the upper surface of the gate insulating layer.
  • the array substrate further includes a pixel electrode on an upper surface of the first insulating layer, and a third insulating layer on an upper surface of the pixel electrode.
  • the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the third insulating layer.
  • the array substrate further includes a data line contacting the upper surface of the first insulating layer, a second insulating layer covering the data line, a pixel electrode on the upper surface of the second insulating layer, and a third insulating layer on the upper surface of the pixel electrode Floor.
  • the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the third insulating layer.
  • the line width of the gate line between the opening and the effective display area of the display screen is greater than the line width of the gate line of the effective display area. Therefore, the load of the gate line between the opening and the effective display area of the display screen can be increased.
  • a data line crossing the gate line is disposed above the first insulating layer.
  • two adjacent data lines and two adjacent two gate lines define a dummy sub-pixel.
  • a thin film transistor is further disposed in the dummy sub-pixel. The gate of the thin film transistor is connected to the gate line, the first pole is connected to the data line, and the second pole is vacant.
  • the parasitic capacitance of the TFT disposed in the dummy sub-pixel can increase the amount of capacitance connected to the gate line between the opening and the effective display area of the display screen, thereby increasing the gap between the opening through the effective display area of the display screen The load of the grid lines.
  • the auxiliary conductive layer comprises at least one row of sub-electrodes spaced apart and electrically connected to each other.
  • the compensation amount of the capacitance connected to the gate line between the opening and the effective display area of the display screen can be obtained, and then the distribution density and shape of a row of sub-electrodes for covering the gate line are set according to the compensation amount.
  • the purpose of capacitor compensation is not limited to capacitor compensation.
  • the orthographic projection of the gate line between the opening and the effective display area of the display screen on the substrate of the array substrate and the auxiliary conductive layer on the substrate At least partially overlapping the orthographic projections such that a portion of the auxiliary conductive layer acts as a plate of the capacitor, and a gate line extending between the opening and the effective display area of the display screen and overlapping the auxiliary conductive layer The other plate of the above capacitor.
  • the opening is a groove disposed on at least one side of the display screen and recessed toward the inside of the display screen.
  • the above grooves are used to set the receiver, the sensor, the microphone, and the like.
  • the array substrate further includes an upper electrode, and the upper electrode is located above the first insulating layer.
  • a mask and an exposure process may be used.
  • An auxiliary conductive layer in the same layer as the upper electrode is formed.
  • the array substrate further includes a pixel defining layer above the first insulating layer.
  • the auxiliary conductive layer is located on an upper surface of the pixel defining layer.
  • the line width of the gate line between the opening and the effective display area of the display screen is greater than the line width of the gate line of the effective display area. Therefore, the load of the gate line between the opening and the effective display area of the display screen can be increased.
  • a data line crossing the gate line is disposed above the first insulating layer.
  • two adjacent data lines and two adjacent two gate lines define a dummy sub-pixel.
  • a thin film transistor is further disposed in the dummy sub-pixel. The gate of the thin film transistor is connected to the gate line, the first pole is connected to the data line, and the second pole is vacant.
  • the parasitic capacitance of the TFT disposed in the dummy sub-pixel can increase the amount of capacitance connected to the gate line between the opening and the effective display area of the display screen, thereby increasing the gap between the opening through the effective display area of the display screen The load of the grid lines.
  • the auxiliary conductive layer comprises at least one row of sub-electrodes spaced apart and electrically connected to each other.
  • the compensation amount of the capacitance connected to the gate line between the opening and the effective display area of the display screen can be obtained, and then the distribution density and shape of a row of sub-electrodes for covering the gate line are set according to the compensation amount.
  • the purpose of capacitor compensation is not limited to capacitor compensation.
  • the orthographic projection of the gate line between the opening and the effective display area of the display screen on the substrate of the array substrate and the auxiliary conductive layer on the substrate At least partially overlapping the orthographic projections such that a portion of the auxiliary conductive layer acts as a plate of the capacitor, and a gate line extending between the opening and the effective display area of the display screen and overlapping the auxiliary conductive layer The other plate of the above capacitor.
  • the opening is a groove disposed on at least one side of the display screen and recessed toward the inside of the display screen.
  • the above grooves are used to set the receiver, the sensor, the microphone, and the like.
  • a display screen having an opening.
  • the display screen includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer is disposed between the array substrate and the counter substrate.
  • the array substrate comprises a first insulating layer. Between the opening and the effective display area of the display screen, a gate line is provided on the lower surface of the first insulating layer.
  • the counter substrate further includes an auxiliary conductive layer, the orthographic projection of the auxiliary conductive layer on the substrate of the substrate substrate being located between the opening and the effective display area of the display screen.
  • the pair of cassette substrates further includes a common electrode layer.
  • an auxiliary conductive layer in the same layer as the common electrode layer may be formed by a masking and exposure process.
  • the auxiliary conductive layer and the common electrode layer are integrated.
  • the auxiliary conductive layer can also receive the above-mentioned common voltage.
  • the line width of the gate line between the opening and the effective display area of the display screen is greater than the line width of the gate line of the effective display area. Therefore, the load of the gate line between the opening and the effective display area of the display screen can be increased.
  • a data line crossing the gate line is disposed above the first insulating layer.
  • two adjacent data lines and two adjacent two gate lines define a dummy sub-pixel.
  • a thin film transistor is further disposed in the dummy sub-pixel. The gate of the thin film transistor is connected to the gate line, the first pole is connected to the data line, and the second pole is vacant.
  • the parasitic capacitance of the TFT disposed in the dummy sub-pixel can increase the amount of capacitance connected to the gate line between the opening and the effective display area of the display screen, thereby increasing the gap between the opening through the effective display area of the display screen The load of the grid lines.
  • the auxiliary conductive layer comprises at least one row of sub-electrodes spaced apart and electrically connected to each other.
  • the compensation amount of the capacitance connected to the gate line between the opening and the effective display area of the display screen can be obtained, and then the distribution density and shape of a row of sub-electrodes for covering the gate line are set according to the compensation amount.
  • the purpose of capacitor compensation is not limited to capacitor compensation.
  • the orthographic projection of the gate line between the opening and the effective display area of the display screen on the substrate of the array substrate and the auxiliary conductive layer on the substrate At least partially overlapping the orthographic projections such that a portion of the auxiliary conductive layer acts as a plate of the capacitor, and a gate line extending between the opening and the effective display area of the display screen and overlapping the auxiliary conductive layer The other plate of the above capacitor.
  • the opening is a groove disposed on at least one side of the display screen and recessed toward the inside of the display screen.
  • the above grooves are used to set the receiver, the sensor, the microphone, and the like.
  • a terminal device comprising any of the display screens described above.
  • the terminal device has the same technical effects as the above display screen, and details are not described herein again.
  • 1a is a schematic structural view of a display screen provided by the present application.
  • 1b is a schematic structural view of a display screen provided by the present application.
  • FIG. 2 is a schematic longitudinal cross-sectional structural view of a display screen according to an embodiment of the present application
  • FIG. 3 is a schematic structural view of an array substrate in the display screen shown in FIG. 2;
  • Figure 4a is a schematic view of the effective display area of the display screen shown in Figure 1a;
  • FIG. 4b is a schematic diagram of a region division of the effective display area shown in FIG. 4b;
  • FIG. 5 is a schematic structural diagram of an array substrate provided by the present application.
  • FIG. 6 is another schematic structural diagram of an array substrate provided by the present application.
  • FIG. 7 is a schematic longitudinal cross-sectional structural view of a display screen having a bottom gate type TFT provided by the present application.
  • FIG. 8 is a schematic longitudinal cross-sectional structural view of a display screen having a top gate type TFT provided by the present application;
  • FIG. 9 is another schematic longitudinal cross-sectional structural view of a display screen having a top gate TFT provided by the present application.
  • FIG. 10 is a top plan view showing a sub-pixel in the structure shown in FIG. 2;
  • FIG. 11 is a schematic diagram of a capacitor compensation scheme according to the structure shown in FIG. 6 according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a principle of capacitance compensation for the structure shown in FIG. 11;
  • FIG. 13 is a schematic diagram of another capacitor compensation scheme provided by the embodiment of the present application based on the structure shown in FIG. 6;
  • FIG. 14 is a schematic diagram of still another capacitance compensation scheme provided by the embodiment of the present application based on the structure shown in FIG. 6;
  • 15 is a schematic structural diagram of another display screen provided by the present application.
  • FIG. 16 is a schematic diagram of a capacitor compensation scheme provided by the embodiment of the present application, in combination with the structure shown in FIG. 15 and FIG. 6;
  • 17 is a schematic diagram of a driving manner of a display screen provided by the present application.
  • 19 is a schematic structural diagram of an array substrate of an OLED display screen provided by the present application.
  • FIG. 20 is a schematic structural view of a sub-pixel of FIG. 19;
  • 21 is a schematic longitudinal cross-sectional structural view of an OLED display device having the array substrate shown in FIG. 19.
  • first and second are used for descriptive purposes only, and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly. In the description of the embodiments of the present application, “multiple” means two or more unless otherwise stated.
  • the display screen according to the embodiment of the present application may be a Thin Film Transistor-Liquid Crystal Display (TFT-LCD).
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the TFT-LCD includes an array substrate 100 and a counter substrate 200 which are disposed opposite each other. Further, the TFT-LCD further includes a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.
  • the array substrate 100 includes a substrate 01 and respective thin film layers sequentially formed over the substrate 01.
  • the array substrate 100 includes a first insulating layer 301 and a common electrode layer 500.
  • the common electrode layer 500 is located above the first insulating layer 301.
  • the lower surface of the first insulating layer 301 is provided with a gate line (Gate Line, GL) as shown in FIG. 3 and a drain of the TFT of the same layer as the GL shown in FIG. 2.
  • a gate line Gate Line, GL
  • an insulating layer covering GL and the upper surface of the gate g of the TFT of the same layer as the GL is referred to as a first insulating layer 301.
  • a thin film layer above a thin film layer is formed after the first insulating layer 301 is formed on the substrate 01.
  • the first insulating layer 301 faces away from the film layer on the side of the substrate 01, for example, the common electrode layer 500 described above.
  • the common electrode layer 500 and the first insulating layer 301 may have at least one other thin film layer. For example, in FIG.
  • FIG. 2 is only a description of the distance of the structure of an array substrate, and the present application is not limited thereto.
  • a data line (Date Line, DL) crossing the GL is further disposed on the array substrate 100.
  • the DL may be disposed in the same layer as the source s or the drain d of the TFT in FIG.
  • some thin film layers may be formed on the substrate 01 by a film forming process (for example, the first insulating layer 301 formed by a coating process), and some thin film layers may be formed.
  • a predetermined pattern for example, GL, DL, gate g of the TFT, source s, and drain d
  • the patterning process includes a photolithography process, an etching step, and the like for forming a predetermined pattern.
  • the above photolithography process includes a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like in a process of film formation, masking, exposure, development, and the like.
  • the above substrate 01 may be a glass substrate or a substrate made of an organic material. This application does not limit this.
  • a method of forming a patterned thin film layer by a photolithography process will be described by taking the formation of DL and the gate g of the TFT as an example.
  • a film forming process such as a deposition process, is used to form a metal thin film layer on the substrate 01 (for example, the metal thin film layer may be composed of molybdenum), and then a photoresist is coated on the metal thin film layer, and then Masking the photoresist with a mask, so that a part of the photoresist is irradiated with light passing through the mask, and the other part is blocked by the light-shielding area on the mask, and is not irradiated with light; Developing the photoresist, taking the photoresist as a positive glue, the portion of the photoresist that is irradiated with the light is dissolved by the developer to expose the metal thin film layer; and then the photoresist The metal thin film layer exposed in the developed region is etched; next, the photore
  • the rectangular area defined by the adjacent two GLs and the adjacent two DL horizontal and vertical intersections is called a sub-pixel (Sub Pixel).
  • a TFT is disposed at the intersection of GL and DL.
  • the gate g of the TFT is connected to the GL
  • the first pole is connected to the DL
  • the second pole is connected to the pixel electrode 501.
  • the first pole of the TFT may be the source s of the TFT
  • the second pole may be the drain d of the TFT
  • the first pole of the TFT may be the drain d of the TFT and the source s of the second TFT.
  • the TFT-LCD further includes a color filter layer disposed on the array substrate 100 or disposed on the counter substrate 200 as shown in FIG. 2, and the color filter layer includes a plurality of filter units 210. At least three sequentially arranged sub-pixels constitute one pixel (Pixel). The position of each sub-pixel in the pixel (Pixel) is in one-to-one correspondence with the position of the filter unit 210 of one color, so that the three sub-pixels in the pixel (Pixel) are filtered by different filter units 210. It is capable of emitting light of different colors, for example, red (R), green (G), and blue (B) light, respectively.
  • RGB red
  • G green
  • B blue
  • the counter substrate 200 provided with the above color filter layer may be referred to as a color filter substrate.
  • a black matrix (BM) for shielding the DL, GL, and TFT on the array substrate 100 is further provided on the cartridge substrate 200.
  • the display screen provided by the present application is provided with an opening 10 as shown in FIG. 4a.
  • the special-shaped cutting process may be used to cut off the local area of the array substrate 100 and the color filter substrate 200 in the display screen at the same position, thereby forming the opening 10.
  • the opening 10 can be used to place a camera, a receiver, a sensor, a microphone, etc., which need to be integrated into the display.
  • the opening 10 can be disposed at any position of the display screen.
  • a part of the structure of the display screen can be cut inwardly on one side of the array substrate 100 (for example, the upper side).
  • the opening 10 is formed, and the opening 10 at this time is a groove which is recessed toward the inside of the display screen.
  • the edge of the opening 10 can be part of the edge of the display screen.
  • part of the structure of the display screen may be cut off inside the four sides of the display screen to form an opening 10. At this time, any side of the display screen remains in its original shape.
  • the opening 10 is a groove, and the groove is disposed at an intermediate position of the upper side of the display screen as an example.
  • the effective display area (AA) of the display screen needs to bypass the opening 10, so the effective display area of the display screen is no longer a Complete rectangle.
  • the effective display area of the above display screen can be divided into the sub-display area 11 on both sides of the opening 10 and the main display area 12 located below the opening 10 and the sub-display area.
  • the sub-pixels in the main display area 12 are arranged in a matrix form, and along the extending direction of the GL, the gates g of the TFTs in the sub-pixels of the same row in the main display area 12 are the same as the same GL electrical connection. Based on this, a plurality of sub-pixels in the main display area 12 that receive the same GL output signal are evenly arranged from the left end (or the right end) of the array substrate 100 to the right end (or the left end). At this time, the main display area 12 is arranged with a plurality of rows of entire sub-pixels.
  • the gate g of the TFT of the same row of sub-pixels still needs to be connected to the same strip GL, but due to the presence of the above-mentioned opening 10, the sub-display area on the left side of the opening 10
  • the GL in 11 needs to pass through the area between the opening 10 and the effective display area of the display screen to route around the opening 10 and then extend to the sub-display area 11 on the right side of the opening 10, thereby opening the left side of the opening 10 and
  • the gates g of the TFTs in the sub-pixels on the right side of the same row are electrically connected.
  • the width of the area between the opening 10 and the effective display area of the display screen is generally less than or equal to about 1 mm.
  • orientation terms such as “left”, “right”, “upper”, and “lower” are defined relative to the orientation of the array substrate or display screen in the drawing, and it should be understood that these directionalities are understood. Terms are relative concepts that are used in relation to the description and clarification, which may vary accordingly depending on the orientation of the array substrate or display screen.
  • the sub-pixels receiving the same GL output signal are affected by the opening 10, and the entire line cannot be arranged. Therefore, the number of sub-pixels in one row in the sub-display area 11 is small, and the number of sub-pixels in one line in the main display area 12 is large.
  • the common electrode layer 500 in the array substrate 100 is distributed over the entire effective display area of the display screen.
  • the orthographic projection of the pixel electrode 501 in each sub-pixel in the effective display region on the substrate 01 of the array substrate overlaps with at least a portion of the orthographic projection of the common electrode layer 500 on the substrate 01.
  • the common electrode layer 500 and the pixel electrode 501 are different layers, there is an insulating layer between the common electrode layer 500 and the pixel electrode 501, which is referred to as a third insulating layer 303 in the present application.
  • the material constituting the third insulating layer 303 may be silicon nitride.
  • the common electrode layer 500 and the pixel electrode 501 are insulated from each other, so that each pixel electrode 501 can form a capacitance between the common electrode layer 500 for controlling the deflection of the liquid crystal molecules, which is called a liquid crystal capacitor C LC. .
  • each DL transfers the data voltage Vdata to the pixel electrode 501 through the turned-on TFT to charge the sub-pixel.
  • a common voltage Vcom is supplied to the common electrode layer 500.
  • the liquid crystal capacitor C LC formed by the common electrode layer 500 and the pixel electrode 501 can control the liquid crystal molecules at the corresponding positions of the sub-pixels of the pixel electrode 501 to be deflected, thereby controlling the transmittance of the light emitted by each sub-pixel. In turn, the display of each gray scale is realized.
  • the light can be displayed in color under the color filter of each of the filter units 210 in the color filter layer.
  • the number of sub-pixels in one sub-display area 11 in FIG. 5 is small, and the number of sub-pixels in one line in the main display area 12 is large. Therefore, in order to reduce the difference in charging time between one row of sub-pixels of the sub-display area 11 and one line of sub-pixels of the main display area 12, the present application provides the following embodiments.
  • the array substrate 100 of the display screen provided by the present application further includes an auxiliary conductive layer 20 disposed between the opening 10 and the effective display area of the display screen and located above the first insulating layer 301.
  • the GL between the opening 10 and the effective display area of the display screen is disposed on the lower surface of the first insulating layer 301.
  • the GL between the auxiliary conductive layer 20 and the opening 10 and the effective display area of the display screen may be differently layered and insulated.
  • the orthographic projection of the GL between the opening and the effective display area of the display screen on the substrate 01 of the array substrate 100 at least partially overlaps the orthographic projection of the auxiliary conductive layer 20 on the substrate 01. Therefore, a capacitance, called a first capacitance C1, can be formed between the auxiliary conductive layer 20 and the GL between the opening 10 and the effective display area of the display screen.
  • GL disposed between the opening and the effective display area of the display screen is referred to as a first gate line, abbreviated as GL1.
  • the GL1 can be extended to the sub-display area 11 and electrically connected to the gate g of the TFT in the sub-pixel of the sub-display area 11, thereby controlling the sub-pixels in the sub-display area 11.
  • GL disposed in the main display area 12 is referred to as a second gate line, abbreviated as GL2.
  • the auxiliary conductive layer 20 may be supplied with the same voltage as the common electrode layer 500, that is, the common voltage Vcom.
  • the voltage on the GL1 needs to be formed to the auxiliary conductive layer 20 and the GL1.
  • the first capacitor C1 is charged, so that the load of the GL1 can be increased to extend the charging time of at least one row of sub-pixels in the sub-display area 11, so that one row of sub-pixels of the sub-display area 11 and one row of sub-pixels of the main display area 12 are charged.
  • the time is the same or basically the same.
  • the deflection speed of the liquid crystal molecules corresponding to the position of the sub-display region 11 is approximately the same as the deflection speed of the liquid crystal molecules corresponding to the position of the main display region 12.
  • the sub-display area 11 and the main display area 12 are both converted from a black screen to a white screen for display. Since the deflection speeds of the liquid crystal molecules corresponding to the two pixel regions are approximately the same, the light provided by the backlight module is The liquid crystal molecules corresponding to the sub display area 11 are not advanced in advance, so that the sub display area 11 displays a white picture in preference to the main display area 12, thereby being able to reduce the display between the white pictures due to the sub display area 11 and the main display area 12. There are successive differences that lead to the occurrence of anomalies such as horizontal stripes or flicker.
  • the position of the auxiliary conductive layer 50 and the position of the auxiliary conductive layer 50 in the array substrate 100 are not limited, as long as the auxiliary conductive layer 50 can be ensured in the opening 10 . It is only between the effective display area of the display screen and above the first insulating layer 301.
  • the material constituting the auxiliary conductive layer 20 may be selected from the materials used to prepare the thin film layer having the conductive function in the array substrate 100.
  • a metal material constituting GL for example, metal molybdenum
  • a metal material constituting DL for example, aluminum titanium alloy
  • a transparent conductive material constituting the common electrode layer 500 and the pixel electrode 501 for example, indium tin oxide, is used.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • the auxiliary conductive layer 20 can be disposed in the same layer as the common electrode layer 500. Based on this, in order to simplify the fabrication process, as shown in FIG. 6, the auxiliary conductive layer 20 and the common electrode layer 500 may be integrally formed so as to be formed by a single mask exposure process.
  • the arrangement manner of the auxiliary conductive layer 20 will be exemplified for the array substrate 100 of different structures.
  • the TFT in each sub-pixel is formed on the array substrate 100 as a bottom-gate TFT.
  • the gate of the TFT is gated with respect to a gate insulating layer (GI) provided between the AL of the TFT and the gate g of the TFT.
  • GI gate insulating layer
  • the electrode g is first formed on the substrate 01.
  • the first insulating layer 301 covering the upper surface of the GL is the gate insulating layer, and the material constituting the gate insulating layer may be silicon nitride or silicon oxide.
  • the array substrate 100 further includes DL (the same as the source s and the drain d of the TFT) in contact with the upper surface of the gate insulating layer (ie, the first insulating layer 301). a second insulating layer 302 covering the upper surface of the DL, and a common electrode layer 500 on the upper surface of the second insulating layer 302. Since the auxiliary conductive layer 20 is disposed in the same layer as the common electrode layer 500, the above-described auxiliary conductive layer 20 is located on the upper surface of the second insulating layer 302.
  • the insulating layer between the DL and the transparent electrode (for example, the common electrode layer 500 or the pixel electrode 501) in this embodiment is referred to as a second insulating layer.
  • the upper surface of the second insulating layer 302 is used to fabricate a transparent electrode.
  • the material constituting the second insulating layer 302 may be an organic resin material.
  • the upper surface of the common electrode layer 500 has a third insulating layer 303, and the upper surface of the third insulating layer 303 has a pixel electrode 501.
  • the pixel electrode 501 is formed on the third insulating layer 303 and the common electrode layer 500.
  • the via hole on the second insulating layer 302 is electrically connected to the drain d of the TFT.
  • FIG. 2 is an illustration of the case where the pixel electrode 501 is positioned above the common electrode layer 500. Further, as shown in FIG. 7, the pixel electrode 501 may also be located below the common electrode layer 500.
  • the array substrate 100 includes DL (same layer as the source s and drain d of the TFT) in contact with the upper surface of the gate insulating layer (ie, the first insulating layer 301), and covers the upper surface of the DL.
  • the auxiliary conductive layer 20 in the same layer as the common electrode layer 500 is also located on the upper surface of the third insulating layer 303.
  • the TFT in each sub-pixel is formed on the array substrate 100 as a top-gate TFT.
  • the gate insulating layer Gate Insulator, GI
  • the AL of the TFT First made on the substrate 01.
  • the GL in the same layer as the gate g of the TFT is located on the upper surface of the gate insulating layer.
  • TFTs using a top gate structure can be fabricated using a low temperature polysilicon (LTPS) process.
  • the TFT prepared by the LTPS process has better conduction performance and higher mobility.
  • the array substrate 100 further includes a pixel electrode 501 on the upper surface of the first insulating layer 301, and a DL on the upper surface of the pixel electrode 501 (with the source s and the drain d of the TFT).
  • the same layer a third insulating layer 303 located on the upper surface of the DL and the pixel electrode 501.
  • the auxiliary conductive layer 20 in the same layer as the common electrode layer 500 is also located on the upper surface of the third insulating layer 303.
  • FIG. 8 is an illustration of the case where the pixel electrode 501 is positioned below the drain d (or DL) of the TFT. Further, as shown in FIG. 9, the pixel electrode 501 may also be located above the drain d (or DL) of the TFT.
  • the array substrate 100 further includes DL (the same layer as the source s and the drain d of the TFT) in contact with the upper surface of the first insulating layer 301, and a second insulating layer 302 covering the DL.
  • the auxiliary conductive layer 20 in the same layer as the common electrode layer 500 is also located on the upper surface of the third insulating layer 303.
  • FIG. 8 and FIG. 9 are described by taking the common electrode layer 500 above the pixel electrode 501 as an example.
  • the structure of the array substrate can be set with reference to FIG. 2, and details are not described herein again.
  • the common electrode layer 500 and the pixel electrode 501 in FIGS. 2, 7, 8, and 9 are all formed on the array substrate 100.
  • the electrode located above is a slit electrode
  • the electrode located below is a planar electrode.
  • the pixel electrode 501 is located above and the common electrode layer 500 is located below, so the pixel electrode 501 is slit-shaped, and the common electrode layer 500 is planar, and at this time, one sub-pixel
  • the specific structure of the slit-shaped pixel electrode 501 and the planar common electrode layer 500 is as shown in FIG.
  • the display panel constructed by using the above array substrate 100 is a Fringe Field Switching (FFS) type display screen.
  • the FFS type display screen can form a multi-dimensional electric field by a parallel electric field generated by an edge of a slit electrode (for example, the pixel electrode 501 in FIG. 10) in a plane, and a longitudinal electric field generated between the pixel electrode 501 and the common electrode layer 500.
  • the liquid crystal layer 300 is located between the slits of the pixel electrode 501, and all liquid crystal molecules between the pixel electrode 501 and the common electrode layer 500 can be driven to be deflected, thereby improving the light transmission efficiency of the liquid crystal layer and improving Display quality.
  • the pixel electrode 501 is simplified, and thus is not depicted as a slit-like structure.
  • a plurality of dummy sub-pixels 40 are disposed between the opening 10 and the effective display area of the display screen.
  • a DL crossing the GL (ie, the above GL1) is disposed above the first insulating layer 301.
  • the two adjacent DLs and the adjacent two GLs define a dummy sub-pixel 40.
  • a TFT is also disposed in the dummy sub-pixel 40.
  • the gate g of the TFT is connected to DL, the first pole is connected to GL, and the second pole is vacant. Since the second pole of the TFT in the dummy sub-pixel 40 is vacant, the sub-pixel 40 is not disposed on the pixel electrode 501 connected to the second pole of the TFT, so the dummy sub-pixel 40 cannot be displayed.
  • the data lines may be formed by metal lines different from the DL and GL, and one data lead is electrically connected to one DL in the main display area 12.
  • the dummy sub-pixels 40 are defined by the intersection of two adjacent data leads and two adjacent GLs.
  • the auxiliary conductive layer 20 and the GL1 which are integrally formed with the common electrode layer 500 are provided in a different layer and insulated, and the first capacitor C1 can be formed between the auxiliary conductive layers 20 and GL1.
  • the common electrode layer 500 and the GL2 are equally layered and insulated, and a second capacitor C2 may be formed between the common electrode layers 500 and GL2.
  • the capacitance values of the first capacitor G1 and the second capacitor G2 may be the same or approximately the same.
  • the interference generated on the auxiliary conductive layer 20 by the gate scan signal of the pulse wave on the GL1 is the same as or similar to the interference generated on the common electrode layer 500 by the gate scan signal on the GL2. The same, so that the difference between the sub display area 11 and the main display area 12 can be reduced.
  • the gates g and GL of the TFT are of the same material, and the source and drain d and drain d of the TFT are of the same material. Therefore, the TFT itself has a parasitic capacitance such as a parasitic capacitance Cgs between the gate g and the source s, and a parasitic capacitance Cgd between the gate g and the drain d. Therefore, by providing the above-described dummy sub-pixel 40, the parasitic capacitance of the plurality of TFTs can be formed between the opening 10 and the effective display area of the display screen.
  • the number of sub-pixels controlled by GL1 is m.
  • GL1 is connected with m liquid crystal capacitors C LC ;
  • GL2 is connected to main display area 12
  • the number of sub-pixels is n.
  • GL2 is connected with n liquid crystal capacitors C LC .
  • n>m,n,m are positive integers.
  • the GL1 is also connected to the parasitic capacitance of a plurality of TFTs.
  • the start of the GL1 receives the gate scan signal (the amplitude is Vg)
  • the gate scan signal transmission process for example, from left to right
  • m can be connected to the GL1.
  • the TFTs in the sub-pixels, and the TFTs in the nm dummy sub-pixels 40 are turned on, thereby charging the liquid crystal capacitors C LC and the parasitic capacitances in the dummy sub-pixels 40 in the sub-pixels, in this case the gate of the GL1 terminal
  • the amplitude of the scan signal is Vg1, where Vg1 is slightly less than Vg.
  • the gate scan signal transmission process (for example, from left to right) can be connected to the GL2.
  • the TFTs in the n sub-pixels are turned on to charge the liquid crystal capacitor C LC in the sub-pixel, in which case the amplitude of the gate scan signal at the end of the GL2 in the main display region 12 is Vg2, where Vg2 Slightly smaller than Vg.
  • the number of sub-pixels (m) controlled by GL1 is smaller than the number of sub-pixels (n) controlled by one GL2 in the main display area 12, but through the effective display area of the opening 10 and the display screen.
  • the dummy sub-pixels 40 are disposed between each other such that the parasitic capacitance of the TFTs disposed in the dummy sub-pixels 40 can increase the number of capacitors connected to the GL1, thereby achieving the purpose of increasing the GL1 load.
  • the voltage difference ⁇ V between the amplitude of the gate scan signal at the end of GL1 and the amplitude of the gate scan signal at the end of GL2 in the main display region 12, Vg2, can be made small.
  • the aspect ratio of the TFT in the dummy sub-pixel 40 described above can be appropriately increased to achieve the purpose of increasing the parasitic capacitance described above such that the voltage difference ⁇ V is approximately equal to zero.
  • the signal states of GL1 and GL2 in the main display area 12 are substantially identical, so that the charging time of one row of sub-pixels in the sub-display area 11 and one row of sub-pixels in the main display area 12 are substantially the same, thereby achieving a reduction. Blinking or horizontal stripes, etc., indicate poor purpose.
  • the line width of the GL between the opening 10 and the effective display area of the display screen is greater than the line width of the GL of the effective display area.
  • the line width of G1 is greater than the line width of G2.
  • the size of the liquid crystal capacitor C LC formed by the pixel electrode 501 and the common electrode layer 500 of each sub-pixel in the main display area 12 and the row of sub-pixels connected to the row GL2 in the main display area 12 can be calculated by software.
  • the total number n Further, a second capacitor C2 formed by the common electrode layer 500 and one of the main display regions 12, GL2, can also be obtained. Thereby, the size of the capacitance connected to one GL2 in the main display area 12 can be calculated, for example, n ⁇ C LC + C2.
  • the total number m of sub-pixels controlled by GL1 is obtained, and the sum of all liquid crystal capacitors C LC to which the row GL1 is connected is calculated, for example, m ⁇ C LC .
  • the difference between the two can be obtained, thereby obtaining a compensation value for compensating for the capacitance to which GL1 is connected.
  • the line width of the GL1 can be adjusted according to the capacitance compensation value obtained above to increase the capacitance value of the first capacitor C1, so that the size of the capacitance connected to the GL1 is, for example, m ⁇ C LC +C1 and
  • the size of the capacitor connected to one GL2 in the main display area 12 is, for example, the same or approximately the same as n ⁇ C LC + C2, and finally achieves the purpose of capacitance compensation.
  • the GL1 may include the first sub-portion 51 and the second sub-portion 52.
  • the first sub-portion 51 is parallel to the GL2 in the main display area 12, and the second sub-portion 52 intersects the first sub-portion 51.
  • the length of GL1 having the first sub-portion 51 and the second sub-portion 52 is long with respect to GL2 in the main display region 12, and therefore the resistance of GL1 is large.
  • the wiring space of the area where the second sub-portion 52 is located is small.
  • the line width of the first sub-portion 51 is greater than the line width of the second sub-portion 52
  • the line width of the second sub-portion 52 is greater than The line width of GL2 in the main display area 12.
  • the solution of the third embodiment is only required to adjust the line width of the GL1 between the opening 10 and the effective display area of the display screen, and the dummy sub-pixel 40 is required. Therefore, the area of the area between the opening 10 and the effective display area of the display screen in the third embodiment is small, so that the frame size of the display screen can be reduced.
  • the auxiliary conductive layer 20 includes at least one row of sub-electrodes 201 spaced apart from each other and electrically connected to each other.
  • the orthographic projection of the first row of sub-electrodes 201 on the substrate 01 in FIG. 14 overlaps with the portion of the first row and the second row GL1 that is orthographically projected on the substrate 01.
  • the auxiliary conductive layer 20 integrally formed with the common electrode layer 500 and the GL1 between the opening 10 and the effective display region of the display screen are disposed and insulated, the sub-electrodes 201 and GL1 of the auxiliary conductive layer 20 are A first capacitor C1 can be formed.
  • the larger the area where the orthographic projection of the sub-electrode 201 on the substrate 01 overlaps with the orthographic projection of GL1 on the substrate 01 the larger the capacitance to which the strip GL1 is connected. Therefore, as described above, it is possible to obtain the compensation amount of the capacitance to which the GL1 is connected, and then set the distribution density and shape of the row of sub-electrodes 201 for covering the GL1 in accordance with the compensation amount.
  • each row of sub-electrodes 201 may be the same. Further, as shown in FIG. 15, when the edge of the opening 10 is a beveled edge, as shown in FIG. 16, in the sub-display area 11, the number of sub-pixels of one line may be different.
  • each row of sub-electrodes 201 may be different.
  • the number of sub-pixels connected to the first row GL1 is smaller than the number of sub-pixels connected to the second row GL1.
  • the compensation value of the capacitance connected to the first row GL1 needs to be larger than the compensation value of the capacitance connected to the second row GL1.
  • the sub-electrodes 201 in the same row can simultaneously overlap the first row and the second row GL1, and each of the row electrode electrodes 201 has a trapezoidal shape, and the long side of the trapezoid is located above, trapezoidal The short side is located below, such that the area of the overlapping portion of the orthographic projection of the sub-electrode 201 on the substrate 01 and the orthographic projection of the first line GL1 on the substrate 01 is larger, and the sub-electrode 201 is on the substrate 01.
  • the area of the overlapping portion of the orthographic projection and the orthographic projection of the second line GL1 on the substrate 01 is small, and finally the capacitance connected to the two GL1s is the same as or approximately the same as the capacitance connected to the GL2 in the main display region 12.
  • the line width of the GL1 or, combining the schemes of the third embodiment and the fourth embodiment, that is, increasing the line width of the GL1 between the opening and the effective display area of the display screen, the effective display of the opening 10 and the display screen
  • the auxiliary conductive layer 20 between the regions is provided with a plurality of sub-electrodes 201 covering the GL1. Other combinations will not be repeated here.
  • an inactive display area on the array substrate 100 outside the sub-display area 11 and the main display area 12 is provided with an array driver on Array (GOA) circuit, and the GOA circuit includes a plurality of shifts.
  • Register Unit (RS) each level RS is connected to a row of GL.
  • the GOA circuit may be disposed in the non-effective display area on the left side, or the area of the non-effective display area is gradually reduced in order to meet the design requirements of the narrow bezel. Therefore, as shown in FIG. 17, the GOA may be divided into two parts. The odd-numbered RS is set to the non-effective display area on the left side, and the even-numbered level RS is set to the non-effective display area on the right side.
  • the first level RS1, the second level RS2, the third level RS3, and the fourth level RS4 are respectively connected to the GL1 in the first row, the second row, the third row, and the fourth row in the sub display area 11;
  • the stage RS5, the sixth stage RS6, the seventh stage RS7, and the eighth stage RS8 are respectively connected to the GL2 of the main display area 12 at the fifth line, the sixth line, the seventh line, and the eighth line position.
  • an above-described non-display area is provided with an integrated circuit (IC) connected to the GOA circuit and the source driver (not shown).
  • the source driver is coupled to the data line DL for providing a data voltage to the data line.
  • each of the RSs in the drive IC control GOA circuit outputs a gate scan signal to the gate line GL connected thereto step by step to realize progressive scan of all the gate lines.
  • Receiving a gate line of the gate scan signal for example, the GL1 at the first row position in the sub-display area 11 receives the gate scan signal, and the TFT in the sub-pixel connected to the GL1 is turned on, and The capacitance of the GL1 connected between the opening 10 and the effective display area of the display screen (for example, the capacitance formed by the common electrode layer 500 and GL1 in the scheme shown in FIG. 11) is in a charged state.
  • the driving IC controls the source driver to output a data voltage to each of the data lines DL, and the data voltage is transmitted to the pixel electrode 501 of the first row of sub-pixels through the turned-on TFT to charge the row of sub-pixels.
  • the time from the leftmost end to the rightmost sub-pixel of the first row being fully charged is extended, for example, the time is T.
  • the second stage RS2 outputs a gate scan signal to the GL1 located in the second row, and the charging process of the sub-pixel connected to the GL1 of the second row is the same as described above, except that the second row of sub-pixels Charging is performed from the right end to the left end, and the time at which the second row of sub-pixels are charged is the same or approximately the same as the above T.
  • the third stage RS3 and the fourth stage RS4 output a gate scan signal to the GL1 located in the third row and the GL1 located in the fourth row row by row.
  • the charging process of the third row of sub-pixels and the fourth row of sub-pixels will not be repeated here as described above.
  • the fifth stage RS5 outputs a gate scan signal to the GL2 located at the fifth row position in the main display area 12, and the sub-pixels arranged in the entire row connected to the GL2 are charged from left to right.
  • the charging process is the same as described above.
  • the number of the first row of sub-pixels in the sub-display area 11 is less than the number of the fifth row of sub-pixels in the main display area 12, it can be seen from the above that between the opening 10 and the effective display area of the display screen.
  • the charging process of the remaining rows of sub-pixels in the remaining main display area 12 is the same as described above, and will not be described herein. It can be seen from the above that although the number of sub-pixels in each row of the array substrate 100 is not completely the same under the influence of the opening 10, the solution provided in the present application can be in the effective display area of the opening 10 and the display screen. Capacitance is set to compensate the load of the gate line GL connecting less sub-pixels, so that the charging of each row of sub-pixels tends to be uniform, so that the liquid crystal molecules corresponding to different sub-pixels are deflected at the same speed, and the reduction is achieved. Small flashing or horizontal stripes, etc. show a bad chance.
  • the above embodiments are described by taking the auxiliary conductive layer 20 and the common electrode layer 500 on the array substrate 100 as an example.
  • the present application can also provide the above-mentioned auxiliary conductive layer 20 on the counter substrate 200, and the orthographic projection of the auxiliary conductive layer 20 on the substrate 01 of the base substrate 100 is located between the opening 10 and the effective display area of the display screen.
  • the auxiliary conductive layer 20 and the common electrode layer 500 may still be the same material and have an integrated structure to realize The auxiliary conductive layer 20 is disposed on the counter substrate 200.
  • the common electrode layer 500 is located on a side surface of the color filter layer composed of the plurality of filter units 210 adjacent to the array substrate 100.
  • the solution of the second embodiment can still be adopted on the array substrate 100, and a dummy sub-pixel 40 and a TFT located in the dummy sub-pixel 40 are formed between the opening 10 and the effective display area of the display screen; or the array
  • the substrate 100 can also adopt the solution of the third embodiment to increase at least a part of the line width of the GL1 between the opening 10 and the effective display area of the display screen; or alternatively, the structure of the array substrate 100 can be changed without changing the above
  • the auxiliary conductive layer 20 on the substrate substrate 100 in the manner of Embodiment 4, at least one row of mutually spaced and electrically connected sub-electrodes 201 are formed at positions between the corresponding openings 10 and the effective display regions of the display screen, and the sub-electrodes 201 are The orthographic projection on the substrate 01 of the array substrate 100 overlaps with the orthographic projection of at least one GL1 on the substrate 01 described above.
  • the display screen shown in FIG. 18 is a Twist Nematic (TN) type display screen.
  • the TN type display screen adopts a vertical electric field principle to drive a liquid crystal molecule in a twisted nematic mode by forming a vertical electric field between the common electrode layer 500 disposed on the counter substrate 200 and the pixel electrode 501 disposed on the array substrate 100. To achieve the purpose of display.
  • the above embodiments are all described by taking a TFT-LCD as an example.
  • the capacitor compensation scheme provided by the embodiment of the present application is also applicable to an organic light emitting diode (OLED) display.
  • OLED organic light emitting diode
  • the OLED display panel includes the array substrate 100 as shown in FIG. 19, and the array substrate 100 is formed with arrayed sub-pixels, and each sub-pixel is provided with an OLED as shown in FIG. A pixel circuit in which OLEDs are connected.
  • the present application does not limit the specific structure of the above pixel circuit.
  • the pixel circuit shown in FIG. 20 is merely an example of the simplest pixel circuit structure including the gate transistor Tc, the driving transistor Td, and the capacitor C. .
  • the cathode of the OLED in FIG. 20 is connected to the ground GND, and when the driving transistor Td is turned on, the voltage terminal VDD forms a voltage difference with the ground GND, so that a driving current flows through the OLED, and the OLED emits light.
  • the above pixel circuit may further include a compensation unit; or, in order to reset the anode of the OLED or the gate of the driving transistor Td, the pixel circuit may further include a reset unit.
  • the above compensation unit and reset unit are composed of a plurality of transistors, and the specific structure of the present application will not be repeated.
  • the longitudinal cross-sectional structure of the above OLED display panel is as shown in FIG. 21, and the OLEDs arrayed on the array substrate 100 can be seen.
  • the OLED includes an upper electrode 60 (eg, a cathode), a lower electrode 61 (eg, an anode), and an organic material functional layer 62 between the upper electrode 60 and the lower electrode 61.
  • the lower electrode 60 and the organic material functional layer 62 are located in the grooves provided in the pixel defining layer 63.
  • the lower electrode 61 is connected to a TFT of one sub-pixel, for example, the above-described driving transistor Td.
  • the organic material functional layer 62 may include a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and the like.
  • the upper electrode 60 may be an entire layer, and the upper electrode 60 covers an effective display area having the sub display area 11 and the main display area 12.
  • the auxiliary conductive layer 20 is disposed between the effective display area and the opening 10, and at least one GL1 between the opening 10 and the effective display area of the display screen is lining the array substrate 100.
  • the orthographic projection on the bottom 01 overlaps with a portion of the orthographic projection of the auxiliary conductive layer 20 on the substrate 01.
  • the auxiliary conductive layer 20 may be in the same layer as the upper electrode 60 and have an integral structure.
  • the upper electrode 60 and the GL1 similarly to the arrangement of the TFTs on the array substrate in the liquid crystal display, the upper electrode 60 and the GL1 have at least the first insulating layer 301 on the upper surface of the GL1. Therefore, the auxiliary conductive layer 20 in the same layer as the upper electrode 60 and the GL1 have at least the first insulating layer 301 as described above.
  • the auxiliary conductive layer 20 in the same layer as the upper electrode 60 and the GL1 may further include the first insulating layer.
  • the pixel above 301 defines a layer 63 that is formed on the upper surface of the pixel defining layer 63.
  • the auxiliary conductive layer 20 can form a capacitance with the GL1 between the opening 10 and the effective display area of the display screen, thereby achieving the purpose of increasing the load of the GL1.
  • the scheme of the second embodiment can still be adopted on the array substrate 100 in the OLED display, and the dummy sub-pixel 40 and the TFT located in the dummy sub-pixel 40 are formed between the opening 10 and the effective display area of the display screen; or
  • the array substrate 100 can also adopt the solution of the third embodiment to increase at least a part of the line width of the GL1 between the opening 10 and the effective display area of the display screen; or the structure of the array substrate 100 can be changed without changing
  • the auxiliary conductive layer 20 of the same structure as the upper electrode 60 is formed in the fourth embodiment, and at least one row of sub-electrodes 201 spaced apart from each other and electrically connected is formed between the opening 10 and the effective display area of the display screen.
  • the above OLED display panel further includes a package substrate 400.
  • the package substrate 400 is used to package an array substrate of an OLED display.
  • the present application provides a terminal device, including any of the above-mentioned display screens, and the structure and technical effects of the display screen are the same as those described above, and are not described herein again.
  • the terminal device can be a device with a display screen such as a mobile phone, a tablet, or a television.

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Abstract

一种显示屏及终端设备，涉及显示技术领域，能够减小显示屏显示过程中出现横纹或闪烁等异常现象的几率。上述显示屏开设有一开口（10）。该显示屏包括相对设置的阵列基板（100）和对盒基板（200），阵列基板（100）和对盒基板（200）之间设置有液晶层（300）。此外，阵列基板（100）包括第一绝缘层（301）以及公共电极层（500）。该公共电极层（500）位于第一绝缘层（301）的上方。在开口（10）与显示屏的有效显示区之间，在第一绝缘层（301）的下表面设有栅线（GL）。在开口（10）与显示屏的有效显示区之间，在第一绝缘层（301）的上方设置有辅助导电层（20）。辅助导电层（20）与公共电极层（500）同层。上述显示屏用于显示图像。

Description

一种显示屏及终端设备 技术领域
本申请涉及显示技术领域，尤其涉及一种显示屏及终端设备。
背景技术
随着显示装置，例如手机的功能不断趋于多样化的发展，手机中集成有多种用于实现不同功能的器件，例如摄像头、受话器、指纹采集用的光敏器件等。基于此，为了提高手机显示屏的屏占比(显示屏的有效显示区域与整个显示屏的比值)，现有技术中，如图1a所示，通常会在显示屏上开设有一开口10，从而可以将上述摄像头、受话器以及光敏器件等部件设置于上述开口10内。在此基础上，上述显示屏中位于该开口10两侧的部分仍然能够进行显示，而无需采用遮光材料进行遮挡，从而达到提高显示屏屏占比的目的。
然而，显示屏中由于上述开口10的存在，因此开口10位置处无法排布亚像素。在此情况下，图1a中开口10两侧被同一行栅线所驱动的亚像素(即同一行亚像素)需要绕开开口10而设置于该开口10的两侧，所以无法实现整行排布，而该开口10下方的同一行亚像素会不受到开口10的影响所以可以整行排布。因此，该开口10两侧同一行亚像素的数量会小于开口10下方同一行亚像素的数量。这样一来，显示屏在显示的过程中，开口10两侧的一行亚像素的充电时间和开口10下方一行亚像素的充电时间会有所差异，使得该开口10两侧的液晶分子的偏转速度与开口10下方液晶分子的偏转速度不同，从而导致显示屏在显示过程中出现横纹或闪烁等异常现象。
发明内容
本本发明实施例提供一种显示屏及终端设备，在显示屏设置有开槽区的情况下，能够减小显示屏显示过程中出现横纹或闪烁等异常现象的几率。
为达到上述目的，本实施例采用如下技术方案：
第一方面，提供一种显示屏，该显示屏开设有一开口。此外，该显示屏包括相对设置的阵列基板和对盒基板，阵列基板和对盒基板之间设置有液晶层。其中，阵列基板包括第一绝缘层。在开口与显示屏的有效显示区之间，在第一绝缘层的下表面设有栅线。此外，阵列基板还包括在开口与显示屏的有效显示区之间，且在第一绝缘层的上方设置有辅助导电层。在此情况下，辅助导电层和该开口与该显示屏的有效显示区之间栅线的之间可以形成电容，称为第一电容。在显示过程中，可以向上述辅助导电层提供与公共电极层相同的电压。此时，穿过上述开口与该显示屏的有效显示区之间栅线上的电压需要向上述第一电容进行充电，从而能够增加穿过上述开口与该显示屏的有效显示区之间栅线的负载，达到开口两侧的显示区中至少一行亚像素的充电时间，使得开口两侧的一行亚像素和开口下方的一行亚像素的充电时间相同或基本相同。这样一来，开与口两侧的显示区位置相对应的液晶分子的偏转速度和与开口下方的显示区位置相对应的液晶分子的偏转速度近似相同，从而可以减小出现横纹或闪烁等异常现象的几率。
结合第一方面，在将阵列基板应用于液晶显示屏的设计中，该阵列基板还包括公共电极层，该公共电极层位于第一绝缘层的上方。为了简化制作工艺，可以采用一次掩膜、曝光工艺形成与该公共电极层同层的辅助导电层。
可选的，在将阵列基板应用于液晶显示屏的设计中，辅助导电层与公共电极层为一体结构。在显示的过程中，只需要向公共电极层提供公共电压，该辅助导电层也可以接收到上述公共电压。
可选的，在将阵列基板应用于液晶显示屏的设计中，第一绝缘层为栅极绝缘层；阵列基板还包括与栅极绝缘层的上表面接触的数据线、覆盖数据线上表面的第二绝缘层、位于第二绝缘层上表面的像素电极，以及位于像素电极上表面的第三绝缘层。在此情况下，与公共电极层同层的辅助导电层位于第三绝缘层的上表面。实现在具有底栅型TFT的阵列基板上设置辅助导电层的一种方案。
可选的，在将阵列基板应用于液晶显示屏的设计中，第一绝缘层为栅极绝缘层；阵列基板还包括与栅极绝缘层的上表面接触的数据线，以及覆盖数据线上表面的第二绝缘层。在此情况下，与公共电极层同层的辅助导电层位于第二绝缘层的上表面。实现在具有底栅型TFT的阵列基板上设置辅助导电层的另一种方案。
可选的，在将阵列基板应用于液晶显示屏的设计中，阵列基板还包括栅极绝缘层；栅线位于栅极绝缘层的上表面。此外，阵列基板还包括位于第一绝缘层上表面的像素电极，以及位于像素电极上表面的第三绝缘层。在此情况下，与公共电极层同层的辅助导电层位于第三绝缘层的上表面。或者，阵列基板还包括与第一绝缘层的上表面相接触的数据线、覆盖数据线的第二绝缘层、位于第二绝缘层上表面的像素电极，以及位于像素电极上表面的第三绝缘层。在此情况下，与公共电极层同层的辅助导电层位于第三绝缘层的上表面。实现在具有顶栅型TFT的阵列基板上设置辅助导电层的方案。
可选的，在将阵列基板应用于液晶显示屏的设计中，在开口与显示屏的有效显示区之间的栅线的线宽大于有效显示区的栅线的线宽。从而可以增大穿过开口与显示屏的有效显示区之间的栅线的负载。
可选的，在将阵列基板应用于液晶显示屏的设计中，在开口与显示屏的有效显示区之间，在第一绝缘层上方设置有与栅线交叉的数据线。此外，相邻的两条数据线和相邻的两条栅线交叉界定一个虚设亚像素。其中，该虚设亚像素内还设置有薄膜晶体管。薄膜晶体管的栅极连接栅线，第一极连接数据线，第二极空置。设置于虚设亚像素中的TFT的寄生电容能够增加穿过开口与显示屏的有效显示区之间的栅线所连接的电容的数量，从而达到增加穿过开口与显示屏的有效显示区之间的栅线的负载。
可选的，在将阵列基板应用于液晶显示屏的设计中，辅助导电层包括至少一排间隔设置，且相互电连接的多个子电极。该开口与显示屏的有效显示区之间的栅线在阵列基板的衬底上的正投影与至少一排子电极在衬底上的正投影的至少部分重叠。子电极在阵列基板衬底上的正投影与穿过开口与显示屏的有效显示区之间的栅线在衬底上的正投影重叠的面积越大，穿过开口与显示屏的有效显示区之间的栅线所连接的电容越大。因此可以获取穿过开口与显示屏的有效显示区之间的栅线所连接的电容的补偿量，然后根据补偿量设定用于覆盖上述栅线的一排子电极的分布密度和形状，达到电容补偿的目的。
可选的，在将阵列基板应用于液晶显示屏的设计中，开口与显示屏的有效显示区之间的栅线在阵列基板的衬底上的正投影与辅助导电层在所述衬底上的正投影的至少部分重叠，从而可以使得辅助导电层的一部分作为电容的一个极板，而穿过开口与显示屏的有效显示区之间的，且正投影与辅助导电层重叠的栅线作为上述电容的另一个极板。
可选的，在将阵列基板应用于液晶显示屏的设计中，开口为设置于显示屏至少一边且向显示屏内部凹陷的凹槽。上述凹槽用于设置受话器、传感器以及送话器等。
结合第一方面，在将阵列基板应用于OLED显示屏的设计中，该阵列基板还包括上电极，该上电极位于第一绝缘层的上方，为了简化制作工艺，可以采用一次掩膜、曝光工艺形成与该上电极同层的辅助导电层。
可选的，在将阵列基板应用于OLED显示屏的设计中，阵列基板还包括位于第一绝缘层上方的像素界定层。该辅助导电层位于像素界定层的上表面。
可选的，在将阵列基板应用于OLED显示屏的设计中，在开口与显示屏的有效显示区之间的栅线的线宽大于有效显示区的栅线的线宽。从而可以增大穿过开口与显示屏的有效显示区之间的栅线的负载。
可选的，在将阵列基板应用于OLED显示屏的设计中，在开口与显示屏的有效显示区之间，在第一绝缘层上方设置有与栅线交叉的数据线。此外，相邻的两条数据线和相邻的两条栅线交叉界定一个虚设亚像素。其中，该虚设亚像素内还设置有薄膜晶体管。薄膜晶体管的栅极连接栅线，第一极连接数据线，第二极空置。设置于虚设亚像素中的TFT的寄生电容能够增加穿过开口与显示屏的有效显示区之间的栅线所连接的电容的数量，从而达到增加穿过开口与显示屏的有效显示区之间的栅线的负载。
可选的，在将阵列基板应用于OLED显示屏的设计中，辅助导电层包括至少一排间隔设置，且相互电连接的多个子电极。该开口与显示屏的有效显示区之间的栅线在阵列基板的衬底上的正投影与至少一排子电极在衬底上的正投影的至少部分重叠。子电极在阵列基板衬底上的正投影与穿过开口与显示屏的有效显示区之间的栅线在衬底上的正投影重叠的面积越大，穿过开口与显示屏的有效显示区之间的栅线所连接的电容越大。因此可以获取穿过开口与显示屏的有效显示区之间的栅线所连接的电容的补偿量，然后根据补偿量设定用于覆盖上述栅线的一排子电极的分布密度和形状，达到电容补偿的目的。
可选的，在将阵列基板应用于OLED显示屏的设计中，开口与显示屏的有效显示区之间的栅线在阵列基板的衬底上的正投影与辅助导电层在所述衬底上的正投影的至少部分重叠，从而可以使得辅助导电层的一部分作为电容的一个极板，而穿过开口与显示屏的有效显示区之间的，且正投影与辅助导电层重叠的栅线作为上述电容的另一个极板。
可选的，在将阵列基板应用于OLED显示屏的设计中，开口为设置于显示屏至少一边且向显示屏内部凹陷的凹槽。上述凹槽用于设置受话器、传感器以及送话器等。
第二方面，提供一种显示屏，该显示屏开设有一开口。此外，该显示屏包括相对设置的阵列基板和对盒基板，阵列基板和对盒基板之间设置有液晶层。其中，阵列基板包括第一绝缘层。在开口与显示屏的有效显示区之间，在第一绝缘层的下表面设有 栅线。此外，对盒基板还包括辅助导电层，该辅助导电层在衬底基板的衬底上的正投影位于开口与显示屏的有效显示区之间。该显示屏具有与第一方面提供的显示屏相同的技术效果，此处不再赘述。
结合第二方面，在将阵列基板应用于液晶显示屏的设计中，该对盒基板还包括公共电极层。为了简化制作工艺，可以采用一次掩膜、曝光工艺形成与公共电极层同层的辅助导电层。
可选的，在将阵列基板应用于液晶显示屏的设计中，辅助导电层与公共电极层为一体结构。在显示的过程中，只需要向公共电极层提供公共电压，该辅助导电层也可以接收到上述公共电压。
可选的，在将阵列基板应用于液晶显示屏的设计中，在开口与显示屏的有效显示区之间的栅线的线宽大于有效显示区的栅线的线宽。从而可以增大穿过开口与显示屏的有效显示区之间的栅线的负载。
可选的，在将阵列基板应用于液晶显示屏的设计中，在开口与显示屏的有效显示区之间，在第一绝缘层上方设置有与栅线交叉的数据线。此外，相邻的两条数据线和相邻的两条栅线交叉界定一个虚设亚像素。其中，该虚设亚像素内还设置有薄膜晶体管。薄膜晶体管的栅极连接栅线，第一极连接数据线，第二极空置。设置于虚设亚像素中的TFT的寄生电容能够增加穿过开口与显示屏的有效显示区之间的栅线所连接的电容的数量，从而达到增加穿过开口与显示屏的有效显示区之间的栅线的负载。
可选的，在将阵列基板应用于液晶显示屏的设计中，辅助导电层包括至少一排间隔设置，且相互电连接的多个子电极。该开口与显示屏的有效显示区之间的栅线在阵列基板的衬底上的正投影与至少一排子电极在衬底上的正投影的至少部分重叠。子电极在阵列基板衬底上的正投影与穿过开口与显示屏的有效显示区之间的栅线在衬底上的正投影重叠的面积越大，穿过开口与显示屏的有效显示区之间的栅线所连接的电容越大。因此可以获取穿过开口与显示屏的有效显示区之间的栅线所连接的电容的补偿量，然后根据补偿量设定用于覆盖上述栅线的一排子电极的分布密度和形状，达到电容补偿的目的。
可选的，在将阵列基板应用于液晶显示屏的设计中，开口与显示屏的有效显示区之间的栅线在阵列基板的衬底上的正投影与辅助导电层在所述衬底上的正投影的至少部分重叠，从而可以使得辅助导电层的一部分作为电容的一个极板，而穿过开口与显示屏的有效显示区之间的，且正投影与辅助导电层重叠的栅线作为上述电容的另一个极板。
可选的，在将阵列基板应用于液晶显示屏的设计中，开口为设置于显示屏至少一边且向显示屏内部凹陷的凹槽。上述凹槽用于设置受话器、传感器以及送话器等。
第三方面，提供一种终端设备，包括如上所述的任意一种显示屏。该终端设备具有与上述显示屏相同的技术效果，此处不再赘述。
附图说明
图1a为本申请提供的一种显示屏的外观结构示意图；
图1b为本申请提供的一种显示屏的外观结构示意图；
图2为本申请实施例提供的一种显示屏的纵向截面结构示意图；
图3为图2所示的显示屏中的阵列基板的一种结构示意图；
图4a为图1a所示的显示屏的有效显示区的示意图；
图4b为图4b所示的有效显示区的一种区域划分示意图；
图5为本申请提供的阵列基板的一种结构示意图；
图6为本申请提供的阵列基板的另一种结构示意图；
图7为本申请提供的具有底栅型TFT的显示屏的一种纵向截面结构示意图；
图8为本申请提供的具有顶栅型TFT的显示屏的一种纵向截面结构示意图；
图9为本申请提供的具有顶栅型TFT的显示屏的另一种纵向截面结构示意图；
图10为图2所示的结构中一个亚像素的俯视结构示意图；
图11为基于图6所示的结构，本申请实施例提供的一种电容补偿方案示意图；
图12为针对图11所示的结构的电容补偿原理示意图；
图13为基于图6所示的结构，本申请实施例提供的另一种电容补偿方案示意图；
图14为基于图6所示的结构，本申请实施例提供的又一种电容补偿方案示意图；
图15为本申请提供的另一种显示屏的外观结构示意图；
图16为结合图15和图6所示的结构，本申请实施例提供的一种电容补偿方案示意图；
图17为本申请提供的一种显示屏的驱动方式示意图；
图18为本申请提供的又一种显示屏的纵向截面结构示意图；
图19为本申请提供的一种OLED显示屏的阵列基板结构示意图；
图20为图19中一个亚像素的结构示意图；
图21为具有图19所示的阵列基板的OLED显示装置的纵向截面结构示意图。
附图标记：
01-衬底；10-开口；11-子显示区；12-主显示区；20-辅助导电层；40-虚设亚像素；51-第一子部；52-第二子部；60-上电极；61-下电极；62-有机材料功能层；63-像素界定层；100-阵列基板；200-对盒基板；300-液晶层；301-第一绝缘层；302-第二绝缘层；303-第三绝缘层；400-封装基板；210-滤光单元；201-子电极；500-公共电极层；501-像素电极。
具体实施方式
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例涉及的显示屏可以为薄膜晶体管-液晶显示屏(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)。
由如图2所示的TFT-LCD的部分纵向截面结构可以看出，该TFT-LCD包括相对设置的阵列基板100和对盒基板200。此外，TFT-LCD还包括设置于阵列基板100和对盒基板200之间的液晶层300。
此外，如图2所示，该阵列基板100包括衬底01以及依次制作于衬底01上方的各个薄膜层。以下对上述阵列基板100中的部分薄膜层进行说明。例如，该阵列基板 100，包括第一绝缘层301以及公共电极层(Common electrode layer)500。其中，上述公共电极层500位于第一绝缘层301的上方。此外，上述第一绝缘层301的下表面设置有如图3所示的栅线(Gate Line，GL)以及如图2所示的与GL同层的TFT的漏极。本申请以下描述中，将覆盖GL以及与该GL同层的TFT的栅极g上表面的绝缘层称为第一绝缘层301。
需要说明的是，本申请的阵列基板100中一薄膜层上方的薄膜层，例如第一绝缘层301的上方的薄膜层，是指在衬底01上制作完该第一绝缘层301之后，制作于该第一绝缘层301背离衬底01一侧的薄膜层，例如上述公共电极层500。此时，该公共电极层500与第一绝缘层301之间可以具有至少一层其他薄膜层。例如，图2中，第一绝缘层301与公共电极层500之间，沿背离衬底01的方向依次具有TFT的有源层(Active Layer，AL)、TFT的源极s以及漏极d、第二绝缘层302。图2仅是对一种阵列基板的结构进行的距离说明，本申请不限于此。
此外，如图3所示，阵列基板100上还设置有与GL交叉的数据线(Date Line，DL)。该DL与图2中TFT的源极s或漏极d可以同层设置。
需要说明的是，上述阵列基板100中，有些薄膜层可以通过成膜工艺在衬底01的上方制作一整层(例如，通过涂覆工艺形成的上述第一绝缘层301)，而有些薄膜层需要通过构图工艺制作出预设的图案(例如GL、DL、TFT的栅极g、源极s以及漏极d)。该构图工艺包括光刻工艺、刻蚀步骤等用于形成预设图案的工艺。上述光刻工艺包括成膜、掩膜、曝光、显影等工艺过程的利用光刻胶、掩膜板、曝光机等形成图案的工艺。此外，上述衬底01可以为玻璃衬底或者有机材料构成的衬底。本申请对此不做限定。
以形成DL以及TFT的栅极g为例，对采用光刻工艺制作具有图案的薄膜层的方法进行说明。具体的，在上述衬底01上采用成膜工艺，例如沉积工艺形成一层金属薄膜层(例如，该金属薄膜层可以由钼构成)，然后在该金属薄膜层上涂覆光刻胶，再用掩膜版对光刻胶进行掩膜曝光，使得上述光刻胶中一部分被透过掩膜版的光线照射，另一部分被掩膜版上的遮光区域遮挡，而未被光线照射；接下来，对光刻胶进行显影，以该光刻胶为正胶为例，该光刻胶上被光线照射到的部分在显影液的作用下溶解，从而露出上述金属薄膜层；然后对光刻胶上显影掉的区域所露出的金属薄膜层进行刻蚀；接下来，对光刻胶进行剥离，从而可以形成具有预设图案的薄膜层，该预设图案中包括多条DL图案以及与DL相连接的TFT的栅极g的图案。
基于此，如图3所示，相邻的两条GL和相邻的两条DL横纵交叉界定的矩形区域称为一个亚像素(Sub Pixel)。每个亚像素中，在GL和DL的交叉位置处设置有一个TFT。该TFT的栅极g与GL相连接，第一极与DL相连接，第二极与像素电极501相连接。其中，TFT的第一极可以为TFT的源极s，第二极可以为TFT的漏极d；或者，TFT的第一极可以为TFT的漏极d，第二极为TFT的源极s。
此外，TFT-LCD还包括设置于上述阵列基板100，或者如图2所示，设置于对盒基板200上的彩色滤光层，该彩色滤光层包括多个滤光单元210。至少三个依次排列的亚像素构成一个像素(Pixel)。该像素(Pixel)中每个亚像素的位置与一种颜色的滤光单元210位置一一对应，从而使得该像素(Pixel)中的三个亚像素在不同滤光单 元210的滤光作用下，能够分别发出不同颜色的光线，例如，分别发出红色(R)、绿色(G)以及蓝色(B)的光线。
设置有上述彩色滤光层的对盒基板200可以称之为彩膜基板。此外，如图2所示，对盒基板200上还设置有用于对阵列基板100上的DL、GL以及TFT进行遮挡的黑矩阵(Black Matrix，BM)。
在此基础上，本申请提供的显示屏如图4a所示，设置有一开口(Notch)10。具体的，在生产加工过程中，可以采用异形切割工艺，对原本一整面的该显示屏中的阵列基板100和彩膜基板200在同一位置的局部区域均进行切除，从而形成上述开口10。在此情况下，该开口10可以用于放置摄像头、受话器、传感器、送话器等需要集成于显示屏中的器件。
其中，上述开口10可以设置于显示屏的任意一个位置，例如，如图1a所示，可以在阵列基板100的其中一个边(例如位于上方的边)向内切除该显示屏的部分结构，以形成上述开口10，此时的开口10为一向显示屏内部凹陷的凹槽。在此情况下，该开口10的边缘可以作为该显示屏边缘(edge)的一部分。或者，如图1b所示，还可以在显示屏的四个边围设的区域内部切除该显示屏的部分结构，形成一开口10，此时，该显示屏的任意一条边仍然保持原有形状。以下为了方便说明，均是以图1a所示的，上述开口10为一凹槽，且该凹槽设置于显示屏上方的边的中间位置为例进行的说明。
在此情况下，受到上述开口10的影响，如图4a所示，该显示屏的有效显示区(Active Area，AA)需要绕开上述开口10，因此该显示屏的有效显示区不再是一个完整的矩形。此时，如图4b所示，可以将上述显示屏的有效显示区划分为位于开口10两侧的子显示区11以及位于开口10和上述子显示区下方的主显示区12。
其中，如图3所示，主显示区12中的亚像素呈矩阵形式排列，且沿GL的延伸方向，该主显示区12中位于同一行的亚像素中的TFT的栅极g与同一条GL电连接。基于此，该主显示区12中接收同一条GL输出信号的多个亚像素由该阵列基板100的左端(或右端)均匀排布至右端(或左端)。此时，该主显示区12排布有多排整行亚像素。
此外，位于开口10两侧的子显示区11中，同一行亚像素的TFT的栅极g仍然需要与同一条GL相连接，但是由于上述开口10的存在，该开口10左侧的子显示区11中的GL需要穿过开口10与显示屏的有效显示区之间的区域，以绕开开口10布线，然后再延伸至开口10右侧的子显示区11中，从而将开口10左侧和右侧位于同一行的亚像素中的TFT的栅极g电连接。
可选的，上述开口10与显示屏的有效显示区之间的区域的宽度通常小于或等于1mm左右。
本申请中，“左”、“右”、“上”以及“下”等方位术语是相对于附图中的阵列基板或显示屏示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据阵列基板或显示屏所放置的方位的变化而相应地发生变化。
由上述可知，如图3所示，该开口10两侧的子显示区11中，接收同一条GL输出信号的亚像素受到上述开口10的影响，而无法实现整行排布。因此，子显示区11中 一行亚像素的数量较少，而主显示区12中一行亚像素的数量较多。
在此基础上，如图5所示，上述阵列基板100中的公共电极层500分布于该显示屏的整个有效显示区内。其中，有效显示区内的每个亚像素中的像素电极501在该阵列基板的衬底01上的正投影与该公共电极层500在上述衬底01上的正投影的至少一部分重叠。
此外，由图2可知，由于公共电极层500和像素电极501不同层，该公共电极层500和像素电极501之间具有绝缘层，该绝缘层在本申请中称为第三绝缘层303。其中，构成该第三绝缘层303的材料可以为氮化硅。在此情况下，该公共电极层500和像素电极501之间绝缘设置，所以每个像素电极501可以与上述公共电极层500之间形成用于控制液晶分子偏转的电容，称为液晶电容C LC。
基于此，当一行GL接收到栅极扫描信号时，可以驱动被该行GL控制的各个亚像素中的TFT导通。此时，每一条DL将数据电压Vdata通过导通的TFT传输给像素电极501中，以对该亚像素进行充电。此外，向公共电极层500提供公共电压Vcom。在此情况下，由公共电极层500和像素电极501形成的液晶电容C LC可以控制该像素电极501所在亚像素对应位置处的液晶分子进行偏转，从而可以控制各个亚像素发出光线的透过率，进而实现各个灰阶的显示。此外，上述光线在彩色滤光层中各个滤光单元210的滤色作用下，可以实现彩色显示。由上述可知，图5中子显示区11中一行亚像素的数量较少，而主显示区12中一行亚像素的数量较多。因此为了减小子显示区11的一行亚像素和主显示区12的一行亚像素的充电时间的差异，本申请提供以下实施例。
实施例一
如图5所示，本申请提供的显示屏的阵列基板100还包括设置于上述开口10与该显示屏的有效显示区之间，且位于上述第一绝缘层301的上方的辅助导电层20。此外，由上述可知，在该上述开口10与该显示屏的有效显示区之间的GL设置于上述第一绝缘层301的下表面。辅助导电层20与该开口10与该显示屏的有效显示区之间的GL可以不同层且绝缘设置。可选的，上述开口与显示屏的有效显示区之间的GL在阵列基板100的衬底01上的正投影与辅助导电层20在衬底01上的正投影的至少部分重叠。因此，辅助导电层20和该开口10与该显示屏的有效显示区之间的GL之间可以形成电容，称为第一电容C1。
以下为了方便说明，如图5所示，将设置于开口与显示屏的有效显示区之间的GL称为第一栅线，简称GL1。该GL1能够延伸到上述子显示区11，并与该子显示区11的亚像素中的TFT的栅极g电连接，从而对子显示区11中的亚像素进行控制。此外，将设置于主显示区12的GL称为第二栅线，简称GL2。
在此情况下，在显示过程中，可以向上述辅助导电层20提供与公共电极层500相同的电压，即上述公共电压Vcom，此时，GL1上的电压需要向辅助导电层20与上述GL1形成第一电容C1进行充电，从而能够增加上述GL1的负载，达到延长子显示区11中至少一行亚像素的充电时间，使得子显示区11的一行亚像素和主显示区12的一行亚像素的充电时间相同或基本相同。这样一来，与子显示区11位置相对应的液晶分子的偏转速度和与主显示区12位置相对应的液晶分子的偏转速度近似相同。
具体的，以子显示区11和主显示区12均由黑画面转换为白画面进行显示为例，由于上述两个像素区对应的液晶分子的偏转速度近似相同，因此，背光模组提供的光线不会提前通过与子显示区11对应的液晶分子，而使得子显示区11优先于主显示区12显示白画面，进而可以减小由于子显示区11和主显示区12显示上述白画面之间存在先后差异而导致出现横纹或闪烁等异常现象的几率。
基于此，本申请对构成辅助导电层50的材料，以及辅助导电层50在该阵列基板100的中位于哪一层薄膜层的位置不做限定，只要能够保证该辅助导电层50在上述开口10与显示屏有效显示区之间，且位于上述第一绝缘层301的上方即可。
在此情况下，由于上述开口10与显示屏有效显示区之间的区域不能显示图像，因此，该区域需要通过对盒基板200上的黑矩阵BM进行遮挡，所以辅助导电层20的材料的选取对显示效果不会造成影响。在此情况下，构成辅助导电层20的材料可以选用制备阵列基板100中具有导电功能的薄膜层所采用的材料。例如，采用构成GL的金属材料(例如金属钼)，或者构成DL的金属材料(例如，铝钛合金)，或者，采用构成公共电极层500和像素电极501的透明导电材料，例如，氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)。
由上述可知，由于公共电极层500同样位于该第一绝缘层301的上方，因此上述辅助导电层20可以与公共电极层500同层设置。基于此，为了简化制作工艺，如图6所示，该辅助导电层20与公共电极层500可以为一体结构，从而可以通过一次掩膜曝光工艺形成。
以下基于辅助导电层20与公共电极层500可以为一体结构的方案，针对不同结构的阵列基板100，对该辅助导电层20的设置方式进行举例说明。
具体的，例如，如图2或图7所示，以该阵列基板100上制作与每个亚像素中的TFT为底栅型TFT为例。其中，底栅型TFT中，如图2或图7所示，相对于设置在该TFT的AL与TFT的栅极g之间的栅极绝缘层(Gate Insulator，GI)而言，TFT的栅极g先制作于衬底01上。在此情况下，上述覆盖GL上表面的第一绝缘层301即为该栅极绝缘层，构成该栅极绝缘层的材料可以为氮化硅或氧化硅。
在此情况下，如图2所示，该阵列基板100还包括与上述栅极绝缘层(即第一绝缘层301)的上表面接触的DL(与TFT的源极s、漏极d同层)、覆盖DL上表面的第二绝缘层302、位于第二绝缘层302上表面的公共电极层500。由于辅助导电层20与公共电极层500同层设置，因此上述辅助导电层20位于该第二绝缘层302的上表面。
需要说明的是，本实施例中将DL与透明电极(例如公共电极层500或像素电极501)之间的绝缘层称为第二绝缘层。其中，上述第二绝缘层302的上表面用于制作透明电极，为了提高该透明电极的平整度，可选的构成该第二绝缘层302的材料可以为有机树脂材料。
在此基础上，公共电极层500的上表面具有第三绝缘层303，该第三绝缘层303的上表面具有像素电极501，该像素电极501通过制作于第三绝缘层303、公共电极层500以及第二绝缘层302上的过孔与TFT的漏极d电连接。
图2是以像素电极501位于公共电极层500上方为例进行的说明。此外，如图7所示，像素电极501还可以位于公共电极层500下方。在此情况下，该阵列基板100 包括与上述栅极绝缘层(即上述第一绝缘层301)的上表面接触的DL(与TFT的源极s、漏极d同层)、覆盖DL上表面的第二绝缘层302、位于第二绝缘层302上表面的像素电极501、位于像素电极501上表面的第三绝缘层303以及位于第三绝缘层303上表面的公共电极层500。在此情况下，与公共电极层500同层的辅助导电层20也位于第三绝缘层303的上表面。
或者又例如，如图8或图9所示，以该阵列基板100上制作与每个亚像素中的TFT为顶栅型TFT为例。其中，顶栅型TFT中，如图8或图9所示，相对于设置在该TFT的AL与TFT的栅极g之间的栅极绝缘层(Gate Insulator，GI)而言，TFT的AL先制作于衬底01上。此时，与TFT的栅极g同层的GL位于栅极绝缘层的上表面。采用顶栅型结构的TFT可以采用低温多晶硅(Low Temperature Poly Silicon，LTPS)工艺制备而成。LTPS工艺制备而成的TFT的导通性能更好，迁移率更高。
在此情况下，如图8所示，该阵列基板100还包括位于第一绝缘层301上表面的像素电极501，以及位于像素电极501上表面的DL(与TFT的源极s、漏极d同层)、位于DL和像素电极501上表面的第三绝缘层303。在此情况下，与公共电极层500同层的辅助导电层20也位于第三绝缘层303的上表面。
图8是以像素电极501位于TFT的漏极d(或DL)下方为例进行的说明。此外，如图9所示，像素电极501还可以位于TFT的漏极d(或DL)上方。在此情况下，上述阵列基板100还包括与第一绝缘层301的上表面相接触的DL(与TFT的源极s、漏极d同层)、覆盖DL的第二绝缘层302、位于第二绝缘层302上表面的像素电极501，以及位于像素电极501上表面的第三绝缘层303。在此情况下，与公共电极层500同层的辅助导电层20也位于第三绝缘层303的上表面。
需要说明的是，图8和图9均是以公共电极层500位于像素电极501上方为例进行的说明。当公共电极层500位于像素电极501的下方时，阵列基板的结构可以参考图2设置，此处不再赘述。
由上述可知，图2、图7、图8以及图9中公共电极层500和像素电极501均制作于阵列基板100上。在此情况下，公共电极层500和像素电极501中，位于上方的电极为狭缝状电极，而位于下方的电极为面状电极。例如，以图2所示的结构为例，像素电极501位于上方，而公共电极层500位于下方，因此像素电极501为狭缝状，而公共电极层500为面状，此时，一个亚像素中狭缝状的像素电极501和面状的公共电极层500的具体结构如图10所示。在此情况下，采用上述阵列基板100构成的显示屏为边缘场开关(Fringe Field Switching，FFS)型显示屏。上述FFS型显示屏可以通过一平面内的狭缝状电极(例如，图10中的像素电极501)边缘所产生的平行电场，以及像素电极501与公共电极层500间产生的纵向电场形成多维电场，使液晶层300中位于像素电极501的狭缝间，以及像素电极501与公共电极层500之间的所有液晶分子都能够被驱动而发生偏转，从而有利于提高液晶层的透光效率，提升显示品质。
需要说明的是，除了图10以外，其余阵列基板100的俯视图中，像素电极501采用简化示意，因此未将其画成狭缝状结构。
实施例二
本实施例的方案中，在上在开口10与显示屏的有效显示区之间设置了多个虚设 (Dummy)亚像素40。
具体的，如图11所示，在开口10与显示屏的有效显示区之间，在上述第一绝缘层301上方设置有与GL(即上述GL1)交叉的DL。其中，相邻的两条DL和相邻的两条GL交叉界定一个虚设亚像素40。该虚设亚像素40内还设置有TFT。TFT的栅极g连接DL，第一极连接GL，第二极空置。由于该虚设亚像素40中TFT的第二极空置，因此该上述亚像素40中未设置于TFT第二极相连接的像素电极501，所以该虚设亚像素40无法进行显示。
需要说明的是，还可以采用与DL以及GL不同层的金属线形成数据引线，一条数据引线与主显示区12中的一条DL电连接。通过相邻两条数据引线和相邻的两条GL交叉界定上述虚设亚像素40。由上述可知，与该公共电极层500为一体结构的辅助导电层20与GL1异层且绝缘设置，辅助导电层20和GL1之间可以形成上述第一电容C1。此外，在上述主显示区12中，公共电极层500与GL2同样异层且绝缘设置，公共电极层500与GL2之间可以形成第二电容C2。其中，在GL1与GL2同层同材料，且线宽相同的情况下，上述第一电容G1和第二电容G2的电容值可以相同或近似相同。在此情况下，显示过程中，GL1上为脉冲波的栅极扫描信号对该辅助导电层20上产生的干扰，与GL2上栅极扫描信号对该公共电极层500上产生的干扰相同或近似相同，从而可以减小子显示区11与主显示区12之间的差异。
此外，由上述可知，TFT的栅极g与GL同层同材料，TFT的源极s和漏极d与DL同层同材料。因此，该TFT自身具有寄生电容，例如，栅极g与源极s之间的寄生电容Cgs、栅极g与漏极d之间的寄生电容Cgd。所以，通过设置上述虚设亚像素40，可以使得开口10与显示屏的有效显示区之间形成多个TFT的寄生电容。
基于此，例如，GL1所控制的亚像素的个数为m，此时，如图12中的(a)所示，GL1连接有m个液晶电容C LC；主显示区12中GL2相连接的亚像素的个数为n，此时，如图12中的(b)所示，GL2连接有n个液晶电容C LC。其中，n＞m，n，m为正整数。在此情况下，由上述可知，GL1还连接有多个TFT的寄生电容。在此情况下，当GL1的起始端接收到栅极扫描信号(幅值为Vg)时，在该栅极扫描信号传输过程(例如从左至右)中，能够将与GL1相连接的m个亚像素中的TFT，以及n-m个虚设亚像素40中的TFT导通，从而对亚像素中的液晶电容C LC和虚设亚像素40中的寄生电容进行充电，在此情况下GL1末端的栅极扫描信号的幅值为Vg1，其中，Vg1略小于Vg。
同理，主显示区12中GL2的起始端接收到栅极扫描信号(幅值为Vg)时，在该栅极扫描信号传输过程(例如从左至右)中，能够将与该GL2相连接的n个亚像素中的TFT导通，从而对亚像素中的液晶电容C LC进行充电，在此情况下该主显示区12中GL2末端的栅极扫描信号的幅值为Vg2，其中，Vg2略小于Vg。
在此情况下，虽然GL1所控制的一行亚像素的数量(m)小于主显示区12中一条GL2所控制的一行亚像素的数量(n)，但是通过在开口10与显示屏的有效显示区之间设置虚设亚像素40，使得设置于虚设亚像素40中的TFT的寄生电容能够增加GL1所连接的电容的数量，从而达到增加GL1负载的目的。此时，可以使得GL1末端的栅极扫描信号的幅值为Vg1与主显示区12中GL2末端的栅极扫描信号的幅值为Vg2之间的电压差△V很小。此外，可以适当增大上述虚设亚像素40中TFT的宽长比，以达到 增大上述寄生电容的目的，使得上述电压差△V近似等于零。在此情况下，GL1和主显示区12中GL2的信号状态基本一致，从而使得子显示区11中的一行亚像素和主显示区12中的一行亚像素的充电时间基本一致，进而达到减小闪烁或横纹等显示不良的目的。
实施例三
本实施例中，在开口10与显示屏的有效显示区之间的GL的线宽大于有效显示区的GL的线宽。例如，G1的线宽大于G2的线宽。
基于此，可以通过软件计算出主显示区12中每个亚像素的像素电极501与公共电极层500构成的液晶电容C LC的大小以及与主显示区12中一行GL2相连接的一行亚像素的总数n。此外，还可以获得公共电极层500与主显示区12中一条GL2形成的第二电容C2。从而可以计算出主显示区12中一条GL2所连接的电容的大小，例如为n×C LC+C2。
接下来，获取GL1所控制的亚像素的总数m，并计算出该行GL1所连接的所有液晶电容C LC的总和，例如为m×C LC。通过将GL1连接的所有液晶电容的大小与上述主显示区12中GL2连接的电容的大小进行比对，可以获得两者的差值，从而得到需要对GL1所连接的电容进行补偿的补偿值。
在此基础上，由上述可知，与公共电极层500一体结构的辅助导电层40与GL1可以形成第一电容C1。因此，可以根据上述获得的电容补偿值，对GL1的线宽进行调节，以增大上述第一电容C1的电容值，从而使得GL1所连接的电容的大小，例如为m×C LC+C1与主显示区12中一条GL2所连接的电容的大小，例如为n×C LC+C2相同或近似相同，最终达到电容补偿的目的。
在此基础上，如图13所示，为了在开口10与显示屏的有效显示区之间的GL1为了绕开开口10，该GL1可以包括第一子部51和第二子部52。
其中，第一子部51与主显示区12中的GL2平行，该第二子部52与第一子部51相交。这样一来，相对于主显示区12中的GL2而言，具有上述第一子部51和第二子部52的GL1的长度较长，因此GL1的电阻较大。此外，第二子部52所在区域的布线空间较小。在此情况下，为了有效利用布线空间，同时降低上述GL1的电阻，可选的，第一子部51的线宽大于第二子部52的线宽，而第二子部52的线宽大于主显示区12中GL2的线宽。
由上述可知，实施例三的方案相对于实施例二的方案而言，只需对在开口10与显示屏的有效显示区之间的GL1的线宽进行调节，而需设置虚设亚像素40。因此实施例三中开口10与显示屏的有效显示区之间的区域的面积较小，从而能够有利于减小显示屏的边框尺寸。
实施例四
如图14所示，辅助导电层20包括至少一排间隔设置，且相互电连接的多个子电极201。开口10与显示屏的有效显示区之间的GL1在阵列基板100的衬底01上的正投影与至少一排子电极201在衬底01上的正投影的至少部分重叠。
例如，图14中第一排子电极201在衬底01上的正投影与第一行和第二行GL1在衬底01上的正投影的部分重叠。
由上述可知，由于与公共电极层500一体结构的辅助导电层20与开口10与显示屏的有效显示区之间的GL1异层且绝缘设置，因此辅助导电层20中每个子电极201与GL1之间可以形成一个第一电容C1。此时，子电极201在衬底01上的正投影与GL1在衬底01上的正投影重叠的面积越大，该条GL1所连接的电容越大。因此由上述可知，可以获取GL1所连接的电容的补偿量，然后根据补偿量设定用于覆盖上述GL1的一排子电极201的分布密度和形状。
当子显示区11中，每一行亚像素的数量相同时，如图14所示，每一排子电极201的分布密度和形状可以相同。此外，如图15所示，当上述开口10的边缘为斜边时，如图16所示，在子显示区11中，一行亚像素的数量可以不相同。
在此情况下，GL1所连接的电容的补偿量不同时，每一排子电极201的分布密度和形状可以不同。
例如，图16中，与第一行GL1相连接的亚像素的个数少于与第二行GL1相连接的亚像素的个数。由上述可知，对第一行GL1所连接的电容的补偿值需要大于第二行GL1所连接的电容的补偿值。因此，位于同一排的子电极201可以同时与第一行和第二行GL1相交叠，且该排子电极201中，每个子电极201的形状为梯形，该梯形的长边位于上方，梯形的短边位于下方，从而使得子电极201在衬底01上的正投影与第一行GL1在衬底01上的正投影的重叠部分的面积较大，而该子电极201在衬底01上的正投影与第二行GL1在衬底01上的正投影的重叠部分的面积较小，最终达到上述两条GL1所连接的电容与主显示区12中GL2所连接的电容相同或近似相同。
需要说明的是，本申请实施例提供的实施例二、实施例三以及实施例四的方案可以相互结合。例如，将实施例二和实施例三的方案进行结合，即在开口10与显示屏的有效显示区之间设置虚设亚像素40的同时，还可以增加开口10与显示屏的有效显示区之间GL1的线宽；或者，将实施例三和实施例四的方案进行结合，即增加开口与显示屏的有效显示区之间中GL1的线宽的同时，将位于开口10与显示屏的有效显示区之间的辅助导电层20设置多个覆盖GL1的子电极201。其他结合方式，在此不再一一赘述。
以下对具有上述阵列基板100的显示屏的显示驱动过程，以及对GL1所连接的电容的补偿效果进行说明。
如图17所示，阵列基板100上在子显示区11和主显示区12外侧的非有效显示区设置有阵列基板行驱动(Gate Driver on Array，GOA)电路，该GOA电路包括多个移位寄存器单元(Register Set，RS)，每一级RS与一行GL相连接。上述GOA电路可以均设置于左侧的非有效显示区，或者，为了满足窄边框的设计要求，上述非有效显示区面积的逐渐减小，因此如图17所示，可以将GOA分成两部分，奇数级RS设置于左侧的非有效显示区，偶数级RS设置于右侧的非有效显示区。
第一级RS1、第二级RS2、第三级RS3以及第四级RS4分别与子显示区11中处于第一行、第二行、第三行以及第四行位置的GL1相连接；第五级RS5、第六级RS6、第七级RS7以及第八级RS8分别与主显示区12中处于第五行、第六行、第七行以及第八行位置的GL2相连接。
此外，上述非显示区域中还设置有与GOA电路和源极驱动器(图中未示出)相连 接的驱动集成电路(Integrated Circuit，IC)。该源极驱动器与数据线DL相连接，用于向数据线提供数据电压。
在显示一帧画面的过程中，驱动IC控制GOA电路中的各个RS逐级向与其相连接的栅线GL输出栅极扫描信号，以实现对所有栅线的逐行扫描。接收到上述栅极扫描信号的一条栅线，例如子显示区11中处于第一行位置的GL1接收到上述栅极扫描信号，此时与该GL1相连接的亚像素中的TFT开启，此外，形成于开口10与显示屏的有效显示区之间的GL1相连接的电容(例如，如图11所示的方案中，公共电极层500与GL1形成的电容)处于充电状态。
与此同时，上述驱动IC控制源极驱动器向各个数据线DL输出数据电压，该数据电压通过导通的TFT传输至上述第一行亚像素的像素电极501中，以对该行亚像素进行充电。在此情况下，在与该第一行的GL1所连接的电容的作用下，第一行最左端至最右端的亚像素全部被充电的时间得到延长，例如该时间为T。
接下来，第二级RS2向位于第二行的GL1输出栅极扫描信号，与该第二行的GL1相连接的亚像素的充电过程同上所述，不同之处为，该第二行亚像素从右端至左端进行充电，且该第二行亚像素被充电的时间与上述T相同或近似相同。
接下来，第三级RS3和第四级RS4逐行向位于第三行的GL1和位于第四行的GL1输出栅极扫描信号。第三行亚像素和第四行亚像素的充电过程同上所述此处不再赘述。
接下来，第五级RS5向主显示区12中位于第五行位置的GL2输出栅极扫描信号，与该GL2相连接的整行排布的亚像素从左至右进行充电。充电过程同上所述。此时，虽然子显示区11中第一行亚像素的数量少于该主显示区12中第五行亚像素的数量，但是由上述可知，在上述开口10与显示屏的有效显示区之间设置有用于对与该第一行亚像素相连接的GL1的负载进行补偿的电容，因此该第五行亚像素被充电的时间与上述T相同或近似相同。
其余主显示区12中的其余各行亚像素的充电过程同上所述，此处不再赘述。由上述可知，虽然在上述开口10的影响下，该阵列基板100每一行的亚像素的数量并不是完全相同，但是本申请提供的方案中，可以在该开口10与显示屏的有效显示区之间设置电容，以对连接较少亚像素的栅线GL的负载进行补偿，从而使得每一行亚像素的充电之间趋于一致，进而使得不同亚像素对应的液晶分子偏转的速度相同，达到减小闪烁或横纹等显示不良的几率。
实施例五
上述实施例均是以辅助导电层20以及公共电极层500设置于阵列基板100为例进行的说明。本申请还可以将上述辅助导电层20设置于对盒基板200上，该辅助导电层20在衬底基板100的衬底01上的正投影位于开口10与显示屏的有效显示区之间。在此情况下，如图18所示，当公共电极层500设置于对盒基板200上时，上述辅助导电层20与该公共电极层500仍然可以同层同材料，且为一体结构，以实现辅助导电层20设置于对盒基板200上的目的。
其中，公共电极层500位于由多个滤光单元210构成的彩色滤光层靠近阵列基板100的一侧表面上。
基于此，阵列基板100上仍然可以采用实施例二的方案，在开口10与显示屏的有 效显示区之间形成有虚设亚像素40，以及位于该虚设亚像素40中的TFT；或者，该阵列基板100还可以采用实施例三的方案，增大开口10与显示屏的有效显示区之间的GL1的至少一部分线宽；又或者，该阵列基板100的结构可以不做改变，而将上述位于对盒基板100上辅助导电层20采用实施例四的方式，在对应开口10与显示屏的有效显示区之间的位置形成至少一排相互间隔且电连接的子电极201，该子电极201在阵列基板100衬底01上的正投影与至少一条GL1在上述衬底01上的正投影重叠。
在此情况下，该显示屏对GL1所连接的电容进行补偿的过程同上所述，此处不再赘述。
需要说明的是，图18所示的显示屏为扭曲向列(Twist Nematic，TN)型显示屏。TN型显示屏，采用垂直电场原理，通过相对设置在对盒基板200上的公共电极层500和设置在阵列基板100上的像素电极501之间形成垂直电场，来驱动扭转向列模式的液晶分子，从而达到显示的目的。
上述实施例均是以TFT-LCD为例进行的说明，本申请实施例提供的电容补偿方案同样可以适用于有机发光二极管(Organic Light Emitting Diode，OLED)显示屏。
具体的，上述OLED显示屏，包括如图19所示的阵列基板100，该阵列基板100上形成有阵列排布的亚像素，每个亚像素中如图20所示，设置有OLED以及与该OLED相连接的像素电路。
本申请对上述像素电路的具体结构不做限定，图20中所示的像素电路仅仅是以最简单的像素电路结构进行的举例说明，该像素电路包括选通晶体管Tc、驱动晶体管Td以及电容C。其中，图20中OLED的阴极连接接地端GND，驱动晶体管Td导通时，电压端VDD与接地端GND形成压差，使得驱动电流流过OLED，该OLED发光。当然，为了实现对驱动晶体管Td的阈值电压Vth进行补偿，上述像素电路还可以包括补偿单元；或者，为了对OLED的阳极或驱动晶体管Td的栅极进行复位，该像素电路还可以包括复位单元。上述补偿单元和复位单元由多个晶体管构成，本申请对其具体结构不再一一赘述。
基于此，上述OLED显示屏的纵向截面结构如图21所示，可以看出阵列基板100上阵列排布的OLED。该OLED包括上电极60(例如阴极)、下电极61(例如阳极)以及位于上电极60和下电极61之间的有机材料功能层62。上述下电极60和有机材料功能层62位于设置于像素界定层63中的凹槽内。
其中，下电极61与一亚像素中的一TFT，例如上述驱动晶体管Td相连接。有机材料功能层62可以包括空穴注入层、空穴传输层、有机发光层、电子传输层、电子注入层等。
此外，如图19和图21所示，上述上电极60可以为一整层，该上电极60覆盖具有子显示区11和主显示区12的有效显示区。在此情况下，在阵列基板100上，上述有效显示区和开口10之间设置有上述辅助导电层20，该开口10与显示屏的有效显示区之间的至少一条GL1在阵列基板100的衬底01上的正投影与该辅助导电层20在该衬底01上的正投影的一部分重叠。基于此，为了简化制作工艺，上述辅助导电层20可以与上电极60同层，且为一体结构。
在此情况下，与液晶显示屏中阵列基板上TFT的设置方式同理，上电极60与GL1 之间至少具有位于该GL1上表面的第一绝缘层301。因此，与该上电极60同层的辅助导电层20与该GL1之间同样至少具有上述第一绝缘层301。此外，如图21所示，由于上电极60制作于像素界定层63的上表面，因此该与该上电极60同层的辅助导电层20与该GL1之间还可以包括位于上述第一绝缘层301上方的像素界定层63，该辅助导电层20制作于像素界定层63的上表面。
这样一来，上述辅助导电层20可与在开口10与显示屏的有效显示区之间的GL1形成电容，从而达到增加该GL1负载的目的。
此外，OLED显示屏中的阵列基板100上仍然可以采用实施例二的方案，在开口10与显示屏的有效显示区之间形成虚设亚像素40，以及位于该虚设亚像素40中的TFT；或者，该阵列基板100还可以采用实施例三的方案，增大开口10与显示屏的有效显示区之间GL1的至少一部分线宽；又或者，该阵列基板100的结构可以不做改变，而将上述与上电极60同层且一体结构的辅助导电层20采用实施例四的方式，在开口10与显示屏的有效显示区之间形成至少一排相互间隔且电连接的子电极201。
在此情况下，该OLED显示屏对GL1所连接的电容进行补偿的过程同上所述，此处不再赘述。
在此基础上，如图21所示，上述OLED显示屏还包括封装基板400。该封装基板400用于对OLED显示屏的阵列基板进行封装。
本申请提供一种终端设备，包括上述任意一种显示屏，该显示屏的结构和技术效果同上所述，此处不再赘述。该终端设备可以为手机、平板、电视机等具有显示屏的设备。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种显示屏，其特征在于，所述显示屏开设有一开口，所述显示屏包括相对设置的阵列基板和对盒基板，所述阵列基板和所述对盒基板之间设置有液晶层；
    所述阵列基板包括第一绝缘层以及公共电极层；所述公共电极层位于所述第一绝缘层的上方；在所述开口与所述显示屏的有效显示区之间，在所述第一绝缘层的下表面设有栅线；在所述开口与所述显示屏的有效显示区之间，在所述第一绝缘层的上方设置有辅助导电层；所述辅助导电层与所述公共电极层同层。
  2. 根据权利要求1所述的显示屏，其特征在于，所述辅助导电层与所述公共电极层为一体结构。
  3. 根据权利要求1或2所述的显示屏，其特征在于，所述第一绝缘层为栅极绝缘层；
    所述阵列基板还包括与所述栅极绝缘层的上表面接触的数据线、覆盖所述数据线上表面的第二绝缘层、位于所述第二绝缘层上表面的像素电极，以及位于所述像素电极上表面的第三绝缘层；所述辅助导电层位于所述第三绝缘层的上表面。
  4. 根据权利要求2所述的显示屏，其特征在于，所述阵列基板还包括栅极绝缘层；所述栅线位于所述栅极绝缘层的上表面；
    所述阵列基板还包括位于所述第一绝缘层上表面的像素电极，以及位于所述像素电极上表面的第三绝缘层；所述辅助导电层位于所述第三绝缘层的上表面；
    或者，所述阵列基板还包括与所述第一绝缘层的上表面相接触的数据线、覆盖所述数据线的第二绝缘层、位于所述第二绝缘层上表面的像素电极，以及位于所述像素电极上表面的第三绝缘层；所述辅助导电层位于所述第三绝缘层的上表面。
  5. 根据权利要求1-4任一项所述的显示屏，其特征在于，在所述开口与所述显示屏的有效显示区之间的栅线的线宽大于所述有效显示区的栅线的线宽。
  6. 根据权利要求1-4任一项所述的显示屏，其特征在于，在所述开口与所述显示屏的有效显示区之间，在所述第一绝缘层上方设置有与所述栅线交叉的数据线；
    相邻的两条所述数据线和相邻的两条所述栅线交叉界定一个虚设亚像素；所述虚设亚像素内还设置有薄膜晶体管；所述薄膜晶体管的栅极连接所述栅线，第一极连接所述数据线，第二极空置。
  7. 根据权利要求1-4任一项所述的显示屏，其特征在于，所述辅助导电层包括至少一排间隔设置，且相互电连接的多个子电极；
    所述开口与所述显示屏的有效显示区之间的栅线在所述阵列基板的衬底上的正投影与至少一排所述子电极在所述衬底上的正投影的至少部分重叠。
  8. 根据权利要求1-7任一所述的显示屏，其特征在于，所述开口与所述显示屏的有效显示区之间的栅线在所述阵列基板的衬底上的正投影与所述辅助导电层在所述衬底上的正投影的至少部分重叠。
  9. 根据权利要求1-7任一所述的显示屏，其特征在于，所述开口为设置于所述显示屏至少一边且向所述显示屏内部凹陷的凹槽。
  10. 一种终端设备，其特征在于，包括显示屏，所述显示屏开设有一开口，所述显示屏包括相对设置的阵列基板和对盒基板，所述阵列基板和所述对盒基板之间设置 有液晶层；
    所述阵列基板包括第一绝缘层以及公共电极层；所述公共电极层位于所述第一绝缘层的上方；在所述开口与所述显示屏的有效显示区之间，在所述第一绝缘层的下表面设有栅线；在所述开口与所述显示屏的有效显示区之间，在所述第一绝缘层的上方设置有辅助导电层；所述辅助导电层与所述公共电极层同层。
  11. 根据权利要求10所述的终端设备，其特征在于，所述辅助导电层与所述公共电极层为一体结构。
  12. 根据权利要求11所述的终端设备，其特征在于，所述第一绝缘层为栅极绝缘层；
    所述阵列基板还包括与所述栅极绝缘层的上表面接触的数据线、覆盖所述数据线上表面的第二绝缘层、位于所述第二绝缘层上表面的像素电极，以及位于所述像素电极上表面的第三绝缘层；所述辅助导电层位于所述第三绝缘层的上表面。
  13. 根据权利要求11所述的终端设备，其特征在于，所述阵列基板还包括栅极绝缘层；所述栅线位于所述栅极绝缘层的上表面；
    所述阵列基板还包括位于所述第一绝缘层上表面的像素电极，以及位于所述像素电极上表面的第三绝缘层；所述辅助导电层位于所述第三绝缘层的上表面；
    或者，所述阵列基板还包括与所述第一绝缘层的上表面相接触的数据线、覆盖所述数据线的第二绝缘层、位于所述第二绝缘层上表面的像素电极，以及位于所述像素电极上表面的第三绝缘层；所述辅助导电层位于所述第三绝缘层的上表面。
  14. 根据权利要求10-13任一项所述的终端设备，其特征在于，在所述开口与所述显示屏的有效显示区之间的栅线的线宽大于所述有效显示区的栅线的线宽。
  15. 根据权利要求10-13任一项所述的终端设备，其特征在于，在所述开口与所述显示屏的有效显示区之间，在所述第一绝缘层上方设置有与所述栅线交叉的数据线；
    相邻的两条所述数据线和相邻的两条所述栅线交叉界定一个虚设亚像素；所述虚设亚像素内还设置有薄膜晶体管；所述薄膜晶体管的栅极连接所述栅线，第一极连接所述数据线，第二极空置。
  16. 根据权利要求10-13任一项所述的终端设备，其特征在于，所述辅助导电层包括至少一排间隔设置，且相互电连接的多个子电极；
    所述开口与所述显示屏的有效显示区之间的栅线在所述阵列基板的衬底上的正投影与至少一排所述子电极在所述衬底上的正投影的至少部分重叠。
  17. 根据权利要求10-16任一所述的终端设备，其特征在于，所述开口与所述显示屏的有效显示区之间的栅线在所述阵列基板的衬底上的正投影与所述辅助导电层在所述衬底上的正投影的至少部分重叠。
  18. 根据权利要求10-16任一所述的终端设备，其特征在于，所述开口为设置于所述显示屏至少一边且向所述显示屏内部凹陷的凹槽。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107094188A (zh) * 2017-04-24 2017-08-25 广东欧珀移动通信有限公司 显示屏以及终端
US20170270342A1 (en) * 2015-06-18 2017-09-21 Shenzhen GOODIX Technology Co., Ltd. Optical collimators for under-screen optical sensor module for on-screen fingerprint sensing
CN107342036A (zh) * 2017-08-21 2017-11-10 厦门天马微电子有限公司 显示面板及显示装置
CN107610636A (zh) * 2017-10-30 2018-01-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN107610645A (zh) * 2017-10-26 2018-01-19 上海天马有机发光显示技术有限公司 一种oled显示面板、其驱动方法及显示装置
CN107633812A (zh) * 2017-10-30 2018-01-26 武汉天马微电子有限公司 一种显示面板及显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000098420A (ja) * 1998-09-22 2000-04-07 Toshiba Corp アクティブマトリクス型液晶表示装置
CN100409089C (zh) * 2005-06-16 2008-08-06 统宝光电股份有限公司 画素结构及其修补方法
JP4711404B2 (ja) * 2005-08-12 2011-06-29 株式会社 日立ディスプレイズ 表示装置
CN100437318C (zh) * 2005-11-24 2008-11-26 统宝光电股份有限公司 像素结构及其修补方法
US20090102824A1 (en) * 2006-03-15 2009-04-23 Sharp Kabushiki Kaisha Active matrix substrate and display device using the same
EP2085952B1 (en) * 2006-11-21 2016-08-10 Sharp Kabushiki Kaisha Active matrix substrate, display panel, and display
CN101414088B (zh) * 2008-11-14 2010-12-29 友达光电股份有限公司 液晶显示面板
TWI490829B (zh) * 2013-01-11 2015-07-01 Au Optronics Corp 顯示面板與顯示裝置
US10062317B2 (en) * 2014-10-16 2018-08-28 Lg Display Co., Ltd. Panel array for display device with narrow bezel
JP2016218216A (ja) * 2015-05-19 2016-12-22 パナソニック液晶ディスプレイ株式会社 表示パネル
US10354578B2 (en) * 2016-04-15 2019-07-16 Samsung Display Co., Ltd. Display device
CN107424551B (zh) * 2017-05-25 2021-01-29 上海天马微电子有限公司 阵列基板、异形显示器及显示装置
CN106991990A (zh) * 2017-05-27 2017-07-28 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN107633807B (zh) * 2017-09-08 2019-10-15 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN107481669A (zh) * 2017-09-08 2017-12-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN107346650A (zh) * 2017-09-14 2017-11-14 厦门天马微电子有限公司 显示面板、显示装置和扫描驱动方法
CN107544189B (zh) * 2017-10-20 2020-05-15 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170270342A1 (en) * 2015-06-18 2017-09-21 Shenzhen GOODIX Technology Co., Ltd. Optical collimators for under-screen optical sensor module for on-screen fingerprint sensing
CN107094188A (zh) * 2017-04-24 2017-08-25 广东欧珀移动通信有限公司 显示屏以及终端
CN107342036A (zh) * 2017-08-21 2017-11-10 厦门天马微电子有限公司 显示面板及显示装置
CN107610645A (zh) * 2017-10-26 2018-01-19 上海天马有机发光显示技术有限公司 一种oled显示面板、其驱动方法及显示装置
CN107610636A (zh) * 2017-10-30 2018-01-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN107633812A (zh) * 2017-10-30 2018-01-26 武汉天马微电子有限公司 一种显示面板及显示装置

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