WO2019141417A1

WO2019141417A1 - Electrical circuit for testing primary internal signals on an asic

Info

Publication number: WO2019141417A1
Application number: PCT/EP2018/082345
Authority: WO
Inventors: Carsten Hermann
Original assignee: Robert Bosch Gmbh
Priority date: 2018-01-17
Filing date: 2018-11-23
Publication date: 2019-07-25
Also published as: CN111615635A; DE102018200723A1; EP3740771B1; US20210063483A1; CN111615635B; EP3740771A1; US11808809B2

Abstract

The invention relates to an electrical circuit for testing primary internal signals on an ASIC, wherein just one test pin (TEST) is provided via which it is possible to select a digital or analogue signal to be monitored (D₁, D₂,..., D_n; A₁, A₂,..., A_n). The electrical circuit comprises a Schmitt trigger (SMT₁) arranged between the test pin (TEST) and an output connection (TM) of the electrical circuit, wherein a test mode is activated when a switching threshold of the Schmitt trigger (SMT₁) is exceeded and at least one partial circuit is provided for monitoring a digital signal (D₁, D₂,..., D_n) having a resistor (R₁, R₂,..., R_n), an NMOS transistor (M₁, M₂,..., M_n) and an AND gate (X₁, X₂,..., X_n), to the first input of which the digital signal (D₁, D₂,..., D_n) is applied, wherein the resistor (R₁, R₂,..., R_n) is arranged between the test pin (TEST) and the drain connection of the NMOS transistor (M₁, M₂,..., M_n), the source connection of the NMOS transistor (M₁, M₂,..., M_n) is connected to earth, the gate connection of the NMOS transistor (M₁, M₂,..., M_n) is connected to the output of the AND gate (X₁, X₂,..., X_n) and the second input of the AND gate (X₁, X₂,..., X_n) is connected to the output connection (TM) of the electrical circuit.

Description

description

title

Electrical circuit for testing primary internal signals of an ASIC

The present invention relates to an electrical circuit for testing primary internal signals of an ASIC, wherein only one test pin is provided, via which a selection of one or more digital signals to be observed or a selection of an analog signal is feasible.

State of the art

Application-specific integrated circuits (ASIC) are tested as part of their manufacturing process and before delivery. For this purpose, internal digital and / or analog signals must be able to be provided observably or measurably via a test interface. The ASIC is generally placed in a test mode in which the digital and / or analog signals can be switched via a multiplexer to one or more separate terminals of the ASIC. The selection of the signals which are generally to be tested one after the other can be carried out, for example, via the Serial Peripheral Interface (SPI) interface or by means of an interface according to IEEE Standard 1149.1 (also known as: Joint Test Action Group, JTAG). This requires so far that essential parts of the ASIC infrastructure such as the internal power supply, the voltage reference, the communication interface and the digital part of the ASIC or at least portions of the digital part of the ASIC and parts of the analog part are in operation.

This allows the testability - especially those of the primary internal

Test variables such as the primary power supply, the primary voltage reference and the reset signals of the primary

Power supply - an ASIC can be restricted. If primary internal signals of an ASIC can be led out to the outside via the test interface, a careful and at times complex design is required to ensure that normal operation of the ASIC, in particular its startup, is not jeopardized by the testability of the corresponding signals. If, for example, the reset signal of the primary internal power supply can be tested, then the

Effect of this reset signal in test mode sometimes suppressed

or can be masked. A suppression in the

Normal operation, however, would affect the normal functioning of the ASIC. It must therefore be ensured that such signals are not affected during normal operation.

Furthermore, if internal analog voltages, such as the primary internal voltage reference, are to be passed out via a decentralized analog multiplexer, it must be ensured that these signals can not be affected during normal operation. Incorrectly controlled during startup

For example, transmission gates of a distributed multiplexer could short-circuit the primary internal voltage reference to another signal under test, preventing startup, even if the wrong one

Control only for a short time.

For example, it may also not be possible to observe a reset signal from an internal primary power supply or a power-on-reset signal through the test interface, where the internal primary voltage must be as small as possible for test purposes internal primary power supply voltage supply for the digital part is insufficient to operate this.

Disclosure of the invention

According to the invention, therefore, an electrical circuit for testing primary internal signals of an ASIC is provided, wherein only one test pin is provided, via which a selection of one or more

observable digital signals or an analog signal is feasible. By allowing in this way metrological detection of

Current that flows into the test pin terminal can be closed to the state of the signal to be monitored or the signals to be observed. Such a circuit is particularly suitable for testing the aforementioned primary test quantities such as the primary power supply, the primary voltage reference and the primary power supply reset signals of an ASIC.

It is according to the invention a between the test pin and a

Provided output terminal of the electrical circuit arranged Schmitt trigger, wherein when exceeding a switching threshold of the Schmitt trigger activation of a test mode is provided. Furthermore, the electrical circuit according to the present invention comprises at least one sub-circuit provided for monitoring a digital signal, comprising a resistor, an NMOS transistor and an AND gate, at the first input of which the digital signal is applied. In this case, the resistor between the test pin and the drain terminal of the NMOS transistor is arranged, the source terminal of the NMOS transistor is connected to ground, the gate terminal of the NMOS transistor is connected to the output of the AND gate and the second input of the AND gate is connected to the output terminal of the electrical circuit.

Advantages of the invention

The proposed circuit is in principle suitable - depending on the corresponding realization form - to test any internal digital signal and, according to a preferred embodiment, also any desired internal analog signal of an ASIC.

A particular advantage of the circuit is that the ASIC infrastructure only has to be ready for operation insofar as only an internal voltage supply is available during the test of a digital or analog signal. In addition to this power supply and according to the

Embodiments proposed circuits no other circuit parts of the ASIC must be ready for operation. In particular, the digital part of the ASIC does not have to be ready for operation, but may be in reset. A communication interface operated by the digital part of the ASIC is also not required.

In contrast to the solutions known from the prior art, according to the invention, the communication for possible switching to a special test mode, the communication for selecting one of the digital or analog signals to be observed and the metrological detection of these signals are effected via a single connection of the ASIC.

This makes it possible for the primary test variables - or any other digital or analog signals - to be tested or observed to a certain extent in their normal function, ie in normal operation. For example, the masking of reset signals is not required. Accordingly, the design of an ASIC can simplify the representation of the actual function.

According to the invention, the test pin can be regarded as a bidirectional interface, because information about it, in particular what exactly should be detected by measurement or which test mode is to be activated, is transferred into the ASIC by applying different high voltages in a suitable time sequence can be. Furthermore, the test pin can also provide information about internal signals in the form of a current flowing into them.

Each internal digital signal changes in the present case according to the formula I _TEST = U _TEST / RX [1/2 ° + 1 / (D _I * 2 ¹ ) + 1 / (D ₂ * 2 ² ) + ... + 1 / (D _n * 2 ⁿ )] weights the current. If all digital signals are LOW, only the current I _TEST = U _TEST / R * 1/2 ° flows into the test pin. If, for example, the internal digital signal Di = HIGH, the current I _TEST = U _TEST / R * 1/2 ¹ additionally flows into the test pin. In an analogous manner, with an internal digital signal D ² = HIGH, the current I _TEST = U _TEST / R * 1/2 ² additionally flows into the test pin. The currents are weighted and overlap. In this way, by metrological detection of the current can be closed simultaneously or in parallel to the states of all internal digital signals. Accordingly, the weighting of the currents is essential for a simultaneous or parallel detection of the internal digital Signals, so that a corresponding weighting of the resistors used for a function of the circuit is observed.

If instead of all the internal digital signals Di,, D _{n of} one of the analog signals Ai,..., A _m selected, then its internal voltage value can be closed by measuring the current flowing into the test pin. This results in I _TEST = U _TEST / R + U _A / R, where U _{A is} the

Voltage value of the one selected internal analog signal Ai, ..., A _m is.

The selection of what can be detected metrologically on the test pin, namely either all digital signals Di, D ₂ , ..., D _n simultaneously via weighted currents or one of the analog signals Ai, A ₂ , ..., A _m via a current proportional to the voltage of the signal, as well as the selection of a test mode, via a protocol, which is also transmitted via the test pin of the ASIC in the ASIC. This is done by the information about what

or which test mode is to be activated, is detected from the different levels of voltage at the test pin with the aid of a voltage divider and with the aid of Schmitt triggers and comparators and evaluated by a logic.

In a particular embodiment, it is provided according to the invention that the electrical circuit also has a connection between the test pin and ground

arranged resistor whose value can be determined by the current is measured, which flows into the test pin, as long as the voltage at the test pin is below the switching threshold of the Schmitt trigger. By knowing this value and measuring the current that flows into the test pin, it is possible in the following to be able to conclude the states of internal digital and analog signals.

According to a further embodiment, the electrical circuit is further configured to observe analog signals and comprises a

Operational amplifier, a circuit comprising a Schmitt trigger for limiting the input voltage at the test pin and at least one provided for monitoring the analog signal sub-circuit. In this way, an additional test of analog signals for the inventive circuit for testing an ASIC can be made possible. In this case, according to a preferred embodiment, the partial circuit provided for monitoring the analog signal comprises a two D flip-flops

having a counter having an AND gate and a transmission gate for each analog signal to be observed. This makes it possible that, depending on the count (00, 01, 10 or 11) of the D flip-flops of one of the AND gate at its output a high level leads .This drives the EN input of the corresponding transmission gate, so selbiges a low-impedance Establishes connection between its two other connections. Preferably, the counter can also be constructed from more than two D flip-flops. Accordingly, m = 2 ^d -1 analog signals Ai, ..., A _m can then be observed, where d is the number of D flip-flops. As a decoder, a classic 1-of-m decoder is provided in a well-known construction, which is referred to in the art as a 1-out-n decoder, consisting of 2 ^d AND gates with each d inputs, the AND - Gates whose inputs are all connected to the inverted outputs Q 'of the D flip-flops, is provided for selecting the observation of all digital signals simultaneously.

Preferably, a first input of the respective AND gate with the non-inverted or the inverted output of a first of the D flip-flops, a second input of the respective AND gate with the non-inverted or the inverted output of a second of the D Flip-flops and the output of the respective AND gate with an input for controlling the respective one

Transmission gates connected. This ensures that the D flip-flops used can take the counts 00, 01, 10 and 11, so that in this way various internal analog signals are selectable for observation.

According to a preferred embodiment of the electrical circuit, an OR gate is further provided, the first input to the non-inverted output of the first of the at least two D flip-flops, the second input to the non-inverted output of the second of the at least two D flip-flops and whose output is connected to an input for controlling the operational amplifier. The advantage of such an embodiment is that, based on the signals output by the D flip-flops, control of the Operational amplifier can be done and in this way the current flowing in the test pin of the electrical circuit, is influenced by the respectively selected internal analog signal.

In a further advantageous embodiment, an AND gate is further provided for the inventive electrical circuit whose first input to the inverted output of the first of the at least two D flip-flops whose second input connected to the inverted output of the second of the at least two D flip-flops is and whose output is connected to a respective third input of the at least one AND gate, which are arranged in the provided for the observation of a digital signal subcircuit. It can thereby be achieved that the outputs of the AND gates, which are used to observe a digital signal, can be set to LOW and thus none of the digital signals can influence the current flowing into the test pin of the ASIC. So only one

Observation of analog signals done.

Advantageously, in the circuit for limiting the input voltage to the test pin whose input between two resistors of an arranged between test pin of the electrical circuit and ground voltage divider arranged and their output connected to the clock signal input of a D flip-flop.

In a preferred embodiment of the invention, the output terminal of the electrical circuit is inverted by means of an inverter and in each case connected to a clear input of a D flip-flop. As a result, the count of the D-flip-flops can be reset again, since by means of the HIGH level of the inverter, the D flip-flops can be reset via clear inputs.

Particularly preferably, the electrical circuit further comprises two

Comparators for selecting the digital or analog signals to be measured via the test pin and for activating different test modes. Such an embodiment is particularly advantageous because an electrical circuit realized in this way enables different test modes or test methods and furthermore can easily be extended to operation with a plurality of terminals, via which signals can be selected and observed in the same way.

In each case, a reference voltage is advantageously applied to the positive input of the comparators and the negative input of the comparators is in each case connected to the test pin. There is a possibility that

Disable comparators and therefore test the internal digital and / or analog signals, even if operating voltage or

Reference voltage did not take their target values, so that

For example, it can be detected metrologically, from which internal

Supply voltage, the internal reference voltage reaches its target value or an internal power-on-reset signal changes state.

Preferably, a circuit consisting of a transistor as well as of a resistor and a capacitor is provided between the negative input of the comparators and the test pin of the electrical circuit. This allows protection of the comparator inputs from excessive voltages at their inputs as well as filtering and delaying the input signals.

According to a further preferred embodiment is in the electrical

Circuit further provided a D-type flip-flop whose clock signal input is connected to the output of the Schmitt trigger and whose non-inverted output is connected to an input for controlling the respective comparator.

Alternatively, it is advantageously provided that the electrical circuit comprises two D flip-flops, which are provided for the provision of output signals. Output of such output signals is advantageous because they can be used in the ASIC to provide certain test conditions.

Alternatively, a shift register consisting of D flip-flops can be provided for selecting the signals to be tested and for setting a test mode.

Advantageous developments of the invention are specified in the subclaims and described in the description. drawings

Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:

1 shows an embodiment of an electrical circuit for testing digital signals,

FIG. 2 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals,

FIG. 3 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals with the possibility of activating various test modes, and

FIG. 4 shows a signal curve for the above-mentioned exemplary embodiment of an electrical circuit for testing digital and analog signals with the possibility of activating various test modes according to FIG. 3.

Embodiments of the invention

In the context of the description of the embodiments of the invention, the voltages are referred to ground GND terminals or networks, for example, with U _TEST for the terminal TEST or U _VDD for the network VDD. On the other hand, currents flowing into terminals are denoted by I _TEST for the ASIC terminal TEST, for example.

FIG. 1 shows an exemplary embodiment of an electrical circuit for testing digital signals, which according to a first circuit implementation is suitable only for testing internal digital signals. The ASIC connection TEST can be used to switch to test mode when a voltage greater than the switching threshold of the Schmitt trigger SMTi is applied. This is done by a high level on the output terminal TM of the circuit connected to the output of the Schmitt trigger SMTi connected is displayed. The Schmitt trigger SMTi and the AND gates Xi to X _n are supplied by a supply voltage U _VDD , which is not shown in FIG. The switching thresholds of the Schmitt trigger are typically 2/3 or 1/3 of the supply voltage U _VDD .

If the voltage U _TEST at the ASIC terminal TEST from 0 V to the

Operating voltage of U _VDD increases, so the output of the Schmitt trigger SMTi remains at a low LOW level until its input voltage

or the voltage U _TEST at the ASIC terminal TEST is above the switching threshold of typically 2/3 * U _VDD . As long as it is possible to use the value of the resistance Ro = 2 ° xR by Ohny's law

determine by determining the current I _TEST flowing into the ASIC terminal TEST at the voltage U _TEST applied to this terminal. The

Resistance yields RO = R = UTEST / ITEST.

As soon as the signal at the output terminal TM = HIGH, the internal digital signals Di to D _{n of} the ASIC determine the additional current which flows into the ASIC terminal TEST, in that the transistors Mi to M _n

Connect resistors Ri to R _n to ground GND. If, as in FIG. 1, the values of the resistors Ri to R _n rise, for example, as Ri = 2 ¹ xR, R ₂ = 2 ² xR,..., R _n = 2 ⁿ xR, then by measuring the total current flowing into the ASIC terminal TEST flows in and are determined taking into account R _o = R, which of the internal digital signals Di to D _n a HIGH or LOW level, since for the ASIC terminal TEST measurable current I _TEST during TM = HIGH the following applies: I _TEST = U _TEST / R ^c [1/2 ° +

1 / (Dix2 ¹ ) + 1 / (D _2X 2 ² ) + ... + 1 / (D _n x2 ⁿ )], where in this formula for Di ... D _n a 1 or a 0 for a logical HIGH - or LOW level is to be used. Since the variables U _TEST and R are known, the states of the digital signals Di to D _n can be determined via the measured current I _TEST SO.

If the voltage at the ASIC terminal TEST of U _{VDD is} reduced to 0 V, the output of the Schmitt trigger SMTi remains at a HIGH level until its input voltage or the voltage at the ASIC terminal TEST below the switching threshold of typically 1 / 3X U _VDD is located. Then TM = LOW and the internal digital signals Di to D _n have none Influence more on the total current flowing into the ASIC terminal TEST.

FIG. 2 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals, in which the circuit known from FIG. 1 has been extended by the testability of internal analog voltage signals, this being exemplified in FIG. 2 for three digital signals D ₁ to D ₃ and three analog signals Ai to A _{3 is} shown. The current flowing into the ASIC terminal TEST can now be additionally influenced by the voltage U _AI to U _{A3 of} one of the analog signals Ai to A ₃ , by one of these signals via one of the transmission gates TG ₁ to TG ₃ to the positive Input of operating using the transistor M ₄ as an impedance converter operational amplifier OP ₁ is performed. The operational amplifier OP ₁ controls the gate of the transistor M ₄ in such a way that the

Input differential voltage between its positive and negative input to 0 V results. The voltage U _A at the positive input of the

Operational amplifier OP ₁ thus corresponds to the voltage drop U _R4 across the resistor R ₄ = R. Accordingly flows through the resistor R _4, a current I _R4 = U _A / R, which is proportional to the voltage U _AI to U _{A3 of} the selected analog voltage signal Ai to A ₃ .

Which of the internal analog signals Ai to A ₃ at the ASIC terminal TEST can be detected by measurement, is from the counter, consisting of the D flip-flops of FF ₁ and FF ₂ and that of the AND gates X ₅ to X ₇

existing decoder determined. Depending on the count (01, 10 or 11) one of the AND gates at its output a high level and thus controls the EN input (enable) of the corresponding transmission gate TG ₁ to TG ₃ , so that this is a low-impedance connection between his produces two other connections. The transmission gates whose EN input are at a low level are correspondingly high-impedance.

If the counter reading is not 00, then the output of the OR gate Xs is HIGH and the operational amplifier OP ₁ operates in the manner previously described.

At the same time, the output of the AND gate X ₄ and thus also the outputs of the AND gates Xi to X _{3 are} switched to LOW, so that none of the digital signals Di to D _3, the current which in the ASIC terminal TEST flows in, can influence. The current flowing into the ASIC terminal TEST results in I _TEST = U _TEST / R + U _A / R, where U _A corresponds to a voltage U _AI to U _A3 corresponding to the count. Since the variables U _TEST and R are known, the voltage of the selected internal analog signal can be determined via the measured current I _TEST SO.

On the other hand, if the counter reading is 00, the output of the OR gate Xs is LOW and the operational amplifier OPi is deactivated. The output of the operational amplifier OPi used here is then at 0 V. Alternatively or additionally, the positive input of the operational amplifier OPi could be pulled from a transistor to ground GND (not shown in Figure 2). When the counter 00 is also the output of the AND gate X ₄ is high, so that the digital signals Di to D _3, the current flowing into the ASIC terminal TEST, as described for Figure 1 can influence.

The count is incremented with each rising edge of the output signal of the Schmitt trigger SMT ₂ . If the counter reading 11 is reached, it is set to 00 again with the next rising edge at the CLK input of the D flip-flop FF ₂ . With TM = LOW it is also set to 00 because the HIGH level of inverter Xg resets D flip-flops FF ₁ and FF ₂ via their CLR inputs (clear) (the outputs Q of the D flip-flops are then LOW).

The output of the Schmitt trigger SMT ₂ changes from LOW to HIGH when its input voltage rises above the switching threshold of typically 2 / 3X U _VDD . It changes from HIGH to LOW when its input voltage drops below the switching threshold of typically 1 / 3X U _VDD . Via the transistors M ₆ and Mg and the voltage divider formed from R ₇ and Rs, where R ₇ = Rs = R / 2, the input of the Schmitt trigger SMT _{2 is} connected to the ASIC test pin TEST. In order for the transistor M _{Q to be able to} conduct, the voltage at its source connection must be above the threshold voltage U _{THP of} a PMOS transistor above the supply voltage U _VDD . This is the case in the circuit of FIG. 2 when U is _TEST ^ 2X (U _VDD + U _THP ). If U _{TEST is} smaller then M _Q blocks and the input of the Schmitt trigger SMT ₂ is pulled from R ₆ to GND. With each voltage pulse whose amplitude is greater than 2X (U _VDD + U _THP ), the counter is incremented accordingly. The transistors Ms and Mg serve to protect the Schmitt triggers SMTi and SMT ₂ . They each limit the input voltage to a maximum of U _VDD -U _THN , where U _{THN is} the threshold voltage of an NMOS transistor. Resistor Rs and transistors M ₇ and Ms, on the other hand, limit the source-to-gate voltage of M _Q. If the voltage at the ASIC terminal TEST is so large that the drain body diode of M ₇ conducts and a channel can be formed in Ms, the gate potential of M _{Q is} raised, so that the source-gate voltage of M _Q can not be much larger than the sum of the threshold voltage of a PMOS transistor and the forward voltage of a drain body diode.

The exemplary embodiment according to FIG. 2 is limited to three analog signals Ai, A ₂ , A ₃ . By adding further transmission gates, D flip-flops and by extending the 1-out-of-m decoder, however, in principle any number of analog signals can be observed. Accordingly, if more than three internal analog signals are to be observable, then the 1-out-of-m decoder must be extended as described above. Accordingly, in the case of more than three analog signals and more than two D flip-flops, the non-inverted outputs of the further D flip-flops must also be connected to additional inputs of the OR gate and the inverted outputs of the further D flip-flops to additional inputs of the AND gate.

FIG. 3 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals with the possibility of activating various test modes, in which the circuit shown in FIG. 2 has been correspondingly extended. Such a circuit makes it possible to activate various test modes via the ASIC terminal TEST in addition to the testability of internal digital and analog signals.

It should be noted that, in principle, the approach illustrated in FIG. 2, in which differently high response thresholds are created for a plurality of Schmitt triggers, could be pursued further. However, since the internal supply voltage U _VDD may also change during the test

(Especially down), then the voltage U _TEST at the ASIC terminal TEST would have to be carried ratiometrically to the internal supply voltage U _VDD , which sometimes can not be possible because the internal Supply voltage may not be measurable via a separate ASIC connection.

It may therefore be advantageous, in addition to the Schmitt trigger SMTi, which serves to activate the test mode, to use a further Schmitt trigger with a very high threshold, so that a significant reduction of the internal supply voltage U _VDD can not lead to this Schmitt trigger unintentionally switches at the same voltage U _TEST at the ASIC terminal TEST and greatly reduced internal supply voltage U _VDD . The use of multiple Schmitt triggers with very high thresholds is still possible, but requires from the components that are internally connected in the ASIC with the ASIC connector TEST, sometimes a very high

Dielectric strength.

In the circuit shown in Figure 3, therefore, in addition to the Schmitt trigger SMTi for activating the test mode another Schmitt trigger SMT _{2 is used} with a very high threshold. This circuit also realizes the testability of three digital signals Di to D ₃ and three analog signals Ai to A ₃ . In addition, four different test modes can be activated.

The output of the Schmitt trigger SMT ₂ changes from LOW to HIGH when its input voltage rises above the switching threshold of typically 2/3 * U _VDD . It changes from HIGH to LOW when its input voltage drops below the switching threshold of typically 1 / 3X U _VDD . Via the transistors M _Q and Mg and the voltage divider from R ₇ to Rg, where R ₇ = 2R / 3 and Rs = R / 12 and Rg = R / 4, is the input of the Schmitt trigger SMT ₂ with the ASIC test -Pin TEST

connected. In order for the transistor M _{Q to be able to} conduct, the voltage at its source connection must be above the threshold voltage U _{THP of} a PMOS transistor above the supply voltage U _VDD . This is the case in the circuit according to FIG. 3, when U is _TEST ^ 3X (U _VDD + U _THP ). If U _{TEST is} smaller, then M _Q blocks and the input of the Schmitt trigger SMT ₂ is pulled from R ₆ to ground GND. With each voltage pulse whose amplitude is greater than 3X (U _VDD + U _THP ), the D flip-flop FF ₃ switches its output Q from LOW to HIGH

(or from HIGH to LOW). With TM = LOW, all the D flip-flops FF ₁ to FF _{6 are set} to Q = LOW because the HIGH level of the inverter Xg is the D flip-flops FFi to FF _{6 is} reset via their CLR inputs (clear) (the outputs Q of the D flip-flops are then LOW).

If the output of the D flip-flop (network EN_CMP) is LOW, the comparators CMPi and CMP _{2 are} deactivated. The outputs of the comparators used here are then LOW. If the output of the D flip-flop is HIGH, then the

Comparators CMP ₁ and CMP ₂ activated. Using the comparators CMP ₁ and CMP ₂ , by varying the voltage on the ASIC test pin TEST, it is possible to select whether the digital signals Di to D ₃ or one of the analog signals Ai to A _{3 are to be selected} via the ASIC connection TEST be metrologically detectable. On the other hand, it is possible to activate different test modes. Due to the possibility of deactivating the comparators CMP ₁ and CMP ₂ , the internal signals Di to D ₃ or Ai to A _{3 can} also be tested if the operating voltage U _VDD or the

Reference _voltage U _{VREF have} not reached their target values. It is thus possible, for example via the ASIC terminal TEST, to detect from which internal supply voltage U _VDD the internal reference _voltage U _{VREF reaches} its target value or an internal power-on-reset signal changes its state without the risk that one of the Comparators CMP ₁ and CMP ₂ could switch unintentionally.

The activated comparators CMP ₁ and CMP ₂ provide HIGH levels when the voltage at their respective negative input is less than

Reference _voltage U _VREF is. The resistors R ₁₀ and Rn and the

Capacitors Ci and C ₂ serve as filters and delay elements. The transistors M ₁₀ and Mn protect the comparator inputs from excessive voltages at their inputs by limiting them to a maximum of U _VDD -U _THN , where U _{THN is} the threshold voltage of an NMOS transistor. Taking into account the voltage divider from the resistors R ₇ to Rg, the comparator outputs of CMP ₁ and CMP _{2 are} correspondingly at a voltage UTEST> 3X UVREF or UTEST> 4X UVREF to HIGH, otherwise the respective comparator output is LOW.

In the exemplary embodiments according to FIG. 2 and FIG. 3, both the flip-flops FF ₁ and FF ₂ and also the flip-flops FF ₄ , FF ₅ and FF _{6 are} reset. The flip-flops FF ₁ and FF ₂ select either all digital signals simultaneously off (count 00) or one of the analog signals (count 01, 10, 11). The flip-flops FFs and FF ₆ , however, are provided for selecting a test mode.

FIG. 4 shows the signal curve for the aforementioned exemplary embodiment of an electrical circuit for testing digital and analog signals with the possibility of activating various test modes according to FIG. 3, wherein a supply voltage of U _VDD = 5V and a reference voltage of U VREF are shown by way of example to illustrate the temporal signal _{characteristics} = 1V are assumed and the times 1 to 7 are marked with encircled numbers.

As shown in FIG. 4, higher voltages occur on the test pin than can be processed by the following Schmitt trigger, for example up to 20 V. The components M ₆ , M ₇ , Ms, Mg, Rs and R ₆ , which is shown in FIG. 2, protects the input of the Schmitt trigger SMT ₂ from these high voltages.

At time 1, the voltage U _{TEST changes} its value from 0 V to 5 V.

Accordingly, the output of the Schmitt trigger SMTI HIGH and that of the inverter X ₉ to LOW (CLR_FF = LOW).

At time 2, the voltage U _TEST briefly changes its value from 5V to 20V (and then back to 5V). Accordingly, the output of the Schmitt trigger SMT ₂ (short-term) is HIGH and that of the D flip-flop FF ₃ changes from LOW to HIGH. The comparators CMP ₁ and CMP ₂ are thus activated.

At time 3, the voltage U _{TEST changes} its value from 5V to 2.5V.

Accordingly, the output of the comparator CMP _{2 with a} time delay from LOW to HIGH (CMPB = HIGH) and that of the comparator CMP ₁ compared to CMP _{2 with a} time delay also changed from LOW to HIGH (CMPA = HIGH).

Accordingly, the output of the D flip-flop FF _{4 changes} from LOW to HIGH (CMPA_Q = HIGH) and the output of the OR gate X ₁₅ changes from LOW to HIGH (CMPB_H = HIGH).

At time 4, the voltage U _{TEST changes} its value from 2.5V to 5V.

Accordingly, the output of the comparator CMP ₁ change with a time delay from HIGH to LOW (CMPA = LOW) and that of the comparator CMP ₂ to CMP ₁ also delayed in time from HIGH to LOW (CMPB = LOW). Due to the delay element consisting of the transistors M ₁₂ and M ₁₃ , the resistor R ₁₂ and the capacitor C ₃ , the output of the OR gate X ₁₅ compared to that of the comparator CMP _{2 is} delayed in time from HIGH to LOW (CMPB_H = LOW) , With CMPB_H = LOW, the output of the OR gate X _{12 is set} to HIGH and that of the D flip-flop FF ₄ to LOW because the HIGH signal of X _{12 is applied} to its CLR input (clear). While CMPB is already LOW and CMPB_H is still high, the output of AND gate X _{13 is} HIGH for a short time (CMPB_P short-time HIGH). Because the output of the D flip-flop FF ₄ was set to HIGH at time 3, the output of the AND gate Xu also produces a short HIGH pulse, which increments the counter consisting of the D flip-flops FF ₅ and FF _6, and thus switches from test mode 00 to test mode 01. The corresponding output signals MDo and MD ₁ can be used in the ASIC to provide certain test conditions. Instead of the present case of the D flip-flop FF ₅ and FF ₆ existing counter, which is also shown in Figure 3, could also be a

Shift registers are used to set a test mode, where the distinction between a 0 and a 1 could be made by short and long pulses.

At time 5, the voltage U _{TEST changes} its value from 5V to 3.5V.

Accordingly (only) the output of the comparator CMP _{2 changes in} time from LOW to HIGH (CMPB = HIGH). Accordingly, the output of the OR gate X _{15 changes} from LOW to HIGH (CMPB_H = HIGH).

At time 6, the voltage U _{TEST changes} its value from 3.5 V to 5 V.

Accordingly, the output of the comparator CMP _{2 changes in} time from HIGH to LOW (CMPB = LOW). Due to the delay element (M ₁₂ , M ₁₃ , R ₁₂ , C ₃ ), the output of the OR gate X _{15 changes} from HIGH to LOW (CMPB_H = LOW) with respect to that of the comparator CMP _{2 with a} time delay. While CMPB is already LOW and CMPB_H is still high, the output of AND gate X _{13 is} HIGH for a short time (CMPB_P short-time HIGH). Because the output of the D flip-flop FF ₄ was set to LOW at time 4, the output of the AND gate X _{10 is} also a short HIGH pulse, the counter consisting of the D flip-flops FF ₁ and FF ₂ of 00 incremented to 01 and thus, as described correspondingly for FIG. 2, the analog signal Ai is switched via the transmission gate TGi to the operational amplifier OPi, so that it can be detected by measurement via the ASIC test pin TEST. At time 7, the voltage U _TEST briefly changes its value from 5V

20V (and then back to 5V). Accordingly, the output of the Schmitt trigger SMT ₂ (short-term) is HIGH and that of the D flip-flop FF ₃ changes from HIGH to LOW. The comparators CMP ₁ and CMP ₂ are thus deactivated. For example, the internal reference voltage U _{VDD could be used to measure} the internal reference voltage via the ASIC connection TEST

U _{VREF reaches} its target value or an internal power-on-reset signal changes its state without the risk that one of the comparators could switch unintentionally. In the further time course after the time 7, it is shown in FIG. 4 that a change in the voltage U _TEST from 5 V to 2.5 V no longer has any influence on the comparators CMP ₁ and CMP ₂ and therefore also no longer has any influence on the state of the D Flip flops has. If the voltage U _{TEST is set} to 0 V, the test mode is completely abandoned and all D flip-flops are reset.

Claims

claims

1. An electrical circuit for testing primary internal signals of an ASIC, wherein only one test pin (TEST) is provided, via which a selection of observed digital signals (Di, D ₂ ,, D _n ) or an analog signal

(Ai, A ₂ , ..., A _m ) is feasible, comprising

a Schmitt trigger (SMTi) arranged between the test pin (TEST) and an output terminal (TM) of the electrical circuit, an activation of a test mode being provided when a switching threshold of the Schmitt trigger (SMTi) is exceeded, and

at least one sub-circuit provided for monitoring a digital signal (Di _, D ₂ ,..., D _n ) with a resistor (Ri, R ₂ ,..., R _n ), an NMOS transistor (Mi _, M ₂ , ..., M _n ) and an AND gate (Xi _, X ₂ , ...,

X _n ), at whose first input the digital signal (Di _, D ₂ , ..., D _n ) is applied, the resistance (Ri, R ₂ , ..., R _n ) between the test pin (TEST) and the drain terminal of the NMOS transistor (Mi _, M ₂ , ..., M _n ), the source terminal of the NMOS transistor (Mi _, M ₂ , ..., M _n ) is grounded (GND ), the gate terminal of the NMOS transistor (Mi _, M ₂ , ..., M _n ) is connected to the output of the AND gate (Xi _, X ₂ , ..., X _n ) and the second Input of the AND gate (Xi _, X ₂ , ..., X _n ) is connected to the output terminal (TM) of the electrical circuit.

2. An electrical circuit according to claim 1, wherein a current measurable at the test pin (TEST) due to the states of all digital signals (Di, D ₂ , ..., D _n ) or a selected analog signal (Ai, A ₂ ,. .., A _m ) and by means of the measurable current on the state of all digital signals (Di, D ₂ , ..., D _n ) or on the state of the selected analog signal (Ai, A ₂ , ..., A _m ) is closable.

The electrical circuit of claim 1 or claim 2 further comprising a resistor (Ro) disposed between the test pin (TEST) and ground (GND).

4. Electrical circuit according to one of claims 1 to 3, wherein

according to the calculation Ro = 2 ° xR, Ri = 2 ¹ xR, R ₂ = 2 ² xR, R _n = 2 ⁿ xR sized resistors (Ri, R ₂ , R _n ) are provided.

5. Electrical circuit according to one of claims 1 to 4, further adapted for the observation of analog signals (Ai, A ₂ , A _m ), comprising

an operational amplifier (OPi),

- A Schmitt trigger (SMT ₂ ) having circuit for

Limitation of the input voltage at the test pin,

at least one sub-circuit provided for observing the analog signal (Ai, A ₂ ,, A _m ).

6. An electrical circuit according to claim 5, wherein provided for observing the analog signal (Ai, A ₂ , ..., A _m ) subcircuit

- Have at least two D flip-flops (FFi, FF ₂ , ..., FF _d )

Counters, and

for each analog signal to be observed (Ai, A ₂ ,..., A _m ) a decoder having an AND gate (X ₅ , C _Q , X ₇ ) and a transmission gate (TG ₁ , TG ₂ , TG ₃ )

includes.

7. An electrical circuit according to claim 5 or claim 6, wherein a first input of the respective AND gate (X ₅ , Cb, X ₇ ) to the non-inverted output (Q) and the inverted output (Q ') of a first of the D flip-flops (FF ₁ ), a second input of the respective AND gate (X ₅ , C _Q , X ₇ ) to the non-inverted output (Q) and the inverted output (Q ') of a second of the D flip-flops (FF ₂ ) and the output of the respective AND gate (X ₅ , C _Q , X ₇ ) to an input (EN) for controlling the respective transmission gate (TG ₁ , TG ₂ , TG ₃ ) are connected.

8. Electrical circuit according to one of claims 5 to 7, wherein further comprises an OR gate (X ₃ ) is provided, the first input to the non- inverted output (Q) of the first of the at least two D flip-flops (FFi, FF ₂ ), its second input to the non-inverted output (Q) of the second of the at least two D flip-flops and its output to an input (EN) Control of the operational amplifier (OP ₁ ) are connected.

9. An electrical circuit according to any one of claims 5 to 8, further comprising an AND gate (X ₄ ) is provided, the first input to the inverted output (Q ') of the first of the at least two D flip-flops, whose second input to the inverted output (Q ') of the second of the at least two D flip-flops is connected, whose third input is connected to the output of the Schmitt trigger SMT ₁ and whose output to a respective third input of the at least one AND gate (Xi, X _2nd , X ₃ ), which in the for the observation of a digital signal (Di _, D ₂ , D ₃ , D _n )

provided subcircuit is arranged, is connected.

10. Electrical circuit according to one of claims 5 to 9, wherein in the one Schmitt trigger (SMT ₂ ) having circuit for limiting the input voltage to the test pin (TEST) whose input between two resistors (R ₇ , Rs) one between test Pin (TEST) of the electrical circuit and ground (GND) arranged voltage divider is arranged and whose output is connected to the clock signal input (CLK) of a D flip-flop (FF ₂ , FF ₃ ).

11. Electrical circuit according to one of claims 5 to 10, wherein the

Output terminal (TM) of the electrical circuit is inverted by means of an inverter (Xg) and in each case with a clear input (CLR) of a D flip-flop (FF ₁ , FF ₂ , FF ₁ , FF ₂ , FF ₃ , FF ₅ , FFe) connected is.

12. Electrical circuit according to one of claims 5 to 1 1, further comprising two comparators (CMP ₁ , CMP ₂ ) for selecting the digital (Di, D ₂ , ..., D _n ) or analog (Ai, A ₂ , ..., A _m ) signals via the test pin (TEST) and to activate different test modes.

13. An electrical circuit according to claim 12, wherein at the positive input of the comparators (CMP ₁ , CMP ₂ ) each have a reference _voltage (U _VREF ) is present and the negative input of the comparators (CMPi, CMP ₂ ) each connected to the test pin (TEST).

14. An electrical circuit according to claim 13, wherein between the negative input of the comparators (CMP ₁ , CMP ₂ ) and the test pin (TEST) of the electrical circuit in each case one of a transistor (M ₁₀ , Mn) and of a resistor (R ₁₀ , R ₁₁ ) and a capacitor (Ci, C ₂ ) existing circuit is provided.

15. An electrical circuit according to any one of claims 12 to 14, further comprising a D flip-flop (FF ₃ ) is provided, the clock signal input (CLK) to the output of the Schmitt trigger (SMT ₂ ) is connected and its non-inverted output (Q) is in each case connected to an input (EN) for controlling the respective comparator (CMP ₁ , CMP ₂ ).

16. An electrical circuit according to any one of claims 12 to 15, further

comprising two D flip-flops (FFs, FFe), which are provided for providing output signals (MDo, MD ₁ ).

17. An electrical circuit according to any one of claims 12 to 15, further

comprising one consisting of D flip-flops (FF ₁ , FF ₂ , FF ₅ , FF ₆ )

Shift register for selecting the signals to be tested (Di, D ₂ , D ₃ , Ai, A ₂ , A ₃ ) and for setting a test mode (00 - 11).